JP2004355801A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing electric power consumption by an external interface buffer, such as a data input buffer. <P>SOLUTION: The semiconductor device has the first input buffer (40) which receives a clock signal (DQS) being a reference for data input and the second input buffer (30) to which the data is inputted. The first input buffer and the second a input buffer are activated after a write command is inputted thereto. The data input buffer is a differential input buffer having interface specifications pursuant to, for example, SSTL, is put into an activated state by an on state of a power switch, runs a penetration current and inputs the signal in prompt follow up to a slight change in a small amplitude signal. The input buffer is put into the active state only upon receipt of an instruction for the operation by the write command and therefore the useless current consumption to be consumed by the data input buffer previously put into the active state before the operation is instructed is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information input technique in a semiconductor device to which information used for executing a command for instructing an operation is supplied after the command is input. For example, the present invention relates to an SDRAM (Synchronous Dynamic) capable of DDR (Double Data Rate) operation. The present invention relates to a technology that is effective when applied to Random Access Memory.

  With an increase in operation speed, external interfaces such as SDRAMs are also shifting to small-amplitude signal interfaces such as SSTL (Stub Series Terminated Transceiver Logic). A differential amplifier circuit having a current mirror load is widely used as an input buffer of the SSTL specification interface. Since the through current always flows in the differential amplifier circuit in the active state, the power consumption is larger than that of the CMOS input buffer composed of the complementary MOS circuit, but a minute signal can be input at a high speed.

  The operation timing of a synchronous memory such as an SDRAM is controlled based on an external clock signal such as an external system clock signal. This type of synchronous memory is characterized in that the timing of an internal operation can be relatively easily set by using an external clock signal, and a relatively high-speed operation can be performed.

  Here, as the SDRAM, a so-called SDR (Single Data Rate) SDRAM in which data input and output are performed in synchronization with a rising edge of an external clock signal, and data input and output are performed in response to a rising edge of an external clock signal. There is known a so-called DDR type SDRAM which is performed in synchronization with both falling edges.

  The SDR type SDRAM and the DDR type SDRAM are different in input data write timing control. In the SDRAM of the SDR format, the supply of external data is specified in the same clock signal cycle as the instruction of the external write operation. Therefore, the write operation is instructed by the write command following the bank active command, and the write data is supplied at the same time. Therefore, if the data input buffer is activated after accepting the write command, it is synchronized with the clock signal together with the write command. Input of write data supplied in time is not enough. Thus, the data input buffer is activated when a bank active command instructing a row address operation is received.

  On the other hand, in the SDRAM of the DDR format, supply of external data synchronized with the data strobe signal is defined from a clock signal cycle after a clock signal cycle in which an external write operation instruction is issued. The data strobe signal is also used for data output. By using such a data strobe signal, the propagation delay of the data and the propagation delay of the data strobe signal are appropriately set for each SDRAM on the memory board. This makes it relatively easy to reduce the variation in data access time depending on the distance from the memory controller to the SDRAM on the memory board.

Japanese Patent Application Laid-Open No. 11-16346 (described about speeding up of write operation of SDRAM)

  The present inventor has studied the activation control of the data input buffer in the DDR type SDRAM. According to this, in the SDRAM of the DDR format, similarly to the SDR format, when the data input buffer is activated in response to the bank active command, the data input buffer is thereafter activated until, for example, a precharge command is accepted. The present inventor has found that the data input buffer consumes unnecessary power from the bank active command until the write command is issued. Also, after a bank active command, a write command is not always issued, and if only a read command is issued, the active state of the data input buffer is totally wasted as a result, resulting in power consumption. Has also been found completely wasteful by the inventor. In particular, the adoption of the SSTL interface of the data input buffer of the DDR-SDRAM is specified by JEDEC (Joint Electron Device Engineering Council), and considering the case of complying with this, the activation of the input buffer in the SSTL interface is considered. It has been found by the present inventors that the conversion control timing is a major factor in achieving low power consumption of the DDR-SDRAM.

  An object of the present invention is to provide a semiconductor device capable of reducing power consumption by an external interface buffer such as a data input buffer.

  Another object of the present invention is to provide a semiconductor device suitable for a DDR type SDRAM aiming at low power consumption.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, in a semiconductor device having a data input buffer capable of inputting write data to a memory unit, the data input buffer is changed from an inactive state to an active state after receiving a write operation instruction for the memory unit.

  The semiconductor device is, but not limited to, a clock-synchronous semiconductor device that performs an operation of writing data to a plurality of memory cells and an operation of reading data from the memory cells in response to a clock signal, for example, an SDRAM. .

  The data input buffer is, for example, a differential input buffer having an interface specification conforming to the SSTL standard. The buffer is activated when the power switch is turned on, and is deactivated when the power switch is turned off. An input buffer typified by the differential input buffer allows a through current to flow in its active state, and can immediately follow a small change in a small-amplitude input signal to transmit an input signal to a subsequent stage.

  Such an input buffer is activated only after receiving an instruction of a write operation to the memory unit, so that the data input buffer is previously activated and consumed before a write operation is instructed. Is reduced.

  In the case of an SDRAM which is a preferable example of the semiconductor device, a control circuit for controlling a data write operation and a data read operation for a memory cell includes a data write operation in which a bit line is designated by a column address by a write command, and a row address. Is selected by a bank active command, a data read operation in which a bit line is specified by a column address is specified by a read command, and initialization of a word line is specified by a precharge command. After receiving the command, the data input buffer is changed from the inactive state to the active state, and the state of the inactive data input buffer remains unchanged even when the bank active command or the read command is received. As described above, since the data input buffer is not activated by the instruction by the bank active command or the read command, if the write command is not instructed at all after the bank activation, no unnecessary power consumption is performed in the data input buffer.

  When the semiconductor device is specified to supply data synchronized with a data strobe signal from a clock signal cycle after the clock signal cycle in which a write operation is instructed by a write command, such as a DDR format SDRAM, The semiconductor device has, for example, a data latch circuit at the next stage of the data input buffer, and the data latch circuit latches data supplied in synchronization with the data strobe signal in synchronization with the data strobe signal. I do. Such a data input specification in a semiconductor device, from one point of view, guarantees that even if the data input buffer is activated after the instruction of the write operation by the clock synchronous write command, the input loss of the write data does not occur. .

  When enabling input / output of data in synchronization with both rising and falling edges of a data strobe signal synchronized with a clock signal as in a DDR SDRAM, the data latch circuit includes, for example, the data latch. The data input to the data input buffer is sequentially latched in synchronization with the rising and falling changes of the strobe signal, and the data can be supplied to the memory cells in parallel in units of one or more cycles of the data strobe signal. A data latch circuit according to a more specific aspect includes a first data latch circuit that latches data input from the data input buffer in synchronization with a rising change of the data strobe signal, and a data input circuit that inputs the data from the data input buffer. A second data latch circuit for latching data in synchronization with a falling transition of the data strobe signal; and a data latch circuit for latching data latched in the first data latch circuit in synchronization with a falling transition of the data strobe signal. And a third data latch circuit that outputs the data from the second data latch circuit and the third data latch circuit in parallel with each other.

  Once write data is taken in from the data input buffer, it is no longer necessary to keep the data input buffer active even if the write operation has not been completed. Therefore, if the highest priority is given to the low power consumption of the data input buffer, the data input buffer waits until the last write data of the write operation by the write command is latched in the second and third data latch circuits. May be changed from the active state to the inactive state. Although this control can be performed in synchronization with the data strobe signal, the reliability of the write operation can be maintained even when the relationship between the data strobe signal and the setup / hold time of the write data fluctuates undesirably. In this case, the data input buffer may be changed from the active state to the inactive state in synchronization with the end of the write operation by the write command.

  The input buffer control based on the same viewpoint as the data input buffer can be applied to the address input buffer and the like. For example, a plurality of address input terminals, a plurality of address input buffers provided corresponding to the plurality of address input terminals, a clock terminal for receiving a clock signal, and a data input / output when a selection terminal is connected to a word line. As an example, a semiconductor device including a plurality of memory cells whose terminals are connected to a bit line, and a control circuit that controls a data write operation and a data read operation for the memory cells in synchronization with a clock signal, In the control circuit, a word line selection operation by a row address is instructed by a bank active command, a data read operation in which a bit line is specified by a column address is instructed by a read command, and a data write operation in which a bit line is specified by a column address is written. Word line initialization, as indicated by command The address input buffer is changed from an inactive state to an active state after receiving the bank active command, the read command or the write command, instructed by a precharge command, and thereafter, for a certain cycle period synchronized with the clock signal. , The address input buffer may be changed from the active state to the inactive state.

  The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.

  That is, in a semiconductor device having a data input buffer capable of inputting write data to a memory unit, the data input buffer is changed from an inactive state to an active state after receiving a write operation instruction for the memory unit. The data input buffer is, for example, a differential input buffer having an interface specification conforming to the SSTL standard. In the active state, the data input buffer allows a through current to flow and immediately follows a small change in a small amplitude signal to input a signal. . Such an input buffer is activated only after receiving an instruction of a write operation to the memory unit, so that the data input buffer is previously activated and consumed before a write operation is instructed. Can be reduced.

  In the case of an SDRAM, which is a preferred example of the semiconductor device, the data input buffer is not activated by an instruction by a bank active command or a read command. No wasteful power consumption is performed.

  The input buffer control based on the same viewpoint as the data input buffer can be applied to the address input buffer and the like. After accepting the bank active command, the read command or the write command, the address input buffer is changed from an inactive state to an active state, and then, after a predetermined cycle period synchronized with the clock signal elapses, the address input buffer is changed. Change the buffer from an active state to an inactive state.

  As described above, a semiconductor device capable of reducing power consumption by an external interface buffer such as a data input buffer can be provided.

<< Overview of DDR-SDRAM >>
FIG. 1 shows a DDR SDRAM (DDR-SDRAM) as an example of a semiconductor device according to the present invention. Although not particularly limited, the DDR-SDRAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known MOS semiconductor integrated circuit manufacturing technique.

  Although not particularly limited, the DDR-SDRAM 1 has four memory banks BNK0 to BNK3. Although not shown, each of the memory banks BNK0 to BNK3 has, although not particularly limited, four memory mats, and each memory mat is constituted by two memory arrays. One memory array is allocated to a data storage area where the least significant bit of the column address signal corresponds to a logical value “0”, and the other memory array is a data area where the least significant bit of the column address signal corresponds to a logical value “1”. Assigned to storage area. The memory mats of the memory banks and the divisional structure of the memory array are not limited to the above. Therefore, in this specification, unless otherwise specified, each memory bank is configured as a single memory mat. explain.

  The memory mat of each of the memory banks BNK0 to BNK3 includes dynamic memory cells MC arranged in a matrix. According to the drawing, the selection terminals of the memory cells MC arranged in the same column are word lines WL for each column. And the data input / output terminals of the memory cells arranged on the same row are connected to one of the complementary bit lines BL, BL for each row. Although only a part of the word line WL and the complementary bit line BL is shown as a representative in the figure, a large number of word lines WL and complementary bit lines BL are actually arranged in a matrix and have a folded bit line structure centered on a sense amplifier. I have.

  Row decoders RDEC0 to RDEC3, data input / output circuits DIO0 to DIO3, and column decoders CDEC0 to CDEC3 are provided for each of the memory banks BNK0 to BNK3.

  The word line WL of the memory mat is selected and driven to a selected level in accordance with a decoding result of a row address signal by row decoders RDEC0 to RDEC3 provided for each of the memory banks BNK0 to BNK3.

  Each of the data input / output circuits DIO0 to DIO3 has a sense amplifier, a column selection circuit, and a write amplifier. The sense amplifier is an amplifier circuit that detects and amplifies a minute potential difference appearing on each of the complementary bit lines BL, BL by reading data from the memory cell MC. The column selection circuit is a switch circuit for selecting the complementary bit lines BL, BL to conduct to the input / output bus 2 such as a complementary common data line. The column selection circuit is selectively operated according to the result of decoding of the column address signal by the corresponding one of the column decoders CDEC0 to CDEC3. The write amplifier is a circuit that differentially amplifies the complementary bit lines BL, BL via a column switch circuit according to write data.

  A data input circuit 3 and a data output circuit 4 are connected to the input / output bus 2. The data input circuit 3 inputs write data supplied from the outside in the write mode and transmits the write data to the input / output bus 2. The data output circuit 4 inputs the read data transmitted from the memory cell MC to the input / output bus 2 in the read mode and outputs the read data to the outside. An input terminal of the data input circuit 3 and an output terminal of the data output circuit 4 are coupled to, but not limited to, 16-bit data input / output terminals DQ0 to DQ15. For convenience, the data that the SDRAM 1 inputs and outputs from the outside may be described with reference characters DQ0 to DQ15.

  Although not particularly limited, the DDR-SDRAM 1 has 15-bit address input terminals A0 to A14. Address input terminals A0 to A14 are coupled to address buffer 5. Of the address information supplied to the address buffer 5 in a multiplex form, the row address signals AX0 to AX12 are provided to the row address latch 6, the column address signals AY0 to AY11 are provided to the column address latch 7, and the bank regarded as a bank selection signal. The select signals AX13 and AX14 are supplied to the bank selector 8, and the mode register setting information A0 to A14 are supplied to the mode register 9.

  The operation of the four memory banks BNK0 to BNK3 is selected by the bank selector 8 according to the logical values of the 2-bit bank selection signals AX13 and AX14. That is, only the memory bank whose operation is selected is enabled for memory operation. For example, a sense amplifier, a write amplifier, a column decoder, and the like are not activated in a memory bank whose operation is not selected.

  The row address signals AX0 to AX12 latched by the row address latch 6 are supplied to row address decoders RDEC0 to RDEC3.

  The column address signals AY0 to AY11 latched by the column address latch 7 are preset in the column address counter 10 and supplied to the column address decoders CDEC0 to CDEC3. When a burst access, which is a continuous memory access, is instructed, the column address counter 10 is incremented by the number of consecutive times (the number of bursts), and a column address signal is internally generated.

  The refresh counter 11 is an address counter that generates a row address for refreshing stored information by itself. When a refresh operation is instructed, word line WL is selected according to a row address signal output from refresh counter 11, and stored information is refreshed.

  The control circuit 12 is not particularly limited, but includes the clock signals CLK and CLKb, the clock enable signal CKE, and the chip select signal CSb (the suffix b means that the signal attached thereto is a low enable signal or a level inversion signal. ), External control signals such as a column address strobe signal CASb, a row address strobe signal RASb, a write enable signal WEb, data mask signals DMU and DML, and a data strobe signal DQS, as well as predetermined information from the mode register 9. The operation of DDR-SDRAM 1 is determined by a command defined by a combination of the states of the input signals, and control circuit 12 has control logic for forming an internal timing signal according to the operation specified by the command.

  The clock signals CLK and CLKb are master clocks of the SDRAM, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

  The chip select signal CSb instructs the start of a command input cycle by its low level. When the chip select signal is at a high level (chip is not selected), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

  The RASb, CASb, and WEb signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle described later.

  The clock enable signal CKE is a control signal for the power-down mode and the self-refresh mode. When the power-down mode (which is also the data retention mode in the SDRAM) is set, the clock enable signal CKE is at a low level.

  The data mask signals DMU and DML are mask data in units of bytes for the input write data. The high level of the data mask signal DMU instructs write suppression by the upper byte of the write data, and the high level of the data mask signal DML indicates the write data. Instructs writing to be inhibited by the lower byte.

  The data strobe signal DQS is externally supplied as a write strobe signal during a write operation. That is, when a write operation is instructed in synchronization with the clock signal CLK, the supply of data synchronized with the data strobe signal DQS from the clock signal cycle after the clock signal cycle in which the write operation is instructed is defined. . During a read operation, the data strobe signal DQS is output to the outside as a read strobe signal. That is, in the data read operation, the data strobe signal is changed in synchronization with the external output of the read data. For this purpose, a DLL (Delayed Lock Loop) circuit 13 and a DQS output buffer 14 are provided. In order to synchronize the clock signal CLK received by the semiconductor device 1 with the data output timing by the data output circuit 4, the DLL circuit 13 controls the clock signal for controlling the data output operation (the control signal having the same phase as the data strobe signal DQS during the read operation). The clock signal 15 is adjusted in phase. The DLL circuit 13 regenerates the internal clock signal 15 capable of compensating for the signal propagation delay time characteristic of the internal circuit by using the replica circuit technology and the phase synchronization technology, although not particularly limited. The data output circuit 4 that is operated to output data can output data at a timing that is reliably synchronized with the external clock signal CLK. The DQS buffer 14 outputs the data strobe signal DQS to the outside in the same phase as the internal clock signal 15.

  The row address signals (AX0 to AX12) are defined by the levels of the address input terminals A0 to A12 in a later-described row address strobe / bank active command (active command) cycle synchronized with the rising edge of the clock signal CLK. In this active command cycle, signals AX13 and AX14 input from address input terminals A13 and A14 are regarded as bank selection signals. When A13 = A14 = "0", banks BNK0, A13 = "1" and A14 = "" When "0", bank BNK1 is selected, when A13 = "0", bank BNK2 when A14 = "1", and bank BNK3 when A13 = "1", A14 = "1". The memory bank selected in this way is subjected to data read by a read command, data write by a write command, and precharge by a precharge command.

  The column address signals (AY0 to AY11) are at the levels of the terminals A0 to A11 in a column address / read command (read command) cycle and a column address / write command (write command) cycle which will be described later in synchronization with the rising edge of the clock signal CLK. Defined by The designated column address is used as the start address of the burst access.

  Although not particularly limited, commands such as the following [1] to [9] are defined in the DDR-SDRAM 1 in advance.

  [1] The mode register set command is a command for setting the mode register 9. This command is specified by CSb, RASb, CASb, WEb = low level, and data to be set (register set data) is given through A0 to A14. The register set data is not particularly limited, but has a burst length, a CAS latency, a burst type, and the like. The burst length that can be set is not particularly limited, but is 2, 4, 8, and the CAS latency that can be set is 2, 2.5, although not particularly limited.

  The CAS latency specifies how many cycles of the clock signal CLK are required from the fall of CASb to the output operation of the data output circuit 4 in a read operation specified by a column address read command described later. Until the read data is determined, an internal operation time for data read is required, which is set according to the operating frequency of the clock signal CLK. In other words, the CAS latency is set to a relatively large value when using a high-frequency clock signal CLK, and the CAS latency is set to a relatively small value when using a low-frequency clock signal CLK.

  [2] The row address strobe / bank active command is a command for validating a row address strobe and selecting a memory bank by A13 and A14. CSb, RASb = low level (“0”), CASb, WEb = Instructed by the high level ("1"), the address supplied to A0 to A12 at this time is taken as a row address signal, and the signals supplied to A13 and A14 are taken in as a memory bank selection signal. The fetch operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is specified, the word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

  [3] The column address read command is a command necessary for starting the burst read operation and a command for giving an instruction of a column address strobe. CSb, CASb, = low level, and RASb, WEb = high level. At this time, the address supplied to A0 to A11 is taken in as a column address signal. The fetched column address signal is preset in the column address counter 10 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. In accordance with the address signal output from the column address counter 10 in synchronization with the data strobe signal DQS, the memory bank is sequentially selected in the memory bank in units of 32 bits and continuously externally in units of 16 bits in synchronization with the rise and fall of the data strobe signal DQS. Is output. The number of data (the number of words) read continuously is set to the number specified by the burst length. The start of reading data from the data output circuit 4 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

  [4] The column address write command is a command necessary to start the burst write operation when the burst write is set in the mode register 9 as a mode of the write operation. Further, the command gives an instruction of a column address strobe in burst write. The command is specified by CSb, CASb, WEb, = low level and RASb = high level. At this time, the addresses supplied to A0 to A11 are captured as column address signals. The fetched column address signal is supplied to the column address counter 10 as a burst start address in burst write. The procedure of the burst write operation instructed thereby is also performed in the same manner as the burst read operation. However, the CAS latency is not set in the write operation, and the capture of the write data is started in synchronization with the data strobe signal DQS one cycle later than the clock signal CLK from the column address / write command cycle.

  [5] The precharge command is a command to start a precharge operation for the memory bank selected by A13 and A14, and is instructed by CSb, RASb, WEb, low level and CASb high level.

  [6] The auto-refresh command is a command required to start auto-refresh, and is instructed by CSb, RASb, CASb = low level and WEb, CKE = high level. The refresh operation by this is the same as the CBR refresh.

  [7] When the self-refresh entry command is set, the self-refresh function operates while CKE is kept at the low level. During that time, the refresh operation is automatically performed at a predetermined interval without an external refresh instruction. Is performed.

  [8] The burst stop command is a command necessary to stop the burst read operation, and is ignored in the burst write operation. This command is specified by CASb, WEb = low level, and RASb, CASb = high level.

  [9] The no operation command is a command instructing not to perform a substantial operation, and is instructed by CSb = low level and RASb, CASb, WEb = high level.

  In the DDR-SDRAM 1, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The operation of the row address system in the other memory bank is enabled without affecting the operation in the other memory bank. That is, a row address operation specified by a bank active command or the like and a column address operation specified by a column address / write command or the like can be performed in parallel between different memory banks. Therefore, as long as data does not collide at the data input / output terminals DQ0 to DQ15, during execution of a command whose processing has not been completed, a precharge command for a memory bank different from the memory bank to be processed by the command being executed, It is possible to issue a row address strobe bank active command to start the internal operation in advance.

  As is clear from the above description, the DDR-SDRAM 1 enables data input / output in synchronization with both rising and falling edges of the data strobe signal DQS in synchronization with the clock signal CLK, and synchronizes with the clock signal CLK. Addresses and control signals can be input and output, so that a large-capacity memory similar to a DRAM can operate at a high speed comparable to an SRAM, and how many data can be accessed for a single selected word line. By designating whether or not to do so, the built-in column address counter 10 sequentially switches the selection state of the column system, so that a plurality of data can be read or written continuously.

<< SSTL interface >>
In the DDR-SDRAM 1, although not particularly limited, the clock signal CLK, the inverted clock signal CLKb, the clock enable signal CKE, the chip select signal CSb, the RAS signal RASb, the CAS signal CASb, the write enable signal WEb, and the address input signals A0 to A0 A14, the input buffer receiving the data mask signal DM and the data strobe signal DQS, the data input buffer of the data input circuit 3, and the interface of the data output buffer of the data output circuit 4 are based on, for example, the publicly known SSTL2 (Class II) standard. You.

  FIG. 2 shows a circuit configuration example of SSTL2 (class II). The transmission line 20 having a characteristic impedance of 50Ω is pulled up by the reference voltage VREF, and is connected to, for example, a memory controller or an SDRAM. The input buffer of the SDRAM is a differential input buffer 21, and the transmission line 20 is coupled to one of the differential inputs. The reference voltage VREF is applied to the other, and the activation of the power switch 22 is controlled by the enable signal DIE. The power supply voltage VDD is, for example, 3.3 V, and the ground voltage VSS of the circuit is 0 V. The output buffer includes a CMOS inverter which uses a power supply voltage VDDQ = 2.5 V and a ground voltage VSS as an operation power supply in an output stage. The memory controller has a driver and a receiver satisfying the interface specifications. The driver drives the transmission line 20, and the receiver inputs data from the transmission line 20.

  FIG. 3 illustrates a signal standard in the SSTL2 (class 2). In the SSTL2 standard, a level of 1.6 volts or more, which is higher than 0.35 V with respect to a reference potential (VREF) such as 1.25 volts, is regarded as an H level, and a level of 0.35 V or less with respect to such a reference potential. That is, the level of 0.90 volt or less is regarded as the L level. The above specific level is a typical example, and may be, for example, a level that conforms to the SSTL3 standard.

  FIG. 4 shows an input first-stage buffer of the data input circuit 3 as a specific example of the differential input buffer conforming to the SSTL. The differential input buffer 30 includes a current mirror load including p-channel MOS transistors Mp1 and Mp2, n-channel differential input MOS transistors Mn3 and Mn4 coupled to the drains of the MOS transistors Mp1 and Mp2, And a n-channel type power switch MOS transistor Mn5 coupled to a common source of the differential input MOS transistors Mn3 and Mn4.

  The gate of one differential input MOS transistor Mn3 is coupled to data terminal DQj (j = 0 to 15), and the gate of the other differential input MOS transistor Mn4 is coupled to reference voltage VREF. The output node of the differential amplifier circuit can be selectively precharged to the power supply voltage VDD by the p-channel type precharge MOS transistor Mp6, and the signal of the node is inverted and output via the inverter 31.

  DIE is an enable control signal for the differential input buffer 30, and is supplied to the gates of the power switch MOS transistor and the precharge MOS transistor Mp6. The differential input buffer is activated by the high level of the enable control signal DIE. In this active state, an operating current flows through the differential amplifier circuit, and a minute potential difference from the signal level of the terminal DQj around the reference voltage VREF is immediately amplified. Due to the differential amplification, the signal input operation from the terminal DQj is fast. The differential input buffer is deactivated by the low level of the enable control signal DIE. In the inactive state of the differential input buffer, no power is consumed in the differential amplifier circuit, and the output of the inverter 31 is forced to a low level by the action of the precharge MOS transistor Mp6 in the on state.

  The enable control signal DIE is asserted from a low level to a high level after the DDR-SDRAM 1 is instructed to perform a write operation by a write command. As described above, since the differential input buffer 30 is activated after the write operation is instructed by the write command, the differential input buffer 30 does not wastefully consume power before the write operation is instructed. Further, even when the bank active command or the read command is received, the state of the inactive data input buffer remains unchanged. Since the differential input buffer 30 is not activated by the instruction by the bank active command or the read command, no useless power consumption is performed in the differential input buffer 30 if no write command is issued after the bank activation.

  FIG. 5 shows a differential input buffer for the data strobe section signal DQS as another example of the differential input buffer based on the SSTL. The differential input buffer 40 is configured by mutually connecting input terminals having different polarities of a pair of differential amplifier circuits. That is, one differential amplifier circuit includes a current mirror load including p-channel MOS transistors Mp11 and Mp12, n-channel differential input MOS transistors Mn13 and Mn14, and an n-channel power switch MOS transistor Mn15. The gate of the MOS transistor Mn13 is an inverting input terminal, and the gate of the MOS transistor Mn14 is a non-inverting input terminal. The other differential amplifier circuit includes a current mirror load composed of p-channel MOS transistors Mp21 and Mp22, n-channel differential input MOS transistors Mn23 and Mn24, and an n-channel power switch MOS transistor Mn25. The gate of the MOS transistor Mn23 is an inverting input terminal, and the gate of the MOS transistor Mn24 is a non-inverting input terminal.

  A data strobe signal DQS is input to the gates of the differential input MOS transistors Mn13 and Mn24, and a reference voltage VREF is input to the gates of the differential input MOS transistors Mn14 and Mn23. , Internal clock signals DSCLKT and DSCLKB at a complementary level to data strobe signal DQS can be obtained from CMOS inverters 41 and 42 connected to the single-ended output node.

  DSEN is an enable control signal for the differential input buffer 40, and is supplied to the gates of the power switch MOS transistors Mn15 and MN25. The differential input buffer is activated by the high level of the enable control signal DSEN. In this active state, an operating current flows through the differential amplifier circuit, and a minute potential difference between the signal level of the terminal DQS and the reference voltage VREF is immediately amplified. Due to the differential amplification, the signal input operation from the terminal DQS is fast. The differential input buffer is deactivated by the low level of the enable control signal DSEN. In the inactive state of the differential input buffer, there is no power consumption in the differential amplifier circuit.

《Data input circuit》
FIG. 6 shows an example of the data input circuit 3 of the DR-SDRAM 1. At the first stage, the differential input buffer 30 of the SSTL specification described in FIG. 4 is arranged. The differential input buffer 30 inputs write data supplied in synchronization with each rising and falling edge of the data strobe signal DQS. At the next stage of the differential input buffer 30, there is provided a latch circuit 50 for latching data supplied in half cycle units of the data strobe signal in parallel in one cycle unit of the data strobe signal. The latch circuit 50 is, for example, different from a first data latch circuit 50A that latches output data of the differential input buffer 30 in synchronization with the rising change of the data strobe signal, in synchronization with the falling change of the data strobe signal. A second data latch circuit 50B for latching the output data of the dynamic input buffer 30, and a third data latch circuit 50C for latching the output data of the first data latch circuit 50A in synchronization with the falling transition of the data strobe signal. And Each of the data latch circuits 50A to 50C is constituted by a master / slave type latch circuit (MSFF). The data latch circuit 50A uses DSCLKT as a master stage latch clock, DSCLKB as a slave stage latch clock, , DSCLKB is the latch clock of the master stage, and DSCLKT is the latch clock of the slave stage. The latch clocks DSCLKT and DSCLKB are signals changed in synchronization with the data strobe signal DQS.

  The parallel output data DINRj and DINFj of the latch circuit 50 are supplied to selector latch circuits 51 and 52, respectively. The selector latch circuits 51 and 52 select either the parallel output data DINRj or DINFj according to the value of the signal DICY0, and latch the selected data in synchronization with the clock signal DICLK. The signal DICY0 is a signal corresponding to the logical value of the least significant bit AY0 of the column address signal (start address of burst write) supplied from the outside to the column address latch 7, and the selector latch circuit 51 outputs DICY0 (= AY0) = 0. At this time, DINRj is selected, and when DICY0 (= AY0) = 1, DINFj is selected. The selection control of the selector latch circuit 52 is opposite to that. Therefore, regardless of the logical value of the least significant bit of the column address of the first input write data, the data with the logical value of the least significant bit “0” is stored in the selector latch circuit 51, and the data with the logical value of “1” is stored in the selector latch circuit 51. The data is latched by the selector latch circuit 52.

  The output of the selector latch circuit 51 is allocated via a signal line DINBY0Bj included in the input / output bus 2 to a data storage area corresponding to data in which the least significant bit of the column address signal is a logical value “0”. Connected to the memory array of each memory bank. The output of the selector latch circuit 52 is allocated via a signal line DINBY0Tj included in the input / output bus 2 to a data storage area corresponding to data in which the least significant bit of the column address signal is a logical value “1”. It is connected to the memory array of each memory bank.

  FIG. 7 schematically shows a connection mode between a selector latch circuit and a memory array of a memory bank. FIG. 7 illustrates one memory mat MAT in each memory bank. The memory array Y0B of each memory mat MAT is for storing data in which the logical value of the least significant bit of the column address is "0". Is for storing data in which the logical value of the least significant bit of the column address is "1". WAmp is a write amplifier for each memory array, and is included in the corresponding data input / output circuits DIO0 to DIO3. YI0WY0T0 to YI0WY0T3 and YI0WY0B0 to YI0WY0B3 are activation control signals for the write amplifier WAmp for each memory array.

  As understood from the description of the data input circuit 3, in the DDR-SDRAM 1, data is externally input in synchronization with both rising and falling of the data strobe signal DQS in synchronization with the clock signal CLK. -The write operation inside the SDRAM 1 is performed using the cycle of the clock signal CLK as a minimum unit. Although a detailed description is omitted, the relationship between the internal operation timing of the SDRAM and the external output operation timing is the same for the data read operation.

<< Control circuit of DDR-SDRAM >>
FIG. 8 shows a detailed example of a stage preceding the control circuit 12 of the DDR-SDRAM, and FIG.

  The CLK input buffer 60, the command input buffer 61, and the DQS input buffer 40 in FIG. 8 are differential input buffers of the SSTL specification. The DQS input buffer 40 is as exemplified in FIG. 5, and the CLK input buffer 60 includes a differential amplifier circuit having a differential input of CLK and CLKb as a first-stage differential input buffer, and is activated by turning on an operation power supply. And is deactivated in response to the instruction of the power down mode. The command input buffer 61 is configured in the same manner as the differential input buffer of FIG. 4, but is activated when the operating power is turned on, and is deactivated in response to the instruction of the power down mode.

  The output of the CLK input buffer 60 is supplied to a one-shot pulse generation circuit 62, which generates various internal clock signals ACLKB, BCLKB, CCLKB, and DCLKB.

  Various signals CSb, RASb, CASb, and WEb input to the command input buffer 61 are decoded by the command decode circuit 63, and an internal control signal corresponding to the above-described operation mode is generated. ACTi is a control signal for activating a bank selected by a bank selection signal when bank activation is instructed by a bank active command. The suffix i means a bank number. The meaning of the suffix i is the same for other signals. WT and WTY are activated in response to a write operation instruction by a write command. The activation timing of WTY is earlier than that of WT. The signal WTL2 is a signal obtained by delaying the signal WT by the shift register 64A. RD is activated when a read operation is instructed by a read command. PREi is a control signal for activating the bank selected by the bank selection signal when precharge is instructed by the precharge command.

  RWWi is a column selection system reference control signal when a write operation is instructed, and is a signal for each memory bank. In the write operation, the column selection timing is set two clock cycles after the instruction of the write command. Therefore, the signal RWWi is delayed by the shift register circuit 64B, and the one-shot pulse synchronized with the internal clock signal BCLKB from the delayed signal RWW2i is output. Signal RWi is output from one-shot pulse generation circuit 64C.

  The result of decoding by the command decode circuit 63 is reflected on various flags (RSFF) of the mode state circuit 66 in FIG. The flag is composed of a set / reset type flip-flop. S indicates a set terminal and R indicates a reset terminal. BAi (i = 0 to 3) indicates a memory bank whose active state is indicated. BEND is a signal indicating the end of the burst operation, and BBi is a signal indicating that the burst write operation is being performed. The signals BWTY, BDRY, and BBYi are signals obtained by latching the signals BWT, BRD, and BBNi in synchronization with the clock signal BCLKB. Based on the column state signal BBYi generated based on the signal BBi, the write pulse generation circuit 67 generates the select signals YI0WY0T0 to YI0WY0T3, YI0WY0B00 to YI0WY0B3 of the memory array for each bank. The write clock DICLK is a signal obtained by latching the signal RWWSTOR in synchronization with the clock signal DCLKB.

  FIG. 10 is a block diagram of a column address input system. The address buffer 5 is a differential input buffer of the SSTL specification. The address buffer 5 is configured in the same manner as the differential input buffer of FIG. 4, but is activated when the operation power is turned on, and is deactivated in response to the instruction of the power down mode. The column address latch 7 includes a master / slave type latch circuit 70, a shift register circuit 71, and a multiplexer 72. When the write operation is instructed, the address signal delayed by the shift register circuit 71 is transferred to the multiplexer 72 by the multiplexer 72 in order to perform writing to the memory cell after the cycle of the clock signal CLK from the instruction of the write operation by the write command. Selected. When the read operation is instructed, the multiplexer 72 directly selects the output of the latch circuit 70. The column address counter 10 performs an increment operation in synchronization with YCLK. The burst end detection circuit 73 asserts a burst end signal BEND when the output address of the column address counter 10 reaches the number of bursts with respect to the burst start address preset in the latch circuit 70.

  A start address latch circuit 74 is provided separately from the latch circuit 70, and holds the least significant bit AY0 of the column address. The one-shot pulse generation circuit 75 generates a selection signal DICY0 corresponding to the logical value of the signal CAY0W held therein in synchronization with the clock signal DICLK.

  Here, a configuration for writing data in the control circuit 12 will be organized and described. When the write operation is instructed by the write command and the signal WTY is pulse-changed, the signal WTY is latched by the latch circuit 65A in synchronization with the clock BCLKB, and the enable signal DIE of the data input buffer 30 is asserted to a high level. . Thereafter, the write data supplied in synchronization with the data strobe signal DQS is input to the latch circuit 50 in synchronization with the signals DSCLKT and DSCLKB output from the input buffer 40, as illustrated in FIG. A timing signal DICLK for controlling the selection operation and the latch operation of the selector latch circuits 51 and 52 (see FIG. 6) for inputting the data output in parallel from the latch circuit 50 is generated by the write-related decode circuit 65B of FIG. . A column clock signal YCLK for controlling a write address of data supplied from the selector latch circuits 51 and 52 to the input / output bus 2 in synchronization with the timing signal DICLK is output from the decode logic 65C in the command decode circuit 63 in FIG. Is done. Write data is written to the column address in synchronization with the column clock signal YCLK. The end of the address count operation of the write data for the number of bursts is detected by the burst end detection circuit 73 in FIG. 10, and the burst end signal BEND is pulse-changed. This change is a state where the generation of the last write column address of the burst write is determined, and is equivalent to the end of the write operation in the column address operation. The signal BWT output from the mode state circuit 66 in FIG. 9 is negated in synchronization with this change, and the latch circuit 65A receiving this negates the enable signal DIE of the data input buffer 30. As a result, the power switch MOS transistor Mn5 (see FIG. 4) of the differential input buffer 30 is turned off and inactivated.

<< Write operation timing of DDR-SDRAM >>
FIG. 11 exemplifies the write operation timing of the burst number 4 in the DDR-SDRAM 1.

  At time t0, a row address strobe / bank active command (bank active command Active) is issued in synchronization with the clock signal CLK, and a row address signal (X-Add) is supplied. By the bank active command, the signal ACTi of the selected memory bank is pulse-changed, and the signal BAi is asserted. Although not shown, a word line corresponding to the row address signal is selected in the selected memory bank, and the storage information of the memory cell having the selected terminal connected to the word line is read out to each complementary bit line. And amplified by a sense amplifier.

  At time t1, a column address write command (Write) is issued in synchronization with the clock signal CLK, and the column address signal (Y-Add) is supplied. The signals WTY, WT, and RWWi are sequentially pulse-changed by the column address write command, and the enable control signal DIE of the differential input buffer 30 is asserted to a high level (time t2), whereby the differential input buffer 30 is deactivated. From the state to the active state.

  At this time, the data strobe signal DQS rises and falls within a tolerance of ± 0.25 Tck with respect to the rising edge of the clock signal CLK following the time t1, and is synchronized with, for example, each rise and fall of DQS. Then, write data D1, D2, D3, and D4 are supplied. Tck is the period of the clock signal.

  When the write data D1 is supplied, the differential input buffer 30 is already activated, and the sequentially supplied data D1 to D4 are synchronized with the signals DSCLKT and DSCLKB output from the input buffer 40, The signal is input to the latch circuit 50. The latch circuit 50 parallelizes and outputs D1 and D2 at time t3, and parallelizes and outputs D3 and D4 at time t4. For the data output in parallel, the selector latch circuits 51 and 52 (see FIG. 6) determine the input selection according to the logical value of the signal DICY0 in synchronization with the first change (time t2a) of the timing signal DICLK. According to the determination result, write data is supplied from the selector latch circuits 51 and 52 to the input / output bus 2 (DINBY0Bj, DINBY0Tj) in synchronization with the subsequent change of the timing signal DICLK (time t3a, t4a).

  The write operation to the memory cell with respect to the write data supplied to the input / output bus 2 is performed after the time t3a, and the column address signal CAa for writing the data D1 and D2 is applied to the column in synchronization with the column clock signal YCLK (time t3b). Output from the address counter 10. A column address signal CAa for writing data D3 and D4 is output from the column address counter 10 in synchronization with the pulse change following the column clock signal YCLK (time t4b). As a result, the data D1, D2 and D3, D4 are written into predetermined memory cells.

  The end of the address count operation of the write data for the number of bursts is detected by the burst end detection circuit 73, and the burst end signal BEND is pulse-changed at time t5. This change is a state in which the generation of the last write column address of the burst write is determined, and is equivalent to the end of the write operation in the column address operation, so that the mode state circuit 66 of FIG. Is negated, and the latch circuit 65A receiving the signal negates the enable signal DIE of the data input buffer 30. As a result, the differential input buffer 30 is deactivated.

  FIG. 12 shows the write operation timing of the SDR-SDRAM as a comparative example of FIG. The SDR-SDRAM is supplied with write data together with the column address / write command in synchronization with the clock signal CLK. For this reason, it is not enough to activate the data input buffer after the write operation is instructed by the write command. Therefore, the enable signal DIOFF of the data input buffer is asserted to the low level in synchronization with the instruction of the row address system operation (pulse change of the signal ACTi) by the bank active command, whereby the data input buffer is activated. This state is maintained until a precharge operation is instructed by a precharge command (Pre) (pulse change of signal PREi). Therefore, until writing is instructed by a write command after bank activation, until a precharge operation is instructed after the writing operation, or when only a read command is issued and no write command is issued after bank activation. Since the data input buffer does not need to operate, power is wasted because the data input buffer is kept activated during that time. If such activation control of the data input buffer is applied to the DDR-SDRAM 1 as it is, due to the SSTL interface specification of the data input buffer, much more power is wasted than in the DDR-SDRAM 1 of FIG. It is expected that

  FIG. 13 shows an operation timing chart when the present invention is applied to an address input buffer. The example of FIG. 13 is based on the assumption that the address input timing of the DDR-SDRAM of FIG. 1 is delayed from the command input by one cycle of the clock signal CLK. That is, as illustrated in FIG. 13, after the bank active command (Active), the row address strobe is set to the timing of the row address strobe with a delay of one cycle of the clock signal CLK, the row address signal (X-Add) is supplied, and the column address is supplied. After the write command (Write), the timing of the column address strobe is set to be one cycle later than the clock signal CLK, and the column address signal (Y-Add) is supplied. At this time, in synchronization with the pulse change of the signal ACTi in response to the bank active instruction, and in synchronization with the pulse change of the signal WT in response to the write operation instruction by the write command, although not shown, although not shown. In synchronization with the pulse change of the read signal in response to the read operation instruction by the column address read command, the activation control signal AIE of the address input buffer is asserted to activate the address input buffer. The deactivation of the address input buffer may be performed after waiting for the timing when the address input operation by the address input buffer is completed. For example, the address input buffer may be synchronized with a predetermined change of the column clock signal CCLKB.

  If the control for activating the address input buffer is performed after the operation is instructed, the power consumed by the SSTL specification address input buffer can be reduced.

  Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it goes without saying that the invention can be variously modified without departing from the gist thereof.

  For example, the input buffer that is activated after the operation is instructed is not limited to the data and address input buffer, but may be another control signal input buffer. Further, the input buffer of the SSTL specification is not limited to the differential input buffer described with reference to FIGS. 4 and 5, and can be appropriately changed. Further, the control logic for generating the enable control signal DIE for the data input buffer or the logic for generating the intermediate signal for generating the control logic is not limited to the above, and can be changed as appropriate. The number of data input / output terminals of the SDRAM is not limited to 16 bits, but may be 8 bits, 4 bits, or the like. Further, the number of memory banks of the SDRAM, the memory mat of the memory bank, and the configuration of the memory array are not limited to those described above, and can be appropriately changed.

  In the above description, the case where the invention made by the present inventor is mainly applied to the DDR-SDRAM, which is the field of application as the background, has been described. However, the present invention is not limited to this. The present invention can be widely applied to semiconductor devices called microcomputers, system LSIs, accelerators, and the like.

1 is a block diagram illustrating a DDR-SDRAM as an example of a semiconductor device according to the present invention. FIG. 3 is a circuit diagram illustrating a circuit configuration example of SSTL2 (class II). FIG. 3 is an explanatory diagram illustrating a signal standard in SSTL2 (class 2). FIG. 2 is a circuit diagram showing an input first-stage buffer of a data input circuit, which is a specific example of a differential input buffer conforming to SSTL. FIG. 9 is a circuit diagram showing a differential input buffer for a data strobe signal DQS as another example of the differential input buffer conforming to the SSTL. FIG. 3 is a block diagram illustrating an example of a data input circuit of the DR-SDRAM 1. FIG. 4 is an explanatory diagram schematically showing a connection mode between a selector latch circuit and a memory array of a memory bank. FIG. 3 is a block diagram mainly showing a write control system at a stage preceding a control circuit of the DDR-SDRAM. FIG. 4 is a block diagram mainly showing a write control system in a subsequent stage of a control circuit of the DDR-SDRAM. It is a block diagram which illustrates a column address input system. 4 is a timing chart illustrating a write operation timing of a burst number 4 in the DDR-SDRAM 1; 12 is a timing chart showing a write operation timing of the SDR-SDRAM as a comparative example of FIG. 5 is a timing chart illustrating an operation timing when the present invention is applied to an address input buffer.

Explanation of reference numerals

1 DDR-SDRAM
BNK0 to BNK3 Memory bank MC Memory cell WL Word line BL Bit line DIO0 to DIO3 Data input / output circuit RDEC0 to RDEC3 Row decoder CDEC0 to CDEC3 Column decoder 2 Input / output bus 3 Data input circuit 4 Data output circuit DQ0 to DQ15 Data input / output terminal A0 to A14 Address input terminal 5 Address buffer 6 Row address latch 7 Column address latch 8 Bank selector 9 Mode register 10 Column address counter 12 Control circuit CLK, CLKb Clock signal DQS Data strobe signal 30 Differential input buffer Mn5 Power switch MOS transistor VREF Reference voltage DIE enable control signal 50 Latch circuit 50A First data latch circuit 50B Second data latch circuit 50 C third data latch circuit 51, 52 selector latch circuit

Claims (7)

A first input buffer receiving a clock signal serving as a reference for data input; and a second input buffer receiving data, wherein the first input buffer and the second input buffer are activated after a write command is input. A semiconductor device characterized by being made into a semiconductor device. A data strobe terminal to which a data strobe signal is input;
A data terminal to which data is input based on the data strobe signal;
A first input buffer connected to the data strobe terminal;
A second input buffer connected to the data terminal;
A plurality of memory cells to which data input to the data terminal is written,
The first input buffer has a first differential amplifier circuit,
The second input buffer has a second differential amplifier circuit,
The semiconductor device according to claim 1, wherein the first and second differential amplifier circuits are activated when a write command instructing writing to the plurality of memory cells is input. In claim 2,
The first input buffer has a third differential amplifier circuit,
The third differential amplifier circuit outputs a complementary signal of a signal output from the first differential amplifier circuit, and is activated when a write command instructing writing to the plurality of memory cells is input. A semiconductor device, comprising: In claim 2 or 3,
The semiconductor device further includes a clock terminal to which a clock signal is input,
The second input buffer includes a first latch circuit connected to the second differential amplifier circuit, and a second latch circuit connected to the first latch circuit,
The semiconductor device according to claim 1, wherein the first latch circuit operates based on the data strobe signal, and the second latch circuit operates based on the clock signal. In any one of claims 2 to 4,
The semiconductor device further includes a plurality of memory cells into which data input from the data terminal is written, and when the write command is input, the data input continuously to the data terminal is transmitted to the plurality of memory cells. A semiconductor device capable of performing a burst operation for writing to a memory cell. In any one of claims 2 to 5,
The semiconductor device further comprises a command decode circuit for analyzing a command input from the outside. In any one of claims 2 to 6,
The first differential amplifier circuit includes a first MOS transistor having a source / drain path provided in a current path of the first differential amplifier circuit,
The second differential amplifier circuit includes a second MOS transistor having a source / drain path provided in a current path of the second differential amplifier circuit,
A control signal is input to the gates of the first and second MOS transistors,
The control signal is asserted so that the first and second MOS transistors are turned on when activating the first and second input buffers, and the control signal is activated when the first and second input buffers are activated. Wherein the first and second MOS transistors are negated so as to be turned off.

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