JP5929115B2 - Semiconductor nanodevice - Google Patents

Semiconductor nanodevice Download PDF

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JP5929115B2
JP5929115B2 JP2011251838A JP2011251838A JP5929115B2 JP 5929115 B2 JP5929115 B2 JP 5929115B2 JP 2011251838 A JP2011251838 A JP 2011251838A JP 2011251838 A JP2011251838 A JP 2011251838A JP 5929115 B2 JP5929115 B2 JP 5929115B2
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研一 河口
研一 河口
中田 義昭
義昭 中田
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本発明は、半導体ナノデバイスに関するものであり、歪を有する半導体層を従来よりも厚く積層したナノ構造体を用いた半導体ナノデバイスに関する。   The present invention relates to a semiconductor nanodevice, and relates to a semiconductor nanodevice using a nanostructure in which semiconductor layers having strains are stacked thicker than in the past.

現在、産業に用いられている半導体レーザやフォトディテクタなどの光デバイス、或いは、高電子移動度トランジスタなどの電子デバイスには、半導体基板上に異種の半導体材料の薄膜を1層以上積層した半導体多層膜構造によって形成されている。   For optical devices such as semiconductor lasers and photodetectors currently used in the industry or electronic devices such as high electron mobility transistors, a semiconductor multilayer film in which one or more thin films of different semiconductor materials are stacked on a semiconductor substrate It is formed by the structure.

この半導体多層膜は、デバイス本来の機能を発現させたり、特性を向上させたりする上で必要不可欠であり、その一つの目的に、バンドギャップの異なる材料を組み合わせることによって、半導体内のキャリア制御がある。   This semiconductor multilayer film is indispensable for expressing the original functions of the device and improving the characteristics. For one purpose, the carrier control in the semiconductor can be controlled by combining materials with different band gaps. is there.

例えば、光デバイスにおいては、バンドギャップエネルギー差の大きな材料でヘテロ構造を形成することによって、発光層からのキャリアの漏れを防ぐことができ、温度特性の良好なデバイスが形成できる。このようなヘテロ構造の組み合わせとしては、InAs/GaAsが代表的である。   For example, in an optical device, by forming a heterostructure with a material having a large band gap energy difference, leakage of carriers from the light emitting layer can be prevented, and a device with excellent temperature characteristics can be formed. A typical combination of such heterostructures is InAs / GaAs.

しかし、従来の半導体基板上の薄膜成長においては、薄膜の膜厚に制限があった。それは、基板材料と薄膜材料の格子定数の違いから生じる歪によって、ある膜厚を超えるとその歪を解放するために薄膜に転位が形成され、半導体の結晶性が著しく低下してしまうということが原因である。   However, in the conventional thin film growth on a semiconductor substrate, the thickness of the thin film is limited. The reason is that dislocations are formed in the thin film to release the strain when the film thickness exceeds a certain thickness due to the difference in lattice constant between the substrate material and the thin film material, and the crystallinity of the semiconductor is significantly reduced. Responsible.

ここで、半導体薄膜基板上の薄膜成長において生じる膜厚の制限について説明する。転位を生じないで薄膜を形成できる限界の膜厚は臨界膜厚hと呼ばれ、J.W.Matthewsらの議論(例えば、非特許文献1参照)を基に、以下のように定式化することが可能である。
=(b/2πε)×(1+ν)−1×{ln(h/b)+1}
但し、
ε:歪
b:バーガースベクトル(0.4nm)
ν:ポアッソン比(1/3)
図7は、この方程式を数値計算により解いてグラフ化した結果を示したもので、歪量が1%以上の場合においては、量子効果の無い、バルク的な層(25nm超)を積層することが不可能である。因みに、GaAs基板上のInAs層で生じる7%の歪(ε=0.07)においては、積層可能な膜厚はわずか1.6nmである。
Here, the limitation of the film thickness that occurs in the growth of the thin film on the semiconductor thin film substrate will be described. The limit film thickness at which a thin film can be formed without causing dislocation is called the critical film thickness h c . W. Based on the discussion by Matthews et al. (For example, see Non-Patent Document 1), it is possible to formulate as follows.
h c = (b / 2πε) × (1 + ν) −1 × {ln (h c / b) +1}
However,
ε: Strain b: Burgers vector (0.4 nm)
ν: Poisson's ratio (1/3)
FIG. 7 shows the result of solving this equation by numerical calculation and graphing. When the amount of strain is 1% or more, a bulk layer (over 25 nm) having no quantum effect is laminated. Is impossible. Incidentally, in the strain of 7% (ε = 0.07) generated in the InAs layer on the GaAs substrate, the stackable film thickness is only 1.6 nm.

このように、膜厚に制限があると、例えば、量子井戸構造を利用した半導体レーザの場合では、発光波長が限られてしまい、GaAs基板上に形成したInAs量子井戸レーザでは、光通信帯で利用可能な1.3μm以上の長波長発光が実現できなかった。   Thus, when the film thickness is limited, for example, in the case of a semiconductor laser using a quantum well structure, the emission wavelength is limited. In an InAs quantum well laser formed on a GaAs substrate, the optical communication band A usable long wavelength light emission of 1.3 μm or more could not be realized.

一方、Si基板等の上にInP等の格子定数の差の大きな半導体層を成長させる方法として、Au等の触媒を用いて半導体層をナノ構造体として垂直方向に成長させることが提案されている(例えば、特許文献1或いは特許文献2参照)。   On the other hand, as a method of growing a semiconductor layer having a large difference in lattice constant such as InP on a Si substrate or the like, it has been proposed to grow the semiconductor layer vertically as a nanostructure using a catalyst such as Au. (For example, refer to Patent Document 1 or Patent Document 2).

特開2009−028797号公報JP 2009-028797 A 特表2005−532181号公報JP 2005-532181 A

Journal of Crystal Growth,Vol.27,pp.118−125,1974Journal of Crystal Growth, Vol. 27, pp. 118-125, 1974

しかし、ナノ構造体を用いたデバイスにおいては、ナノ構造体の成長方向の一部を機能領域として利用するものであり、ヘテロ接合を形成する場合には、触媒を用いる関係から工程が複雑になるという問題がある。また、ナノ構造体の径は当然に小さいため、光出力や電気出力は非常に小さいものになり、用途が極めて制限されるという問題がある。   However, in a device using nanostructures, a part of the growth direction of nanostructures is used as a functional region. When forming a heterojunction, the process is complicated due to the use of a catalyst. There is a problem. Further, since the diameter of the nanostructure is naturally small, the light output and the electric output are very small, and there is a problem that the application is extremely limited.

したがって、本発明は、基板上における臨界膜厚を超えた厚さの歪のある半導体薄膜を形成してデバイス領域とすることを目的とする。   Therefore, an object of the present invention is to form a semiconductor thin film having a strain exceeding a critical film thickness on a substrate to form a device region.

開示する一観点からは、基板と、前記基板上に前記基板の成長面に対して垂直方向に延在し、長径が1μm未満の半導体ナノワイヤコアと、前記半導体ナノワイヤコアの側壁に形成され、前記半導体ナノワイヤコアの構成材料との歪εが1%以上異なる半導体材料からなり、且つ、膜厚t〔nm〕が、前記半導体ナノワイヤコアの構成材料を平坦基板とした場合に、前記平坦基板上における臨界膜厚を超えた膜厚であり、膜厚t〔nm〕と歪ε〔%〕とが、
−0.720+0.0988(ε/100) −1.2<t≦−0.705+0.227(ε/100) −1.2
の関係を満たす少なくとも一層の半導体薄膜とを有し、前記半導体ナノワイヤコアと前記半導体薄膜との接合界面或いは前記半導体薄膜同士の接合界面を発光領域或いは光吸収領域のいずれかとしたことを特徴とする半導体ナノデバイスが提供される。
From one aspect disclosed, formed on the substrate, a semiconductor nanowire core extending in a direction perpendicular to the growth surface of the substrate on the substrate and having a major axis of less than 1 μm, and a sidewall of the semiconductor nanowire core, When the semiconductor nanowire core is made of a semiconductor material having a strain ε different by 1% or more and the film thickness t [nm] is a flat substrate as the constituent material of the semiconductor nanowire core, The film thickness exceeds the critical film thickness, and the film thickness t [nm] and strain ε [%]
−0.720 + 0.0988 (ε / 100) −1.2 <t ≦ −0.705 + 0.227 (ε / 100) −1.2
And at least one semiconductor thin film satisfying the above relationship, and the junction interface between the semiconductor nanowire core and the semiconductor thin film or the junction interface between the semiconductor thin films is either a light emitting region or a light absorbing region. A semiconductor nanodevice is provided.

開示の半導体ナノデバイスによれば、基板上における臨界膜厚を超えた厚さの歪のある半導体薄膜を形成してデバイス領域とすることが可能になる。   According to the disclosed semiconductor nanodevice, a strained semiconductor thin film having a thickness exceeding the critical film thickness on the substrate can be formed to form a device region.

本発明の実施の形態の半導体ナノデバイスの構成説明図である。1 is a configuration explanatory diagram of a semiconductor nanodevice according to an embodiment of the present invention. 本発明の半導体ナノワイヤ構造を用いた場合の臨界膜厚の説明図である。It is explanatory drawing of the critical film thickness at the time of using the semiconductor nanowire structure of this invention. 本発明の実施例1の半導体レーザの途中までの製造工程の説明図である。It is explanatory drawing of the manufacturing process to the middle of the semiconductor laser of Example 1 of this invention. 本発明の実施例1の半導体レーザの図3以降の途中までの製造工程の説明図である。It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the semiconductor laser of Example 1 of this invention. 本発明の実施例1の半導体レーザの図4以降の途中までの製造工程の説明図である。It is explanatory drawing of the manufacturing process to the middle after FIG. 4 of the semiconductor laser of Example 1 of this invention. 本発明の実施例1の半導体レーザの図5以降の製造工程の説明図である。It is explanatory drawing of the manufacturing process after FIG. 5 of the semiconductor laser of Example 1 of this invention. 半導体基板上に成長させた場合の臨界膜厚の説明図である。It is explanatory drawing of the critical film thickness at the time of making it grow on a semiconductor substrate.

ここで、図1及び図2を参照して、本発明の実施の形態の半導体ナノデバイスを説明する。図1は、本発明の実施の形態の半導体ナノデバイスの構成説明図である。図1(a)に示すように、基板1上に、基板1の主面の法線方向に延在する半導体ナノワイヤコア2を設け、この半導体ナノワイヤコア2の側面に半導体薄膜3を形成し、半導体ナノワイヤコア2と半導体薄膜3との接合界面を機能領域とする。或いは、図1(b)に示すように、半導体薄膜3を多層構造で形成して、半導体薄膜3同士の接合界面を機能領域とする。この時、半導体薄膜3のトータルの膜厚は、半導体基板上における臨界膜厚を超えた厚さになるように成長する。   Here, with reference to FIG.1 and FIG.2, the semiconductor nanodevice of embodiment of this invention is demonstrated. FIG. 1 is a configuration explanatory diagram of a semiconductor nanodevice according to an embodiment of the present invention. As shown in FIG. 1A, a semiconductor nanowire core 2 extending in the normal direction of the main surface of the substrate 1 is provided on the substrate 1, and a semiconductor thin film 3 is formed on the side surface of the semiconductor nanowire core 2, A bonding interface between the semiconductor nanowire core 2 and the semiconductor thin film 3 is defined as a functional region. Alternatively, as shown in FIG. 1B, the semiconductor thin film 3 is formed in a multilayer structure, and the bonding interface between the semiconductor thin films 3 is used as a functional region. At this time, the total film thickness of the semiconductor thin film 3 grows to a thickness exceeding the critical film thickness on the semiconductor substrate.

これは、半導体薄膜2と接合界面を形成する半導体ナノワイヤコア2が、弾性変形するため、積層可能な膜厚が大幅に増大するためである。本発明における臨界膜厚hnewは、半導体ナノワイヤコア2と歪を有する半導体薄膜3の弾性変形の度合いが1:1の状態をもとに導出することができ、
new=(b/2πε)×(1+ν)−1×{ln(hnew/b)+1}
となる。
This is because the semiconductor nanowire core 2 that forms a bonding interface with the semiconductor thin film 2 is elastically deformed, so that the film thickness that can be stacked is greatly increased. The critical film thickness h new in the present invention can be derived based on a state where the degree of elastic deformation of the semiconductor nanowire core 2 and the strained semiconductor thin film 3 is 1: 1,
h new = (b / 2πε) × (1 + ν) −1 × {ln (h new / b) +1}
It becomes.

図2は、本発明の半導体ナノワイヤ構造を用いた場合の臨界膜厚の説明図である。本発明によれば、歪みが1%以上、好適には、1%〜16%の材料において、臨界膜厚を従来技術より改善しつつ量子効果も得られる薄膜(25nm以下)として機能させることが可能である。例えば、GaAsナノワイヤコアの側面にはInAs薄膜を膜厚5nmまで積層ができるようになり、従来技術の約3倍となる。また、従来技術では、薄膜が全く成長できなかったような、16%の歪においても、薄膜として機能する膜厚1.3nmの薄膜を成長することができる。このような大きな歪みの材料の組わせとして、AlPとInSb(歪み:16%)がある。   FIG. 2 is an explanatory diagram of the critical film thickness when the semiconductor nanowire structure of the present invention is used. According to the present invention, a material having a strain of 1% or more, preferably 1% to 16%, can be made to function as a thin film (25 nm or less) that can obtain a quantum effect while improving the critical film thickness from the prior art. Is possible. For example, an InAs thin film can be laminated on the side surface of a GaAs nanowire core to a film thickness of 5 nm, which is about three times that of the prior art. In addition, a thin film having a film thickness of 1.3 nm that functions as a thin film can be grown even with a strain of 16%, in which the thin film could not be grown at all by the prior art. As a combination of such large strain materials, there are AlP and InSb (strain: 16%).

従来技術で転位を生じることなく積層することが不可能であった領域で、本発明によって初めて積層が可能となる膜厚t〔nm〕の領域は、図2の曲線を、フィッティングにより近似化することにより求めることができ、歪εを〔%〕とした場合、
−0.720+0.0988(ε/100) −1.2<t≦−0.705+0.227(ε/100) −1.2
となる。
The region of the film thickness t [nm] that can be stacked for the first time according to the present invention in the region where it was impossible to stack without causing dislocation in the prior art approximates the curve of FIG. 2 by fitting. When the strain ε is [%],
−0.720 + 0.0988 (ε / 100) −1.2 <t ≦ −0.705 + 0.227 (ε / 100) −1.2
It becomes.

この場合、基板1上にAu,Cu,Ag,Pt等の触媒金属を設け、成長温度において、溶融した触媒金属中に半導体材料を取り込んで、半導体ナノワイヤコア2が垂直方向に成長していく。この時、触媒金属は常に成長を続ける半導体ナノワイヤコア2の頂面に存在する。また、半導体ナノワイヤコア2の径は触媒金属の径に依存し、ほぼ同じサイズになる。   In this case, a catalytic metal such as Au, Cu, Ag, or Pt is provided on the substrate 1, and a semiconductor material is taken into the molten catalytic metal at the growth temperature, so that the semiconductor nanowire core 2 grows in the vertical direction. At this time, the catalytic metal always exists on the top surface of the semiconductor nanowire core 2 that continues to grow. Further, the diameter of the semiconductor nanowire core 2 depends on the diameter of the catalyst metal and is almost the same size.

基板1は、Si等のIV族半導体基板やGaAs等のIII−V族半導体基板を用いるものであるが、場合によっては、サファイア等の結晶性絶縁基板を用いても良い。また、基板1と半導体ナノワイヤコア2とは、GaAs基板に対するGaAsナノワイヤコア等の様に互いに同じ材料でも良いし、或いは、Si基板に対するInPナノワイヤコア等のようにヘテロ接合を形成する材料の組み合わせでも良い。   The substrate 1 is a group IV semiconductor substrate such as Si or a group III-V semiconductor substrate such as GaAs, but a crystalline insulating substrate such as sapphire may be used depending on circumstances. The substrate 1 and the semiconductor nanowire core 2 may be the same material as each other, such as a GaAs nanowire core for a GaAs substrate, or a combination of materials that form a heterojunction such as an InP nanowire core for a Si substrate. good.

半導体ナノワイヤコア2の成長方向に垂直な断面形状は、三角形、四角形、六角形或いは円形になり、その長径は、1μm未満、より好適には、10nm〜400nm、特に金属微粒子を用いた形成法においては、50nm〜200nmが好ましい。長さは、長径の3倍以上が好適であり、1μm〜10μm、より好適には2μm〜5μmとする。   The cross-sectional shape perpendicular to the growth direction of the semiconductor nanowire core 2 is a triangle, a quadrangle, a hexagon, or a circle, and its major axis is less than 1 μm, more preferably 10 nm to 400 nm, particularly in a forming method using metal fine particles. Is preferably 50 nm to 200 nm. The length is preferably 3 times or more the major axis, and is 1 μm to 10 μm, more preferably 2 μm to 5 μm.

なお、半導体ナノワイヤコア2の成長方向に垂直な断面形状は、基板1の主面の面方位が(111)面の場合に、三角形や六角形になりやすく、(001)面の場合に、四角形になりやすく、円形は成長途中で現れやすい。   The cross-sectional shape perpendicular to the growth direction of the semiconductor nanowire core 2 is likely to be a triangle or a hexagon when the plane orientation of the main surface of the substrate 1 is the (111) plane, and is quadrilateral when the plane is the (001) plane. The circle tends to appear during growth.

また、基板1の面方位が(001)面の場合には、半導体ナノワイヤコア2及び半導体薄膜3の結晶構造は閃亜鉛鉱型結晶構造になり、(111)面の場合には、ウルツ鉱型結晶構造になりやすい。   When the plane orientation of the substrate 1 is the (001) plane, the crystal structure of the semiconductor nanowire core 2 and the semiconductor thin film 3 is a zinc blende type crystal structure. When the plane orientation is the (111) plane, the wurtzite type is used. It tends to have a crystal structure.

このように、本発明の実施の形態においては、従来技術では不可能であった厚さの歪層を有する構造体およびデバイスを形成することが可能となり、接合界面を機能領域とすることによって、半導体内のキャリア制御が可能となる。これによって、上述の特許文献1或いは特許文献2の従来のナノデバイスに比べて出力が大きく温度特性が良好な長波長のレーザを実現することができる。因みに、半導体ナノワイヤコア2をGaAsとし、半導体薄膜3をGaAs/InAs量子井戸とした場合には、1.3μmより長波長で発振する半導体レーザを実現することができる。 As described above, in the embodiment of the present invention, it is possible to form a structure and a device having a strained layer having a thickness that was impossible with the prior art, and by using the bonding interface as a functional region, Carrier control in the semiconductor becomes possible. As a result, it is possible to realize a long-wavelength laser that has a larger output and better temperature characteristics than the conventional nanodevice of Patent Document 1 or Patent Document 2 described above. Incidentally, when the semiconductor nanowire core 2 is made of GaAs and the semiconductor thin film 3 is made of a GaAs / InAs quantum well, a semiconductor laser that oscillates at a wavelength longer than 1.3 μm can be realized.

次に、図3乃至図6を参照して、本発明の実施例1の半導体レーザの製造工程を説明する。まず、図3(a)に示すように、(111)面を主面とし、不純物濃度が5×1017cm−3〜1×1019cm−3のn型GaAs基板11上に、SiO膜12を形成し、開口部13を形成し、この開口部13内に金微粒子14を設ける。成長触媒となる金微粒子14は、市販のコロイド粒子を用いても良いし、或いは、リソグラフィによって形成した小面積の金薄膜を加熱することによって粒子化しても良い。 Next, with reference to FIGS. 3 to 6, the manufacturing process of the semiconductor laser of Example 1 of the present invention will be described. First, as shown in FIG. 3A, SiO 2 is formed on an n-type GaAs substrate 11 having a (111) plane as a main surface and an impurity concentration of 5 × 10 17 cm −3 to 1 × 10 19 cm −3. A film 12 is formed, an opening 13 is formed, and gold fine particles 14 are provided in the opening 13. The gold fine particles 14 serving as the growth catalyst may be commercially available colloidal particles, or may be formed into particles by heating a small-area gold thin film formed by lithography.

次いで、図3(b)に示すように、MOVPE法によって、トリメチルガリウム(TMG)とアルシン(AsH)とドーパントとしてのジシラン(Si)を供給することにより、n型GaAsナノワイヤ15を成長温度300℃〜500℃で成長する。この場合のn型GaAsナノワイヤ15の不純物濃度は、5×1017cm−3〜1×1019cm−3とする。 Next, as shown in FIG. 3B, trimethylgallium (TMG), arsine (AsH 3 ), and disilane (Si 2 H 6 ) as a dopant are supplied by the MOVPE method to form the n-type GaAs nanowire 15. It grows at a growth temperature of 300 ° C to 500 ° C. In this case, the n-type GaAs nanowire 15 has an impurity concentration of 5 × 10 17 cm −3 to 1 × 10 19 cm −3 .

次いで、図3(c)に示すように、金微粒子14を除去した後、ノンドープのGaAs/InAs量子井戸構造16を形成する。InAs井戸層18は、単層でも多層であっても良く、多層の場合は、InAs井戸層18の合計の膜厚が本発明の臨界膜厚hnew以下、すなわち5nm以下であれば良い。なお、図においては、3層のGaAsバリア層17と2層のInAs井戸層18を示している。InAs井戸層18を成長させる場合には、同じくMOVPE法により、トリメチルインジウム(TMI)とAsHを供給することにより、成長温度300℃〜500℃で成長させる。 Next, as shown in FIG. 3C, after removing the gold fine particles 14, a non-doped GaAs / InAs quantum well structure 16 is formed. The InAs well layer 18 may be a single layer or multiple layers. In the case of multiple layers, the total film thickness of the InAs well layers 18 may be equal to or less than the critical thickness h new of the present invention, that is, 5 nm or less. In the drawing, three GaAs barrier layers 17 and two InAs well layers 18 are shown. When the InAs well layer 18 is grown, it is grown at a growth temperature of 300 ° C. to 500 ° C. by supplying trimethylindium (TMI) and AsH 3 by the MOVPE method.

引き続いて、図4(d)に示すように、MOVPE原料としては、TMG、AsH、Al原料としてトリメチルアルミニウム(TMAl)、ドーパント源としてジエチル亜鉛(DEZ)を供給して、p型AlGaAs層19を成長させる。なお、p型AlGaAs層19の不純物濃度は、5×1017cm−3〜1×1019cm−3とし、膜厚は、50nm〜300nmとする。なお、良好な導電性を得るために、p型AlGaAs層19のAl組成は、0.1〜0.3が好ましい。 Subsequently, as shown in FIG. 4D, as the MOVPE raw material, TMG, AsH 3 , trimethylaluminum (TMAl) as the Al raw material, and diethylzinc (DEZ) as the dopant source are supplied, and the p-type AlGaAs layer 19 is supplied. Grow. The impurity concentration of the p-type AlGaAs layer 19 is 5 × 10 17 cm −3 to 1 × 10 19 cm −3 and the film thickness is 50 nm to 300 nm. In order to obtain good conductivity, the Al composition of the p-type AlGaAs layer 19 is preferably 0.1 to 0.3.

引き続いて、TMG、AsH、DEZを供給して、厚さが1nm〜10nmのp型GaAsコンタクト層20を成長させる。この場合、AlGaAs及びGaAsはn型GaAs基板11と格子整合しているので、成長膜厚に制限はない。なお、n型GaAsナノワイヤ15の頂面にも半導体薄膜が成長するが、側壁に成長する半導体薄膜よりかなり薄く且つ途中の工程でエッチング等により除去するので問題はない。 Subsequently, TMG, AsH 3 and DEZ are supplied to grow a p-type GaAs contact layer 20 having a thickness of 1 nm to 10 nm. In this case, since AlGaAs and GaAs are lattice-matched with the n-type GaAs substrate 11, there is no limitation on the growth film thickness. Although a semiconductor thin film grows also on the top surface of the n-type GaAs nanowire 15, there is no problem because it is much thinner than the semiconductor thin film grown on the side wall and is removed by etching or the like in the middle of the process.

次いで、図4(e)に示すように、SiO膜12に開口部を形成し、AuGe/Auを堆積させてn側電極21を形成する。次いで、図4(f)に示すように、全面に厚さが100nmのSiO膜22を堆積する。次いで、図5(g)に示すように、全面にフォトレジスト23を塗布する。 Next, as shown in FIG. 4E, an opening is formed in the SiO 2 film 12, and AuGe / Au is deposited to form the n-side electrode 21. Next, as shown in FIG. 4F, a SiO 2 film 22 having a thickness of 100 nm is deposited on the entire surface. Next, as shown in FIG. 5G, a photoresist 23 is applied to the entire surface.

次いで、図5(h)に示すように、フォトレジスト23を露光したのち、現像することによって、ナノワイヤ構造より大径の開口部25を有するレジストマスク24を形成する。次いで、図5(i)に示すように、レジストマスク24をマスクとしてフッ酸系エッチング液によりナノワイヤ構造の側面及び頂面のSiO膜22を除去する。 Next, as shown in FIG. 5H, the photoresist 23 is exposed and then developed to form a resist mask 24 having an opening 25 having a diameter larger than that of the nanowire structure. Next, as shown in FIG. 5I, the SiO 2 film 22 on the side and top surfaces of the nanowire structure is removed with a hydrofluoric acid-based etchant using the resist mask 24 as a mask.

次いで、図6(j)に示すように、全面にAuZn/Au膜を堆積させた後、頂面に堆積したAuGe/Au膜を選択的に除去することによって、p側電極26を形成する。次いで、図6(k)に示すように、閾値電流を低減するために、上下に、誘電体多層膜27,28を形成する。なお、両方の誘電体多層膜27,28を反射膜としても良いし、一方の誘電体多層膜27を反射防止膜としても良い。最後に、p側電極26の一部及びSiO2膜22の一部を除去してコンタクトホール29を形成することによって本発明の実施例1の半導体レーザの基本構造が完成する。   Next, as shown in FIG. 6J, after depositing an AuZn / Au film on the entire surface, the AuGe / Au film deposited on the top surface is selectively removed to form the p-side electrode 26. Next, as shown in FIG. 6 (k), dielectric multilayer films 27 and 28 are formed on the upper and lower sides in order to reduce the threshold current. Both of the dielectric multilayer films 27 and 28 may be reflective films, and one of the dielectric multilayer films 27 may be an antireflection film. Finally, by removing a part of the p-side electrode 26 and a part of the SiO 2 film 22 to form a contact hole 29, the basic structure of the semiconductor laser of Example 1 of the present invention is completed.

このように、本発明の実施例1においては、半導体ナノワイヤを用いているので、GaAsに対して歪の大きなInAsを従来より厚く成長させることができ、1.3μm以上の長波長帯での発振が可能になる。 As described above, in Example 1 of the present invention, since semiconductor nanowires are used, InAs having a large strain relative to GaAs can be grown thicker than before, and oscillation in a long wavelength band of 1.3 μm or more is possible. Is possible.

ここで、実施例1を含む本発明の実施の形態に関して、以下の付記を付す。
(付記1)
基板と、
前記基板上に前記基板の成長面に対して垂直方向に延在し、長径が1μm未満の半導体ナノワイヤコアと、
前記半導体ナノワイヤコアの側壁に形成され、前記半導体ナノワイヤコアの構成材料との歪εが1%以上異なる半導体材料からなり、且つ、膜厚t〔nm〕が、前記半導体ナノワイヤコアの構成材料を平坦基板とした場合に、前記平坦基板上における臨界膜厚を超えた膜厚であり、膜厚t〔nm〕と歪ε〔%〕とが、
−0.720+0.0988(ε/100) −1.2<t≦−0.705+0.227(ε/100) −1.2
の関係を満たす少なくとも一層の半導体薄膜とを有し、前記半導体ナノワイヤコアと前記半導体薄膜との接合界面或いは前記半導体薄膜同士の接合界面を発光領域或いは光吸収領域のいずれかとしたことを特徴とする半導体ナノデバイス。
(付記2)
前記半導体ナノワイヤコアと前記半導体薄膜とは、互いにバンドギャップエネルギーが異なる半導体材料からなることを特徴とする付記1に記載の半導体ナノデバイス。
(付記3)
前記半導体ナノワイヤコアが、前記基板と異なった材料からなることを特徴とする付記1または付記2に記載の半導体ナノデバイス。
(付記4)
前記半導体ナノワイヤコア及び前記半導体薄膜が、閃亜鉛鉱型結晶構造或いはウルツ鉱型結晶構造のいずれかであることを特徴とする付記1乃至付記3のいずれか1に記載の半導体ナノデバイス。
(付記
前記基板が半導体基板であり、前記半導体基板と前記半導体ナノワイヤコアとが第1の導電型であり、且つ、前記半導体薄膜の少なくとも最外層が前記第1の導電型と反対の導電型であることを特徴とする付記に記載の半導体ナノデバイス。
(付記
前記半導体ナノワイヤコアがAlGa1−xAs(但し、xは0を含む)からなり、且つ、前記半導体薄膜が、GaAs/InAsからなる量子井戸構造膜からなり、前記量子井戸構造膜における発光波長が1.3μm以上の長波長であることを特徴とする付記に記載の半導体ナノデバイス。
Here, the following supplementary notes are attached to the embodiment of the present invention including the first embodiment.
(Appendix 1)
A substrate,
A semiconductor nanowire core extending on the substrate in a direction perpendicular to a growth surface of the substrate and having a major axis of less than 1 μm;
The semiconductor nanowire core is made of a semiconductor material having a strain ε different by 1% or more from the constituent material of the semiconductor nanowire core, and the thickness t [nm] is flattened of the constituent material of the semiconductor nanowire core. In the case of a substrate, it is a film thickness exceeding the critical film thickness on the flat substrate, and the film thickness t [nm] and the strain ε [%]
−0.720 + 0.0988 (ε / 100) −1.2 <t ≦ −0.705 + 0.227 (ε / 100) −1.2
And at least one semiconductor thin film satisfying the above relationship, and the junction interface between the semiconductor nanowire core and the semiconductor thin film or the junction interface between the semiconductor thin films is either a light emitting region or a light absorbing region. Semiconductor nanodevices.
(Appendix 2)
The semiconductor nanodevice according to appendix 1, wherein the semiconductor nanowire core and the semiconductor thin film are made of semiconductor materials having different band gap energies.
(Appendix 3)
The semiconductor nanodevice according to appendix 1 or appendix 2, wherein the semiconductor nanowire core is made of a material different from that of the substrate.
(Appendix 4)
The semiconductor nanodevice according to any one of appendix 1 to appendix 3, wherein the semiconductor nanowire core and the semiconductor thin film have either a zinc blende crystal structure or a wurtzite crystal structure.
(Appendix 5 )
The substrate is a semiconductor substrate, the semiconductor substrate and the semiconductor nanowire core are of a first conductivity type, and at least the outermost layer of the semiconductor thin film is of a conductivity type opposite to the first conductivity type. The semiconductor nanodevice according to appendix 4 , characterized by:
(Appendix 6 )
The semiconductor nanowire core is made of Al x Ga 1-x As (where x includes 0), the semiconductor thin film is made of a quantum well structure film made of GaAs / InAs, and light emission in the quantum well structure film 6. The semiconductor nanodevice according to appendix 5 , wherein the wavelength is a long wavelength of 1.3 μm or more.

1 基板
2 半導体ナノワイヤコア
3 半導体薄膜
11 n型GaAs基板
12 SiO
13 開口部
14 金微粒子
15 n型GaAsナノワイヤ
16 GaAs/InAs量子井戸構造
17 GaAsバリア層
18 InAs井戸層
19 p型AlGaAs層
20 p型GaAsコンタクト層
21 n側電極
22 SiO
23 フォトレジスト
24 レジストマスク
25 開口部
26 p側電極
27,28 誘電体多層膜
29 コンタクトホール
DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor nanowire core 3 Semiconductor thin film 11 n-type GaAs substrate 12 SiO 2 film 13 Opening 14 Gold fine particle 15 n-type GaAs nanowire 16 GaAs / InAs quantum well structure 17 GaAs barrier layer 18 InAs well layer 19 p-type AlGaAs layer 20 p-type GaAs contact layer 21 n-side electrode 22 SiO 2 film 23 photoresist 24 resist mask 25 opening 26 p-side electrodes 27 and 28 dielectric multilayer film 29 contact hole

Claims (3)

基板と、
前記基板上に前記基板の成長面に対して垂直方向に延在し、長径が1μm未満の半導体ナノワイヤコアと、
前記半導体ナノワイヤコアの側壁に形成され、前記半導体ナノワイヤコアの構成材料との歪εが1%以上異なる半導体材料からなり、且つ、膜厚t〔nm〕が、前記半導体ナノワイヤコアの構成材料を平坦基板とした場合に、前記平坦基板上における臨界膜厚を超えた膜厚であり、膜厚t〔nm〕と歪ε〔%〕とが、
−0.720+0.0988(ε/100) −1.2<t≦−0.705+0.227(ε/100) −1.2
の関係を満たす少なくとも一層の半導体薄膜とを有し、
前記半導体ナノワイヤコアと前記半導体薄膜との接合界面或いは前記半導体薄膜同士の接合界面を発光領域或いは光吸収領域のいずれかとしたことを特徴とする半導体ナノデバイス。
A substrate,
A semiconductor nanowire core extending on the substrate in a direction perpendicular to a growth surface of the substrate and having a major axis of less than 1 μm;
The semiconductor nanowire core is made of a semiconductor material having a strain ε different by 1% or more from the constituent material of the semiconductor nanowire core, and the thickness t [nm] is flattened of the constituent material of the semiconductor nanowire core. In the case of a substrate, it is a film thickness exceeding the critical film thickness on the flat substrate, and the film thickness t [nm] and the strain ε [%]
−0.720 + 0.0988 (ε / 100) −1.2 <t ≦ −0.705 + 0.227 (ε / 100) −1.2
And at least one semiconductor thin film satisfying the relationship
A semiconductor nanodevice, wherein a bonding interface between the semiconductor nanowire core and the semiconductor thin film or a bonding interface between the semiconductor thin films is set to either a light emitting region or a light absorbing region .
前記半導体ナノワイヤコアが、前記基板と異なった材料からなることを特徴とする請求項1に記載の半導体ナノデバイス。   The semiconductor nanodevice according to claim 1, wherein the semiconductor nanowire core is made of a material different from that of the substrate. 前記半導体ナノワイヤコア及び前記半導体薄膜が、閃亜鉛鉱型結晶構造或いはウルツ鉱型結晶構造のいずれかであることを特徴とする請求項1または請求項2に記載の半導体ナノデバイス。   The semiconductor nanodevice according to claim 1, wherein the semiconductor nanowire core and the semiconductor thin film have either a zinc blende crystal structure or a wurtzite crystal structure.
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