WO2004111319A2 - Sacrificial template method of fabricating a nanotube - Google Patents
Sacrificial template method of fabricating a nanotube Download PDFInfo
- Publication number
- WO2004111319A2 WO2004111319A2 PCT/US2003/039200 US0339200W WO2004111319A2 WO 2004111319 A2 WO2004111319 A2 WO 2004111319A2 US 0339200 W US0339200 W US 0339200W WO 2004111319 A2 WO2004111319 A2 WO 2004111319A2
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- WIPO (PCT)
- Prior art keywords
- nanowire
- recited
- nanotube
- sheath
- nanotubes
- Prior art date
Links
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- 238000000034 method Methods 0.000 claims abstract description 89
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- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
- B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
- C30B29/602—Nanotubes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/16—Oxides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/109—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN heterojunction type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention pertains generally to fabricating nanotubes, and more particularly to a method of fabricating a nanotube over a sacrificial nanowire template.
- tubular nanostructures generally requires a layered or anisotropic crystal structure (see Tenne, R. & Zettl, A. K., Nanotubes from inorganic materials, Top. Appl. Phys. 80, 81-112 (2001); Tenne, R., Inorganic nanoclusters with fluorine-like structure and nanotubes, Prig. Inure. Chem. 50, 269-315 (2001 ); Partake, G.
- nanotubes produced by the above methods are either amorphous, polycrystalline, or they exist only in ultra-high vacuum environments.
- the significance of hollow inorganic nanotubes is being recognized and they have wide applicability in bioanalysis and catalysis (see Lee, S. B.;
- silica nanotubes are of special interest because of their hydrophilic nature, colloidal suspension formation, and surface functionalization accessibility for both inner and outer walls.
- modified silica nanotubes and nanotube membranes for example have applicability for bioseparation and biocatalysis (see Mitchell, D. T.; Lee, S. B.; Trofin, L.; Li, N. C; Nevanen, T. K.; Soderlund, H.; Martin, C. R. J. Am. Chem. Soc.
- Silica nanotubes have been synthesized typically within the pores of porous alumina membrane templates using the sol-gel coating technique (see Martin, C. R. Chem. Mater. 1996, 8, 1739, incorporated herein by reference).
- Alumina templates can be dissolved to liberate single silica nanotubes. These nanotubes prepared at low temperature have porous walls and are relatively fragile. Once the templates are removed, the silica nanotubes will generally bundle up and become less oriented. The same applies to the silica nanotubes prepared at low temperature using other templates (see Obare, S. O.; Jana, N. R.; Murphy, C. J. Nano Lett. 2001 , 1 , 601 ; Jung, J. H.; Shinkai, S.; Shimizu, T. Nano Lett. 2002, 2, 17; Yin, Y. D.; Lu, Y.; Sun, Y. G.; Xia, Y. N.
- the present invention comprises single and multiple layer nanotube structures and methods of fabrication.
- the interface between cylindrical layers of the nanotubes in the structure may form insulated or non-insulated device junctions, or provide other material properties.
- longitudinal portions (segments) of the nanotube may be processed differently to yield longitudinal junctions along a given nanotube.
- a key aspect of the present invention is that the nanotubes and composite structures are formed over a sacrificial template which is preferably a nanowire core.
- the general fabrication process of the present invention involves creating a core (nanotube template), over which a sheath is formed. Numerous methods may be utilized for creating both the core and forming one or more sheaths. It will be appreciated that the core and sheath sections may be formed from a variety of materials.
- the core for example, may be selected from material comprising ZnO,
- the sheath may be selected from the materials consisting of gallium nitride (GaN), silicon oxide (Si0 2 ), group II - VI materials, group III - V materials, elemental group IV (i.e. Si, Ge), metals, oxides of the above materials, and polymers. It should also be appreciated that the sheath material may be doped as desired (i.e. during formation) to alter the characteristics of the base material.
- the invention generally comprises a method for fabricating a nanotube, comprising (a) forming a nanowire template; (b) depositing a sheath over the nanowire template; and (c) removing the nanowire template.
- a method for fabricating a nanotube comprising (a) forming a nanowire template; (b) depositing a sheath over the nanowire template; and (c) removing the nanowire template.
- Two embodiments of the method will now be described, one for forming GaN nanotubes over a zinc oxide nanowire template, and one for Si0 2 nanotubes over a Si nanowire template.
- nanotubes according to the present invention may be formed utilizing a casting process, an etching process, or combinations thereof.
- an epitaxial casting process will be described first for producing GaN nanotubes.
- nanotube fabrication process an "epitaxial casting" approach is utilized for the synthesis of single-crystalline nanotubes, such as technologically important gallium (III) nitride (GaN) nanotubes with inner diameters of approximately 30 nm to 200 nm and wall thicknesses of approximately 5 nm to 50 nm.
- Nanowires such as within a nanowire array, were used as templates for the epitaxial overgrowth of thin GaN layers in a chemical vapor deposition system.
- the nanowire templates can be fabricated from hexagonal zinc (II) oxide (ZnO) material over which the GaN nanotube is grown.
- the template material is subsequently removed, preferably by a simple thermal reduction and evaporation step, resulting in ordered arrays of GaN nanotubes on the substrates.
- Arrays of the ZnO nanowires were grown on substrates, such as sapphire wafers, using a vapor deposition process.
- substrates such as sapphire wafers
- the same approach to synthesizing nanotubes detailed herein may operate for the majority of group III nitrides.
- nanotubes are formed of silicon oxide (Si0 2 ) in an oxidation process and the nanowire cores removed in an etching process.
- the nanotube cores are created from silicon (Si) nanowires, with a cap (i.e. Au), such as fabricated using thermal oxidation and etching.
- the process comprises thermal oxidation of the Si nanowire arrays which results in arrays of thin Si nanowires sheathed by a thick layer of silicon oxide (Si0 2 ).
- This oxidized nanowire array is then selectively etched, such as with xenon fluorine (XeF 2 ) to remove the silicon nanowire cores, leaving an array of ordered silicon dioxide nanotubes with controllable inner diameters.
- the inner diameters are controlled by the initial diameters of the silicon nanowires and the thermal oxidation process.
- the inner tube diameter of the nanotubes may be controlled in the range of from approximately 10 nm to 200 nm. It is contemplated that, with further refinements of the oxidation and etching process, nanotubes having an inside diameter of less than 5 nm can be produced in this manner. [0022] A number of aspects of the invention are addressed herein, including but not limited to the following. [0023] An aspect of the invention is the formation of nanotube structures. [0024] An aspect of the invention is the formation of single-crystalline nanotube structures. [0025] Another aspect of the invention is forming nanotubes of gallium nitride
- silica nanotubes Si0 2
- a nanowire to utilize as a template for forming the nanotube.
- a zinc oxide (ZnO) nanowire as a template for forming the nanotube.
- a silicon (Si) nanowire as a template for forming the nanotube.
- Another aspect of the invention is utilizing an epitaxial casting process to form a sheath of over the nanowire, such as GaN over a ZnO nanowire.
- Another aspect of the invention is utilizing an oxidation and etching process to form a sheath of material over the nanowire, such as Si0 2 over a Si nanowire.
- Another aspect of the invention is the formation of multiple sheath layers over a sacrificial template (core).
- Another aspect of the invention is the formation of multiple sheath layers over a sacrificial core.
- Another aspect of the invention is the formation of sheath layers in longitudinal segments along the length of a sacrificial core.
- a still further aspect of the invention are methods for forming single- crystalline nanotubes which may be utilized in electronic devices, nanofluidic devices, or combinations thereof.
- FIG. 1A-1C are cross section views of the epitaxial casting process for fabricating nanotubes according to an embodiment of the present invention, showing GaN nanotubes formed over ZnO nanowires.
- FIG. 2A is an image of a nanowire template array according to an aspect of the present invention fabricated from ZnO, showing in an inset the cross-sections of the nanowire array.
- FIG. 2B is an image of a nanotube array formed over the sacrificial nanowire array of FIG. 2A according to an aspect of the present invention fabricated from GaN, shown in an inset is the fractured interface between the GaN nanotubes and the substrates.
- FIG. 3 is a plot of diffraction of the GaN nanotube array of FIG. 2B according to an aspect of the present invention, showing nanotube composition.
- FIG. 4A-4C are images of the nanotubes of FIG. 2B according to an aspect of the present invention, showing the relative uniformity in diameter and wall thickness.
- FIG. 4D is a high resolution image of the exterior wall structure in a
- FIG. 4E is a high resolution image of the interior wall structure in a GaN nanotube of FIG. 2B according to an aspect of the present invention, shown
- FIG. 5 is a plot of nanotube composition across the nanotube profile according to an aspect of the present invention, as probed by energy dispersive X-ray spectroscopy.
- FIG. 6 is an image of nanotubes formed according to an embodiment of the present invention and shown end-on.
- FIG. 7 is an image of a single-crystalline GaN nanotube fabricated according to an embodiment of the present invention and showing its smooth features.
- FIG. 8 is a plot of the electron energy loss spectrum collected on the GaN nanotube of FIG. 7.
- FIG. 9A is an image of an array of nanotubes fabricated according to an embodiment of the present invention, and shown with the nanowire template partially removed.
- FIG. 9B is an image of a nanotube fabricated according to an embodiment of the present invention with nanowire template partially removed, showing insets of electron diffraction patterns recorded on the core-
- FIG. 10 is a plot of line profiles for the core-sheath of a nanotube at the upper arrow position in FIG. 9B, and showing Ga and Zn signals.
- FIG. 11 is a plot of line profiles for the core-sheath of a nanotube at the lower arrow position in FIG. 9B, and showing Ga and Zn signals.
- FIG. 12 is a plot of photoluminescence spectra collected on a GaN nanotube according to an aspect of the present invention, showing spectra from both a thin-walled and thick-walled nanotube. [0054] FIG.
- FIG. 13 is a plot of temperature dependence curves of a single GaN nanotube according to an aspect of the present invention.
- FIG. 14A-14G are steps in forming Si0 2 nanotubes according to an embodiment of the present invention, shown with parylene deposition stages during etching.
- FIG. 15A-15D are images of silicon nanotube array formation according to aspects of the present invention, shown including detail views on insets of FIG. 15B-15D.
- FIG. 16A-16B are images of silica nanotubes according to aspects of the present invention.
- FIG. 14A-14G are steps in forming Si0 2 nanotubes according to an embodiment of the present invention, shown with parylene deposition stages during etching.
- FIG. 15A-15D are images of silicon nanotube array formation according to aspects of the present invention, shown including detail views on insets of FIG. 15B-15D.
- FIG. 16A-16B are images of silica nanotubes according to aspects of the present invention.
- FIG. 17 is a cross-section of a multilayer nanotube according to an aspect of the present invention and shown with a gallium nitride sheath sandwiched between insulating aluminum nitride layers.
- FIG. 18 is a cross-section of a multilayer nanotube according to an aspect of the present invention and shown with a P-doped sheath over an N- doped sheath which surrounds the sacrificial core.
- FIG. 19 is a cross-section of a multilayer nanotube according to an aspect of the present invention and shown with an N-doped sheath over a P- doped sheath which surrounds the sacrificial core.
- FIG. 20 is a perspective view of a sacrificial core covered with a solid sheath and having two longitudinal nanotube segments according to an aspect of the present invention.
- FIG. 21 is a perspective view of a sacrificial core covered with multiple sheaths and having multiple longitudinal nanotube segments according to an aspect of the present invention.
- FIG. 22 is a cross-section of fabricating a nanotubular device according to an aspect of the present invention, shown comprising a hollow core NPN transistor.
- a nanotube is formed by creating at least one sheath layer around a nanowire template.
- the nanowire template functions as a sacrificial core which is later removed to establish the central opening through the nanotube. Once the sacrificial core is removed, the nanotube can be used in any conventional manner.
- two embodiments of a method of fabricating nanotubes using a sacrificial core in accordance with the present invention will be described. It will be appreciated, however, that the invention contemplates any method in which a sacrificial core is used as a template for nanotube fabrication.
- a layer of material such as gallium nitride (GaN) is epitaxially grown on the exterior of a nanowire core, such as zinc oxide (ZnO), followed by removal of the nanowire core.
- a nanowire core such as silicon (Si) is oxidized to form an Si0 2 sheath layer, and then the nanowire core is removed to leave the oxide sheath.
- FIG. 1A through FIG. 1C illustrate the general steps in what we refer to as an "epitaxial casting" approach.
- FIG. 1A depicts a substrate 10 upon which a nanowire 12 is being formed, preferably a single-crystalline nanowire.
- FIG. 1 B depicts depositing a preferably single-crystalline sheath 14 over nanowire
- FIG. 1C depicts removing the nanowire template (core) 12 thereby forming a nanotube 14'.
- the template 12 (FIG. 1A) is subsequently removed, such as by thermal processes, leaving a GaN nanotube 14'.
- two possible mechanisms for the removal of ZnO templates can be employed.
- ZnO is chemically etched by ammonia (NH 3 ) at high temperature (see Hamdani F. et al., Effect of buffer layer and substrate surface polarity on the growth by molecular beam epitaxy of GaN on ZnO,
- the nanowire cores employed in the present invention can be formed in any conventional manner. For example, arrays of zinc oxide (ZnO) nanowires were grown on a substrate material, such as (110) sapphire wafers, preferably using a vapor deposition process (see Huang M. et al., Room- temperature ultraviolet nanowire nanolasers, Science, 292, 1897-99 (2001), incorporated herein by reference). These ZnO nanowire arrays were placed inside a reaction tube (i.e.
- FIG. 2A shows a scanning electron microscopy (SEM) image of the starting ZnO nanowire array templates, which were found to have uniform lengths, such as in the range of from 2-5 ⁇ m, and each having a uniform diameter with diameters within the array of nanowires ranging from 30-200 nm.
- the nanowires are well-facetted as seen in the inset of FIG. 2A with hexagonal cross-sections, exhibiting ⁇ 110 ⁇ planes on the sides. After the GaN deposition and template removal to form the nanotubes, the color of the sample had shifted from white to yellowish or darker.
- FIG. 2B is an example image illustrating that the morphology of the initial nanowire arrays was maintained in the nanotubes, except for the increase in the diameters of the resulting nanostructures.
- the nanostructures appear less facetted compared with the original ZnO nanowire templates. Compositional analysis on the final product shows only a relatively minor Zn signal.
- FIG. 3 illustrates the result of X-ray diffraction (XRD) on the sample which shows only (001) diffraction peaks of the wurtzite GaN structure indicative of excellent epitaxy/texturing for the GaN coating.
- FIG. 4A through FIG. 4C depict images of dispersing the GaN nanotubes sample in FIG.
- TEM transmission electron microscopy
- FIG. 5 illustrates compositional line profile probed by energy dispersive
- FIG. 6 is a transmission electron microscopy image of an end-on view of several GaN nanotubes.
- the inner cross-section of the tubes is pseudo-hexagonal
- nanotubes are connected at their base with a porous GaN layer, which is believed to be the primary pathway for the escape of zinc and oxygen species during thermal/chemical etching.
- FIG. 7 is a transmission electron microscopy image of a single- crystalline GaN nanotube showing its very smooth internal and external surface.
- FIG. 8 is a plot of nitrogen K-edge electron energy loss spectrum collected on the GaN nanotube of FIG. 7.
- FIG. 9A, 9B and FIG. 10, FIG. 11 illustrate details of removing the nanowire template within the single-crystalline nanotube.
- the "epitaxial casting" mechanism described by the invention has been confirmed with TEM studies.
- arrays of GaN nanotubes are shown with their ZnO nanowire templates partially removed. It should be noted that at the bottom of these nanotubes a thin layer of porous GaN film exists.
- FIG. 9B a detailed view of a nanotube with a partially removed template is shown at the boundary between the filled (upper arrow) and empty portions (lower arrow) of the nanotube. Electron diffraction shown on the insets of FIG. 9B for the filled and unfilled portions of the nanotube depict an identical set of diffraction patterns for both the tube and the core-sheath region, indicating the wurtzite GaN growth is epitaxial.
- the core-sheath nanostructure can be considered as a seamless single domain of a wurtzite GaN/ZnO structure type. Furthermore, comparison of EDX line profiles across the GaN nanotube (aligned at lower arrow) shown in FIG. 11 and the ZnO-GaN core-sheath structure, aligned at the upper arrow, and shown in FIG. 10 unambiguously support the growth mechanism of GaN nanotubes on the ZnO nanowire templates. Once the ZnO nanocylinder is removed, single-crystalline tubes of GaN result. The formation of these single-crystalline GaN nanotubes as taught herein accords a number of benefits over the use of polycrystalline nanotubes (see Li, J. Y. et al.
- the electrical and optical characteristics of these single- crystalline GaN nanotubes are comparable to those of high-quality GaN epilayers grown on ZnO substrates (see Hamdani F. et al., Microstructure and optical properties of epitaxial GaN on ZnO (0001) grown by reactive molecular beam epitaxy, J. Appl. Phys. 83, 983-990 (1998), incorporated herein by reference) as well as those of GaN nanowires (see Huang, Y., Duan, X., Cui, Y. & Lieber, C. M. Gallium nitride nanowire nanodevices, Nano. Lett. 2, 101- 104 (2002); Kim, J. et al.
- FIG. 12 depicts a low temperature photoluminescence (PL) spectra plot of the as produced nanotubes measured using fourth harmonic output of a YAG laser (266 nm) as an excitation source. It should be noted that no midgap yellow emission was observed. The band edge emission was observed in these nanotube samples between 375 nm and 360 nm, with the thinner tubes emitting at shorter wavelengths. This slight blue shift of the emission (see Hamdani F.
- the photoluminescence signal was transmitted to a 0.3 meter imaging monochromator by an optical fiber, detected by an intensified CCD working under gate mode. Only band edge emission was observed, with the spectra depicted on the left corresponding to the spectra collected on thin-walled ( ⁇ 10nm) GaN nanotubes, while the spectra depicted on the right corresponds to the spectra collected from thick- walled (> 10nm) GaN nanotubes, respectively. It should be appreciated that the emission spectra for the thin tubes is relatively broad due to the broad distribution of tube wall thicknesses for the tested sample. [0093] FIG.
- FIG. 13 depicts an example of electron transport measurements which indicate the resistances of these nanotubes are on the order of 10 M ⁇ at room temperature and increases with decreasing temperature, similar to those of high quality GaN nanowires.
- temperature dependence l-V curves of a single GaN nanotube are shown.
- the electrodes (20 nm titanium, Ti and 80 nm gold, Au) for the electrical measurements were fabricated using e-beam lithography and thermal evaporation, although other techniques may be utilized.
- a rapid thermal annealing step was performed at 450 °C for about thirty seconds, although any convenient means of contact formation may be utilized.
- the successful preparation of single-crystalline GaN nanocapillaries utilizing the present epitaxial casting process is indicative of the ability to prepare nanotubes/nanocapillaries, in particular single-crystalline nanotubes/nanocapillaries, of inorganic solids having non-layered crystal structures. It is anticipated that this new class of semiconductor nanotubes/nanocapillaries can be utilized in a number of beneficial technical applications in the fields of nanoscale electronics, optoelectronics, and chemistry in addition to use with fluidic systems.
- the present invention provides robust semiconductor nanotubes, having uniform inner diameter, and inner walls that can be readily functionalized, while both ends of the nanotubes can be made accessible for fluid flow applications.
- nanotube cores are formed from silicon (Si) nanowires, with a metal cap (i.e.
- the Si nanowire arrays are thermally oxidized which results in arrays of thin Si nanowires sheathed by a thick layer of silicon oxide (Si0 2 ).
- This oxidized nanowire array is then selectively etched, such as with xenon fluorine (XeF 2 ) to remove the silicon nanowire cores, leaving an array of ordered silicon dioxide nanotubes with controllable inner diameters.
- the inner diameters are controlled by the initial diameters of the silicon nanowires and the thermal oxidation process.
- the inner tube diameter of the nanotubes may be in the range of from approximately 10 nm to 200 nm.
- FIG. 14A illustrates silicon nanowire arrays which were prepared using chemical vapor deposition (CVD) epitaxial growth employing silicon tetrachloride (SiCI 4 , Aldrich, 99.99%) as the silicon source. Hydrogen (10% balanced by argon) was used to reduce SiCI 4 at high temperature (900-950 °C). Gold (Au) thin film was coated on Si (111 ) substrates 30 to initiate the growth of silicon nanowires 32 via the vapor-liquid-solid growth mechanism.
- CVD chemical vapor deposition
- FIG. 14B depicts the nanowires 32 after being uniformly oxidized to provide Si0 2 sheaths 36 with continuous silicon cores inside.
- the nanowire tips 34 are preferably oxidized to provide an oxide cap 34' on each vertical wire for preventing the selective etching of silicon cores. Therefore, the first step after thermal oxidation is to selectively remove the Si0 2 caps 34' from the Si/Si0 2 core-sheath nanowires.
- FIG. 14C illustrates a preferred mode of removing the Si0 2 caps.
- a polymer 38 is deposited to fill in the space between the nanowires such that the Si0 2 sidewall 36 is protected by the matrix polymer as an etch-resistant material.
- parylene dimer (di-para-xylylene, CH2-Ph- CH 2 -> 2 ) was thermally evaporated at 160 °C, dissociated at about 650 °C and deposited onto the Si/Si0 2 core-sheath nanowire array sample for approximately five (5) hours to yield a continuous coating of parylene (poly- para-xylylene, CH2-Ph-CH2-) n ) polymer.
- This parylene deposition is conformal, starting from thin layer coating on the surface of nanowires and then filling all the interval space between nanowires. This process leads to a highly conformal wrapping of the nanowires without pinholes or cracks.
- FIG. 14D illustrates the core-sheath array subsequent to oxygen plasma etching of the surface of the polymer fill 38, such as the parylene in order to expose the tips of the Si/Si0 2 nanowires.
- FIG. 14E depicts the core-sheath array after immersion in a buffered hydrofluoric acid solution for about two (2) minutes to selectively remove the Si0 2 caps 34' and expose the silicon cores 32.
- FIG. 14F illustrates the sheath array after the silicon nanowire cores 32 were removed by an etchant, such as XeF 2 etchant gas. It will be noted that although some material has been removed, a layer of etch-resistant material 38' still protects the bulk of the nanotube walls.
- FIG. 14G depicts a resulting nanotube array 36' after the parylene matrix was etched away, such as using high-power oxygen plasma treatment for thirty (30) minutes to yield a vertically oriented, robust silica nanotube matrix attached to substrate 30.
- Example 3 FIG. 15A-15D are images of nanotube formation according to the invention, registered as scanning electron micrographs (SEM). A silicon nanowire array is shown in FIG. 15A, with the Si nanowires vertically orientated to form a substantially perfect array. Typical sizes of the silicon nanowires are 50-200 nm, and the length is around 8 ⁇ m.
- FIG. 15B illustrates the nanotubes after parylene deposition, Si0 2 cap removal, and the etching of the silicon cores, wherein a silica nanotube array embedded in parylene membrane is formed.
- the pores can be readily seen on the polymer surface.
- the membrane has a relatively flat surface.
- the inset within FIG. 15B depicts high magnification of two silica nanotubes embedded in the parylene membrane, clearly showing the hollow pores with silica walls.
- FIG. 15D are perspective and top views, respectively, of the nanotube array after oxygen (0 2 ) plasma etching of parylene wherein a free-standing silica nanotube array is obtained.
- the nanotubes are well aligned and retain the vertical orientation of the starting silicon nanowire templates.
- the inset of FIG. 15C shows a zoom view of the nanotubes in a high magnification SEM image showing clearly the morphology of the vertical nanotube array.
- the images reveal that the Si nanowires are vertically oriented in an array, with uniform diameters along their length ranging from approximately 50 nm to 200 nm, with lengths of up to approximately 8 ⁇ m, and an average length of about 5 ⁇ m.
- FIG. 15D is a detailed top view from which the hexagonal shape of the tube is visible.
- the scale bars on FIG. 15A, 15B, 15C are 10 ⁇ m, 1 ⁇ m, and 10 ⁇ m respectively.
- the silica walls of the nanotubes were found to exhibit a well-defined hexagonal shape indicative of the ⁇ 111> orientation of the original Si nanowires and the anisotropic in-plane etching rates.
- FIG. 16A and 16B are transmission electron microscopy (TEM) images which further illustrate the high-quality of the silica nanotube formation.
- TEM transmission electron microscopy
- the uniform inner diameter is shown, which generally persists along the entire length of the nanotube.
- the pore sizes for the nanotubes range from about 10 nm to 200 nm, with smooth inner and outer walls.
- Nanotube thickness was found to be around 70 nm for a 1000 °C thermal treatment, despite the range of pore sizes for the nanotubes. This result is considered reasonable because the oxidation layer thickness is expected to be the same for the nanowires under a constant thermal treatment condition since the thermal oxidation of the silicon is a self-limiting process.
- the self-limitation of the process can be taken advantage of for controlling tube size and wall thickness by adjusting the characteristics of the thermal treatment process, such as the treatment temperature.
- a sample oxidized at 900 °C has a typical wall thickness of around 55-65 nm, while a temperature of about 800 °C yields a wall thickness of around 30-35 nm.
- the nanotube shown in FIG. 16B has a pore size of approximately 20 nm, however as can be seen, it still is uniform and has a smooth inner wall. Occasionally branched nanotubes were produced, it should be appreciated that these nanotubes will provide benefits for select nanofluidic and electronic applications.
- This multiuse approach of making silica nanotube array templates from silicon nanowire arrays is a well-controlled process capable of controlling the pore size and the array height, while the resultant nanotubes can be readily subjected to different surface modification on inner and outer walls.
- the respective surface modification of inner and outer walls can be important in applications such as bioseparation and smart molecule transport.
- the walls of these nanotubes are formed from pinhole-free condensed thermal oxide, which can be advantageous in terms of its mechanical robustness and fluidic stability. [00115] Consequently, this new class of semiconductor nanotubes represented by the present invention is mechanically robust, electrically and optically active.
- these nanotubes could offer additional opportunities for further fundamental research as well as technological applications in nanocapillary electrophoresis, nanofluidic biochemical sensing, nanoscale electronics and optoelectronics (see Schoening, M & Poghossian, A. Recent advances in biologically sensitive field-effect transistors (BioFETs), Analyst, 127, 1137-1151 (2002), incorporated herein by reference). It should be appreciated that the successful preparation of single-crystalline GaN nanotubes using this "epitaxial casting" approach suggests that it is generally possible to prepare single-crystalline nanotubes of inorganic solids that have non-layered crystal structures (see Lauhon, L. J., Gudiksen, M. S., Wang, D. & Lieber, C. M.
- FIG. 17 depicts a multilayer nanotube 50 comprising a sacrificial ZnO nanowire 12 (prior to removal) over which a gallium nitride (GaN) sheath 54 is held between two sheaths 52, 56 of aluminum nitride (AIN).
- GaN gallium nitride
- AIN aluminum nitride
- FIG. 18 shows P-doped GaN 62 over a sacrificial core 12 (prior to removal), such as ZnO, and N-doped GaN material 64 over the P-doped material.
- FIG. 19 illustrates the converse of FIG. 18 with P-doped material 74 over N-doped material 72 which sheaths core 12 (prior to its removal).
- numerous circuits may be fabricated, including diodes, light emitters, light detectors, electron transport devices (i.e. bipolar transistors, FETs, insulated gate FETs, and so forth) and combinations thereof. Connection to device layers can be provided from the core, or external circumferential connections, while connections may also be embedded into the material layers.
- FIG. 20 and FIG. 21 depict forming segmented nanotube sheaths by the present invention, wherein the different segments are formed from different materials, different dopants, different levels of doping, or combinations thereof. These sheaths may be fabricated segment-by-segment in any convenient manner, such as utilizing conventional masking techniques.
- a nanotube 80 is depicted having two segments of different sheath material 84, 86 disposed longitudinally over a sacrificial core 82.
- FIG. 21 depicts a nanotube 90 formed from three or more longitudinal segments of different material, differently doped material, or material that is otherwise configured to provide different properties. Furthermore, the nanotube is shown having at least two sheaths of material. [00121] A core 92 is shown prior to removal, with an upper-inner sheath 94, an upper-outer sheath 96, a middle-inner sheath 98, a middle-outer sheath 100, a lower-inner sheath 102, and a lower-outer sheath 104. It should be recognized that any desired number of sheath layers may be deposited and that nanotube may be fabricated with any number of longitudinal segments.
- FIG. 22 illustrates by way of example a cross-section of a nested sheath of layers 110 forming a bipolar transistor.
- a hollow 12' represents from where the sacrificial nanowire core was removed.
- the interior of hollow 12' is shown lined as a metallic contact 112.
- Three sheaths are shown in the figure.
- a P-doped semiconducting inner sheath 114 is shown.
- the present invention comprises a method of fabricating nanotubes by forming a sheath over a sacrificial core, and then removing the core. Two general methods were described: (i) epitaxial casting and (ii) oxidation and etching.
- examples of specific nanotube structures were described, such as a GaN nanotube (over a ZnO sheath) using the epitaxial casting method and a Si0 2 nanotube (over a Si sheath) using the oxidation and etching method.
- other materials can be used including, without limitation. GaN, Ge, Ag, group ll-VI, lll-V, elemental group IV (e.g., Si, Ge), and metals as core materials, and further, including without limitation, group ll-VI, ll-V, elemental group IV, metals, oxides of the above, and polymers as sheath materials. Note also that all of the sheaths can be doped during formation.
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US20040175844A1 (en) * | 2002-12-09 | 2004-09-09 | The Regents Of The University Of California | Sacrificial template method of fabricating a nanotube |
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- 2003-12-08 WO PCT/US2003/039200 patent/WO2004111319A2/en active Application Filing
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US20020175408A1 (en) * | 2001-03-30 | 2002-11-28 | The Regents Of The University Of California | Methods of fabricating nanostructures and nanowires and devices fabricated therefrom |
US20040175844A1 (en) * | 2002-12-09 | 2004-09-09 | The Regents Of The University Of California | Sacrificial template method of fabricating a nanotube |
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Cited By (6)
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JP2007294908A (en) * | 2006-03-30 | 2007-11-08 | Matsushita Electric Ind Co Ltd | Nanowire transistor, and method of fabricating same |
US8368049B2 (en) | 2006-03-30 | 2013-02-05 | Panasonic Corporation | Nanowire transistor and method for fabricating the same |
US8734666B2 (en) | 2008-10-27 | 2014-05-27 | Samsung Electronics Co., Ltd. | Method for preparing nanotubes of piezoelectric material and nanotubes of piezoelectric material obtained thereby |
CN102820213A (en) * | 2012-09-05 | 2012-12-12 | 中国科学院半导体研究所 | Method for growing single crystal GaN nanometer pipes by utilizing InN nanometer rods as nucleation layers |
EP4047359A1 (en) * | 2021-02-22 | 2022-08-24 | Meilleur Temps | Electrode for an electrochemical sensor |
CN113964003A (en) * | 2021-10-09 | 2022-01-21 | 电子科技大学长三角研究院(湖州) | GaN photocathode with nanotube structure and preparation method thereof |
Also Published As
Publication number | Publication date |
---|---|
EP1583858A2 (en) | 2005-10-12 |
KR20050085437A (en) | 2005-08-29 |
AU2003304214A1 (en) | 2005-01-04 |
EP1583858A4 (en) | 2008-03-12 |
CA2509257A1 (en) | 2004-12-23 |
WO2004111319A3 (en) | 2005-07-07 |
JP2006512218A (en) | 2006-04-13 |
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