JPH10117016A - Manufacturing method of nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a nitride semiconductor device, using a nitride semiconductor as its substrate by making an n-type nitride semiconductor layer with a specific film thickness to grow on a substrate, and by making nitride semiconductor layers containing acceptor impurities grow on the foregoing nitride semiconductor layer, and further, by removing thereafter the substrate therefrom. SOLUTION: A buffer layer 11 is made to grow in contact with a substrate 10 made of spinel (MgAl2 O4 ). Then, an n-type nitride compound semiconductor layer 1 with a film thickness not smaller than 20μm is made to grow in contact with the buffer layer 11. Further, an active layer 2 is made to grow in contact with the semiconductor layer 1. Subsequently, nitride semiconductor layers 3, 4 containing acceptor impurities are made to grow on the active layer 2. Then, a resultant wafer is taken out from a reaction container, to remove the substrate 10 therefrom. In this case, the buffer layer 11 is also removed naturally therefrom. Further, an n-electrode 20 is provided on the surface of the semiconductor layer 1 corresponding to the bottom surface of the wafer, and an electrode comprising a translucent p-type electrode 21 and a pad electrode 22 is formed on the uppermost semiconductor layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an LED (light emitting diode)
Light-emitting devices such as laser diodes (LDs)
Nitriding used for light receiving devices such as solar cells and optical sensors
Semiconductor (In _XAl_YGa_1-XYN, 0 ≦ X, 0 ≦ Y, X +
Y ≦ 1) It relates to a method for manufacturing the element.

[0002]

2. Description of the Related Art Nitride semiconductors are currently in practical use as blue light emitting LEDs and green light emitting LEDs. Since the nitride semiconductor has no lattice-matched substrate, the lattice constant is 1
It is grown via an AlN or GaN buffer layer with a thickness of several hundred angstroms formed directly on a sapphire substrate having a thickness of 3.5%. On the other hand, an attempt to fabricate a bulk crystal of GaN to be a lattice-matched substrate has been made in a foreign research period, but at present, the bulk crystal of GaN is at a high temperature and a high pressure of 1200 ° C. or more and 10,000 atmospheres or more. In reality, only small crystals of about several millimeters φ can be obtained.

Since a GaN substrate using a bulk single crystal cannot be expected, a technique using a GaN thick film as a substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 8-116090. According to this technique, GaN is formed in a thickness of 50 to 200 μm on a substrate such as GaAs, GaP, InP, or Si via a buffer layer, and then the substrate is removed by means such as polishing or chemical etching. On the remaining GaN layer, a new n-type layer, p
A nitride semiconductor including a mold layer is grown.

In addition, Japanese Patent Application Laid-Open No. Hei 7-165498 describes a method of forming a GaN substrate by repeatedly growing a buffer layer and a GaN single crystal layer on a substrate. No. -202265 discloses a method of obtaining a thick-film GaN single-crystal substrate by growing a buffer layer made of ZnO on a sapphire substrate, growing a thick-film GaN on the buffer layer, and then dissolving and removing ZnO. It is shown. Further, Japanese Patent Application Laid-Open No.
A light emitting device in which nitride semiconductor layers of different conductivity types are stacked on an aN single crystal substrate is disclosed.

[0005]

As described above, various techniques have been proposed for a GaN substrate for growing a nitride semiconductor. However, nitride semiconductors using this GaN substrate have yet to appear. In reality, it is very difficult to manufacture various device elements having a thick film GaN having a thickness of several tens of μm or more on a substrate.

Therefore, an object of the present invention is to manufacture a device element made of a nitride semiconductor.
An object of the present invention is to provide a manufacturing method capable of realizing an element using a nitride semiconductor for a substrate.

[0007]

The method of manufacturing a nitride semiconductor device according to the present invention comprises two types of modes. The first mode is that an n-type nitride semiconductor layer (hereinafter referred to as an n-type layer) is formed on a substrate. .) Is grown to a thickness of 20 μm or more;
The method is characterized by including at least a step of growing a nitride semiconductor layer containing an acceptor impurity above the mold layer, and a step of removing the substrate after growing the nitride semiconductor layer containing the acceptor impurity. In particular, in the first embodiment of the present invention, it is desirable to use spinel (MgAl ₂ O ₄ ) for the substrate, and among them, it is preferable that the (111) plane of the spinel substrate be the growth surface of the nitride semiconductor.

The first aspect of the present invention includes a step of annealing (heat treatment) in an atmosphere containing nitrogen after growing a nitride semiconductor layer containing an acceptor impurity, and then annealing in an atmosphere containing no hydrogen source. It is characterized by. Annealing in an atmosphere containing a nitrogen source is performed using N
By supplying the source, the decomposition of the nitride semiconductor is prevented and the crystallinity is adjusted. Therefore, ammonia, hydrazine, or the like is used as the N source at 300 ° C to 1200 ° C.
It is desirable to anneal in an atmosphere. The highest crystallinity is at 400 ° C. or higher. Annealing in an atmosphere containing no H source is performed by removing H bonded to the acceptor impurity from the crystal during the reaction or by the N-source annealing to further reduce the resistance of the nitride semiconductor layer doped with the acceptor impurity. To do that. This annealing is also desirably performed at 400 ° C. or higher.

In a second aspect of the present invention, a step of growing an n-type layer on the spinel substrate with a thickness of 20 μm or more, a step of removing the substrate after growing the n-type layer, a step of removing the n-type layer after the substrate is removed, A nitride semiconductor layer containing at least an acceptor impurity is grown on the layer. Also,
Also in the second embodiment of the present invention, (11) of the spinel substrate
1) The surface is desirably a growth surface of a nitride semiconductor.

[0010] In the claims of the present application, the n-type layer grown on the substrate does not necessarily mean that the n-type layer is grown in contact with the substrate, but GaN, AlN,
This includes growing a buffer layer of ZnO or the like and growing an n-type layer having a thickness of 20 μm or more in contact with the buffer layer. The n-type layer having a thickness of 20 μm or more may be a nitride semiconductor having a single composition or a layer in which thin films of n-type layers having different compositions are stacked. Similarly, growing a nitride semiconductor layer doped with an acceptor impurity on the n-type layer does not necessarily mean that the nitride semiconductor layer doped with the acceptor impurity is grown in contact with the n-type layer. The method also includes growing a buffer layer, an i-type layer, an active layer, or the like in contact with the buffer layer, the i-type layer, or the active layer, and growing a nitride semiconductor doped with an acceptor impurity.

Further, a second aspect of the present invention is characterized in that, after growing the n-type layer, the surface of the n-type layer is made mirror-like.

In a second aspect of the present invention, after the substrate is removed, the n-type nitride semiconductor is annealed in an atmosphere containing a nitrogen source, and after the nitride semiconductor layer containing an acceptor impurity is grown, a hydrogen source is contained. It is characterized by annealing in a non-ambient atmosphere. The reason why annealing is performed in an atmosphere containing a nitrogen source after the substrate is removed is to supply a N source to prevent decomposition of the nitride semiconductor and prepare a substrate having good crystallinity, as in the first embodiment. Similarly, using ammonia, hydrazine, etc.
It is desirable to anneal in an atmosphere of 0 ° C. The temperature at which the crystallinity is best is 400 ° C. or higher. Annealing in an atmosphere containing no H source removes H bonded to the acceptor impurity from the crystal during the reaction as in the first embodiment, and further reduces the resistance of the nitride semiconductor layer doped with the acceptor impurity. 400 ° C
It is desirable to perform the above. In the first and second aspects of the present invention, the n-type layer has a lower carrier concentration on the side closer to the p-type layer and a higher carrier concentration on the side farther from the p-type nitride semiconductor. It is characterized by.

[0013]

1 (a) to 1 (e) are schematic sectional views showing a partial structure of a wafer obtained in each step of the first embodiment of the present invention. The first embodiment of the present invention will be described based on these drawings.

The method for growing the nitride semiconductor is not particularly limited. For example, conventional nitride semiconductors such as MOVPE (metalorganic vapor phase epitaxy), HDVPE (halide vapor phase epitaxy), MBE (molecular beam vapor phase epitaxy), etc. Any of the methods proposed for growing semiconductors can be applied.

In FIG. 1A, reference numeral 10 denotes a substrate. A nitride semiconductor is first grown on the substrate 10. First
In the embodiment, sapphire, spinel, Si
Substrates of C, GaAs, Si, ZnO, etc. can be used,
Preferably, spinel is used. Spinel can grow a nitride semiconductor having a single composition as a film having a thickness of 20 μm or more as compared with other materials. Moreover, Spinel's (11
If the 1) plane is a nitride semiconductor growth plane, a nitride semiconductor with good crystallinity can be grown as a thick film. The quality of the crystallinity can be determined by measuring the half width of the X-ray rocking curve of the two-crystal method, and a crystal having a half width of 200 seconds or less, more preferably 150 seconds or less, and most preferably 100 seconds or less is obtained. If so, it can be determined that the nitride semiconductor crystal has few cracks and a uniform surface is obtained. Spinel has a small lattice constant difference with nitride semiconductors (9
%) And the difference in thermal expansion coefficient is small, and the crystal is softer than the substrate on which other nitride semiconductors are grown.
The feature is that cracks are unlikely to occur even when a thick nitride semiconductor is grown. For example, when GaN is grown on a substrate such as sapphire or SiC with a film thickness of 10 μm or more, cracks tend to occur.

Next, the buffer layer 1 is brought into contact with the substrate 10.
Grow one. The buffer layer 11 is made of, for example, AlN, Al
200 nitride semiconductors such as GaN, GaN and InGaN
It is grown at a low temperature of from 900C to 900C. The buffer layer 11 has an effect of alleviating lattice mismatch between the substrate 10 and a nitride semiconductor grown next to the buffer layer. Note that, since the nitride semiconductor has a property of being n-type in a non-doped state (not doped with impurities) due to a lattice defect of the semiconductor itself, the buffer layer 11 usually has n-type conductivity.

Further, as shown in FIG.
1, the n-type layer 1 is grown to a thickness of 20 μm or more. The n-type layer 1 is grown at a higher temperature than the buffer layer. n
When the mold layer 1 is grown with a single composition of 20 μm or more, the composition is preferably GaN. GaN is easier to grow than a nitride semiconductor containing In or Al, and GaN having the highest crystallinity can be obtained. Further, the n-type layer 1 may be formed by laminating a plurality of n-type layers to have a thickness of 20 μm or more. For example, GaN is grown to 5 μm on the buffer layer 11, and InGaN is further grown to 0.1 μm and GaN is further grown to 5 μm.
A thin n-type layer can also be laminated, for example, by growing the film and repeating the process to a film thickness of 20 μm or more. As described above, even when a thin film nitride semiconductor is grown, if the substrate 10 is spinel, an n-type layer that does not easily crack can be grown. Note that the nitride semiconductor becomes n-type even if it is non-doped as described above. However, it is preferable to grow an n-type layer in which the carrier concentration is adjusted by doping a donor impurity such as Si, Ge, or Sn. The thickness of the n-type layer 1 is 20 μm or more, more preferably 50 μm or more, and most preferably 1 μm or more.
It is grown to a thickness of 00 μm or more. If the thickness is less than 20 μm, the wafer is likely to be broken when the substrate is removed later, and it is difficult to produce a chip having an accurate shape. Although the upper limit of the film thickness is not particularly defined, it is usually adjusted to 1 mm or less.

When the carrier concentration is adjusted by doping with a donor impurity, the carrier concentration of the n-type layer 1 is
It is desirable to increase the carrier concentration on the side closer to the active layer 2 while decreasing the carrier concentration on the side closer to the active layer 2 to be grown next. As described above, when the carrier concentration on the side close to the p-type layer is reduced and the carrier concentration on the side away from the p-type layer is increased, the substrate 10 is later deleted, and
The carrier injection efficiency when the n-electrode is formed on the mold layer 1 side is improved, and the light emission output is improved.

Next, an active layer 2 is grown in contact with the n-type layer 1 as shown in FIG. The conductivity type of the active layer 2 formed in contact with the n-type layer may be n-type, i-type, or p-type. The active layer 2 is configured to include a well layer made of a nitride semiconductor containing In, and preferably a well layer made of ternary mixed crystal InGaN. Since ternary mixed crystal lnGaN can be obtained with better crystallinity than that of quaternary mixed crystal, the light emission output is improved. When fabricating an LED element, the active layer is a single quantum well structure (SQW: Single-
quantum-well). In the case of manufacturing an LD element, a multiple quantum well structure (MQW: Multi-q) in which an active layer is formed by stacking a well layer made of InGaN and a barrier layer made of a nitride semiconductor having a larger band gap than the well layer.
uantum-well). Similarly, the barrier layer is made of ternary mixed crystal In.
_{X ′} Ga _{1−X ′} N (0 ≦ X ′ <1, X ′ <X) is preferable, and the layers are stacked such that well + barrier + well + ... ten barrier + well (or vice versa). Configure MQW. When the active layer is MQW in which lnGaN is stacked as described above, it is possible to realize a high-power LD between about 365 nm and 660 nm by quantum level emission. Further, lnGa is formed on the well layer.
When a barrier layer made of N is stacked, the crystal of the barrier layer made of InGaN is softer than that of AIGaN. Therefore, the thickness of the AIGaN of the cladding layer can be increased, so that laser oscillation can be realized. Further, lnGaN and AIGaN have different crystal growth temperatures. For example, in the MOVPE method, lnGaN is grown at 600 ° C. to 800 ° C., whereas AIGaN is grown at a temperature higher than 900 ° C.
Therefore, after growing a well layer of InGaN, A
In order to grow a barrier layer made of IGaN, it is necessary to raise the growth temperature. When the growth temperature is increased, the lnGaN well layer grown earlier is decomposed, so that it is difficult to obtain a well layer with good crystallinity. Further, the thickness of the well layer is only several tens of angstroms, and it becomes difficult to manufacture the MQW when the well layer of the thin film is decomposed. On the other hand, if the barrier layer is also made of InGaN, the well layer and the barrier layer can be grown at the same temperature. Therefore, since the well layer formed earlier does not decompose, an MQW with good crystallinity can be formed. This shows the most preferable mode of the MQW. In addition, the well layer is made of InGaN, and the barrier layer is made of Ga.
Any composition may be used as long as the band gap energy of the barrier layer is larger than that of the well layer, such as N and AIGaN. In an active layer having an InGaN multiple quantum well structure or a single quantum well structure, excitons are localized in an In-rich energy potential well layer formed by non-uniform composition of the InGaN well layer, and localized excitons are formed. The light emission output is improved by the localized exciton light emission. In other words, when such thin films having a thickness of several tens of angstroms are stacked, both the well layer and the barrier layer are not grown to have a uniform thickness, and a state in which uneven layers are overlapped many times. Has become. By realizing a double hetero structure in which an active layer with irregularities is sandwiched by a cladding layer having a band gap larger than that of the active layer, electrons and holes injected into the active layer are confined in recesses, and the cladding layer is formed. In both the vertical and horizontal directions along with the vertical direction. Therefore, the carriers are confined in a three-dimensional InGaN quantum box or quantum disk having a difference of about 10 to 70 angstroms, and a quantum effect different from the conventional quantum well structure appears.

Next, as shown in FIG. 1C, the nitride semiconductor layers 3 and 4 containing acceptor impurities are formed on the active layer 2.
(Hereinafter, the nitride semiconductor layer containing the acceptor impurity is referred to as p.
It is called a mold layer. Grow). In this figure, the simplest L
Since the ED structure is shown, the p-type layer is a p-type cladding layer 3
And a p-type contact layer 4. In addition to these p-type layers, a p-type layer having a different composition can be newly inserted anywhere on the active layer, if necessary. it can. It should be noted that these p-type layers can be further annealed after growth to realize a p-type layer with lower resistance.

As described above, the n-type layer 1
Is grown to a thickness of 20 μm or more, and at least the p-type layers 3 and 4 are grown on the n-type layer 1. The n-type layer 1
It is within the scope of the present invention to grow a buffer layer 11 between the substrate and the substrate 10, or to grow an active layer 2 between the n-type layer 1 and the p-type layer 3, Further, an n-type layer (for example, an n-type clad layer) having another composition can be grown between the n-type layer 1 and the active layer 2.

Next, after growing a device structure made of a nitride semiconductor, the wafer is taken out of the reaction vessel and
As shown in (d), the substrate 10 is removed. For removing the substrate 10, there are means such as polishing and etching. In the case of polishing, lapping is performed using SiC powder and diamond powder, and then polishing is performed. In the case of chemical etching, it can be removed by dissolving the substrate side with, for example, a mixed acid of sulfuric acid and phosphoric acid or sulfuric acid and hydrogen peroxide. Although the buffer layer 11 is also removed in FIG. 1, the buffer layer 11 is a very thin layer, and the substrate is not necessarily removed uniformly with a precision of several tens of angstroms by techniques such as etching and polishing. Therefore, the buffer layer 11 is naturally removed.
In this manner, a wafer made of a nitride semiconductor and having the surface of the n-type layer 1 and the surface of the p-type layer 4 exposed vertically can be manufactured.

FIG. 1 (e) shows a nitride semiconductor chip structure cut out from the wafer of FIG. 1 (d) into chips.
An n-electrode 20 is provided on the surface of the n-type layer 1 corresponding to the bottom surface,
An electrode composed of a translucent p-electrode 21 and a pad electrode 22 is formed on the uppermost p-type contact layer 4. The p-electrode 21 is a light-transmitting metal electrode, is formed to a thickness of, for example, 0.1 μm or less, and has a favorable ohmic contact with the p-type contact layer 4. The translucent p-electrode 21 allows the light emission of the active layer 2 to be observed from the p-type layer side, and transmits the hydrogen contained in the p-type layer at the time of annealing, because of its small thickness, to form a low-resistance p-type layer. It has contributed to the realization. When the pad electrode 22 is directly wire-bonded to the translucent p-electrode 21, the translucent electrode 21 is easily peeled off.
The peeling of the electrode 21 is prevented, and the wire bonding position is clarified. Further, when the pad electrode is located at the center of the p-electrode 21, bonding positioning at the time of wire bonding becomes easy, and the element yield is improved.

The first aspect of the present invention is different from the conventional technique for manufacturing a GaN substrate in that an n-type layer is grown, and then an active layer and a p-type layer are formed. After the fabrication, the substrate is to be removed.
In this way, mass production of the device is improved by forming the nitride semiconductor once grown up to the device structure without taking it out of the reaction vessel. Further, since the substrate is not taken out of the reaction container until the element structure is completed, oxidation and alteration of the substrate on the nitride semiconductor growth surface due to contact with air can be prevented.

FIGS. 2F to 2J are schematic sectional views showing a partial structure of a wafer obtained in each step of the second embodiment of the present invention. Based on these figures, the second embodiment of the present invention
Will be described.

The substrate 10 shown in FIG. 2F is made of spinel. In the second embodiment, the substrate needs to be spinel. This is because the second embodiment differs from the first embodiment in that an n-type layer is grown on the substrate 10 and then the substrate is removed. Therefore, it is better to grow an n-type layer having a single composition as a thick film, when the n-type layer is transferred again into the reaction vessel and crystal growth is performed at a high temperature of 1000 ° C. or more, cracking, chipping, etc. of the n-type layer. It is desirable to prevent physical deformation such as crystal damage and warpage of the n-type layer. As described in the first embodiment, a spinel substrate is most easily grown to grow an n-type layer having a single composition as a thick film.

The buffer layer 11 is grown in contact with the spinel substrate 10. The buffer layer 11 does not particularly replace the first embodiment.

Next, the n-type layer 1 is brought into contact with the buffer layer 11.
Is grown to a thickness of 20 μm or more. In the second embodiment, the n-type layer 1 has a single nitride semiconductor composition, preferably Ga
It is desirable to grow with N at a film thickness of 20 μm or more.
Further, in the second embodiment, the thickness of the n-type layer is preferably 5
It is desirable to grow with a film thickness of 0 μm or more, more preferably 100 μm or more, and most preferably 120 μm or more. This is because the substrate 10 is removed after the growth of the n-type layer 1,
A single n-type layer serving as a new substrate is formed.
Crystal growth is performed on the mold layer at a high temperature. If the n-type layer serving as the substrate is thin, it may crack or warp during growth, and thus a nitride semiconductor layer having a uniform thickness may not be laminated. Therefore, in the second embodiment, it is desirable that the n-type layer 1 be grown thicker than in the first embodiment.

Also in the second embodiment as in the first embodiment, it is desirable that the n-type layer 1 is doped with a donor impurity such as Si, Ge, Sn or the like to grow an n-type layer whose carrier concentration is adjusted. When the carrier concentration is adjusted by doping a donor impurity, the carrier concentration of the n-type layer 1 should be increased on the side closer to the buffer layer 11 and decreased on the side farther from the buffer layer 11. Is desirable.

Next, after growing the n-type layer 1, the wafer is taken out of the reaction vessel, and the substrate 10 is removed by means such as polishing and etching as shown in FIG. 2 (h). By removing the substrate, a wafer made of the n-type layer 1 with the first main surface and the second main surface exposed can be manufactured.
In FIG. 2H, the buffer layer 11 is also removed, but the cause is the same as in the first embodiment.

Furthermore, in the second embodiment, after removing the substrate 10, it is desirable that the surface of the n-type layer 1 on which a nitride semiconductor layer having another conductivity type is to be grown has a mirror-like surface.
In order to make a mirror surface, there are physical etching means such as polishing and dry etching in addition to chemical etching,
Polishing is most preferable because there are few solvents capable of etching the nitride semiconductor such as sulfuric acid + phosphoric acid and the danger is high. By making one of the surfaces of the n-type layer 1 mirror-like, a nitride semiconductor having a uniform plane orientation can be grown.

Next, as shown in FIG.
The active layer 2, the p-type cladding layer 3, and the p-type contact layer 4 are sequentially laminated on the surface of the substrate. The active layer 2 is most preferably the same as the active layer described in the first embodiment. Another layer made of an n-type nitride semiconductor having a composition different from that of n-type layer 1 may be grown between active layer 2 and n-type layer 1. The p-type cladding layer 3 and the p-type contact layer 4 are the same as those in the first embodiment, and if necessary, may have a different composition.
The mold layer may be inserted into any layer on the active layer.

FIG. 2H shows a nitride semiconductor chip structure cut into chips from the wafer of FIG. 2I. The effect of the light-transmitting electrode 21 and the pad electrode 22 is the first.
This chip is not particularly different from the embodiment of FIG.
The difference from the chip of (e) is that the n-type layer 1 under the active layer 2 is etched. That is, the p-type layer is etched to expose the n-type layer under the active layer 2, and between the exposed etching grooves,
The wafer is cut into chips. This operation is as follows. According to the present invention, since the substrate is a nitride semiconductor, the nitride semiconductor can be cleaved. However, since the nitride semiconductor is a hexagonal crystal, it is difficult to cleave all the semiconductor into a rectangular chip. Therefore, any one of the surfaces has to take cutting means such as dicing. Since the nitride semiconductor has a very hard crystalline property, dicing tends to cause chipping or cracking at the dicing end face, and in particular, if such crystal defects occur at the end face of the active layer, the reliability of the element itself decreases. I do. Therefore, by etching up to the n-type layer below the active layer, the blade edge during dicing can be prevented from touching the end face of the active layer, thereby improving the reliability of the element. This shape of (j) is similarly applicable to the first embodiment.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for growing a nitride semiconductor by the MOCVD method will be described below. The method of the present invention is not limited to MOCVD, and any method conventionally proposed for growing a nitride semiconductor such as MBE or HDVPE is used. Applicable to the method. Regarding the element structure, a typical LED element and L
Although only the D element is described, the structure is not limited to this embodiment.

Embodiment 1 (First Embodiment) A first embodiment of the present invention will be described with reference to FIG. (11
1) Spinel substrate 10 (MgAl
₂ O ₄ ) was set in the reaction vessel, and the inside of the reaction vessel was sufficiently replaced with hydrogen.
The temperature is raised to 0 ° C., and the substrate is cleaned.

Subsequently, the temperature was lowered to 510 ° C., and a buffer layer 11 made of GaN was formed on a spinel substrate with a thickness of about 200 Å using hydrogen as a carrier gas, ammonia and TMG (trimethylgallium) as source gases. Let it grow. The buffer layer is made of AlN, GaN, AlGa
N or the like can be formed at a temperature of 900 ° C. or less with a film thickness of several tens angstroms to several hundred angstroms. This buffer layer is formed to alleviate the lattice constant irregularity between the substrate and the nitride semiconductor, but may be omitted depending on the nitride semiconductor growth method.

After the growth of the buffer layer 11, only TMG is stopped, and the temperature is increased to 1030 ° C. When the temperature reaches 1030 ° C., TMG, ammonia gas and silane gas are used as the source gas and the Si-doped n-type GaN is used as the n-type contact layer 1 as shown in FIG.
The layer is grown to a thickness of 100 μm. In the n-type contact layer 1, the first 50 μm is defined as n + having a high carrier concentration, and the next 50 μm is defined as n− having a low carrier concentration. The n-type contact layer is made of In _X Al _Y Ga _{1 -XYN} (0 ≦ X, 0 ≦ Y, X + Y
≦ 1), particularly GaN, InGa
By using N and, among them, GaN doped with Si, an n-type layer having a high carrier concentration can be obtained, and a favorable ohmic contact with the negative electrode can be obtained. As a material for the negative electrode, a metal or alloy such as Al, Ti, W, Cu, Zn, Sn, and In can be used to obtain an ohmic.

Next, TMG, TMI, and ammonia were used as source gases, and the temperature was maintained at 800 ° C.
An active layer 2 having a single quantum well structure (SQW) made of 0.2Ga0.8N is grown to a thickness of 30 angstroms. When the active layer 2 has a single quantum well structure or a multiple quantum well structure including a well layer made of InGaN, it is possible to realize a high-power light emitting element having a light emission between about 365 nm to 660 nm by quantum level emission. In the multiple quantum well structure, the well layer has a thickness of 70 Å or less and the barrier layer has a thickness of 15 Å or less.
It is desirable to adjust the thickness to 0 angstrom or less. On the other hand, in a single quantum well structure, it is desirable to adjust the film thickness to 70 Å or less.

Next, the temperature was increased to 1050 ° C.
P-type cladding layer 3 made of doped p-type Al0.2Ga0.8N
Is grown to a thickness of 0.5 μm. It is desirable that the p-type cladding layer grown in contact with the active layer grows a nitride semiconductor containing Al, preferably AlGaN. Mg, Zn, and p-type acceptor impurities
Group II elements such as Cd can be mentioned. A p-type crystal can be obtained by doping these acceptor impurities during the growth of the nitride semiconductor. Preferably, the crystal doped with the acceptor impurities is annealed after the growth. By removing hydrogen bonded to the acceptor impurity from the crystal, a more preferable p-type can be obtained.

Next, at 1050 ° C., Mg-doped p-type GaN
A p-type contact layer 4 is grown to a thickness of 0.5 μm. FIG. 1C is a cross-sectional view after the growth. The p-type contact layer 4 is made of p-type In _x Al _Y Ga _{1 -XYN} (0 ≦ X, 0 ≦
Y, X + Y ≦ 1), especially InGa
When N and GaN, among them, p-type GaN doped with Mg, a p-type layer having the highest carrier concentration can be obtained, and good ohmic contact with the positive electrode can be obtained. As the material of the positive electrode, a metal or alloy having a relatively high work function, such as Ni, Pd, Ir, Rh, Pt, Ag, or Au, can easily obtain an ohmic.

After completion of the reaction, the wafer is taken out of the reaction vessel, and the spinel substrate 10 on which the nitride semiconductor is not grown is wrapped using a polishing machine, and as shown in FIG. The buffer layer 11 is removed. After removing the buffer layer, the n-type contact layer 1 on the buffer layer side is further polished to a mirror surface.

Next, the wrapped wafer is transferred to an annealing device, and is heated at 1000 ° C. in an ammonia atmosphere.
Annealing. This annealing is performed at 300 ° C.
At a temperature of 1200 ° C. or less,
Performing in an atmosphere containing the source has the effect of adjusting the crystallinity of the entire crystal.

After annealing, in an annealing apparatus, this time in an atmosphere containing no H (nitrogen atmosphere),
Annealing is performed at 700 ° C. to further reduce the resistance of the p-type layer. This annealing is usually performed at 400 ° C. or higher in an atmosphere containing no H to remove hydrogen bonded to the acceptor impurity from the crystal, thereby further reducing the resistance of the p-type layer.

After annealing, an n-electrode 20 containing Ti and Al is formed with a thickness of 2 μm on almost the entire surface of the polished n-type contact layer 1, while Ni and Au are formed on almost the entire surface of the p-type contact layer 4. Is formed with a thickness of 100 Å. To obtain a preferable ohmic contact on the surface of the p-type contact layer 4,
It is desirable that the thickness of the electrode be 1000 Å or less so that the electrode is transparent. This is because hydrogen is released from the p-type layer through the translucent electrode during the electrode annealing, and the resistance of the p-type layer is further reduced. Next, a pad electrode 22 having a thickness of 2 μm is formed substantially at the center of the p electrode 20.

After the above steps are completed, the nitride semiconductor wafer is cleaved using the cleavage of n-type contact
An LED element of 0 μm square is used. This LED element has an upper and lower opposing n-electrode and p-electrode, and a forward current (I
f) At 20 mA, a forward voltage (Vf) of 3.5 V;
The light emission output was 5 mW, showing excellent characteristics.

Example 2 A buffer layer made of GaN was formed on a sapphire substrate with a thickness of 200 Å on the sapphire substrate in the same manner as in Example 1 except that a sapphire (0001) plane was used for the substrate. I do.

Next, a 5 μm Si-doped n-type GaN layer is grown on the buffer layer. Next, the temperature was set to 800 ° C., and the Si-doped n-type I-type
The n0.1Ga0.9N layer is grown to 500 Å. Next, Si-doped n-type GaN is grown to 5 μm, and Si-doped n-type In0.1Ga0.9N is further grown to 500 Å. This operation is repeated 16 times to grow an n-type contact layer having a total thickness of 60.6 μm. Thereafter, when an LED element was manufactured in the same manner as in Example 1, the forward voltage (Vf) was 4 V and the light emission output was 2 mW at a forward current (If) of 20 mA.

Embodiment 3 (Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. In the same manner as in the first embodiment, the spinel substrate 10 (MgAl ₂ O ₄ ) having the (111) plane as a growth surface is cleaned, and a buffer layer 11 made of GaN is formed on the spinel substrate 10 for 20 minutes.
On the buffer layer, a Si-doped n-type GaN layer is grown with a thickness of 100 μm as an n-type contact layer 1 having n + and n− layers. FIG. 2 (g)

After the growth, the wafer is taken out of the reaction vessel,
Using a polisher, the spinel substrate 10 on which the nitride semiconductor is not grown is wrapped, and the spinel substrate 10 and the buffer layer 11 are removed as shown in FIG. . Further, the n-type contact layer on the low carrier concentration (n−) side is polished to a mirror surface.

After polishing, the n-type contact layer substrate is transferred to a reaction vessel, and is annealed at 1000 ° C. in an ammonia atmosphere. The mirror-shaped n-type contact layer on the low carrier concentration side is used as a nitride semiconductor growth surface.

Next, an active layer 2 having a SQW structure is grown to a thickness of 30 Å on the surface of the n-type contact layer 1 polished in the same manner as in the first embodiment. A 0.5 μm-thick p-type cladding layer 3 of.
A p-type contact layer 4 of type GaN is grown to a thickness of 0.5 μm. FIG. 2I is a cross-sectional view after the growth.
Before growing the active layer 2, a buffer layer made of GaN, InGaN, or AlGaN can be grown on the surface of the n-type contact layer 1.

After the completion of the reaction, the reaction vessel is placed in an atmosphere containing no H, for example, nitrogen, Ar, or the like.
Annealing is performed at 0 ° C. to further reduce the resistance of the p-type layer.

After annealing, the wafer is taken out of the reaction vessel, and RIE (reactive ion etching) etching is performed in a grid pattern with a width of 10 μm from the side of the p-type contact layer 4 to form an n-type contact as shown in FIG. Expose the plane of the layer.

Next, in the same manner as in Example 1, an n-electrode 20 containing Ti and Al is formed with a thickness of 2 μm on almost the entire surface of the n-type contact layer 1 on which no nitride semiconductor is grown. , Ni and Au are formed almost all over the p-type contact layer 4.
Is formed to a thickness of 100 Å, and a pad electrode 22 having a thickness of 2 μm is formed substantially at the center of the p-electrode 20.

After the above steps are completed, the nitride semiconductor wafer is cut between the etching grooves by using a dicer to obtain a light emitting device of 350 μm square. This light-emitting element also has an n-electrode and a p-electrode opposing vertically,
At 0 mA, Vf 3.5 V and light emission output of 5 mW showed excellent characteristics.

Embodiment 4 FIG. 3 is a schematic sectional view showing the structure of a laser device obtained by the method of the present invention.
More specifically, FIG. 3 shows a diagram when the element is cut in a direction perpendicular to the resonance direction of the laser light. Hereinafter, a method of manufacturing an LD by the method of the present invention will be described with reference to FIG.

In Example 3, the spinel substrate 10 and the buffer layer 11 were removed, the growth surface was polished, and a 100 μm-thick n-type contact layer 1 wafer made of Si-doped GaN was placed in a reaction vessel. 80
At 0 ° C., a crack prevention layer 101 made of Si-doped In0.1Ga0.9N is grown to a thickness of 500 Å by using TMG, TMI (trimethylindium) and ammonia as source gases and silane gas as an impurity gas. The crack prevention layer 101 is grown from an n-type nitride semiconductor containing In, preferably InGaN, so that the first n-type nitride semiconductor layer 102 containing Al to be grown next can be grown as a thick film. It is possible and very favorable. In the case of LD, it is necessary to grow a layer to be a light confinement layer, preferably with a thickness of 0.1 μm or more. Conventionally, when a thick AlGaN is grown directly on a GaN or AlGaN layer, the AlGa that has been grown later is grown.
Although cracks were formed in N, it was difficult to fabricate the device. However, the crack preventing layer 101 can prevent cracks from being formed in the first n-type nitride semiconductor layer 102 containing Al to be grown next. . This crack prevention layer is 10
It is preferable to grow the film with a thickness of 0 Å to 0.5 μm. If it is thinner than 100 Å, it is difficult to act as a crack prevention as described above,
If it is thicker than 0.5 μm, the crystals themselves tend to turn black. The crack preventing layer 101 can be omitted depending on conditions such as a growth method and a growth apparatus.

Next, the temperature was raised to 1030 ° C., and TMA (trimethylaluminum), TMG, NH ₃ ,
Using SiH ₄ , a first n-type nitride semiconductor layer 102 made of Si-doped n-type Al 0.2 Ga 0.8 N is grown to a thickness of 0.5 μm. This first n-type nitride semiconductor layer 102
Acts as a carrier confinement layer and a light confinement layer, and it is desirable to grow a nitride semiconductor containing Al, preferably AlGaN, as described above, and more than 100 Å and less than 2 μm, more preferably 500 μm.
A carrier confinement layer with good crystallinity can be formed by growing the layer at a thickness of Å or more and 1 μm or less.

The temperature was lowered to 800 ° C. and the Si-doped n-type G
the second n-type nitride semiconductor layer 103 of aN
It is grown to a thickness of μm. The second n-type nitride semiconductor layer functions as an optical guide layer and is preferably used for growing GaN or InGaN. The second n-type nitride semiconductor layer is usually formed to have a thickness of 100 Å to 5 μm, more preferably 200 Å to 1 μm. desirable.

Next, the temperature of the active layer for growing the active layer 2 using TMG, TMI, and ammonia as the source gas is set to 80 ° C.
While maintaining the temperature at 0 ° C., first, a well layer made of non-doped In0.2Ga0.8N is grown to a thickness of 25 Å. Next, a barrier layer made of non-doped In0.01Ga0.95N was deposited at the same temperature by changing only the molar ratio of TMI.
It is grown to a thickness of 0 Å. This operation 2
This is repeated twice, and finally, an active layer 2 having a multiple quantum well structure in which well layers are stacked is grown.

Next, the temperature was raised to 1050 ° C., and TMG,
TMA, NH _3, Cp2Mg used (cyclopentadienyl magnesium), a band gap energy than the active layer is large, the first p-type nitride semiconductor layer 104 made of Mg-doped p-type Al0.1Ga0.9N 300 Å It grows with the film thickness of. Although the first p-type nitride semiconductor layer 104 is p-type in the present embodiment, since the film thickness is small, the i-type impurity is doped with n-type impurities to compensate for carriers.
Although it may be of a p-type, it is most preferably a p-type. The thickness of the first p-type nitride semiconductor layer 104 is adjusted to 0.1 μm or less, more preferably 500 Å or less, and most preferably 300 Å or less. 0.1
This is because if the layer is grown with a thickness larger than μm, cracks are easily formed in the first nitride semiconductor layer, and it is difficult to grow a nitride semiconductor layer having good crystallinity. In addition, carriers cannot pass through the energy barrier due to the tunnel effect. Also, when the AlGaN having a higher Al composition ratio is formed to be thinner, the LD element is more likely to oscillate. For example, in the case of Al _Y Ga ₁ -YN having a Y value of 0.2 or more, it is desirable to adjust the value to 500 Å or less. Although the lower limit of the thickness of the first nitride semiconductor layer 104 is not particularly limited, it is preferable that the first nitride semiconductor layer 104 be formed to have a thickness of 10 Å or more.

Subsequently, at 1050 ° C., a second p-type nitride semiconductor layer 105 made of Mg-doped p-type GaN having a band gap energy smaller than that of the first p-type nitride semiconductor layer 104 is formed into a 0.2 μm film. Grow in thickness. This layer functions as a light guide layer, and is preferably made of GaN or InGaN, like the second n-type nitride semiconductor 103. This layer is the third p-type nitride semiconductor layer 1
06 also acts as a buffer layer when growing
0 angstrom to 5 μm, more preferably 200
By growing the layer to a thickness of オ ン 1 μm to 1 μm, it functions as a preferable light guide layer.

Subsequently, at 1050 ° C., the band gap energy is higher than that of the second nitride semiconductor
A third p-type nitride semiconductor layer 106 made of g-doped p-type Al0.2Ga0.8N is grown to a thickness of 0.5 μm. This layer acts as a carrier confinement layer and a light confinement layer, like the first n-type nitride semiconductor layer 102, and
It is desirable to grow a nitride semiconductor, preferably AlGaN, containing 100 Å or more and 2 μm.
m, more preferably 500 Å or more and 1 μm or less, a carrier confinement layer with good crystallinity can be formed.

In the case of an active layer having a well layer made of InGaN as in this embodiment, a first p-type nitride semiconductor layer 104 containing Al having a thickness of 0.1 μm or less is provided in contact with the active layer. A second p-type nitride semiconductor layer 105 having a smaller gap energy than the first p-type nitride semiconductor layer is provided at a position farther from the active layer than the p-type nitride semiconductor layer; P-type nitride semiconductor layer 105
It is very preferable to provide a third p-type nitride semiconductor layer 106 made of a nitride semiconductor containing Al having a band gap larger than that of the second p-type nitride semiconductor layer at a position farther from the active layer than the second p-type nitride semiconductor layer. . Moreover, since the thickness of the first p-type nitride semiconductor layer 104 is set to be as thin as 0.1 μm or less, it does not act as a carrier barrier.
The holes injected from the p-layer can pass through the first p-type nitride semiconductor layer due to the tunnel effect, are efficiently recombined in the active layer, and the output of the LD is improved. That is,
The injected carriers are formed in the first p-type nitride semiconductor layer 10.
4, the carrier does not overflow the active layer even if the temperature of the semiconductor element rises or the injected current density increases, and the first p
Since the carriers are blocked by the type nitride semiconductor layer 104, carriers are accumulated in the active layer and light can be emitted efficiently.
Therefore, even if the temperature of the semiconductor element rises, the luminous efficiency is hardly reduced, so that an LD with a low threshold current can be realized.

Finally, the third p-type nitride semiconductor layer 106
Of p-type Mg-doped GaN at 1050 ° C.
The mold contact layer 4 is grown to a thickness of 0.5 μm.

After the completion of the reaction, the temperature is lowered to room temperature, the wafer is taken out of the reaction vessel, and the wafer is annealed at 700 ° C. to further reduce the resistance of the p-type layer.

After annealing, the uppermost p
Contact layer 4 and third p-type nitride semiconductor layer 106
Are etched to form a ridge shape having a stripe width of 2 μm. Thus, by forming the p-type layer above the active layer into a stripe-shaped ridge,
The light emission of the active layer is concentrated below the stripe ridge, and the threshold value decreases. Then, as shown in FIG. 3, a p-electrode 21 made of Ni and Au is formed on the surface of the p-type contact layer 4.
Are formed in a stripe shape. Since the p-electrode 21 is a laser element, it does not need to be particularly translucent. On the other hand, Ti
And an n-electrode 20 made of Al is formed on almost the entire surface of the n-type contact layer 1 on the side where the nitride semiconductor layer is not formed.

Next, the wafer is cleaved in a bar shape in a direction perpendicular to the stripe-shaped electrodes, and a resonator is formed on the cleaved surface. Since the substrate is made of GaN, the resonator can be easily manufactured using the cleavage properties of GaN. In this case, the cleavage plane is

[Outside 1] Face. The outer one surface is a surface corresponding to a square surface (M surface) corresponding to the side surface of the hexagonal prism when the nitride semiconductor is approximated by a hexagonal system of a regular hexagonal prism. In addition, the resonator can be manufactured by etching the end face by dry etching means such as RIE. In addition, the cleavage plane can be formed by mirror polishing.

After the cleavage, a dielectric multilayer film composed of SiO ₂ and TiO ₂ was formed on the resonator surface, and finally the bar was cut in a direction parallel to the p-electrode to form a laser chip. Then placed in the heat sink and tip face down (= p state electrode is opposed to the heat sink), it was tried laser oscillation at room temperature, at a threshold current density of 2 kA / cm ^2, the continuous oscillation of an oscillation wavelength of 400nm confirmed. Thus, GaN
When a substrate is used, face-down bonding can be easily performed, so that the heat radiation of the chip is significantly improved, and continuous oscillation can be performed.

[0070]

As described above, according to the method of the present invention, a device using a gallium nitride-based compound semiconductor as a substrate can be manufactured.
An electrode structure facing in the up-down direction can be used without having to take out a type of electrode. Further, since the chip size can be reduced, the number of chips to be taken from a single-area wafer increases, so that the cost can be reduced. Also,
Since GaN is a substrate, in a device such as an LD that requires a resonance surface close to a mirror surface, a resonance surface can be easily formed by cleavage of GaN, and its industrial utility value is very large.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a structure of a wafer for explaining each step of a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a structure of a wafer for explaining each step of a second embodiment of the present invention.

FIG. 3 is a schematic sectional view showing the structure of a laser device obtained by the method of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... n-type contact layer 2 ... active layer 3 ... p-type cladding layer 4 ... p-type contact layer 10 ... substrate 11 ... buffer layer 20 ... n-electrode 21 ...・ P electrode 22 ・ ・ ・ pad electrode

Claims (7)

[Claims] 1. An n-type nitride semiconductor layer having a thickness of 20 μm is formed on a substrate.
removing the substrate after growing the nitride semiconductor layer containing the acceptor impurity, and growing the nitride semiconductor layer containing at least the acceptor impurity on the n-type nitride semiconductor layer. And a method for manufacturing a nitride semiconductor device. 2. The method according to claim 1, wherein the substrate is made of spinel. 3. The method according to claim 1, further comprising, after growing the nitride semiconductor layer containing the acceptor impurity, annealing in an atmosphere containing a nitrogen source, and thereafter annealing in an atmosphere containing no hydrogen source. 3. The method for manufacturing a nitride semiconductor device according to item 2. 4. A step of growing an n-type nitride semiconductor layer on the spinel substrate to a thickness of 20 μm or more, a step of removing the substrate after growing the n-type nitride semiconductor layer, and an step of removing the n-type nitride after removing the substrate. A method for manufacturing a nitride semiconductor device, comprising a step of growing at least a nitride semiconductor layer containing an acceptor impurity on a semiconductor layer. 5. After the growth of the n-type nitride semiconductor layer, the n-type nitride semiconductor
The method for manufacturing a nitride semiconductor according to claim 4, wherein the surface of the nitride semiconductor layer is mirror-finished. 6. A step of annealing the n-type nitride semiconductor in an atmosphere containing a nitrogen source after removing the substrate, and thereafter annealing in an atmosphere containing no hydrogen source after growing a nitride semiconductor layer containing an acceptor impurity. 6. The method for manufacturing a nitride semiconductor device according to claim 4, further comprising the steps of: 7. The n-type nitride semiconductor layer, wherein the carrier concentration on the side close to the p-type nitride semiconductor layer is reduced and the carrier concentration on the side away from the p-type nitride semiconductor is increased. The method for manufacturing a nitride semiconductor according to any one of claims 1 to 7, wherein: