JP5917673B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device manufacturing method and a semiconductor device.
Semiconductor integrated circuits, in particular, integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. As the miniaturization of MOS transistors progresses, there is a problem that it is difficult to suppress the leakage current, and the area occupied by the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds a columnar semiconductor layer has been proposed (for example, Patent Documents). 1, Patent Document 2, Patent Document 3).

  By using metal instead of polysilicon for the gate electrode, depletion can be suppressed and the resistance of the gate electrode can be reduced. However, the post-process after forming the metal gate must always be a manufacturing process that considers metal contamination by the metal gate.

  Further, in a conventional MOS transistor, in order to achieve both a metal gate process and a high temperature process, a metal gate last process for creating a metal gate after a high temperature process is used in an actual product (Non-Patent Document 1). After forming a gate with polysilicon, an interlayer insulating film is deposited, then the polysilicon gate is exposed by chemical mechanical polishing, and after etching the polysilicon gate, a metal is deposited. Therefore, also in SGT, in order to make a metal gate process and a high temperature process compatible, it is necessary to use the metal gate last process which produces a metal gate after a high temperature process. In SGT, since the upper part of the columnar silicon layer is higher than the gate, it is necessary to devise for using the metal gate last process.

  In the metal gate last process, after a polysilicon gate is formed, a diffusion layer is formed by ion implantation. In SGT, since the upper part of the columnar silicon layer is covered with the polysilicon gate, a device is required.

When the silicon pillar is thinned, the density of silicon is 5 × 10 ²² pieces / cm ³ , so that it becomes difficult for impurities to exist in the silicon pillar.

In the conventional SGT, it is proposed to determine the threshold voltage by changing the work function of the gate material by setting the channel concentration to a low impurity concentration of 10 ¹⁷ cm ⁻³ or less (see, for example, Patent Document 4). ).

  In the planar MOS transistor, the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer, and the surface carrier of the LDD region is induced by the work function difference, so that the oxide film sidewall LDD type MOS It has been shown that the impedance of the LDD region can be reduced as compared with a transistor (see, for example, Patent Document 5). The polycrystalline silicon sidewall is shown to be electrically insulated from the gate electrode. In the figure, it is shown that the polysilicon side wall and the source / drain are insulated by an interlayer insulating film.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2004-356314 A JP 11-297984 A

IEDM2007 K. Mistry et.al, pp 247-250 IEDM2010 CC. Wu, et.al, 27.1.1-27.1.4.

  Accordingly, the present invention provides an SGT manufacturing method that is a gate last process, and an SGT having a structure in which an upper portion of a columnar semiconductor layer functions as an n-type semiconductor layer or a p-type semiconductor layer by a work function difference between a metal and a semiconductor. The purpose is to do.

  According to the method of manufacturing a semiconductor device of the present invention, a fin-shaped semiconductor layer is formed on a semiconductor substrate, a first insulating film is formed around the fin-shaped semiconductor layer, and a columnar semiconductor layer is formed on the fin-shaped semiconductor layer. A first step of forming a second insulating film, a polysilicon gate electrode, and a polysilicon gate wiring after the first step, wherein the second insulating film is formed in the columnar shape. Covers the periphery and top of the semiconductor layer, and the polysilicon gate electrode covers the second insulating film. After the second step, a diffusion layer is formed above the fin-like semiconductor layer and below the columnar silicon layer. After the third step, after the third step, a fourth step of forming a metal and semiconductor compound on the diffusion layer above the fin-like semiconductor layer, and after the fourth step, an interlayer insulating film is formed. Depositing the polysilicon gate electrode And a fifth step of exposing the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, depositing a first metal, and forming a metal gate electrode and a metal gate wiring; And a sixth step of forming a sidewall made of a third metal on the upper side wall of the columnar semiconductor layer after the fifth step, and the sidewall made of the third metal and the upper surface of the columnar semiconductor layer are It is connected.

  In the first step, a first resist for forming a fin-like semiconductor layer is formed on a semiconductor substrate, the semiconductor substrate is etched, the fin-like semiconductor layer is formed, and the first resist is formed. Removing, depositing a first insulating film around the fin-shaped semiconductor layer, etching back the first insulating film, exposing an upper portion of the fin-shaped semiconductor layer, and orthogonal to the fin-shaped semiconductor layer Thus, the second resist is formed, the fin-like semiconductor layer is etched, and the second resist is removed, so that the portion where the fin-like semiconductor layer and the second resist are orthogonal is the columnar silicon. The columnar semiconductor layer is formed to be a layer.

  The second step is formed on the fin-shaped semiconductor layer, a fin-shaped semiconductor layer formed on the semiconductor substrate, a first insulating film formed around the fin-shaped semiconductor layer, and the fin-shaped semiconductor layer. A second insulating film is formed in a structure having a columnar semiconductor layer, polysilicon is deposited, and the upper surface of the polysilicon after planarizing the polysilicon is the second insulating film above the columnar semiconductor layer. Planarizing to a higher position, depositing a first nitride film, forming a third resist for forming a polysilicon gate electrode and polysilicon gate wiring, and etching the first nitride film Etching the polysilicon, forming the polysilicon gate electrode and the polysilicon gate wiring, etching the second insulating film, and removing the third resist.

  In the fourth step, a second nitride film is deposited, the second nitride film is etched, remains in a sidewall shape, a second metal is deposited, and a compound of the metal and the semiconductor is formed into a fin shape. It is characterized by being formed above the diffusion layer above the semiconductor layer.

  In the fifth step, a third nitride film is deposited, an interlayer insulating film is deposited and planarized, a polysilicon gate electrode and a polysilicon gate wiring are exposed, and the exposed second nitride film and the first nitride film are exposed. 3 is removed, the polysilicon gate electrode, the polysilicon gate wiring and the second insulating film are removed, a gate insulating film is deposited, and the polysilicon gate electrode and the polysilicon gate wiring are The first metal is buried in the portion, the first metal is etched, the gate insulating film above the columnar silicon layer is exposed, and a metal gate electrode and a metal gate wiring are formed.

  In the sixth step, the upper part of the columnar semiconductor layer is exposed, the third metal is deposited, the third metal is etched, and the columnar semiconductor layer upper sidewall is made of the third metal. A side wall is formed.

  The semiconductor device of the present invention is formed on the fin-like semiconductor layer, the fin-like semiconductor layer formed on the semiconductor substrate, the first insulating film formed around the fin-like semiconductor layer, and the fin-like semiconductor layer. A columnar semiconductor layer; a diffusion layer formed above the fin-like semiconductor layer; and a lower portion of the columnar semiconductor layer; a metal-semiconductor compound formed above the diffusion layer above the fin-like semiconductor layer; A gate insulating film formed around the columnar semiconductor layer; a metal gate electrode formed around the gate insulating film; a metal gate wiring connected to the metal gate electrode; and an upper sidewall of the columnar semiconductor layer A side wall made of a third metal, and the side wall made of the third metal and the upper surface of the columnar semiconductor layer are connected to each other.

  Further, the width of the columnar semiconductor layer is the same as the shorter width of the fin-shaped semiconductor layer.

  In addition, a sidewall made of the third metal is formed on the upper side wall of the columnar semiconductor layer with an insulating film interposed therebetween.

  The semiconductor layer is a silicon layer.

  Further, the diffusion layer is an n-type diffusion layer, and the work function of the third metal is between 4.0 eV and 4.2 eV.

  The diffusion layer is a p-type diffusion layer, and the work function of the third metal is between 5.0 eV and 5.2 eV.

  In addition, a sidewall made of the third metal is formed on the upper side wall of the columnar semiconductor layer with an insulating film interposed therebetween.

  According to the present invention, there is provided an SGT manufacturing method that is a gate last process, and an SGT having a structure in which an upper portion of a columnar semiconductor layer functions as an n-type semiconductor layer or a p-type semiconductor layer by a work function difference between a metal and a semiconductor. can do.

  If the metal gate last process is applied to SGT, the upper part of the columnar semiconductor layer is covered with the polysilicon gate, so that it is difficult to form a diffusion layer on the upper part of the columnar semiconductor layer. Therefore, a diffusion layer is formed on the columnar semiconductor layer before forming the polysilicon gate. On the other hand, in the present invention, the diffusion layer is not formed on the upper part of the columnar semiconductor layer, and the upper part of the columnar semiconductor layer can function as an n-type semiconductor layer or a p-type semiconductor layer depending on a work function difference between the metal and the semiconductor. Therefore, it is possible to reduce the step of forming the diffusion layer on the columnar semiconductor layer.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a first resist for forming a fin-shaped semiconductor layer is formed on a semiconductor substrate, the semiconductor substrate is etched, the fin-shaped semiconductor layer is formed, the first resist is removed, and the fin-shaped semiconductor layer is removed. A first insulating film is deposited around the semiconductor layer, the first insulating film is etched back, an upper portion of the fin-like semiconductor layer is exposed, and a second resist is formed so as to be orthogonal to the fin-like semiconductor layer. Forming the columnar silicon layer by etching the fin-like semiconductor layer and removing the second resist so that the portion where the fin-like semiconductor layer and the second resist are orthogonal to each other becomes the columnar silicon layer. The 1st process of forming a semiconductor layer is shown. In this embodiment, silicon is used as the material for the semiconductor substrate, but a semiconductor material other than silicon can also be used.

  As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used as the mask.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. As the first insulating film, an oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition may be used.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed.

  As shown in FIG. 7, a second resist 105 is formed so as to be orthogonal to the fin-like silicon layer 103. A portion where the fin-like silicon layer 103 and the resist 105 are orthogonal to each other is a portion that becomes a columnar silicon layer. Since a line-shaped resist can be used, the possibility that the resist falls after patterning is low, and the process is stable.

  As shown in FIG. 8, the fin-like silicon layer 103 is etched. A portion where the fin-like silicon layer 103 and the second resist 105 are orthogonally becomes the columnar silicon layer 106. Therefore, the width of the columnar silicon layer 106 is the same as the width of the fin-like silicon layer. A columnar silicon layer 106 is formed on the fin-shaped silicon layer 103, and a first insulating film 104 is formed around the fin-shaped silicon layer 103.

  As shown in FIG. 9, the second resist 105 is removed.

  Thus, the first resist for forming the fin-like semiconductor layer is formed on the semiconductor substrate, the semiconductor substrate is etched, the fin-like semiconductor layer is formed, the first resist is removed, and the fin A first insulating film is deposited around the semiconductor layer, the first insulating film is etched back, an upper portion of the fin-like semiconductor layer is exposed, and a second insulating film is perpendicular to the fin-like semiconductor layer. The resist is formed, the fin-like semiconductor layer is etched, and the second resist is removed, so that the portion where the fin-like semiconductor layer and the second resist are orthogonal to each other becomes the columnar silicon layer. The first step of forming the columnar semiconductor layer is shown.

  Next, a second insulating film is formed, polysilicon is deposited, and the upper surface of the polysilicon after planarizing the polysilicon is positioned higher than the second insulating film above the columnar semiconductor layer. Planarizing, depositing a first nitride film, forming a third resist for forming a polysilicon gate electrode and polysilicon gate wiring, etching the first nitride film, etching the polysilicon; 2 shows a second step of forming the polysilicon gate electrode and the polysilicon gate wiring, etching the second insulating film, and removing the third resist.

  As shown in FIG. 10, a second insulating film 113 is formed, and polysilicon 114 is deposited and planarized. The upper surface of the planarized polysilicon is higher than the second insulating film 113 above the columnar silicon layer 106. Thus, when the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after depositing the interlayer insulating film, the upper part of the columnar silicon layer is not exposed by chemical mechanical polishing. As the second insulating film, an oxide film or a thermal oxide film by deposition is preferable. A first nitride film 115 is deposited. The first nitride film 115 is a film that inhibits formation of silicide on the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed on the fin-like silicon layer.

  As shown in FIG. 11, the 3rd resist 116 for forming a polysilicon gate electrode and a polysilicon gate wiring is formed. It is desirable that a portion to be a gate wiring is orthogonal to the fin-like silicon layer 103. This is because the parasitic capacitance between the gate wiring and the substrate is reduced.

  As shown in FIG. 12, the first nitride film 115 is etched.

  As shown in FIG. 13, the polysilicon 114 is etched to form a polysilicon gate electrode 114a and a polysilicon gate wiring 114b.

  As shown in FIG. 14, the second insulating film 113 is etched.

  As shown in FIG. 15, the third resist 116 is removed.

  Thus, the second insulating film is formed, polysilicon is deposited, and the upper surface of the polysilicon after planarizing the polysilicon is positioned higher than the second insulating film above the columnar semiconductor layer. Planarizing, depositing a first nitride film, forming a third resist for forming a polysilicon gate electrode and polysilicon gate wiring, etching the first nitride film, etching the polysilicon; The second step of forming the polysilicon gate electrode and the polysilicon gate wiring, etching the second insulating film, and removing the third resist is shown.

  Next, a third step of forming a diffusion layer above the fin-like semiconductor layer and below the columnar silicon layer will be described.

  As shown in FIG. 16, an impurity such as arsenic or phosphorus is implanted for nMOS and boron or BF2 is implanted for pMOS, and heat treatment is performed. Form. At this time, since the upper part of the columnar silicon layer 106 is covered with the polysilicon gate electrode, no diffusion layer is formed.

  Thus, the third step of forming the diffusion layer on the fin-like semiconductor layer and on the columnar silicon layer is shown.

  Next, a second nitride film is deposited, the second nitride film is etched, remains in a sidewall shape, a second metal is deposited, and a metal-semiconductor compound is deposited on the upper portion of the fin-like semiconductor layer. The 4th process formed in the upper part of a diffusion layer is shown.

  As shown in FIG. 17, a second nitride film 117 is deposited.

  As shown in FIG. 18, the second nitride film 117 is etched and left in a sidewall shape.

  As shown in FIG. 19, a second metal such as nickel or cobalt is deposited, and a compound of metal and semiconductor, that is, silicide 118 is formed on the diffusion layer 112 above the fin-like silicon layer 103. At this time, the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are covered with the second nitride film 117 and the first nitride film 115, and the upper part of the columnar silicon layer 106 is the second insulating film 113 and the polysilicon gate. Since it is covered with the electrode 114a and the polysilicon gate wiring 114b, no silicide is formed.

  As described above, the second nitride film is deposited, the second nitride film is etched, remains in the sidewall shape, the second metal is deposited, and the compound of the metal and the semiconductor is deposited on the upper part of the fin-shaped semiconductor layer. A fourth step of forming on the diffusion layer is shown.

  Next, a third nitride film is deposited, an interlayer insulating film is deposited and planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, and the exposed second nitride film and third nitride film are exposed. Removing, removing the polysilicon gate electrode, the polysilicon gate wiring and the second insulating film, depositing a gate insulating film, and in the portion where the polysilicon gate electrode and the polysilicon gate wiring are present. A fifth step of embedding the metal, etching the first metal, exposing the gate insulating film above the columnar silicon layer, and forming a metal gate electrode and a metal gate wiring is shown.

  As shown in FIG. 20, a third nitride film 119 is deposited to protect the silicide 118.

  As shown in FIG. 21, an interlayer insulating film 120 is deposited and planarized by chemical mechanical polishing.

  As shown in FIG. 22, the interlayer insulating film 120 is etched back to expose the second nitride film 115 and the third nitride film 119 that cover the polysilicon gate electrode 114a and the polysilicon gate wiring 114b.

  As shown in FIG. 23, the exposed second nitride film 115 and third nitride film 119 are removed, and the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are exposed. The etching used for removing the second nitride film 115 and the third nitride film 119 is preferably isotropic etching or wet etching.

  As shown in FIG. 24, the exposed polysilicon gate electrode 114a and polysilicon gate wiring 114b are removed. The etching at this time is also preferably isotropic etching or wet etching.

  As shown in FIG. 25, the second insulating film 113 is removed.

  As shown in FIG. 26, a gate insulating film 121 and a first metal 122 are deposited. The first metal 122 is buried in the portion where the polysilicon gate electrode 114a and the polysilicon gate wiring 114b exist. It is preferable to use atomic layer deposition for this embedding. As the gate insulating film 121, a film generally used in a semiconductor process such as an oxide film, an oxynitride film, and a high dielectric film can be used. The first metal 122 may be any metal that is used in a semiconductor process and sets a threshold voltage of a transistor. At this time, when the work function of the first metal 112 is between 4.2 eV and 5.0 eV, the first metal 112 can operate as an enhancement type.

  As shown in FIG. 27, the 1st metal 122 is etched and the gate insulating film 121 on the columnar silicon layer 106 is exposed. Thereby, the metal gate electrode 122a and the metal gate wiring 122b are formed.

  Thus, the third nitride film is deposited, the interlayer insulating film is deposited and planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, and the exposed second nitride film and third nitride film are removed. Removing, removing the polysilicon gate electrode, the polysilicon gate wiring and the second insulating film, depositing a gate insulating film, and in the portion where the polysilicon gate electrode and the polysilicon gate wiring are present. The fifth step of embedding the metal, etching the first metal, exposing the gate insulating film above the columnar silicon layer, and forming the metal gate electrode and the metal gate wiring is shown.

  Next, an upper portion of the columnar semiconductor layer is exposed, the third metal is deposited, the third metal is etched, and a sidewall made of the third metal is formed on the upper sidewall of the columnar semiconductor layer. 6th process is shown.

  As shown in FIG. 28, an oxide film 123 is deposited.

  As shown in FIG. 29, the oxide film 123 is etched back and left on the upper surface of the metal gate electrode 122a. The etching at this time is preferably isotropic etching. At this time, the upper part of the columnar silicon layer 106 is exposed.

  As shown in FIG. 30, a third metal 124 is deposited.

  When the work function of the third metal 124 is between 4.0 eV and 4.2 eV, it is in the vicinity of the work function of n-type silicon 4.05 eV, so that the upper part of the columnar silicon layer 106 functions as n-type silicon. To do. As the third metal 124 at this time, for example, a compound of tantalum and titanium (TaTi) or tantalum nitride (TaN) is preferable.

  When the work function of the third metal 124 is between 5.0 eV and 5.2 eV, the work function of the p-type silicon is in the vicinity of 5.15 eV, so that the upper part of the columnar silicon layer 106 functions as p-type silicon. To do. As the third metal 124 at this time, for example, ruthenium (Ru) or titanium nitride (TiN) is preferable.

  As shown in FIG. 31, the third metal 124 is etched to form a side wall made of the third metal 124 on the upper side wall of the columnar silicon layer 106. When the gate insulating film 121 remains on the side wall of the columnar silicon layer 106, a side wall made of the third metal 124 is formed on the upper side wall of the columnar silicon layer 106 with the insulating film 121 interposed therebetween.

  As described above, the upper portion of the columnar semiconductor layer is exposed, the third metal is deposited, the third metal is etched, and a sidewall made of the third metal is formed on the upper sidewall of the columnar semiconductor layer. A sixth step was indicated.

  Next, a process of forming a contact and a metal wiring is shown.

  As shown in FIG. 32, an interlayer insulating film 125 is deposited, planarized, and etched back to expose the upper surface of the columnar silicon layer 106 and the upper surface of the side wall made of the third metal 124.

  As shown in FIG. 33, the 4th resist 126 for forming a contact hole on the metal gate wiring 122b and the fin-like silicon layer 103 is formed.

  As shown in FIG. 34, the interlayer insulating films 120 and 125 and the oxide film 123 are etched to form contact holes 127 and 128.

  As shown in FIG. 35, the 4th resist 126 is removed.

  As shown in FIG. 36, the third nitride film 119 is etched to expose the silicide 118.

  As shown in FIG. 37, metal 129 is deposited. Thereby, the contacts 130 and 131 are formed. At this time, the sidewall made of the third metal 124 and the upper surface of the columnar silicon layer 106 are connected. Therefore, the same potential is applied to the upper part of the columnar silicon layer 106 and the sidewall made of the third metal 124. In the upper part of the columnar silicon layer 106, carriers are induced by the work function difference between the third metal 124 and silicon.

  As shown in FIG. 38, the 5th resist 132, 133, 134 for forming metal wiring is formed.

  As shown in FIG. 39, the metal 129 is etched to form metal wirings 135, 136, and 137.

  As shown in FIG. 40, the 5th resists 132, 133, and 134 are removed.

  As described above, the process of forming the contact and the metal wiring is shown.

  The result of the manufacturing method is shown in FIG.

  A fin-like silicon layer 103 formed on the silicon substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and a columnar silicon layer 106 formed on the fin-like silicon layer 103. A diffusion layer 112 formed above the fin-like silicon layer 103 and below the columnar silicon layer 106; and a metal / semiconductor compound formed above the diffusion layer 112 above the fin-like silicon layer 103. 118, a gate insulating film 121 formed around the columnar silicon layer 106, a metal gate electrode 122a formed around the gate insulating film 121, and a metal gate wiring 122b connected to the metal gate electrode 112a And a side wall made of the third metal 124 formed on the upper side wall of the columnar silicon layer 106. And, side wall and the pillar-shaped silicon layer 106 top surface made of the third metal 124 is characterized in that it is connected.

  A diffusion layer is not formed on the columnar silicon layer 106, and the upper portion of the columnar silicon layer 106 can function as an n-type semiconductor layer or a p-type semiconductor layer depending on a work function difference between a metal and a semiconductor. Therefore, it is possible to reduce the step of forming the diffusion layer on the columnar silicon layer 106.

In addition, since no diffusion layer is formed on the upper part of the columnar silicon layer, if the silicon column is thinned, the density of silicon is 5 × 10 ²² pieces / cm ³ , so that it is difficult to make impurities exist in the silicon column. The problem can be avoided.

  As described above, the manufacturing process and structure for forming the structure of the SGT according to the embodiment of the present invention are shown.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.

101. Silicon substrate 102. First resist 103. Fin-like silicon layer 104. First insulating film 105. Second resist 106. Columnar silicon layer 112. Diffusion layer 113. Second insulating film 114. Polysilicon 114a. Polysilicon gate electrode 114b. Polysilicon gate wiring 115. First nitride film 116. Third resist 117. Second nitride film 118. Silicide 119. Third nitride film 120. Interlayer insulating film 121. Gate insulating film 122. First metal 122a. Metal gate electrode 122b. Metal gate wiring 123. Oxide film 124. Third metal 125. Interlayer insulating film 126. Fourth resist 127. Contact hole 128. Contact hole 129. Metal 130. Contact 131. Contact 132. Fifth resist 133. Fifth resist 134. Fifth resist 135. Metal wiring 136. Metal wiring 137. Metal wiring

Claims (5)

A fin-like semiconductor layer formed on a semiconductor substrate;
A first insulating film formed around the fin-like semiconductor layer;
A columnar semiconductor layer formed on the fin-shaped semiconductor layer;
A diffusion layer formed above the fin-like semiconductor layer and below the columnar semiconductor layer;
A gate insulating film formed around the columnar semiconductor layer;
A metal gate electrode formed around the gate insulating film;
A metal gate wiring connected to the metal gate electrode;
A sidewall made of a third metal formed on an upper side wall of the columnar semiconductor layer via an insulating film ,
Wherein a that are connected by the metal and the pillar-shaped semiconductor layer top surface and the sidewall upper surface made of the third metal.   2. The semiconductor device according to claim 1, wherein the width of the columnar semiconductor layer is the same as the shorter width of the fin-shaped semiconductor layer. The semiconductor layer, the semiconductor device according to any one of claims 1 to 2, characterized in that a silicon layer. The diffusion layer is a n-type diffusion layer, the work function of the third metal, according to any one of claims 1 to 3, characterized in that is between 4.0eV of 4.2eV Semiconductor device. The diffusion layer is a p-type diffusion layer, the work function of the third metal, according to any one of claims 1 to 3, characterized in that is between 5.0eV of 5.2eV Semiconductor device.

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