JP5892083B2 - Parameter setting device, parameter setting program and parameter setting method - Google Patents

Description

  The present invention relates to a parameter setting device, a parameter setting program, and a parameter setting method.

  A fault-tolerant server (hereinafter referred to as FT server: Fault Tolerant server) is a system that includes two systems and enables these two systems to operate in synchronization. In the FT server, all hardware modules constituting the system are multiplexed. All hardware modules are operating synchronously. That is, for each clock, the internal logic states of the two systems are exactly the same. Such a state is called a lock step. In the FT server, even if a failure occurs in a certain part, the hardware module related to this part is disconnected, and the process is continued with another normal hardware module equivalent to this part. Due to this feature, the FT server is more fault tolerant than a normal server.

  However, it is difficult to realize an operation of dynamically changing the clock frequency in the FT server. When the clock is dynamically changed, each CPU (Central Processor Unit) changes the clock at different timings, so that the two systems start to move differently from each other. As a result, the FT server cannot maintain the lock step state that is a feature of the FT server. The reason for the different timing is that there is a difference in temperature or the like in the environment where the two hardware modules are placed.

In order to prevent such disturbance of the lock step, in the FT server, the turbo mode of the processor has to be always set to an invalid state (Disable). The turbo mode is a function of monitoring the temperature or the like and dynamically changing the frequency in an analog manner according to the situation. However, this function is not effectively used in the FT server for the above reason.
For the same reason, the voltage limiting function is not used.

  Patent Document 1 discloses a processor having a separation / combination instruction unit that couples two processor devices or separates two coupled processor devices, and a state storage unit that stores clock synchronization states before and after the combination / separation. An apparatus is disclosed.

  Patent Document 2 discloses an FT system in which two systems each having a CPU, an FT control unit, and a south bridge are coupled with each other by the FT control unit, and even if the south bridge fails, the standby south Insist on an effect that can be exchanged with a bridge.

  In Patent Document 3, a master processor among a plurality of processors connected to a bus dynamically changes the clock frequency of the plurality of processors by issuing a bus transaction for switching the clock frequency to the bus. It is disclosed.

JP-A-10-293697 JP 2006-178659 A JP2002-23848

Patent Document 1 discloses storing the clock synchronization states of two processor devices before and after combining, but there is no disclosure about changing the clocks of two processor devices at the same time. Patent Document 2 discloses that the two systems and the south bridge operate synchronously, but there is no disclosure about changing the clocks of two processor devices at the same time.
Patent Document 3 discloses that the frequencies of a plurality of processors are dynamically changed when a bus transaction is issued, but the timings of the changes are not necessarily the same.

  An object of the present invention is to simultaneously change operating parameters such as clock frequency and operating voltage of two CPUs in an information processing apparatus to the same value.

According to the present invention, a first processor, as well as connected to a second processor connected to the other device operating in synchronization with its own device, the first clock is a clock frequency of said first processor and said second processor And a setting means for changing the first clock of the first processor based on an output from the control means , the predetermined timing being determined by the first timing. The timing at which the rising or falling edge of the second clock obtained by dividing one clock is detected, and the control means sends a change request designating the change value and the predetermined timing to the first processor and the other device. When the rising edge or the falling edge of the second clock is detected after the reception of the change value, the change value is inputted to the setting means and the other device. Output to, the setting means, wherein at the detected next rise of the first clock rising or falling edge of the second clock, the parameters for changing the first clock of the first processor to the change value A setting device is obtained.

According to the present invention, the clock of the first processor and the second processor is connected to the computer of the parameter setting device that is connected to the first processor and the other device that is connected to the second processor and operates in synchronization with the own processor. A first process for outputting a change value of the first clock, which is a frequency, triggered by a predetermined timing, and a second process for changing the first clock of the first processor based on an output in the first process are executed. The predetermined timing is a timing at which a rising or falling edge of a second clock obtained by dividing the first clock is detected, and the first process includes the change value and the predetermined timing. After receiving a change request designating the timing from the first processor and the other device, the rise of the second clock Alternatively, when a falling edge is detected, the second process includes a process of outputting the change value. The second process includes the first clock rising at the rising edge of the first clock next to the rising edge or the falling edge of the detected second clock. A parameter setting program including a process of changing the first clock of the processor to the change value is obtained.
According to the present invention, the clock of the first processor and the second processor is connected to the computer of the parameter setting device that is connected to the first processor and the other device that is connected to the second processor and operates in synchronization with the own processor. A first process for outputting a change value of the first clock, which is a frequency, triggered by a predetermined timing, and a second process for changing the first clock of the first processor based on an output in the first process are executed. The predetermined timing is a timing at which a rising or falling edge of a second clock obtained by dividing the first clock is detected, and the first process includes the change value and the predetermined timing. A change request designating the timing is received from the first processor, and the change request is notified to the other device. After receiving an acknowledgment signal from the device, the second value includes a process of outputting the change value when the rising or falling edge of the second clock is detected, and the second process includes the detected rising or falling edge of the second clock. A parameter setting program including a process of changing the first clock of the first processor to the change value at the rise of the first clock next to the fall is obtained.

According to the present invention, the parameter setting device connected to the first processor and the other device connected to the second processor and operating in synchronism with the own processor is provided at a clock frequency of the first processor and the second processor. A parameter setting method for outputting a change value of a first clock to the other device at a predetermined timing, and changing the first clock of the first processor based on the change value. The timing is a timing at which a rising or falling edge of a second clock obtained by dividing the first clock is detected, and a change request designating the change value and the predetermined timing is sent to the first processor and the other device. When the rising edge or the falling edge of the second clock is detected after receiving from the above, the change value is output to the other device. Wherein at the detected next rise of the first clock rising or falling edge of the second clock, a parameter setting method of changing the first clock of the first processor to the change value is obtained.
According to the present invention, the parameter setting device connected to the first processor and the other device connected to the second processor and operating in synchronism with the own processor is provided at a clock frequency of the first processor and the second processor. A parameter setting method for outputting a change value of a first clock to the other device at a predetermined timing, and changing the first clock of the first processor based on the change value. The timing is a timing at which a rising or falling edge of a second clock obtained by dividing the first clock is detected, a change request designating the change value and the predetermined timing is received from the first processor, and After the change request is notified to the other device and an acknowledgment signal is received from the other device, the second clock rises. Alternatively, when the falling edge is detected, the change value is output to the other device, and at the rising edge of the first clock next to the detected rising edge or falling edge of the second processor, the first value of the first processor is output. A parameter setting method for changing one clock to the changed value is obtained.

  In the present invention, it is possible to simultaneously change the operating parameters of the two processors in the information processing apparatus to the same value.

FIG. 1 is a block diagram showing the configuration of the present invention. FIG. 2 is a diagram for explaining the transition of the state machine constituting the control logic circuit of the present invention. FIG. 3 shows a timing diagram of the first embodiment of the present invention. FIG. 4 is a flowchart showing the operation of the first exemplary embodiment of the present invention. FIG. 5 shows a timing diagram of the second embodiment of the present invention. FIG. 6 is a flowchart showing the operation of the second exemplary embodiment of the present invention. FIG. 7 is a block diagram showing the configuration of the third exemplary embodiment of the present invention.

(First embodiment)
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration diagram of the embodiment.

  The fault tolerant computer system (hereinafter referred to as FT system 100) is configured by connecting two subsystems, subsystem 10 and subsystem 20. The internal logic states of subsystem 10 and subsystem 20 are exactly the same for each clock at any time during operation. That is, the fault tolerance computer 100 operates in a state called a lock step.

  In the subsystem 10, a CPU 11, a parameter setting device 40, a first clock generator 14 that generates a base clock, and a frequency divider 15 that generates a second clock generator 16 are mounted on one board. The parameter setting device 40 includes a setting unit 12 that changes the clock of the CPU 11 and a control logic circuit 13 that includes a memory and a waiting logic circuit. The clock signal generated by the second clock generator 16 is also called a slow clock or a global alignment signal. The frequency of the clock signal generated by the second clock generator 16 is lower than the frequency of the clock signal generated by the first clock generator 14.

  In the subsystem 20, a CPU 21 having the same specifications as the CPU 11 and a parameter setting device 50 having the same specifications as the parameter setting device 40 are mounted on one board. The parameter setting device 50 includes a setting unit 22 having the same specifications as the setting unit 12 and a control logic circuit 23 having the same specifications as the control logic circuit 13. The control logic circuit 13 and the control logic circuit 23 are configured by a state machine.

  The subsystem 10 and the subsystem 20 are connected via a backplane and configured as one computer system as a whole. The control logic circuit 13 and the control logic circuit 23 may be referred to as a control unit 30. Subsystem 10 and subsystem 20 operate synchronously in lockstep. Therefore, even if one of the subsystem 10 and the subsystem 20 fails, the FT computer 100 performs the same operation as before the failure by causing the non-failed subsystem to take over the function of the failed subsystem. Can continue.

  One or several signal lines are connected between the CPU 11 and the setting unit 12 and between the CPU 21 and the setting unit 22. One or several signal lines are connected between the setting unit 12 and the control logic circuit 13, between the setting unit 22 and the control logic circuit 23, and between the control logic circuit 13 and the control logic circuit 23. ing. These signals are used to convey the state transition of one subsystem to the other, or to convey a clock change instruction.

  The first clock generator 14 is connected to the control logic circuit 13 and the control logic circuit 23. The second clock generator 16 is used to match the timing of the clock change between the two subsystems. The frequency of the clock signal generated by the second clock generator 16 is one tenth of the clock frequency generated by the first clock generator 14.

  The clock signal of the second clock generator 16 is obtained by dividing the clock signal of the first clock generator 14 by several tens of times by the frequency divider 15. The first clock generator 14 and the second clock generator 16 are mounted in one of the subsystems, and the clock signal generated by these is also supplied to the other subsystem. In this embodiment, the first clock generator 14 and the second clock generator 16 are mounted on the subsystem 10, and the signals are also supplied to the subsystem 20. By reducing the frequency of the second clock generator 16 to a low frequency that is not affected by variations between boards, the rising edge and the falling edge can be accurately detected.

  The first clock generator 14 includes a crystal oscillator or a ceramic oscillator. The phase of the clock signal of the first clock generator 14 is adjusted by a delay circuit (not shown) so as to be supplied to the boards of the subsystem 10 and the subsystem 20 at exactly the same timing.

  The control logic circuit 13 and the control logic circuit 23 are designed to operate in synchronization with each other. In other words, these two logic circuits are designed so that the timings for changing the clock frequency or voltage of the CPU to the setting unit 12 and the setting unit 22 connected to each other coincide with each other. The signal generated by the first clock generator 14 is called a first clock, and the signal generated by the second clock generator 16 is called a second clock. The control logic circuit 13 and the control logic circuit 23 are designed to perform state machine control. The logic state of the control logic circuit 23 is exactly the same as that of the control logic circuit 13 because of the lock step state. Accordingly, the timing of the change instruction set in the control logic circuit 13 is also set to the same timing in the control logic circuit 23.

  In the description on the left, the same conclusion can be reached even if the control logic circuit 13 and the control logic circuit 23 are interchanged. The setting unit 12, the setting unit 22, the control logic circuit 13, and the control logic circuit 23 may be realized by hardware configured by combining logic elements, or may be realized by software that executes a computer program.

  Next, the operation of the first exemplary embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a state machine transition diagram showing state transitions of the control logic circuit 13 and the control logic circuit 23. The control logic circuit 13 and the control logic circuit 23 set “WAIT” to wait for the clock change request of the own device, “other system standby” to wait for the clock change request of the other device, and change instruction timing. It includes four states: “clock change trigger” and “end”.

  FIG. 3 represents a timing diagram of the FT system 100. In the following description, the subsystem 10 is the own device and the subsystem 20 is the other device (also called another system). After initialization, the subsystem 10 is in a “WAIT” state waiting for its own clock change request from its own CPU 11 (own device state 1). After receiving the own clock change request, the subsystem 10 transitions to a “other system standby” state in which the subsystem 20 which is another device waits for a clock change request. After receiving the clock change request from the subsystem 20, the subsystem 10 transitions to a “clock change trigger” state in which the change instruction timing is set.

  On the other hand, the subsystem 20 is in a “WAIT” state waiting for a clock change request from the CPU 21 (another device state 2). The subsystem 20 receives the change request from the CPU 21, transitions to the “other system standby” state, and then transitions to the “clock change trigger” state simultaneously with the subsystem 10. When the next rising edge of the second clock is designated as a change trigger in the state of “clock change trigger”, the CPU 11 and CPU 12 are detected when the next rising edge of the second clock (in the circle in FIG. 3) is detected. Is sent from the setting unit 12 and the setting unit 22. The second clock is set to a frequency sufficiently lower than the first clock. For this reason, variations in characteristics of the subsystem 10 and the subsystem 20 hardly cause variations in signals for detecting rising edges.

  Next, the operation of the FT system 100 will be described using the flowchart of FIG. Here, the subsystem 10 will be mainly described. The control logic circuit 13 of the subsystem 10 is first initialized with a state machine (S-1). Next, the control logic circuit 13 shifts to a state (FIG. 2 WAIT) waiting for the arrival of a clock frequency change request (also called a change request) from the CPU 11 (S-2). The change request designates a newly set frequency and a change trigger that is a change timing.

  When a clock change request arrives from the CPU 11 (S-3 YES), the control logic circuit 13 enters a state (FIG. 2 standby for other system) that waits for a change request from another subsystem 20 to be sent. Enter (S-4). If no change request has been received (S-3 NO), the control logic circuit 13 continues to be in a state of waiting for the arrival of the change request (S-2). When a change request is received from the subsystem 20 (YES in S-5), the control logic circuit 13 moves to a state (FIG. 2 clock change trigger) for setting a change instruction timing, a new frequency or voltage (S-6). . At this time, the control logic circuit 23 shifts to the same state as the control logic circuit 13 by the signal output from the control logic circuit 13. Therefore, the same change instruction timing, changing frequency or voltage as in the control logic circuit 13 are set in the control logic circuit 23.

  In this embodiment, the control logic circuit 13 waits for the next rising edge of the second clock and sets a change trigger for changing the clock frequency or voltage to the CPU 11. The change opportunity is not limited to the example of this embodiment. The setting of the change trigger is performed according to the content of the change request, and the falling edge of the signal may be designated. When the change request from the subsystem 20 has not been received (S-5 NO), the control logic circuit 13 continues to be in a state waiting for the arrival of the change request from the subsystem 20 (S-4). When a change request is received from the subsystem 20 and a change trigger is set, the control logic circuit 13 moves to a state of waiting for detection of the rising edge of the signal (FIG. 2 clock change trigger) (S-7).

  The control logic circuit 13 outputs an instruction to change the clock frequency to the setting unit 12 and a change value of the frequency or voltage, which is an operation parameter to be changed, when the rising edge of the signal is detected (S-8 YES). (S-9). The setting unit 12 changes the clock frequency or voltage value of the CPU 11 based on this instruction (S-10).

  Since the control logic circuit 23 of the subsystem 20 also has the same function as the control logic circuit 13 of the subsystem 10 and is synchronized so as to take the same state, the control logic circuit 13 in S-6 is used. After receiving the instruction from, the same operation as the control logic circuit 13 is performed. That is, the control logic circuit 23 issues an instruction to the CPU 21 to change the clock frequency at the rising edge of the second clock, similar to the control logic circuit 13. As a result, in the subsystem 20, the clock frequency or voltage of the CPU 21 is changed to the same value as the clock frequency or voltage of the CPU 11 simultaneously with the subsystem 10.

  In this way, the clocks of the CPUs mounted on the two subsystems are changed simultaneously.

  In the present embodiment, the control logic circuit 13 outputs the clock frequencies of the CPU 11 and the CPU 21 to the control logic circuit 23 when the signal of the second clock generator 16 is changed, so that the subsystem 10 and the subsystem 20 At the same time, it can be changed to the same clock frequency or voltage.

  In the above embodiment, each part is connected by a signal line, but each part may be connected by infrared rays, short-range wireless, or the like.

  In the above embodiment, the second clock generator 16 is used and its signal is used as a trigger for change. However, when the frequency of the first clock generator 14 is sufficiently low, the signal of the first clock generator 14 is used as a trigger for change. The second clock generator 16 is not necessarily required.

  Although the case where the clock frequency or voltage is changed has been described in the above embodiment, the change target is not necessarily limited to the clock frequency. Any parameter that changes the conditions for operating the CPU can be changed. In this case, the setting unit 12 and the setting unit 22 simultaneously change the change parameters of the CPU 11 and the CPU 21 to the same value based on the outputs of the control logic circuit 13 and the control logic circuit 23, respectively.

  In the above embodiment, the first clock generator 14 and the second clock generator 16 are provided in the subsystem 10. However, these may be externally attached to the subsystem 10.

  In the above embodiment, the CPU 10 is provided in the subsystem 10. However, the CPU 11 may be externally attached to the subsystem 10.

Although the FT system 100 has been described in the above embodiment, the present embodiment can be applied not only to the FT system but also to general information processing.
(Second Embodiment)
In the first embodiment, when a clock frequency change request is issued from the subsystem 10, the clock frequency change request from the subsystem 20 is awaited.

  In the second embodiment, a clock change request from the subsystem 20 is not waited for. The configuration of the second embodiment is the same as that of the first embodiment. FIG. 5 is a timing diagram of the second embodiment. 3 is different from the timing diagram of FIG. 3 in that the subsystem 10 (own device) performs notification, and the subsystem 20 (other device) that has received the notification sends an acknowledgment signal. It is a point to set a change opportunity.

  FIG. 6 is a flowchart showing the operation of the FT system 100 in the second embodiment. S-21 to S-23 are the same as S1 to S3 of the first embodiment shown in FIG. After receiving the change instruction, the subsystem 10 notifies the subsystem 20 of this (S-24). The subsystem 20 that has received the notification sends an acknowledgment signal. When the subsystem 10 receives this signal (YES in S-25), the control logic circuit 13 sets a change opportunity (S-26). S-27 to S-29 are the same as S-8 to S-10 of the first embodiment shown in FIG.

In the present embodiment, since it is not necessary for the other subsystem to wait for a change request from one subsystem, it is possible to change the clock more quickly than in the first embodiment.
(Third embodiment)
The third embodiment is connected to one of a plurality of processors operating in synchronism, and further connected to another device connected to another processor of the plurality of processors. A setting unit 12 that changes an operation parameter of a processor connected to the apparatus to a specified new operation parameter; and a control unit 30 that outputs this new operation parameter to the setting unit and another apparatus. The parameter setting device 40 is provided.

  In this embodiment, it is possible to simultaneously change the operating parameters of the two processors in the information processing apparatus to the same value.

10 Subsystem 11 CPU
DESCRIPTION OF SYMBOLS 12 Setting part 13 Control logic circuit 14 1st clock generator 15 Frequency divider 16 2nd clock generator 20 Subsystem 21 CPU
DESCRIPTION OF SYMBOLS 22 Setting part 23 Control logic circuit 30 Control part 40 Parameter setting apparatus 50 Parameter setting apparatus 100 FT system

Claims (6)

A first processor, connected to other devices operating in synchronization with its own device while connected to the second processor,
Control means for outputting a change value of the first clock, which is a clock frequency of the first processor and the second processor, at a predetermined timing;
Setting means for changing the first clock of the first processor based on an output from the control means ;
The predetermined timing is a timing at which rising or falling of a second clock obtained by dividing the first clock is detected,
The control means receives the change request designating the change value and the predetermined timing from the first processor and the other device, and then detects the change value when the rising or falling edge of the second clock is detected. To the setting means and the other device,
The parameter setting device, wherein the setting means changes the first clock of the first processor to the change value at the rise of the first clock next to the detected rise or fall of the second clock . A first processor, connected to other devices operating in synchronization with its own device while connected to the second processor,
Control means for outputting a change value of the first clock, which is a clock frequency of the first processor and the second processor, at a predetermined timing;
Setting means for changing the first clock of the first processor based on an output from the control means ;
The predetermined timing is a timing at which rising or falling of a second clock obtained by dividing the first clock is detected,
The control means receives a change request designating the change value and the predetermined timing from the first processor, and notifies the change request to the other device and receives an acknowledgment signal from the other device. After detecting the rising or falling edge of the second clock, the change value is output to the setting means and the other device,
The parameter setting device, wherein the setting means changes the first clock of the first processor to the change value at the rise of the first clock next to the detected rise or fall of the second clock . In the computer of the parameter setting device that is connected to the first processor and the second processor and connected to another device that operates in synchronization with the own device,
A first process for outputting a change value of a first clock that is a clock frequency of the first processor and the second processor at a predetermined timing;
A program for executing a second process for changing the first clock of the first processor based on an output in the first process,
The predetermined timing is a timing at which rising or falling of a second clock obtained by dividing the first clock is detected,
The first process receives the change request specifying the change value and the predetermined timing from the first processor and the other device, and then detects the change when the rising or falling edge of the second clock is detected. Including processing to output values,
The second process includes a process of changing the first clock of the first processor to the change value at the rise of the first clock next to the detected rise or fall of the second clock.
Parameter setting program. In the computer of the parameter setting device that is connected to the first processor and the second processor and connected to another device that operates in synchronization with the own device,
A first process for outputting a change value of a first clock that is a clock frequency of the first processor and the second processor at a predetermined timing;
A program for executing a second process for changing the first clock of the first processor based on an output in the first process,
The predetermined timing is a timing at which rising or falling of a second clock obtained by dividing the first clock is detected,
The first process receives a change request designating the change value and the predetermined timing from the first processor, notifies the change request to the other device, and receives an acknowledgment signal from the other device. After receiving, when detecting the rising or falling edge of the second clock, including the process of outputting the change value,
The second process includes a process of changing the first clock of the first processor to the change value at the rise of the first clock next to the detected rise or fall of the second clock.
Parameter setting program. A parameter setting device that is connected to the first processor and the second processor and is connected to another device that operates in synchronization with the own device.
A change value of the first clock, which is a clock frequency of the first processor and the second processor, is output to the other device in response to a predetermined timing;
A parameter setting method for changing the first clock of the first processor based on the change value,
The predetermined timing is a timing at which rising or falling of a second clock obtained by dividing the first clock is detected,
After receiving a change request designating the change value and the predetermined timing from the first processor and the other device, when the rising or falling edge of the second clock is detected, the change value is sent to the other device. Output to
The first clock of the first processor is changed to the change value at the rise of the first clock next to the detected rise or fall of the second clock.
Parameter setting method. A parameter setting device that is connected to the first processor and the second processor and is connected to another device that operates in synchronization with the own device.
A change value of the first clock, which is a clock frequency of the first processor and the second processor, is output to the other device in response to a predetermined timing;
A parameter setting method for changing the first clock of the first processor based on the change value,
The predetermined timing is a timing at which rising or falling of a second clock obtained by dividing the first clock is detected,
After receiving a change request specifying the change value and the predetermined timing from the first processor, and notifying the change request to the other device and receiving an acknowledgment signal from the other device, When the rising or falling edge of 2 clocks is detected, the change value is output to the other device,
The first clock of the first processor is changed to the change value at the rise of the first clock next to the detected rise or fall of the second clock.
Parameter setting method.

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