JP2009098988A - Fault tolerant computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lock-step type fault tolerant computer system that can improve the performance and reliability of a system by suppressing the stop of the system. <P>SOLUTION: The lock-step type fault tolerant computer system in which a plurality of computer systems provided with a processor and a memory are connected, wherein each computer system performs clock synchronization to perform the same processing, is provided with a synchronization variation detecting means for detecting a variation in a synchronization process of each computer system, and a data synchronizing means for transmitting data written in a memory of a prescribed computer system to the other computers system and synchronizing each memory equipped with each computer system after detecting a synchronization variation. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a fault tolerant computer system, and more particularly to a lockstep fault tolerant computer system.

  In order to improve the reliability of a computer system, a fault-tolerant computer system has been developed in which even if a failure occurs in a part of the system, continuous processing can be performed without stopping the system. This fault-tolerant computer system can be realized by multiplexing devices constituting the computer such as CPU and memory or the computer system itself.

  In particular, as shown in Patent Document 1, a lock-step fault-tolerant computer system that executes the same instruction sequence synchronously in a plurality of computer systems is realized. However, in the lock step type computer system, the lock step may be lost due to some trouble. In this case, it is necessary to execute a process for resynchronization, and a resynchronization function is provided.

JP 2004-46611 A JP 2003-15901 A JP 2006-268709 A

  However, in the memory resynchronization processing in the fault tolerant computer system, it is necessary to restrict memory access, that is, stop the operation state of the system and perform resynchronization of the memory. Further, in the resynchronization process, there is a problem that the system stop time becomes longer in proportion to the data amount of the memory to be resynchronized.

  Here, Patent Document 2 discloses a redundant system including an active system and a standby system. The redundancy system disclosed in Patent Document 2 employs a configuration in which information written to the active system is stored in a shared memory, and this is read later by the standby system. Patent Document 3 also discloses a redundant system including an active system and a standby system. The redundancy system of Patent Document 3 adopts a configuration in which when writing is detected in the active memory, the information is transmitted to the standby system.

  However, the redundant system disclosed in Patent Documents 2 and 3 is a redundant system including an active system and a standby system as described above, and is not a lock-step fault tolerant computer system. The system outage problem is not considered when synchronizing the data. For this reason, there is no disclosure of a technique for suppressing the system stop in the data resynchronization of the above-described lockstep fault tolerant computer system. Furthermore, there is a problem that the processing load of the operation system increases because the timing of synchronization is always when data is written to the operation system.

  Therefore, an object of the present invention is to provide a lock-step fault tolerant computer system that can suppress the stop of the system and improve the performance and reliability of the system. is there.

Therefore, a fault tolerant computer system which is an embodiment of the present invention is:
A lock-step fault-tolerant computer system comprising a plurality of computer systems each including a processor and a memory, each computer system performing the same processing in synchronization with a clock,
Synchronization deviation detecting means for detecting a deviation in synchronization processing of each computer system;
Data synchronization means for transmitting data written to a memory of a predetermined computer system to a memory of another computer system after synchronization is detected, and synchronizing each memory provided in each computer system;
With
The structure is taken.

  Since the present invention is configured as described above, even if a synchronization error occurs, data can be synchronized by suppressing the stop of the system, and the performance and reliability of the system are improved. It has an unprecedented excellent effect of being able to.

A fault tolerant computer system according to one aspect of the present invention is:
A lock-step fault-tolerant computer system comprising a plurality of computer systems each including a processor and a memory, each computer system performing the same processing in synchronization with a clock,
Synchronization deviation detecting means for detecting a deviation in synchronization processing of each computer system;
Data synchronization means for transmitting data written to a memory of a predetermined computer system to a memory of another computer system after synchronization is detected, and synchronizing each memory provided in each computer system; The structure that is equipped with.

The data synchronization means includes a write detection means for detecting writing of predetermined data to a memory of a predetermined computer system after the synchronization deviation is detected by the synchronization deviation detection means, and a detection by the write detection means. Write data transmission means for transmitting the written data to a memory of another computer system;
The structure that is equipped with.

  In addition, the write detection means monitors the write access to the memory from the processor and detects the data write to the memory. Further, the data synchronization means adopts a configuration in which when there are a plurality of connection paths from a predetermined computer to another computer system, write data is transmitted from all the connection paths to the other computer system. Further, the computer system in the operating state and the computer system in the standby state are provided with initial synchronization means for synchronizing the data in the respective memories.

  According to the above invention, first, the plurality of computer systems synchronize the data in the memory. Then, synchronization processing is executed with the same clock. Thereafter, when a shift occurs in the synchronization process due to some factor, this is detected. Then, after a shift occurs in the synchronization processing, the write access to the memory in the predetermined computer system is monitored, and when the write is detected, the write data is transmitted to another computer system. Then, since the data written in the memory of a predetermined computer is written in the memory of another computer system, the memories can be synchronized. Therefore, the memory of each computer system can be synchronized without stopping access from the processor. As a result, the minimum required stop time such as resetting the computer system itself, such as recovery of synchronization, is necessary, but the system stop and the system performance and reliability can be improved. .

Moreover, the program which is the other form of this invention is:
A control unit for controlling the operation of a computer system in a lock-step fault tolerant computer system in which a plurality of computer systems each including a processor and a memory are connected and each computer system performs the same processing in clock synchronization In addition,
Synchronization deviation detecting means for detecting a deviation in synchronization processing of each computer system;
Data synchronization means for transmitting data written to a memory of a predetermined computer system to a memory of another computer system after synchronization is detected, and synchronizing each memory provided in each computer system;
To achieve the above.

  The data synchronization means includes a write detection means for detecting writing of predetermined data to a memory of a predetermined computer system after the synchronization deviation is detected by the synchronization deviation detection means, and a detection by the write detection means. And a write data transmitting means for transmitting the written data to a memory of another computer system.

In addition, a data synchronization method according to another aspect of the present invention includes:
A data synchronization method in a fault-step tolerant computer system of a lockstep method in which a plurality of computer systems each including a processor and a memory are connected and each computer system performs the same processing in synchronization with a clock,
A synchronization shift detection step for detecting a shift in synchronization processing of each computer system;
A data synchronization step of transmitting data written to a memory of a predetermined computer system to a memory of another computer system after synchronization loss is detected, and synchronizing each memory provided in each computer system;
It has the configuration of having.

  The data synchronization step includes a write detection step for detecting writing of predetermined data to a memory of a predetermined computer system after the synchronization shift is detected by the synchronization shift detection means, and detection by this write detection step. A write data transmission step of transmitting the written data to a memory of another computer system.

  Even the invention of the program and the data synchronization method having the above-described configuration operates in the same manner as the fault-tolerant system described above, so that the object of the present invention described above can be achieved. Hereinafter, specific configurations and operations of the present invention will be described in the embodiments.

<Embodiment 1>
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing the overall configuration of a fault tolerant computer system. FIG. 2 is a block diagram showing the configuration of the computer system that constitutes the fault-tolerant computer system. FIG. 3 is a flowchart showing the operation of the computer system.

[Constitution]
As shown in FIG. 1, the fault-tolerant computer system in the present embodiment is composed of two computer systems 1 and 2. The two computer systems 1 and 2 are lock-step fault tolerant computer systems that perform the same processing in synchronization with each other. Here, the computer system 1 indicated by reference numeral 1 is a system (predetermined computer system) in an operating state, and the computer system 2 indicated by reference numeral 2 is a computer system (another computer system) in a standby state.

  Note that the fault-tolerant computer system in the present invention is not limited to being configured by two computer systems, and may be configured by more computer systems. In that case, one computer system is connected to all other computer systems through a plurality of connection paths.

  The computer system 1 includes a CPU 11, a main memory 13, an IO 14, and a controller 12 that controls these operations. Since the configuration of the other computer system 2 is the same, detailed description is omitted. The CPU 11 (processor) operates by synchronizing the instruction issued by the CPU every clock. The main memory 13 (memory) stores instructions and processing data issued by the CPU 11.

  In addition, the controller 12 (control unit) incorporates a predetermined program so as to transfer a Routing control function for decoding an IO command issued from the CPU 11 and a command issued from the CPU 11 to another system synchronous control unit. A data transfer function, a synchronization control function for monitoring the synchronization state for each clock, and an IO control function for accessing a plurality of mounted devices are provided. Specifically, the controller 12 includes a memory controller 40 that controls writing or reading of data to the main memory 13 and a memory of another computer system 2 as shown in FIG. And a data synchronization circuit 30 (data synchronization means) including a write detection unit 31 and a data transfer unit 32.

  The synchronization control circuit 50 is a function for checking a difference in data of instructions issued from the CPU 11 and sent from an internal path and a data transfer function of another computer system to detect a deviation in synchronization processing ( (Synchronization detecting means). When the synchronization shift is detected, the light detection unit 31 is notified.

  When the write detection unit 31 (write detection unit) receives the detection notification of the synchronization shift, the write detection unit 31 detects the data write access to the main memory 13 from the CPU 1 or IO. When write access is detected, write data is taken out and passed to the data transfer unit 32.

  The data transfer unit 32 (write data transmission means) transmits the write data to be stored in the main memory 23 of another computer system 2 via the synchronization control circuit 50. That is, the controller 22 of the other computer system 2 has a function of storing the write data transmitted from the operating computer system 1 in the main memory 23. Thereby, the data in the main memories 13 and 23 of the computer systems 1 and 2 are synchronized. In addition, when there are a plurality of connection paths to other computer systems 2, the data transfer unit 32 transmits write data from all the connection paths to the other computer systems.

  Further, the synchronization control circuit 50 is an initial synchronization function that synchronizes data in each memory provided in the computer system 1 in the active state and the other computer system 2 in the standby state before starting the synchronization process. (Initial synchronization means).

[Operation]
Next, the operation of the fault tolerant computer system configured as described above, in particular, the operation of the computer system 1 in the operating state will be described with reference to the flowchart of FIG.

  Between the computer systems 1 and 2 to be operated synchronously, first, it is necessary to make the contents of the main memories 13 and 23 all the same. Therefore, the memory data is transferred from the computer system 1 in the operating state to the computer system 2 that is in the standby state in advance to completely match the contents of the memory (step S1, initial synchronization step). Then, once reset, the operation of the multiplexed fault tolerant computer system is started simultaneously. Then, the computer systems 1 and 2 operate in synchronization with each clock (step S2).

  Thereafter, the lock step is lost due to some failure. Then, the controller 12 of the computer system 1 that monitors the IO command and the memory access detects a synchronization error (Yes in step S3, a synchronization error detection step). When the synchronization shift is detected in this way, the controller 12 monitors a write access to the main memory 12 that occurs thereafter. When the occurrence of the write access to the main memory 12 is detected (Yes in step S4, the write detection step), the write data to be written to the main memory 13 generated along with this write access is taken out, It transmits to the other computer system 2 (step S5, write data transmission process). At this time, in a system in which there are a plurality of paths connecting to other computer systems, data is transferred to all paths in order to ensure the latest data.

  Then, in the computer system 1, write data is stored in the main memory 13 in response to the write access, and in the other computer system 2, the transmitted write data is stored in the main memory 23. Thereby, the main memories 13 and 23 in the computer systems 1 and 2 can be synchronized (data synchronization step). After that, by performing a reset or the like, the computer systems 1 and 2 again return to the synchronization processing.

  Here, a data synchronization method in a fault tolerant computer system that is not configured as described above will be described. In a computer system that does not include the write detection unit 31 and the data transfer unit 32, when the controller detects a synchronization error, the subsequent difference information is stored. Then, the controller issues a read request to the main memory based on the stored difference information, and transmits the read data to the computer system 2 on the standby side. Then, since there is no regularity in the address read at that time, it becomes necessary to stop access from the processor and IO. Therefore, while this access is stopped, there is a problem that the system is stopped and the performance is temporarily deteriorated. In particular, when a large amount of difference information is accumulated, there may be a problem that the time for stopping becomes longer.

  On the other hand, in the fault-tolerant computer system according to the above-described invention, after the synchronization shift is detected, the write data is transferred and synchronized every time writing occurs, so the CPU accesses during the memory data synchronization processing. There is no need to stop. When starting the resynchronization process, the minimum required stop time such as resetting is required, but the stop time is minimized and the system stop is suppressed, and the system performance and reliability are reduced. Improvements can be made.

  The present invention can be used for a lock-step fault tolerant computer system used in a multiplexed manner, and has industrial applicability.

It is a block diagram which shows the whole structure of a fault tolerant computer system. It is a block diagram which shows the structure of the computer system disclosed in FIG. 2 is a flowchart illustrating an operation of the computer system disclosed in FIG. 1.

Explanation of symbols

1, 2 Computer system 11, 21 CPU
12, 22 Controllers 13, 23 Main memory 31 Write detection unit 32 Data transfer unit 40 Memory controller 50 Synchronization control circuit

Claims (9)

A lock-step fault-tolerant computer system comprising a plurality of computer systems each including a processor and a memory, each computer system performing the same processing in synchronization with a clock,
A synchronization error detection means for detecting a synchronization error of each computer system;
Data synchronization is performed by transmitting data written to a predetermined memory of the computer system to a memory of another computer system after synchronization is detected, and synchronizing each memory provided in each computer system. Means,
A fault tolerant computer system characterized by comprising: The data synchronization means includes a write detection means for detecting writing of predetermined data to the memory of the predetermined computer system after the synchronization deviation is detected by the synchronization deviation detection means, and a detection by the write detection means. Write data transmitting means for transmitting the written data to the memory of the other computer system,
The fault-tolerant computer system according to claim 1. The write detection means detects write access to the memory by monitoring write access to the memory from the processor;
The fault tolerant computer system according to claim 2. The data synchronization means transmits the write data from all connection paths to the other computer system when there are a plurality of connection paths from the predetermined computer to the other computer system.
The fault tolerant computer system according to claim 1, 2, or 3. The computer system in an operating state and the computer system in a standby state, each comprising an initial synchronization means for synchronizing data in each of the memories provided;
5. A fault tolerant computer system according to claim 1, 2, 3 or 4. Control for controlling the operation of a computer system in a lock-step type fault tolerant computer system comprising a plurality of computer systems each including a processor and a memory, and each computer system performing the same processing in synchronization with a clock. Part
A synchronization error detection means for detecting a synchronization error of each computer system;
Data synchronization is performed by transmitting data written to a predetermined memory of the computer system to a memory of another computer system after synchronization is detected, and synchronizing each memory provided in each computer system. Means,
A program to realize The data synchronization means includes a write detection means for detecting writing of predetermined data to the memory of the predetermined computer system after the synchronization deviation is detected by the synchronization deviation detection means, and a detection by the write detection means. Write data transmitting means for transmitting the written data to the memory of the other computer system,
The program according to claim 6. A data synchronization method in a fault-step tolerant computer system of a lockstep method in which a plurality of computer systems each including a processor and a memory are connected and each computer system performs the same processing in synchronization with a clock,
A synchronization error detection step of detecting a synchronization error in each computer system;
Data synchronization is performed by transmitting data written to a predetermined memory of the computer system to a memory of another computer system after synchronization is detected, and synchronizing each memory provided in each computer system. Process,
A data synchronization method comprising: The data synchronization step includes a write detection step for detecting writing of predetermined data to the memory of the predetermined computer system after the synchronization shift is detected by the synchronization shift detection means, and detection by this write detection step A write data transmission step of transmitting the written data to the memory of the other computer system,
9. The data synchronization method according to claim 8, wherein:

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