JP5380884B2 - Data processing apparatus and synchronization method - Google Patents

Description

  The present invention relates to a data processing apparatus including at least two systems each having a processor and an input / output unit, each having a processor, an input / output unit, and a time counter, and operating with clock signals from different clock sources. The present invention relates to a synchronization method for synchronizing at least two systems.

  As a computer that provides high reliability, there is a fault-tolerant computer (hereinafter abbreviated as “FT computer”) (see, for example, Patent Document 1). The FT computer has a redundant configuration in which modules having the same hardware configuration are duplicated or multiplexed. All modules that are duplicated or multiplexed operate synchronously. Therefore, for example, even if a failure occurs in a certain module, the module can be disconnected and the process can be continued with only a normal module. Thereby, the tolerance to the failure of the module is improved, and high reliability can be obtained.

  Each module of the FT computer includes a CPU subsystem having a processor and memory. The same software is incorporated in each CPU subsystem. When each CPU subsystem gives the same timing clock signal and the same data, it always performs the same operation if it is normal. This characteristic is called determinism. Based on this determinism, a state in which a plurality of CPU subsystems perform exactly the same operation is called lockstep synchronization. In the FT computer, duplex processing or multiplexing processing is realized by synchronizing the CPU subsystem of each module with lockstep.

  There are two methods for inputting clock signals of the same timing input to each CPU subsystem: a method of sharing a clock source among CPU subsystems and a method of using a plurality of clock sources having the same output frequency. It is done.

  However, when the clock source is shared, if the clock source fails, all the modules of the FT computer must be stopped. In addition, since wiring for inputting one clock signal to all modules is required, the degree of freedom in designing the mechanism of the apparatus is significantly limited.

  On the other hand, when a plurality of clock sources are used, the clock signals output from the respective clock sources are shifted over time due to minute variations in the output frequency of each clock source. Thus, for instructions executed simultaneously by each CPU subsystem, a method is disclosed in which the execution timing of all the CPU subsystems is matched to the CPU subsystem having the lowest clock signal frequency and the lowest execution speed (for example, patents). Reference 2). Also disclosed is a data processing device that detects the phase difference of a clock signal and adjusts the frequency of the clock signal based on the phase difference (see, for example, Patent Document 3). Furthermore, a data processing device is disclosed that keeps the lock step synchronization by minimizing the phase difference of the clock signal by periodically resetting the count value of the time counter (for example, Patent Documents 4 and 5). reference).

JP 2006-172391 A JP-T-2006-512634 JP 2005-182893 A JP-A-7-73059 JP 2007-249518 A

  However, when the execution timings of all the CPU subsystems are matched with the CPU subsystem having a low execution speed, there is a concern that the processing speed of the entire apparatus is lowered.

  Further, when detecting the shift of the clock signal, dedicated hardware for comparing the clock signals input to the CPU subsystems is required, and the independence of the hardware of each module is lowered.

  In addition, when the clock signal input to each CPU subsystem is periodically reset by applying a timer interrupt or the like, the time for applying the timer interrupt is not set appropriately, or the output frequencies of multiple clock sources If there is too much variation, it will be difficult to maintain lockstep synchronization.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a more reliable data processing apparatus.

To achieve the above object, a data processing apparatus according to the first aspect of the present invention is a data processing apparatus including at least two systems each having a processor and an input / output unit, and each of the systems includes: A clock source that outputs a clock signal, an adjustment unit that adjusts the frequency of the clock signal output from the clock source and inputs the clock signal, and a time counter that measures time based on the clock signal output from the adjustment unit And when the data input from the input / output unit is transmitted to the processor, the first count value of the time counter at the time of transmission and a scheduled execution time corresponding to the data processed by the processor 2 of the count value transmitted in addition to the data, the first, the data which the second count value are added, sent to other systems And receiving the data transmitted from the first transmitter, obtaining a third count value of the time counter at the time of reception, and the first transmission of the other system The first receiving unit that receives the data transmitted from the unit and obtains the fourth count value of the time counter at the time of reception, and the data that has the same added first count value A calculation unit that calculates a count deviation between the count value of the time counter and the count value of the time counter of the other system based on the third and fourth count values; and the count deviation calculated by the calculation unit as decreases, and a control section for controlling the adjustment unit, until the count value of the time counter becomes the second count value, for the processor, received by said first receiver A holding unit for holding the input of the received data, a second transmission unit for transmitting the data input from the processor to the input / output unit, and the data transmitted from the second transmission unit A second receiving unit for outputting to the entry output unit.

The synchronization method according to the second aspect of the present invention is a synchronization method for synchronizing at least two systems, each of which has a processor, an input / output unit, and a time counter and operates with clock signals from different clock sources. When the data input from the input / output unit is transmitted to the processor, it corresponds to the first count value of the time counter at the time of transmission and the scheduled execution time at which the data is processed by the processor A first step of transmitting the second count value to the data and transmitting the data to which the first and second count values have been added to another system; Receiving the data transmitted in the process, obtaining the third count value of the time counter at the time of reception, receiving the data transmitted from the other system, and at the time of reception Based on the second step of acquiring the fourth count value of the time counter and the third and fourth count values of the data having the same added first count value, the time counter A third step of calculating a count deviation between the count value of the other system and the count value of the time counter of the other system, and the frequency of the clock signal so that the count deviation calculated in the third step is reduced And a fifth step of deferring input of the data received in the second step to the processor until the count value of the time counter reaches the second count value. ,including.

  According to the present invention, a more reliable data processing apparatus can be provided.

<< First Embodiment >>
Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows the configuration of a data processing apparatus 100 according to the first embodiment of the present invention. As shown in FIG. 1, the data processing apparatus 100 includes a system 1 </ b> A, a system 1 </ b> B, and a cross link 2. The system 1A and the system 1B are the same type modules having the same hardware configuration and software configuration. That is, the data processing apparatus 100 is an FT computer having a redundant configuration in which a system having the same hardware configuration and the same software operating on the hardware is duplicated.

  The cross link 2 is a data transmission path that enables mutual data transmission / reception between the system 1A and the system 1B. As the reference numerals of the constituent elements of the system 1A, numbers obtained by adding A are used. Moreover, what added B to the same number is used for the component of the system 1B corresponding to the component. Below, although the component of the system 1A is mainly demonstrated, each component of the system 1B is demonstrated as needed as what has the same function as the corresponding component of the system 1A.

  The system 1A includes a clock source 10A, a PLL (phase synchronization circuit) 11A as an adjustment unit, a CPU subsystem 12A, and an I / O subsystem 13A.

  The clock source 10A includes, for example, a crystal oscillator and outputs a clock signal having a predetermined frequency.

  The PLL 11A finely adjusts the frequency of the clock signal output from the clock source 10A according to the set parameters. From the PLL 11A, a clock signal whose frequency is adjusted is output. The clock signal whose frequency is adjusted by the PLL 11A is input to the CPU subsystem 12A.

  The CPU subsystem 12A is a subsystem of the system 1A that is configured around a CPU unit 20A including a CPU (central processing unit) and a memory (main storage device). The CPU unit 20A executes a series of instruction sequences, and has an arbitrary number of CPUs, an arbitrary capacity memory, and an internal bus (not shown) interconnecting them. The CPU of the CPU unit 20A executes a series of instruction sequences (programs) stored in the memory using the input data in accordance with a clock signal input from the clock source 10A via the PLL 11A. Such an instruction sequence includes a data input / output instruction, a data operation instruction, a program control instruction such as a branch, and the like.

  The CPU subsystem 12A is further provided with a time counter 21A. The time counter 21A measures time based on a clock signal input via the PLL 11A. The time counter 21A resets the count value when a reset signal (not shown) is input. After reset, the time counter 21A increments the count value, for example, at the rising edge of the clock signal input from the clock source 10A via the PLL 11A. The time counter 21A holds the number of clock cycles since it was reset. The count value of the time counter 20A can always be referred to from the CPU unit 20A constituting the CPU subsystem 12A, a transmitting unit 22A, a receiving unit 23A, a packet processing unit 24A, a PLL control unit 25A, etc., which will be described later. Yes. Further, the count value of the time counter 21A is constantly transmitted from the CPU subsystem 12A to the I / O subsystem 13A by a dedicated sideband signal.

  The CPU unit 20A executes the same program as the program executed by the CPU unit 20B of the other system 1B described later. The CPU subsystem 12A includes a transmission unit 22A, a reception unit 23A, a packet processing unit 24A, and a PLL control unit 25A in addition to the CPU unit 20A as a processor. Details of these will be described later. To do.

  The I / O subsystem 13A is a subsystem of the system 1A configured around an I / O device (simply I / O in the figure) 30A as an input / output unit. The I / O device 30A is an input / output interface that inputs and outputs data with an external device (not shown). The I / O device 30A may be an arbitrary plurality of devices such as a SCSI controller and a LAN adapter. The I / O subsystem 13A includes a transmission unit 32A and a reception unit 33A in addition to the I / O device 30A. Details thereof will be described later.

  In the system 1A, the entire operation is realized by transmitting and receiving data packets between the CPU unit 20A of the CPU subsystem 12A and the I / O device 30A of the I / O subsystem 13A. As shown in FIG. 2, the data packet 50 is provided with a plurality of fields including a packet type field 51, a packet length field 52, a data field 53, a transmission time field 54, and an execution time field 55.

  The packet type field 51 stores the type of the data packet 50. The packet length field 52 stores the packet length of the data packet 50. The data field 53 stores substantive data such as data input from an external device to the I / O device 30A and data generated by executing a program of the CPU unit 20A. The packet type field 51, the packet length field 52, and the data field 53 constitute a general data field.

  In addition to the general data field, the data packet 50 is provided with a transmission time field 54 and an execution time field 55. The transmission time field 54 stores the count value (first count value) of the time counter 21A when data is transmitted from the I / O subsystem 13A to the CPU subsystem 12A. The execution time field 55 stores the count value (second count value) of the time counter when the data included in the data field 53 of the data packet 50 is to be executed by the CPU unit 20A. Note that the same count value is also stored in the execution time field 55 of the data packet 50 in the CPU unit 20B.

  In order to establish transmission / reception of the data packet 50 and lock step synchronization (hereinafter simply referred to as “synchronization”) between the system 1A and the system 1B, the CPU subsystem 12A includes the CPU unit 20A and the time counter 21A. , A transmission unit 22A, a reception unit 23A, a packet processing unit 24A, and a PLL control unit 25A. In addition to the I / O device 30A, the I / O subsystem 13A includes a transmission unit 32A and a reception unit 33A. In the system 1A according to the present embodiment, the transmission unit 32A of the I / O subsystem 13A corresponds to the first transmission unit, and the reception unit 23A of the CPU subsystem 12A corresponds to the first reception unit. The transmission unit 22A of the CPU subsystem 12A corresponds to the second transmission unit, and the reception unit 33A of the I / O subsystem 13A corresponds to the second reception unit.

  The transmission unit 32A configuring the I / O subsystem 13A sets the count value (first count value) of the time counter 21A at the time of transmission in the transmission time field 54 of the data packet 50 input from the I / O device 30. Store. Then, the transmitting unit 32A stores a count value (second count value) corresponding to the scheduled execution time at which the data packet 50 is processed by the CPU unit 20A in the execution time field 55 of the data packet 50. Further, the transmission unit 32A transmits the data packet 50 to which these count values are added to the reception unit 23A and also to the reception unit 23B of the other system 1B via the cross link 2.

  The receiving unit 23A constituting the CPU subsystem 12A receives the data packet 50 transmitted from the transmitting unit 32A, and at the same time, obtains the count value (third count value) of the time counter 21A when the data packet 50 is received. get. The receiving unit 23A receives the data packet 50 transmitted from the transmitting unit 32B of the other system 1B, and obtains the count value (fourth count value) of the time counter 21A when the data packet 50 is received. To do.

  FIG. 3 shows a detailed configuration of the receiving unit 23A. As shown in FIG. 3, the receiving unit 23A includes FIFO (first-in-first-out) memories 40A, 40B, 41A, and 41B.

  The receiving unit 23A holds the data packet 50 transmitted from the transmitting unit 32A of the I / O subsystem 13A in the FIFO memory 40A. The receiving unit 23A holds the third count value in the FIFO memory 41A.

  In addition, the reception unit 23A holds the data packet 50 transmitted from the transmission unit 32B in the other system 1B in the FIFO memory 40B. The receiving unit 23A holds the fourth count value in the FIFO memory 41B.

  Note that a time difference occurs between the third count value and the fourth count value due to the latency of the cross link 2 (potential time required for data transmission / reception between the system 1A and the system 1B). Therefore, it is assumed that a new data packet 50 is sent from the transmission unit 32A before the data packet 50 is received from the transmission unit 32B in the system 1B. For this reason, the FIFO memory 40A, 40B, 41A, 41B is provided in the receiving unit 23A so that the received data is not lost. The capacities of the FIFO memories 40A, 40B, 41A and 41B are set in consideration of the balance between the latency of the cross link 2 and the transmission frequency of data transmitted from the I / O subsystem 13A to the CPU subsystem 12A. Is desirable. Further, it is desirable that these capacities are such that data input / output between the receiving unit 23A and the packet processing unit 24A is not excessively delayed.

  The receiving unit 23A also sets the time counter 21A based on the third count value of the data packet 50 stored in the FIFO memory 41A and the fourth count value of the data packet 50 stored in the FIFO memory 41B. A count deviation between the count value and the count value of the time counter 21B of the other system 1B is calculated. The third count value and the fourth count value considered for calculating the count deviation are those of the data packet 50 having the same count value (first count value) stored in the transmission time field. Used.

  More specifically, the receiving unit 23A first subtracts the latency of the cross link 2 from the fourth count value. Then, the receiving unit 23A calculates a difference between the subtracted count value and the third count value, thereby counting the count value of the time counter 21A and the count value of the time counter 21B of the other system 1B. Calculate the deviation. This count deviation is output to the packet processing unit 24A together with the data packet 50.

  The packet processing unit 24A receives the data packet 50 received by the receiving unit 23A until the count value of the time counter 21A reaches the count value (second count value) stored in the execution time field 55 of the data packet 50. The input to the CPU unit 20A is suspended.

  Further, when the count deviation output from the receiving unit 23A exceeds the allowable value, the packet processing unit 24A outputs the count deviation to the PLL control unit 25A.

  The PLL control unit 25A controls the PLL 11A by changing the parameters of the PLL 11A based on the count deviation output from the packet processing unit 24A. As a result, the frequency of the clock signal output from the PLL 11A is finely adjusted, and the count deviation between the time counter 21A of the system 1A and the time counter 21B of the system 1B is reduced.

  On the other hand, the transmission unit 22A configuring the CPU subsystem 12A inputs the data packet 50 output from the CPU unit 20A. The transmission unit 22A transmits the input data packet 50 to the reception unit 33A of the I / O subsystem 13A and also to the reception unit 33B of the other system 1B via the cross link 2.

  The receiving unit 33A configuring the I / O subsystem 13A receives the data packet 50 transmitted from the transmitting unit 22A and outputs it to the I / O device 30A. The receiving unit 33A also receives the data packet 50 from the transmitting unit 22B of the other system 1B. In the present embodiment, the receiving unit 33A receives the data packet 50 transmitted from the other system 1B. Processing is not particularly performed.

  As described above, the configuration of the system 1B is the same as the configuration of the system 1A. That is, the system 1B includes a clock source 10B, a PLL 11B, a CPU subsystem 12B, and an I / O subsystem 13B. The CPU subsystem 12B includes a CPU unit 20B, a time counter 21B, a transmission unit 22B, a reception unit 23B, a packet processing unit 24B, and a PLL control unit 25B. The I / O subsystem 13B includes an I / O device 30B, a transmission unit 32B, and a reception unit 33B.

  The clock source 10A and the clock source 10B are clock sources of the same standard and output clock signals having the same frequency. These clock signals are input to the CPU subsystems 12A and 13A via the PLLs 11A and 11B, respectively. That is, the CPU subsystems 12A and 12B operate under a clock signal having substantially the same frequency.

  In addition, exactly the same data is input from the external device to the I / O subsystems 13A and 13B at the same timing. If normal, these data are transmitted from the I / O subsystems 13A and 13B to the CPU subsystems 12A and 12B at the same timing. The same data is input to the CPU unit 20A of the CPU subsystem 12A and the CPU unit 20B of the CPU subsystem 12B at the same timing. The CPU units 20A and 20B execute the same program. Therefore, the CPU units 20A and 20B perform exactly the same operation based on determinism and output the same data at the same timing. As a result, synchronization between the systems 1A and 1B is realized.

  Next, the operation of the data processing apparatus 100 according to the first embodiment of the present invention will be described in detail with reference to the flowcharts of FIGS. 4 to 6 and FIGS. 7 (A) to 7 (C). In the present embodiment, the operation of the system 1A and the operation of the system 1B are the same, and thus the operation of the system 1A will be mainly described. First, the operation of the system 1A until the data input from the external device to the I / O device 30A is input to the CPU unit 20A will be described.

  The operation of the transmission unit 32A will be described. FIG. 4 shows a flowchart of the operation of the transmission unit 32A. When a reset signal (not shown) is input after the power is turned on, the operation of the transmission unit 32A is started. First, in step 201, the transmission unit 32A performs an initialization process. After the initialization process, in step 203, the transmission unit 32A waits until the data packet 50 is input from the I / O device 30A.

  When the data packet 50 is input from the I / O device 30A, the determination in step 203 is affirmed, and the transmission unit 32A proceeds to step 205. In step 205, the transmission unit 32A stores the current count value of the time counter 21A in the transmission time field 54, stores the count value corresponding to the execution time of the CPU unit 20 in the execution time field 55, and the data packet 50 Is transmitted to the receiving unit 23A and also to the receiving unit 23B of the other system 1B.

  FIG. 7A shows an example of setting the count value stored in the transmission time field 54 and the count value stored in the execution time field 55 of the data packet 50 in the transmission unit 32A. A clock pulse shown in FIG. 7A indicates a clock signal input to the CPU subsystem 12A.

  Here, it is assumed that the transmission time of the data packet 50 in the transmission unit 32A is the time point of the count value t1. In this case, the transmission unit 32A stores the count value t1 in the transmission time field 54.

  The time required for data transmission from the transmission unit 32A to the reception unit 23A is set as time S, and the cross link latency is set as L. These times S and L are known. Further, let P be an allowable value of the time difference between the processing of the CPU units 20A and 20B. The transmission unit 32A stores the count value t2 obtained by adding the time S, the time L, and the allowable value P to the count value t1 in the execution time field 55. That is, the count value stored in the execution time field 55 is set to a value obtained by adding the latency of the cross link 2 and the allowable deviation between the CPU units 20A and 20B to the count value of the current time counter 21A. Is desirable.

  Note that the data packet 50 transmitted from the transmission unit 32A is received by the reception unit 23A at the time after the time S has elapsed, that is, the time when the count value of the time counter 21A becomes t3. In addition, when the receiving unit 23A receives the data packet 50 transmitted from the transmitting unit 32B of the system 1B, the count value of the time counter 21A is t4 if there is no count deviation between the time counters 21A and 21B. It will be a time.

  Returning to FIG. 4, after transmitting the data packet 50, the process returns to step 203 again and waits until the next data packet 50 is input from the I / O device 30 </ b> A.

  In this way, each time the data packet 50 is input from the I / O device 30A, the transmission unit 32A stores the respective count values in the transmission time field 54 and the execution time field 55 of the data packet 50. The data packet 50 is transmitted to the receiving units 23A and 23B.

  Next, the operation of the receiving unit 23A will be described. FIG. 5 shows a flowchart showing the operation of the receiving unit 23A. As shown in FIG. 5, when a reset signal (not shown) is input after turning on the power, the operation of the receiving unit 23A is started. First, in step 301, the receiving unit 23A performs an initialization process. After the initialization process, in step 303, the receiving unit 23A waits until the data packet 50 is received.

  When the data packet 50 is received from the transmission unit 32A and stored in the FIFO memory 40A, the determination in step 303 is affirmed, and the reception unit 23A proceeds to step 305. At the reception unit 23A, the reception of the data packet 50 from the transmission unit 32A is completed, and at the same time, the count value of the time counter 21A at the time of reception (third count value, t3 in FIG. 7A) is the FIFO memory. 41A.

  In step 305, the receiving unit 23A determines whether or not the data packet 50 having the same count value (first count value) stored in the transmission time field 54 has been received from another system 1B. If this determination is affirmed, the reception unit 23A proceeds to step 309, and if negative, the reception unit 23A returns to step 303.

  In step 303, the receiving unit 23A again waits for reception of the data packet 50. Here, when the data packet 50 from the transmission unit 32A is received or the data packet 50 from the transmission unit 32B of another system 1B is received, the reception unit 23A proceeds to Step 305.

  When the data packet 50 from the transmission unit 32A is received, the received data packet 50 is stored in the FIFO memory 40A, and the count value of the time counter 21A at the time of reception is stored in the FIFO memory 41A. Then, the determination at step 305 is denied, and the receiving unit 23A returns to step 303.

  On the other hand, when the data packet 50 is received from the transmission unit 32B of the other system 1B, the data packet 50 is stored in the FIFO memory 40B, and the count value (fourth count value, 7 (A) is stored in the FIFO memory 41B. If the received data packet 50 from the other system 1B is in a normal state, the data packet 50 previously stored in the FIFO memory 40A and the count value stored in the transmission time field 54 (first count) Data packets with the same value). If the count value stored in the transmission time field 54 of the data packet 50 stored in the FIFO memory 40B is the same as that of the data packet 50 stored in the FIFO memory 40A, the determination in step 305 is affirmed. Then, the receiving unit 23A proceeds to Step 309.

  In step 309, based on the third count value stored in the FIFO memory 41A and the fourth count value stored in the FIFO 41B having the same data and transmission time field, the count value of the time counter 21A The count deviation from the count value of the time counter 21B of the other system 1B is calculated.

  As shown in FIG. 7A, it is assumed that the count value stored in the FIFO memory 41A is t3 and the count value stored in the FIFO memory 41B is t4. The receiving unit 23A calculates the difference between the count value t4 and the count value t3 as the difference between the count value of the time counter 21A and the count value of the time counter 21B. . In FIG. 7A, this count deviation is zero.

  On the other hand, as shown in FIG. 7B, the clock signal (lower signal) input to the CPU subsystem 12B with respect to the clock signal (upper signal) input to the CPU subsystem 12A. Suppose that was late. Such a delay is caused by the difference in frequency of the clock signals of both systems. If the frequency of the clock signal of the clock source 10A and the frequency of the clock signal of the clock source 10B are slightly different, the timing at which the time counter 21A is counted and the timing at which the time counter 21B is counted are between. Deviation occurs, and the deviations accumulate and appear as count deviations.

  In the example shown in FIG. 7B, the time when the data packet 50 from the system 1B is received by the receiving unit 23A is not the time corresponding to the count value t4, but is delayed by the time difference d of the clock signal from that time. The time point, that is, the time point corresponding to the count value t4 ′. The receiving unit 23A calculates the difference between the count value t4 ′ obtained by subtracting the latency L of the cross link 2 and the count value t3 as a count deviation between the count value of the time counter 21A and the count value of the time counter 21B. To do. In step 309, the count deviation d is calculated in this way.

  Returning to FIG. 5, in the next step 311, the receiving unit 23A outputs the data packet 50 stored in the FIFO memory 40A to the packet processing unit 24A. At this time, the count deviation calculated in step 309 is also output to the packet processing unit 24A.

  Next, the operation of the packet processing unit 24A will be described. FIG. 6 shows a flowchart of the operation of the packet processing unit 24A. As shown in FIG. 6, when a reset signal (not shown) is input after the power is turned on, the operation of the packet processing unit 24A is started. First, in step 401, the packet processing unit 24A performs an initialization process. . After the initialization process, in step 403, the packet processing unit 24A waits until the data packet 50 and the count deviation are input from the receiving unit 23A.

  When the data packet 50 is input, the packet processing unit 24A proceeds to Step 405. In step 405, the packet processing unit 24A waits until the count value of the time counter 21A reaches the count value stored in the execution time field 55. When the count value of the time counter 21A becomes the count value stored in the execution time field 55, the packet processing unit 24A proceeds to Step 407. In step 407, the data packet 50 is input to the CPU unit 20A. Thereby, in the CPU unit 20A, processing based on the data packet 50 is executed at a time corresponding to the count value stored in the execution time field 55. For example, in the example shown in FIG. 7A, when the count value of the time counter 21A reaches t2, the data packet 50 is input to the CPU unit 20A and stored in the data field 53 of the data packet 50. Processing using data is executed.

  In the next step 409, the packet processing unit 24A determines whether or not the absolute value of the count deviation input from the receiving unit 23A exceeds a threshold value. Only when this determination is affirmative, step 411 is executed. In step 411, the packet processing unit 24A outputs the count deviation to the PLL control unit 25A. The PLL control unit 25A changes the parameters of the PLL 11A and adjusts the frequency of the clock signal output from the PLL 11A so that the count deviation is reduced.

  Thus, every time the data packet 50 is input from the receiving unit 23A, the packet processing unit 24A performs time adjustment of the input of the data packet 50 to the CPU unit 20A and controls the PLL 11A when necessary. Yes.

  In FIG. 7B, the frequency of the clock signal of the system 1A is higher than the frequency of the clock signal of the system 1B. In this case, the packet processing unit 24A controls the PLL control unit 25A based on this count deviation so that the frequency of the clock signal of the system 1A is lowered, that is, the frequency approaches the frequency of the lower clock signal. In this manner, the PLL 11A is adjusted.

  If such a count shift is detected in the system 1A, a count shift with the opposite polarity is detected in the system 1B, and the clock signal in the system 1B is also adjusted. It is desirable that the frequency of the clock signals of the systems 1A and 1B be adjusted to a frequency intermediate between the frequencies of the two signals so far.

  FIG. 7C shows a case where the clock signal input to the CPU subsystem 12A and the clock signal input to the CPU subsystem 12B are not shifted and are completely synchronized. In this case, the CPU units 20A and 20B execute the same processing at the same actual time (time corresponding to the count value t4). Based on determinism, the CPU units 20A and 20B output the same data to the transmission units 22A and 22B at the same time, and the data output to the transmission units 22A and 22B are received at the same time at the reception unit 33A, 33B and output simultaneously from the I / O devices 30A and 30B. In the data processing apparatus 100 according to the present embodiment, the state shown in FIG. 7C is normally maintained. Then, when the state shown in FIG. 7B is reached due to the characteristics of the clock sources 10A and 11B, that is, subtle variations in the clock signal, the above-described adjustment of the clock signal is performed, and FIG. Return to the indicated state. Thereby, lockstep synchronization is realized.

  As described above in detail, the data processing apparatus 100 according to the present embodiment includes at least two systems 1A and 1B each having the CPU units 20A and 20B and the I / O devices 30A and 30B. In the system 1A, the data packet 50 is transmitted and received between the I / O device 30A and the CPU unit 20A. The data packet 50 transmitted from the I / O device 30A to the CPU unit 20A is a time counter at the time of transmission. A count value (first count value) of 21A is added and transmitted to another system 1B. Furthermore, the receiving unit 23A receives the data packet 50 transmitted from the I / O device 30A to the CPU unit 20A and also receives the data packet 50 transmitted from the other system 1B. At the time of reception, the count value (third and fourth count values) of the time counter 21A is acquired. Then, the count deviation between the time counter 21A and the time counter 21B is calculated based on the third count value and the fourth count value of data having the same first count value, and the calculated count Based on the deviation, the frequency of the clock signal input to the time counter 21A and the CPU unit 20 is adjusted.

  In the present embodiment, the system 1B operates in the same manner as the system 1A.

  In this way, even if the frequency of the clock signal input to the CPU units 20A and 20B of the systems 1A and 1B is slightly different and a count deviation occurs in the time counters 21A and 21B, the count deviation is reduced. In addition, the frequency of both clock signals can be adjusted. As a result, even if different clock sources are used as the clock sources of the systems 1A and 1B, lockstep synchronization can be maintained.

  In this embodiment, since the CPU units 20A and 20B are executed when the count values of the time counters 21A and 21B become the count values stored in the execution time field 55 of the data packet 50, the CPU unit 20A and 20B can be performed at the same time as the same processing.

  Note that steps 409 and 411 in FIG. 6 may be performed while waiting for the execution time in step 405.

<< Second Embodiment >>
Next, a second embodiment of the present invention will be described in detail with reference to the flowchart of FIG. 8 and the timing chart of FIG. Since the data processing apparatus according to the present embodiment is the same as the configuration of the data processing apparatus 100 according to the first embodiment, detailed description thereof is omitted. In the data processing apparatus 100 according to the present embodiment, the operations of the packet processing units 24A and 24B are different from those in the first embodiment.

  FIG. 8 shows a flowchart of the operation of the packet processing unit 24A according to the present embodiment. As shown in FIG. 8, the present embodiment is different from the flowchart of FIG. 6 in that the processes of steps 413, 415, and 417 are newly added. Since other points are the same as those of the first embodiment, detailed description thereof is omitted.

  When the data packet 50 is input from the receiving unit 23A and the determination in step 403 is affirmed, the packet processing unit 24A proceeds to step 413. In step 413, the packet processing unit 24A calculates a difference (margin) between the count value stored in the execution time field 55 of the data packet 50 and the count value of the current time counter 21A. The timing chart of FIG. 9 shows an example in which the count value stored in the execution time field 55 of the data packet 50 is t2, and the count value of the time counter 21A is t2 '. In this case, the packet processing unit 24A calculates a difference M between the count value t2 and the count value t2 '.

  Returning to FIG. 8, after step 413, the packet processing unit 24A waits for the execution time (step 405) → data input to the CPU unit 20A (step 407) → determination of count deviation, as in the first embodiment. (Step 409) → Count deviation output (step 411) when the above determination is affirmed.

  After the determination is denied in step 409 or after step 411 is executed, the packet processing unit 24A proceeds to step 415. In step 415, the packet processing unit 24A determines whether or not the margin exceeds a threshold value. This threshold value is a different threshold value from the threshold value in step 409. If this determination is positive, the process proceeds to step 417, and the margin is output to the PLL control unit 25A. The PLL control unit 25A changes the parameters of the PLL 11A so as to reduce this margin, and finely adjusts so that the frequency of the clock signal is increased. In this way, the execution time of the CPU unit 20A can be accelerated, so that the processing speed of the data processing apparatus 100 is improved.

  The packet processing unit 24B operates in the same manner as the packet processing unit 24A, and outputs a margin to the PLL control unit 25B. Similarly to the PLL control unit 25A, the PLL control unit 25B also changes the parameters of the PLL 11B so as to reduce this margin and finely adjusts the frequency of the clock signal to be high. As a result, the execution time of the CPU unit 20B is accelerated in the same manner as the execution time of the CPU unit 20A, and no deviation occurs between the execution time of the CPU unit 20A and the execution time of the CPU unit 20B.

  Note that the order of steps 409 and 411 and steps 415 and 417 may be reversed. Also, steps 409, 411, 415, and 417 in FIG. 8 may be performed while waiting for the execution time in step 405.

<< Third Embodiment >>
Next, a third embodiment of the present invention will be described in detail with reference to FIGS. FIG. 10 shows the configuration of the data processing apparatus 100 according to the present embodiment. As shown in FIG. 10, the data processing apparatus 100 according to the present embodiment is different from the above embodiments in that reception units 23A ′ and 23B ′ are provided instead of the reception units 23A and 23B. ing. The receiving units 23A ′ and 23B ′ according to the present embodiment correspond to a reset unit.

  The receiving unit 23A ′ is different from the receiving unit 23A in that it outputs a reset signal to the time counter 21A, and the receiving unit 23B ′ is different from the receiving unit 23B in that it outputs a reset signal to the time counter 21B. Yes. When the reset signal is output, the count values of the time counters 21A and 22B are reset to zero.

  FIG. 11 shows a flowchart of the operation of the receiving unit 23A ′ according to this embodiment. As shown in FIG. 11, the present embodiment is different from the flowchart of FIG. 5 in that the processes of steps 313 and 315 are newly added.

  In step 309, after the count difference between the time counter 21 </ b> A and the time counter 21 </ b> B is calculated, the reception unit 23 </ b> A ′ proceeds to step 313. In step 313, the receiving unit 23A 'determines whether or not the absolute value of the count deviation exceeds a threshold value. If this determination is positive, the reception unit 23A ′ proceeds to step 315, and if negative, the reception unit 23A ′ proceeds to step 311. As the threshold value, a value larger than the threshold value in step 409 in FIG. 8, that is, a value that can be regarded as a synchronization error is set.

  In step 315, the receiving unit 23A 'performs a reset process. That is, if the time difference between the reception time of the data packet 50 from the transmission unit 32A and the reception time of the data packet 50 from the other system 1B is too large, it is assumed that a synchronization error has occurred, and the reception unit 23A ′ A reset signal is output to the time counter 21A. Thereby, the count value of the time counter 21A becomes 0, and the count-up from 0 is started.

  In step 315, the receiving unit 23A 'rewrites the count value already received and stored in the execution time field 55 of the data packet 50 held in the FIFO memory 40A with the reset count value.

  Thus, when a synchronization error is detected in the receiving unit 23A ', the synchronization error is also detected in the receiving unit 23B' of the system 1B. Accordingly, the receiving unit 23B 'also outputs a reset signal to the time counter 21B. As a result, the count values of the time counters 21A and 21B are reset almost simultaneously, and the drift of the count values of both due to the frequency of the clock signal is eliminated.

  After executing Step 315, the process proceeds to Step 311 and the receiving unit 23A 'outputs the data packets 50 stored in the FIFO memory 40A to the packet processing unit 24A in the order in which they are stored. At this time, since the time counter 21A is reset, the count deviation is not output to the packet processing unit 24A. The packet processing unit 24A performs the same processing as in the above embodiments.

  In this embodiment, a synchronization error is detected based on the time difference between the reception time of the data packet 50 from the transmission unit 32A and the reception time of the data packet 50 from the other system 1B. However, for example, the FIFO memory 40A overflows Then, the time counter 21A may be reset on the assumption that a synchronization error has occurred.

<< Fourth Embodiment >>
Next, a fourth embodiment of the present invention will be described in detail with reference to FIG. Since the data processing apparatus according to the present embodiment is the same as the configuration of the data processing apparatus according to the third embodiment, detailed description of the configuration will be omitted. In the data processing apparatus 100 according to the present embodiment, the operations of the receiving units 23A ′ and 23B ′ are different from those of the third embodiment. The receiving units 23A ′ and 23B ′ according to the present embodiment correspond to a failure detecting unit.

  FIG. 12 shows a flowchart of the operation of the receiving unit 23A ′ according to this embodiment. As shown in FIG. 12, the present embodiment is different from the flowchart of FIG. 11 in that the processing of steps 317 and 319 is newly added.

  After executing Step 313 or Step 315, the receiving unit 23A 'proceeds to Step 317. In step 317, it is determined whether or not the data packet 50 stored in the FIFO memory 40A matches the data packet 50 stored in the FIFO memory 40B. If this determination is affirmed, the reception unit 23A ′ proceeds to step 311; otherwise, the reception unit 23A ′ proceeds to step 319.

  In step 319, error processing is performed. In this error processing, first, it is determined whether the system 1A has failed or the system 1B has failed. For example, if an error correction code is added to the data packet 50, an error in the data packet 50 can be detected based on the error correction code. As a result, it is possible to detect which of the data packet 50 held in the FIFO memory 40A and the data packet 50 held in the FIFO memory 40B has an error and to identify the failed system.

  For example, assume that an error is detected in the data packet 50 transmitted from the I / O subsystem 13A. In this case, the system 1A is stopped, and thereafter, the processing is continued only by the system 1B. Conversely, when an error in the data packet transmitted from the I / O subsystem 13B is detected, the system 1B is stopped, and thereafter, the processing is continued only by the system 1A. Then, maintenance or repair is performed on the system in which the failure is detected. If any failure of the I / O subsystem 13A, 13B is detected, only the I / O subsystem is stopped, and the CPU subsystem in the same system as the I / O subsystem is Processing may be continued in cooperation with an I / O subsystem of another system.

<< Fifth Embodiment >>
Next, a fifth embodiment of the present invention will be described in detail with reference to FIGS. FIG. 13 shows the configuration of the data processing apparatus 100 according to the present embodiment. The data processing apparatus 100 according to the present embodiment is different from the configuration of the data processing apparatus 100 according to the fourth embodiment in that reception units 33A ′ and 33B ′ are provided instead of the reception units 33A and 33B. Thus, the operations of the transmission units 22A and 22B are different from those of the fourth embodiment. Since other parts are the same as those in the fourth embodiment, detailed description thereof is omitted.

  As shown in FIG. 13, the receiving unit 33A 'is connected to the time counter 21A and the PLL control unit 25A, and the receiving unit 33B' is connected to the time counter 21B and the PLL control unit 25B. The reception units 33A ′ and 33B ′ receive the points that the PLL control units 25A and 25B can be controlled and the reset signals are output to the time counters 21A and 21B in the same manner as the packet processing units 24A and 24B. It is different from the parts 33A and 33B.

  FIG. 14 shows a flowchart of the operation of the transmission unit 22A. As shown in FIG. 14, the operation of the transmission unit 22A is different from the operation of the transmission unit 32A in that step 205 'is executed instead of step 205. In step 205 ', the transmission unit 22A stores the count value of the current time counter 21A in the transmission time field 54 of the data packet 50, and transmits the data packet 50 to the reception units 33A' and 33B '. That is, in the transmission unit 22A, the execution time field 55 transmits the data packet 50 without storing the count value.

  FIG. 15 shows a flowchart of the operation of the receiving unit 33A ′. As shown in FIG. 15, the operation of the reception unit 33A ′ is the same as the processing of Step 501 to Step 509, Steps 513 and 515, Steps 517 and 519, and the operation of the reception unit 23A of FIG. 309, steps 313 and 315, and steps 317 and 319 are the same. In step 511, the receiving unit 33A 'outputs the data packet 50 to the I / O device 30A.

  After execution of step 511, the receiving unit 33A ′ determines whether or not the absolute value of the count deviation calculated in step 509 is equal to or greater than a threshold value, and only when this determination is affirmed, in step 523, The count deviation is output to the PLL control unit 25A. As a result, the frequency of the clock signal input to the CPU subsystem 12A is adjusted. Note that since the threshold value in step 513 is a threshold value used for determination of synchronization error, a value larger than the threshold value in step 521 is set.

  Note that the reception unit 33A 'does not necessarily need to perform the processing in steps 513 and 515 and the processing in steps 517 and 519. Further, in the data processing device 100 according to the present embodiment, instead of the reception unit 23A ′ and the reception unit 23B ′, the reception unit 23A and the reception unit 23B are provided in the same manner as in the first and second embodiments. May be.

  Further, the order of steps 513 and 515 and steps 517 and 519 in FIG. 15 may be reversed.

  As is clear from the above description, in each of the above embodiments, steps 203 and 205 in FIG. 4 correspond to the first step, step 303 in FIG. 5 corresponds to the second step, and steps 305 and 309. Corresponds to the third process, steps 409 and 411 in FIG. 6 correspond to the fourth process, and steps 405 and 409 correspond to the fifth process. Further, step 413 in FIG. 8 corresponds to the sixth process, and steps 415 and 417 correspond to the seventh process. 14 corresponds to the eighth process, step 503 in FIG. 15 corresponds to the ninth process, steps 505 and 509 correspond to the tenth process, and steps 521 and 523 correspond to the eighth process. This corresponds to 11 steps.

  As described above in detail, according to each of the above embodiments, the time counter 21A is caused by the difference in the reception timing of the data packet 50 transmitted and received between the CPU units 20A and 20B and the I / O devices 30A and 30B. And the time counter 21B are detected, and the frequency of the clock signal of each of the systems 1A and 1B is adjusted based on the count difference. Thereby, the relative time difference of the execution time in the real time in the CPU units 20A and 30A can be kept within a certain range. As a result, the synchronization of both systems 1A and 1B is maintained.

  According to each of the above embodiments, since the frequency of the clock signal is adjusted, it is not necessary to match the execution timings of all the CPU subsystems with the CPU subsystem having a low execution speed. For this reason, the processing speed of the entire apparatus does not decrease. On the contrary, since the execution times of the CPU units 20A and 20B can be optimized as in the data processing apparatus according to the second embodiment, the processing capability of the entire apparatus is improved.

  Moreover, according to each said embodiment, lockstep synchronization is implement | achieved using the data transmitted / received via the cross link 2 essential in order to detect the failure of each system. That is, according to each of the above-described embodiments, since dedicated clock for comparing clock signals input to the CPU subsystems is not required to detect a clock signal shift, Hardware independence is guaranteed.

  Further, according to each of the above embodiments, since the frequency of the clock signal is adjusted, it is not necessary to periodically reset the clock signal input to each of the CPU subsystems 12A and 12B by giving a timer interrupt or the like. For this reason, even when the variation in the output frequency of the plurality of clock sources is large, the frequency of the clock signal input to each of the CPU subsystems 12A and 12B is quickly adjusted, and lock step synchronization can be maintained. .

  That is, according to the data processing apparatus according to each of the above-described embodiments, using the data packet 50 that is bidirectionally transmitted / received between the systems via the cross link 2, the synchronization between the systems 1A and 1B based on determinism is achieved. While realizing, the reception timing of the data packet 50 is measured and the frequency of the clock signal input to each system 1A, 1B is adjusted, so both systems 1A, 1B are synchronized even in real time. Be able to. As a result, the fault tolerance of the apparatus is improved, and its reliability is extremely high.

  Further, according to each of the above embodiments, for example, the time difference between the reception time of the data packet 50 in the system 1A and the reception time of the data packet 50 from the other system 1B at the reception unit 23A or the like becomes too large. It is also possible to prevent the FIFO memory 40A or the like in which the received data packet 50 is held from overflowing.

  Also, according to the second embodiment, the execution time margin of the CPU units 20A and 20B is calculated, and when the margin is large, the frequency of the clock signal is adjusted based on the margin. As a result, the execution times of the CPU units 20A and 20B can be made as early as possible. As a result, the processing speed of the entire data processing apparatus can be improved.

  Further, according to the above embodiments, the scheduled execution times of the CPUs 20A and 20B are set in consideration of the latency of the cross link 2. Thereby, after confirming that the synchronization between the systems 1A and 1B is maintained, the processing of the CPUs 20A and 20B can be executed. As a result, the CPUs 20A and 20B can be more reliably synchronized.

  Further, according to each of the above embodiments, the count deviation of the time counters 21A and 21B is detected in consideration of the latency of the cross link 2, so that the count deviation can be accurately detected. As a result, the CPUs 20A and 20B can be more reliably synchronized.

  Further, according to the third embodiment, when the time difference between the time counters 21A and 21B exceeds a predetermined level, the time counters 21A and 21B are reset. As a result, the systems 1A and 1B can be quickly recovered to the synchronized state. As a result, the CPUs 20A and 20B can be more reliably synchronized.

  Further, according to the fourth embodiment, the data packets 50 of both systems 1A and 1B are compared to detect a failure that has occurred in each system, so that the system in which the failure has occurred is excluded and only the remaining systems are excluded. You will be able to continue processing. As a result, the reliability of the entire apparatus is improved.

  Further, according to the first to fourth embodiments, the systems 1A and 1B are synchronized using data input to the I / O devices 30A and 30B. However, as in the fifth embodiment. If the systems 1A and 1B are synchronized using the data output from the CPUs 20A and 30B, the systems 1A and 1B can be synchronized more accurately, and the reliability of the apparatus is further improved.

  In each of the above embodiments, the receiving units 23A and 23B and the packet processing units 24A and 24B of the CPU subsystems 12A and 12B may be integrated. On the contrary, the receiving units 33A and 33B of the I / O subsystems 13A and 13B may be divided into a receiving unit and a packet processing unit in the same manner as the CPU subsystems 12A and 13B.

  In the data processing device 100 according to each of the embodiments described above, the system is a duplexed device. However, the present invention can be applied to a case where the system is more than tripled, that is, multiplexed. It is.

It is a block diagram which shows the structure of the data processor which concerns on the 1st Embodiment of this invention. It is a figure which shows the data structure of a data packet. It is a block diagram which shows the structure of the receiving part of FIG. It is a flowchart which shows operation | movement of the transmission part of FIG. It is a flowchart which shows operation | movement of the receiving part of FIG. It is a flowchart which shows operation | movement of the packet process part of FIG. FIG. 7A to FIG. 7C are timing charts showing timings related to data transmission / reception. It is a flowchart which shows operation | movement of the packet processing part which concerns on the 2nd Embodiment of this invention. It is a timing chart of the timing regarding transmission and reception of data. It is a block diagram which shows the structure of the data processor which concerns on the 3rd Embodiment of this invention. FIG. 11 is a flowchart showing an operation of the receiving unit in FIG. 10. FIG. It is a flowchart which shows operation | movement of the receiving part which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the data processor which concerns on the 5th Embodiment of this invention. It is a flowchart which shows operation | movement of the transmission part of FIG. It is a flowchart which shows operation | movement of the receiving part of FIG.

Explanation of symbols

1A, 1B system 2 Crosslink 10A, 10B Clock source 11A, 11B PLL
12A, 12B CPU subsystem 13A, 13B I / O subsystem 20A, 20B CPU unit 21A, 21B Time counter 22A, 22B Transmitter unit 23A, 23B, 23A ′, 23B ′ Receiver unit 24A, 24B Packet processing unit 25A, 25B PLL Control unit 30A, 30B I / O device 32A, 32B Transmitter 33A, 33B, 33A ', 33B' Receiver 40A, 40B, 41A, 41B FIFO memory 50 Data packet 51 Packet type field 52 Packet length field 53 Data field 54 Transmission Time field 55 Execution time field 100 Data processing device

Claims (13)

A data processing apparatus comprising at least two systems each having a processor and an input / output unit,
Each said system
A clock source for outputting a clock signal;
An adjusting unit that adjusts the frequency of the clock signal output from the clock source and inputs the frequency to the processor;
A time counter for measuring time based on the clock signal output from the adjustment unit;
When transmitting data input from the input / output unit to the processor, a first count value of the time counter at the time of transmission and a second execution time corresponding to the scheduled execution time at which the data is processed by the processor A first transmission unit that adds a count value to the data and transmits the data, and transmits the data to which the first and second count values are added to another system;
Receives data transmitted from the first transmitter, obtains a third count value of the time counter at the time of reception, and receives data transmitted from the first transmitter of the other system And a first receiving unit for obtaining a fourth count value of the time counter at the time of reception;
Based on the third and fourth count values of the added data having the same first count value, the count value of the time counter and the count value of the time counter of the other system are counted. A calculation unit for calculating the deviation;
A control unit that controls the adjustment unit such that the count deviation calculated by the calculation unit is reduced;
A holding unit for holding input of data received by the first receiving unit to the processor until a count value of the time counter becomes a second count value;
A second transmission unit that transmits data input from the processor to the input / output unit;
A data processing apparatus comprising: a second reception unit that receives data transmitted from the second transmission unit and outputs the data to the input / output unit. The holding section is
Calculating the difference between the second count value added to the data and the count value of the time counter;
The controller is
The data processing apparatus according to claim 1, wherein the adjustment unit is controlled so that a difference calculated by the holding unit is small. The first transmitter is
3. The second count value is added based on a time required for data transmission / reception between the systems and an allowable value of a time difference in processor processing between the systems. The data processing apparatus described in 1. The calculation unit includes:
4. The data processing apparatus according to claim 1, wherein the count deviation is calculated in consideration of a time required for data transmission / reception between the systems. 5.   5. The data processing according to claim 1, further comprising: a reset unit that resets the time counter when the count deviation calculated by the calculation unit exceeds a predetermined value. 6. apparatus.   6. The apparatus according to claim 1, further comprising a failure detection unit that detects occurrence of a failure by comparing the added data having the same first count value. Data processing equipment. The second transmitter is
When transmitting the data input from the processor to the input / output unit, the fifth count value of the time counter at the time of transmission is added and transmitted, and the data to which the fifth count value is added, Send it to the other system,
The second receiver is
Receives data transmitted from the second transmitter, obtains a sixth count value of the time counter at the time of reception, and receives data transmitted from the second transmitter of the other system And obtaining a seventh count value of the time counter at the time of reception,
The calculation unit includes:
Based on the sixth and seventh count values of the added data having the same fifth count value, the count value of the time counter and the count value of the time counter of the other system are counted. Calculate the deviation,
The controller is
The data processing apparatus according to claim 1, wherein the adjustment unit is controlled such that the count deviation calculated by the calculation unit is reduced. The calculation unit includes:
The data processing apparatus according to claim 7, wherein the count deviation is calculated in consideration of a time required for data transmission / reception between the systems.   The data processing apparatus according to claim 7, further comprising a reset unit that resets the time counter when the count deviation calculated by the calculation unit exceeds a predetermined value.   10. The apparatus according to claim 7, further comprising a failure detection unit that detects the occurrence of a failure by comparing the added data having the same fifth count value. 10. Data processing equipment. A synchronization method for synchronizing at least two systems, each having a processor, an input / output unit, and a time counter, and operating with clock signals from different clock sources,
When transmitting data input from the input / output unit to the processor, a first count value of the time counter at the time of transmission and a second execution time corresponding to the scheduled execution time at which the data is processed by the processor A first step of adding a count value to the data and transmitting the data, and transmitting the data with the first and second count values added to another system;
The data transmitted in the first step is received, the third count value of the time counter at the time of reception is acquired, the data transmitted from the other system is received, and the time at the time of reception is received. A second step of obtaining a fourth count value of the counter;
Based on the third and fourth count values of the added data having the same first count value, the count value of the time counter and the count value of the time counter of the other system are counted. A third step of calculating the deviation;
A fourth step of adjusting the frequency of the clock signal so that the count deviation calculated in the third step is reduced;
A fifth step of suspending input of the data received in the second step to the processor until the count value of the time counter reaches the second count value. A sixth step of calculating a difference between the second count value added to the data and the count value of the time counter;
The synchronization method according to claim 11, further comprising a seventh step of adjusting a frequency of the clock signal so that the difference calculated in the sixth step becomes small. When transmitting the data input from the processor to the input / output unit, the fifth count value of the time counter at the time of transmission is added and transmitted, and the data to which the fifth count value is added, An eighth step of transmitting to the other system;
The data transmitted in the eighth step is received, the sixth count value of the time counter at the time of reception is obtained, the data transmitted from the other system is received, and the time at the time of reception is received. A ninth step of obtaining a seventh count value of the counter;
Based on the sixth and seventh count values of the added data having the same fifth count value, the count value of the time counter and the count value of the time counter of the other system are counted. A tenth step of calculating the deviation;
The synchronization method according to claim 11, further comprising an eleventh step of adjusting a frequency of the clock signal so that the count deviation calculated in the tenth step is reduced. .

Images