JP2000200255A - Method and circuit for synchronization between processors - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and speedily synchronize processors in operation in a multiprocessor system. SOLUTION: Processors 10a and 10b which request themselves to be synchronized with each other a read access to the synchronizing circuit 21. The synchronizing circuit 21 pass answer data showing that the synchronization is successful to the processors when the read access from the processors is completed within a predetermined time. When not, on the other hand, the circuit passes answer data showing that the synchronization ends in failure to the processors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing system having a plurality of processors, and more particularly to a system for synchronizing processors so that a plurality of processors operating at the same clock execute the same processing.

[0002]

2. Description of the Related Art Conventionally, there has been known a system in which a plurality of processors are multiplexed and the same processing is executed in synchronization with each other in order to improve the reliability of the system. In such a system, for example, a synchronization method during system operation is required in order to perform a multiplexing operation again after a recovery process for the occurrence of a failure.

As a method of such synchronization, for example, there is a method described in Japanese Patent Application Laid-Open No. 08-278950. In this publication, in a multiplexed computer system composed of a plurality of arithmetic processing devices, when re-synchronizing an arithmetic processing device recovered from a failure, an arithmetic processing device operating normally and an arithmetic processing device recovered from a failure Thus, an access request is made to a predetermined address, and the time difference between the access request time from the normally operating arithmetic processing device and the access request time from the arithmetic processing device that has recovered from the failure is a predetermined time difference. If it is within the range, both arithmetic processing units receive an access permission from the processing device to which both arithmetic processing units are connected, and use the access from both arithmetic processing units that have received the access permission as a reference signal for synchronization, and A failure recovery method for resynchronizing the operation of an arithmetic processing unit is described.

[0004]

However, in the above-described method, there is a time difference between the time when the reference signal for synchronization is obtained and the time when the synchronization processing is completed. It takes.

An object of the present invention is to provide a synchronizing method and a synchronizing circuit for easily and quickly realizing synchronization between a plurality of processors during system operation.

[0006]

A synchronization method according to the present invention is a method for synchronizing a plurality of processors operating with clocks of the same frequency. Then, in the first synchronization method according to the present invention, each processor performs access (for example, read access) to a predetermined address,
If the access is performed by another processor within a predetermined time from the start of access of the processor that first accessed, the first processor responds to the access of the processor that last accessed the first processor. Is returned.

[0007] The first response data is data for notifying each processor that synchronization has been successful among all the processors, for example.

[0008] A second synchronization method according to the present invention provides:
The first processor issues an interrupt request to each processor, and each processor that has received the interrupt request accesses a predetermined address as an interrupt process, and performs an access first. When an access is made from another processor within a predetermined time from the start of access of the processor, the first response data is returned to each processor in response to the access of the processor that made the last access. It is characterized by.

In this case, if the access from at least one processor is not within the predetermined time, second response data is returned to the accessing processor in response to the lapse of the time. You may do so.

[0010] The second response data is data for notifying each processor that, for example, synchronization has not been successful for at least one processor. Each processor that has received the second response data may interrupt the synchronization process and perform another process.

A synchronization circuit according to the present invention is a synchronization circuit for synchronizing a plurality of processors operating with clocks of the same frequency. And the first synchronous circuit according to the present invention comprises:
Detecting means for detecting an access from each processor, and when the access from each processor is performed within a predetermined time from the start of access of the processor that first accessed, the processor that last accessed the processor Response means for returning first response data to each processor in response to the access.

In this case, for each processor,
An interrupt generating means for generating an interrupt request may be further provided. The interrupt generating means may generate an interrupt request to each processor when receiving an access (for example, a write access) from each processor.

If the access from at least one processor is not within a predetermined time, the response means may access the second response data in response to the lapse of the time. May be returned. Further, a data waiting signal may be output to the accessing processor until the response data is returned.

A multiplexing system according to the present invention is a multiplexing system including a plurality of processors operating with clocks of the same frequency, characterized by including the above-described synchronization circuit.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a duplex system to which the present invention is applied.

As shown in FIG. 1, the present system comprises an A-system 1a, a B-system 1b, a bus controller 2,
An I / O device 4 and a clock generation circuit 8 are provided.

A system 1a and B system 1b
Are connected to the bus control unit 2 via buses 3a and 3b, respectively. The bus control unit 2 and the I / O device 4 are connected by a common bus 5.

The clock generation circuit 8 includes the A system 1
a, The same clock 9 is supplied to the B-system 1b and the bus controller 2. The A-system 1a, the B-system 1b, and the bus controller 2 operate in synchronization with the clock 9.

The A-system 1a includes a processor 10a for executing predetermined arithmetic processing, a memory 11a for storing a processing program of the processor and arithmetic data, and an I / O device 12a for executing predetermined operations in accordance with instructions from the processor.
, And each component is connected to the bus 3a.

The B-system 1b has the same configuration as the A-system 1a, and has a processor 10b and a memory 1b.
1b and an I / O device 12a, and each component is connected to a bus 3b.

The bus control unit 2 comprises a bus control circuit 20 and a synchronizing circuit 21.
a, 3b.

The bus control circuit 20 includes both buses 3a, 3b
And control of access to the I / O device 4 on the common bus 5 from both systems 1a and 1b.

The A-system processor 10a and the B-system processor 10b execute the same processing in synchronism, and the bus control circuit 20 compares and compares the signals of the two-system buses 3a and 3b, thereby obtaining the two-system system. In 1a and 1b, it is monitored whether or not the same processing is being executed in synchronization.

The synchronizing circuit 21 includes two processors 10a,
Synchronization of both processors is realized by receiving read access from 10b and returning response data to the access to both systems simultaneously.

The synchronizing circuit 21 includes two processors 10a,
For example, it is mapped to a predetermined area of the address space of each of the processors 10a and 10b so as to be accessible from the processor 10b. Further, the synchronization circuit 21 sends the wait signals 6a, 6b to return the response data to both systems simultaneously.
Is used to control the state of the processor. Note that the wait signals 6a and 6b are a type of control signal on the buses 3a and 3b.

In the duplex system shown in FIG. 1, when the two processors 10a and 10b are executing the same processing, for example, if a synchronization error occurs due to a failure or the like, a predetermined error recovery processing is performed. Later, both processors 10
The synchronization circuit 21 is accessed to synchronize a and 10b again. This makes it possible to easily synchronize the processors.

That is, when the time difference between the access times from the processors is within a predetermined value, the synchronization circuit 21 realizes synchronization between the processors by simultaneously returning specific response data to the processors. .

FIG. 2 is a diagram showing a configuration of the synchronization circuit 21 shown in FIG.

As shown in the figure, the synchronization circuit 21 includes decoders 211a and 211b, flags 212a and 212b for holding the presence or absence of a synchronization request from each system, weight control circuits 210a and 210b, and an AND gate 213. It is composed of

The decoders 211a and 211b are connected to the bus 3
When the access to the synchronization circuit 21 is detected from the address and the control signal output on a and 3b, the synchronization request signal 215a and 215b are output.

When the synchronization request signals 215a and 215b are asserted, the flags 212a and 212b become logical 1
Is kept in synchronization with the clock. AND gate 213
Takes the logical product of the values of the flags 212a and 212b and outputs the result as a synchronization signal 216. That is, the synchronization signal 216 has the logical value 1 when the read access to the synchronization circuit 21 is being executed from both systems. Therefore, the synchronization signal 216 is a reference signal for simultaneously executing responses to accesses from both systems.

The weight control circuits 210a, 210
b generates wait signals 6a and 6b from the synchronization request signals 215a and 215b and the synchronization signal 216, and outputs response data to read access to the synchronization circuit 21 on the buses 3a and 3b.

FIG. 3 shows the weight control circuit 2 shown in FIG.
It is a figure which shows the internal structure of 10a. The weight control circuit 210b has the same configuration as the weight control circuit 210a.

As shown in FIG.
0a is a data output unit 2100a and a timer 2101a
And an AND gate 2102a.

The data output unit 2100a outputs the synchronization signal 2
When 16 is asserted, the data value "1" is output as the response data on the bus 3a, otherwise the data value "0" is output.

The timer 2101a starts measuring time at the rise of the synchronization request signal 215a, and asserts a time-up signal 2103a when a predetermined time-up time comes.

The AND gate 2102a calculates the logical product of the negation of the synchronization signal 216, the negation of the synchronization request signal 215a, and the negation of the time-up signal 2103a, and outputs the result as a wait signal 6a.

That is, the wait signal 6a is asserted simultaneously with the assertion of the synchronization request signal 215a (since the synchronization signal 216 and the time-up signal 2103a are normally negated), and access to the synchronization circuit 21 is prevented. The synchronization signal 216 is asserted when executed from both systems, or the wait signal 6 is asserted for a predetermined time.
This signal is negated when the time-up signal 2103a is asserted while the signal a is continuously asserted.

Next, the operation of the synchronization circuit 21 will be described.

FIG. 4 is a time chart showing the operation of the synchronization circuit 21 when synchronization is successful.

As shown in FIG.
When the processor 10a performs read access to the synchronization circuit 21, the synchronization request signal 215a is asserted in the cycle t1.

Thus, the logic value 1 is set in the flag 212a in the next cycle t2. Further, the wait signal 6a is asserted in the t1 cycle, the processor 10a enters the wait state in the next t2 cycle, and the synchronization request signal 215a is kept asserted. The t3 cycle is the same as the t2 cycle.

The processor 1 of the B system 1b
0b makes read access to the synchronous circuit 21 and t
When the synchronization request signal 215b is asserted in four cycles, the logical value 1 is set in the flag 212b in the next t5 cycle. Also, the wait signal 6b in cycle t4
Is asserted, and in the next t5 cycle, the processor 10b
Are in a wait state, and the synchronization request signal 215b is kept asserted.

In the cycle t5, the flag 212a,
Each of the values of 212b becomes a logical value 1 and the synchronization signal 2
16 is asserted, and wait signals 6a and 6b are both negated. As a result, in the next t6 cycle, the synchronization request signals 215a and 215b are both negated, and the synchronization of the processors 10a and 10b is realized. Further, in the t5 cycle, as response data,
"1" is output on the buses 3a and 3b to notify the processors 10a and 10b that the synchronization has succeeded.

FIG. 5 is a time chart showing the operation of the synchronization circuit 21 when synchronization fails.

As shown in FIG.
When the processor 10a performs read access to the synchronization circuit 21, the synchronization request signal 215a is asserted in the cycle t1.

As a result, the logical value 1 is set in the flag 212a from the next cycle t2. Further, the wait signal 6a is asserted in the t1 cycle, the processor 10a enters the wait state from the next cycle, and the synchronization request signal 215a is kept asserted.

If the access from the processor 10b of the B-system system 1b is not executed even if the predetermined time tx has elapsed, the time-up signal 2103a is asserted in the t2 cycle, and the wait signal 6
a is negated. As a result, in the next t3 cycle,
The synchronization request signal 215a is negated. in this case,
Since the synchronization signal 216 is not asserted, "0" is output to the bus 3a as response data, and the processor 10a is notified that synchronization has failed.

Next, a synchronization method using the above-described system configuration will be described.

FIG. 6 is a flowchart showing a synchronization process executed by each processor to synchronize the processors 10a and 10b. As shown in the figure, each processor first performs read access to the synchronous circuit 21 (S80). Then, the value of the response data to the read access is determined (S81). As a result, when the value of the response data is “0”, the synchronization has failed, and the access to the synchronization circuit 21 is repeated until the synchronization succeeds (S80). On the other hand, when the value of the response data is “1”,
Since the synchronization has succeeded, the synchronization processing ends. The processors 10a and 10b can realize synchronization between the processors by executing such simple processing.

FIG. 7 is a flow chart showing the processing of each processor in the duplex system shown in FIG. 1 from when an error occurs to when recovery processing is performed and duplex processing is resumed.

During normal duplication processing by the system, the results of the bus comparison by the bus control circuit 2 match. However, if the processing of one of the processors temporarily changes for some reason and the result of the bus comparison becomes inconsistent, the system detects the occurrence of an error. After detecting the occurrence of the error, if the error can be recovered, the system performs a predetermined recovery process and resumes the normal process. for that reason,
After executing processing such as restoration of the saved data, each processor performs the synchronization processing shown in FIG. 6 in order to perform resynchronization.

That is, first, each processor makes a read access to the synchronous circuit 21, and when the response data of the synchronous circuit 21 to the read access is "0", the read to the synchronous circuit 20 is repeatedly executed. Then, when the response data of the synchronization circuit 20 to the read access becomes “1”, it is detected that the synchronization has succeeded, and the duplexing process is restarted. As described above, in the present embodiment, resynchronization when a synchronization error occurs can be easily performed.

FIG. 8 is a diagram showing a state of processing in each processor when synchronizing the processors.

As shown in the figure, the processor 10a that has executed the process A1 in the non-synchronized state starts the first synchronization process in the next process in order to synchronize the processors. At this time, the processor 10b is executing the processing B1 and the processing B2,
The synchronization by the first synchronization processing of a does not succeed.

Subsequently, the processor 10a starts a second synchronization process. While the processor 10a is executing the second synchronization process, the processor 10b also executes the synchronization process, and the synchronization succeeds here. Thus, in the subsequent processing, the processors 10a and 10b can execute the same processing synchronously.

In the above description, the control for returning the response data to both systems at the same time using the wait signals 6a and 6b is performed. However, the present invention is not limited to this. Control may be performed to return response data to both systems at the same time (for example, a data acknowledge signal).

In the multiplexing system described above, the A-system processor 10a and the B-system processor 10
b executed the same processing. However, in a multiplexed system, in order to achieve more complicated operations, it is possible to make each processor perform different operations and synchronize only when performing processes that require reliability and security to perform the same process. Conceivable.

As described above, the above-described method can be applied even when synchronizing processors that are completely different in operation, but in the above-described system configuration, a long time may be required for synchronization. . So, next,
A redundant system more suitable for such a case will be described.

FIG. 9 is a diagram showing a configuration of a second duplex system to which the present invention is applied. In this system, even when each processor is operating completely asynchronously, synchronization can be successfully completed in a short time.

The system shown in FIG.
The configuration is the same as that of the system shown in FIG. 1 except that an interrupt generation circuit 23 is added.

The interrupt generation circuit 23 is connected to the buses 3a and 3b, and receives an access (for example, a write access) from the processors 10a and 10b, and
0a and 10b, respectively, an interrupt request signal 7a,
7b is output.

The processors 10a and 10b receiving the interrupt request signals 7a and 7b execute predetermined interrupt processing.

FIG. 10 is a diagram showing a configuration of the interrupt generation circuit 23.

As shown in the figure, the interrupt generation circuit 23
Decoders 230a and 230b and interrupt pulse generation circuit 2
31a and 231b and OR gates 232a and 232b.

The decoders 230a and 230b are connected to the bus 3
When an access to the interrupt generation circuit 23 is detected based on the address and control signals output on a and 3b, access request signals 233a and 233b are output.

Interrupt pulse generating circuits 231a, 231b
Outputs the interrupt pulses 234a and 234b when the access request signals 233a and 233b are asserted. The interrupt pulses 234a and 234b are connected to the OR gate 232a,
The interrupt request signals 7a and 7b are output to both of the processors 10a and 10b via 232b.

FIG. 11B is a diagram showing the state of the processing of each processor when synchronizing the processors operating completely differently in the system shown in FIG. For comparison, FIG. 11A shows a state of processing of each processor when synchronizing between processors in the system shown in FIG. 1 under the same situation.

In FIG. 11A, the processor 10a
Starts the synchronization process in the process following the process A1. However, the processor 10b starts the synchronization processing after executing the processing B1 to the processing B4.
Will fail to synchronize until the third synchronization process is performed. In other words, it takes at least twice as long as the time for the timer 2101a to time up until the synchronization is successful.

On the other hand, in FIG. 11B, the processor 10a executes an interrupt generation circuit 23 in a process following the process A1.
Is executed to generate an interrupt. If the synchronous processing in FIG. 6 is designated as the interrupt processing, the processor 10a receives the interrupt request signal 7a and starts the synchronous processing. Also, in the processor 10b, the interrupt request signal 7b is asserted during the execution of the process B2, and the process following the process B2 is an interrupt process, and the synchronous process is started. That is, in this case, the processor 10a succeeds in synchronization in the first synchronization process.

As described above, if the interrupt generation circuit 23 shown in FIG. 9 is used, synchronization can be quickly realized even when each processor operates completely differently.

In the above description, a duplicated system has been described as an example. However, the present invention can be applied to a system in which more processors are multiplexed. In this case, a plurality of processors may execute access to the synchronization circuit, and when all processors perform access, response data for notifying that synchronization has succeeded may be passed simultaneously.

In the above description, clocks of the same phase are input to each processor, but clocks of the same frequency having different phases (for example, clock phases shifted by half a cycle) are input. You may. In this case, the bus control circuit 20 performs signal comparison and collation after synchronizing the phases of the signals of the buses 3a and 3b in consideration of the phase shift. The synchronization circuit 21 returns response data to each processor at a timing for each processor in consideration of a phase shift.

[0075]

As described above in detail, according to the present invention, a synchronous circuit passes specific response data at a specific timing (for example, simultaneously) to read accesses from a plurality of processors, It is possible to easily synchronize the processors. Furthermore, by executing access to the synchronous circuit as an interrupt process using the interrupt generation circuit, the processors can be quickly synchronized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a duplex system according to the present invention.

FIG. 2 is a diagram showing a configuration of a synchronization circuit 21.

FIG. 3 is a diagram illustrating a configuration of a weight control circuit 210a.

FIG. 4 is a time chart showing the operation of the synchronization circuit 21 when synchronization is successful.

FIG. 5 is a time chart showing the operation of the synchronization circuit 21 when synchronization fails.

FIG. 6 is a diagram illustrating a flowchart of a synchronization process executed by each processor for synchronization.

FIG. 7 is a flowchart showing a process up to restart of the duplexing process after an error occurs in the duplexing system.

FIG. 8 is a diagram showing a state of processing of processors 10a and 10b when performing synchronization between processors.

FIG. 9 is a diagram showing a configuration of a second duplex system according to the present invention.

FIG. 10 is a diagram showing a configuration of an interrupt generation circuit 23.

FIG. 11 is a diagram showing a state of processing of processors 10a and 10b when synchronizing between processors.

[Explanation of symbols]

 1a A-system 1b B-system 2 Bus controller 3a, 3b Bus 4 I / O device 5 Common bus 6a, 6b Wait signal 8 Clock generator 9 Clock signal 10a, 10b Processor 11a, 11b Memory 12a, 12b I / O device 20 Bus control circuit 21 Synchronous circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Naoto Miyazaki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Michio Fujiwara 1070, Imo, Hitachinaka-shi, Ibaraki Shares Inside the Mito Plant of Hitachi, Ltd. (72) Inventor Naohiro Ikeda 1070 Ma, Hitachinaka-shi, Ibaraki F-term inside the Mito Plant of Hitachi, Ltd. FB (reference)

Claims (8)

[Claims] 1. A method for synchronizing a plurality of processors operating with a clock having the same frequency, wherein each processor accesses a predetermined address and starts access of a processor that has accessed first. When the access is performed from another processor within a predetermined time from the first processor, the first response data is returned to each processor in response to the access of the processor that has accessed last. Synchronization method. 2. A method for synchronizing a plurality of processors operating with a clock having the same frequency, wherein a first processor issues an interrupt request to each processor, and each processor receives the interrupt request. Performs an access to a predetermined address as an interrupt process, and when the access is performed from another processor within a predetermined time from the start of access of the processor that first accesses the address, A method of synchronizing, wherein first response data is returned to each processor in response to an access of a processor that has accessed last. 3. If the access from at least one processor is not within the predetermined time, returning the second response data to the accessing processor in response to the lapse of the time. The synchronization method according to claim 1 or 2, wherein 4. A synchronizing circuit for synchronizing a plurality of processors operating with a clock of the same frequency, wherein a detecting means for detecting an access from each processor and an access from each processor perform an access first. Response means for returning first response data to each processor in response to the access of the processor which has made the last access when the access is performed within a predetermined time from the start of the access of the processor. And a synchronous circuit. 5. The synchronous circuit according to claim 4, further comprising an interrupt generating means for generating an interrupt request for each processor. 6. When the access from at least one processor is not within the predetermined time, the response means responds to the lapse of the time by providing a second response to the processor performing the access. The synchronization circuit according to claim 4, wherein the synchronization circuit returns data. 7. The apparatus according to claim 4, wherein the response unit outputs a data waiting signal to the processor that has accessed the data until the response data is returned. Synchronous circuit. 8. A multiplexing system comprising a plurality of processors operating with clocks of the same frequency, wherein the multiplexing system comprises the synchronization circuit according to any one of claims 4 to 7. system.