JP5849849B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device provided with an identification marking for a semiconductor chip on which a semiconductor element is formed.

  Conventionally, in Patent Document 1, a semiconductor device is configured using a semiconductor substrate having an element circuit formed on a first main surface, an element circuit formation prohibition region is provided on the first main surface, and this element circuit formation prohibition is provided. There has been proposed a structure in which a metal pattern for displaying the direction of a semiconductor device is formed in a region. With such a structure, the metal pattern can be identified and the direction of the semiconductor device can be recognized by performing transmission imaging on the semiconductor substrate.

JP 2005-322704 A

  However, in the semiconductor device described in Patent Document 1, the first main surface side of the semiconductor substrate is covered with the sealing resin, and is connected to the element circuit on the opposite side of the semiconductor substrate with the sealing resin interposed therebetween. It is a structure provided with external metal terminals composed of bumps. For this reason, the metal pattern cannot be identified unless the semiconductor substrate is photographed through transmission. In addition, a metal pattern can be identified in a structure in which an electrode is formed not only on the first main surface but also on the back surface opposite to the first main surface as in a semiconductor device in which a vertical semiconductor element is formed. Have difficulty. Therefore, it is required to make it possible to more easily identify a marking constituted by a metal pattern or the like.

  An object of this invention is to make it possible to identify the marking which consists of a metal more easily in view of the said point.

In order to achieve the above object, the invention according to claim 1 is formed using a semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface, A surface electrode having a cell region (2) in which a semiconductor element is formed and an outer peripheral region (3) formed on the outer periphery surrounding the cell region, and on the main surface side, the cell region is connected to the semiconductor element The first electrode (4) is formed, and an identification marking (9) made of metal is provided. The height from the main surface of the first electrode is higher than the height from the main surface of the identification marking. It is also characterized by high price.

  In the semiconductor device configured as described above, an identification marking made of metal is provided on the main surface side of the semiconductor substrate, that is, on the same surface as the surface on which the first electrode serving as the surface electrode is formed. For this reason, it is possible to easily identify the identification marking without performing the transmission imaging of the semiconductor substrate instead of the conventional structure covered with the sealing resin.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a top layout view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing on the II-II line of FIG. It is sectional drawing of the semiconductor device concerning 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device demonstrated by other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the semiconductor device of the present embodiment uses a semiconductor substrate 1 made of, for example, silicon carbide (hereinafter referred to as SiC) having a main surface 1a on one side and a back surface 1b on the opposite side. An element is formed and the semiconductor chip is used as the element.

  As shown in FIGS. 1 and 2, the semiconductor device is configured such that a region where a vertical semiconductor element is formed is a cell region 2, and an outer peripheral portion of the cell region 2 is an outer peripheral region 3. The vertical semiconductor element is configured to pass a current through the main surface 1a and the back surface 1b of the substrate, and includes a vertical power MOSFET, a vertical IGBT, a vertical diode, and the like. In the present embodiment, a case where a vertical power MOSFET is provided as an example of the vertical semiconductor element will be described. However, other vertical semiconductor elements such as a vertical IGBT and a vertical diode may be formed. . In the cross section shown in FIG. 2, various diffusion layers, interlayer insulating films, metal patterns and the like constituting the vertical power MOSFET are actually formed on the semiconductor substrate 1, but the vertical power MOSFET is well known. Since it is a structure, illustration is omitted here.

  In the cell region 2, a vertical power MOSFET is formed as a vertical semiconductor element. The vertical power MOSFET is formed by performing a well-known device manufacturing process on a semiconductor substrate. After the vertical power MOSFET is formed on the semiconductor substrate, it is diced and divided into chips. Thus, the semiconductor device shown in FIGS. 1 and 2 is configured.

  Specifically, in the cell region 2, at least a first electrode 4 provided on the main surface 1 a side and a second electrode 5 provided on the back surface 1 b side are formed. It is formed not only in the entire cell region 2 but also in the outer peripheral region 3, and is formed in the entire back surface 1b. Although not shown, the vertical power MOSFET includes a source region and a source electrode on the main surface 1a side of the semiconductor substrate 1 and a drain region on the back surface 1b side. The first electrode 4 is a source electrode connected to the source region, and the second electrode 5 is a drain electrode connected to the drain region. The first electrode 4 is composed of a laminate of a plurality of types of metal layers. In this embodiment, the first layer 4a made of an Al (aluminum) layer, the second layer 4b made of a Ni (nickel) layer, and Au ( And a third layer 4c made of a metal containing Au such as gold) plating. The second electrode 5 is also composed of a laminate of a plurality of types of metal layers. In the present embodiment, a first layer 5a made of a Ti layer, a second layer 5b made of a Ni layer, and a third layer made of a metal containing Au. The layer 5c is included.

  The metal material constituting the first and second electrodes 4 and 5 may be any metal material applicable as an electrode material, but in the case of a vertical power MOSFET, the source region and the drain An ohmic contact material with the region is selected. When the vertical semiconductor element is a diode, either a PN diode or a Schottky diode can be used. However, in the case of a Schottky diode, a Schottky contact material is used as the metal material constituting the first electrode 4. Will choose. The second layer 4b is provided for forming the third layer 4c, and the third layer 4c is provided in consideration of bonding with bonding wires and terminals and prevention of surface corrosion (oxidation alteration). ing. Since the third layer 4c is made of a noble material (higher material) than the first and second layers 4a and 4b so that the corrosion of the first and second layers 4a and 4b can be prevented, As described above, a metal containing Au such as Au plating is used.

  The outer peripheral region 3 is a region provided with an outer peripheral withstand voltage structure or the like. For example, the outer peripheral region 3 is configured to include a RESURF layer, a guard ring layer, or the like formed so as to surround the cell region 2 in the surface layer portion of the semiconductor substrate. . Various pads 6 to 8 are formed in the outer peripheral region 3, and an identification marking 9 is also provided.

  The various pads 6 to 8 are the gate pad 6, the sense pad 7, and other pads 8. The gate pad 6 is a pad connected to the gate electrode of the vertical power MOSFET. The gate electrode of the vertical power MOSFET is routed from the cell region 2 to the outer peripheral region 3 side, and the gate pad 6 is connected to the gate electrode in the outer peripheral region 3. The sense pad 7 is a pad for sensing the drain current flowing through the vertical power MOSFET. The vertical power MOSFET is divided into a main cell and a sense cell, and a sense current obtained by reducing a drain current flowing in the main cell at a predetermined ratio is supplied to the sense cell. By extracting this sense current through the sense pad 7, the drain current flowing in the main cell of the vertical power MOSFET can be detected. Other pads 8 include a temperature sensor pad for detecting an excessive temperature rise of the semiconductor device. In addition to the pads 6-8, a metal mark used for alignment can also be provided.

  The identification marking 9 is formed at a position away from the first electrode 4 and the various pads 6 to 8 in the outer peripheral region 3. For this reason, the influence by forming the identification marking 9 on the vertical semiconductor element or the like is more reliably prevented. In the case of the present embodiment, a plurality of markings are configured to extend in a direction perpendicular to one side of the cell region 2 (or the first electrode 4) configured in a rectangle.

  The identification marking 9 can be recognized at least through an optical microscope or the like, and records device characteristics including a vertical power MOSFET or a manufacturing number of a semiconductor device. Based on the identification marking 9, quality data management of the semiconductor device can be performed. For example, the identification marking 9 is constituted by a barcode as shown in the figure.

  Specifically, the identification marking 9 is configured by a metal pattern formed on the main surface 1a side of the semiconductor substrate 1 as shown in FIG. The metal pattern can be recognized through an optical microscope or the like because it appears as any one of unevenness, shading, gloss and color on the surface of the semiconductor device. That is, since it has a convex shape compared to where there is no metal pattern, the unevenness is configured based on the level difference from the surroundings, and the lightness or darkness is based on the difference in gloss or color from the unevenness or the surroundings. Or appear as a difference in luster or color from the surroundings. For this reason, the identification marking 9 can be identified by visually recognizing unevenness, shading, gloss, color, etc. through an optical microscope or the like.

  The identification marking 9 is formed by using an electrode material constituting the first electrode 4 provided in the vertical power MOSFET, and is formed at the same time when the first electrode 4 is patterned. For example, after forming an interlayer insulating film on the main surface 1a side of the semiconductor substrate 1 on which the vertical power MOSFET has been formed or forming a contact hole with respect to the interlayer insulating film, various types constituting the first electrode 4 The formation process of the metal layers 4a-4c is performed. And when the various electrodes 4a-4c are patterned and the 1st electrode 4 is formed, the identification marking 9 is formed simultaneously. By doing in this way, it becomes possible to share the identification marking 9 with the formation process of the 1st electrode 4, and it becomes possible to aim at simplification of a manufacturing process.

  In addition, although demonstrated here as a process of forming the 1st electrode 4 and the identification marking 9, it can also form simultaneously with the 1st electrode 4 etc. also about the pads 6-8. In this way, the identification marking 9 is constituted by a laminate of metal layers having the same structure as the first to third layers 4 a to 4 c constituting the first electrode 4. For this reason, the outermost surface of the identification marking 9 is made of the same material as the outermost surface of the first electrode 4, and the identification marking 9 can be simultaneously checked when the appearance inspection of the first electrode 4 is performed.

  Moreover, in the case of such a manufacturing process, the identification marking 9 is comprised by the laminated body of the metal layer which has the same structure as the 1st-3rd layers 4a-4c which comprise the 1st electrode 4. However, the identification marking 9 may be configured by only one or two of them. In that case, for example, after patterning the first layer 4a to remove the metal layer constituting the first layer 4a from the formation region of the identification marking 9, the second and third layers 4b and 4c are formed. The first to third layers 4a to 4c constituting the first electrode 4 are separately patterned. However, at least a part of the processes can be made common, such as patterning the identification marking 9 at the same time when patterning the second and third layers 4b and 4c.

  Further, as shown in FIG. 2, the outer edge of the first electrode 4 and the outer edge of the identification marking 9 are surrounded, and the region located inside the outer edge of the first electrode 4 and the identification marking 9 is exposed. In addition, a protective film 10 is formed. The protective film 10 is formed of a protective material such as polyimide resin, for example, and protects it by covering the surface of the semiconductor substrate 1 and the like. In the case of the present embodiment, the first electrode 4 and the identification marking 9 are configured by the same structure, and therefore, the surface of the first electrode 4 and the height of the identification marking 9 from the main surface 1a are the same. It has become. Therefore, when the wire bonding or terminal connection is performed on the first electrode 4 in order to connect the semiconductor device to an external circuit, the identification marking 9 can be prevented from getting in the way.

  The semiconductor device according to the present embodiment is configured by the structure as described above. The semiconductor device configured as described above includes an identification marking 9 made of metal on the main surface 1a side of the semiconductor substrate 1, that is, on the same surface as the surface on which the first electrode 4 serving as the surface electrode is formed. For this reason, the identification marking 9 can be easily identified without having to have a structure covered with the sealing resin as in the prior art and without taking a transmission image of the semiconductor substrate 1.

  Further, since the identification marking 9 is constituted by a metal layer having the same structure as the first electrode 4 of the vertical semiconductor element or a part of the same structure, the process of forming the first electrode 4 and the identification marking 9 is made common. Therefore, the manufacturing process can be simplified. In particular, if the outermost surface of the first electrode 4 (the third layer 4c) and the outermost surface of the identification marking 9 are made of the same material, the identification marking 9 is also checked simultaneously when the appearance inspection of the first electrode 4 is performed. It becomes possible to do. For this reason, it is possible to perform a visual inspection in common.

  Further, since the height of the surface of the first electrode 4 can be equal to or higher than the height of the identification marking 9, wire bonding or a terminal is connected to the first electrode 4 in order to connect the semiconductor device to an external circuit. It is possible to prevent the identification marking 9 from interfering with the connection.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the configuration of the first electrode 4 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

  As shown in FIG. 3, in the present embodiment, the first electrode 4 is made higher than the identification marking 9. Specifically, the first electrode 4 is provided with a fourth layer 4 d and the number of stacked layers is larger than that of the identification marking 9 so that the height of the first electrode 4 is higher than that of the identification marking 9. Yes. For example, as shown in FIG. 3, the fourth layer 4 d is disposed between the first layer 4 a and the semiconductor substrate 1. Examples of the fourth layer 4d include a barrier layer made of Ti (titanium), Mo (molybdenum), or the like.

  As described above, the number of stacked layers constituting the fourth layer 4d may be increased as compared with the first embodiment. In this case, the number of stacked identification markings 9 may be further reduced. In this way, by making the first electrode 4 higher than the identification marking 9, the identification marking 9 becomes more obstructive when performing wire bonding or terminal connection to the first electrode 4 in order to connect the semiconductor device to an external circuit. Can be avoided.

(Third embodiment)
A third embodiment of the present invention will be described. The present embodiment is obtained by changing the configuration of the identification marking 9 and the protective film 10 with respect to the first embodiment, and is otherwise the same as the first embodiment. Therefore, only the portions different from the first embodiment are described. explain.

  As shown in FIG. 4, in this embodiment, the surface of the identification marking 9 is covered with the protective film 10, and the protective film 10 is made of a visible light transmissive material. Thus, if the identification marking 9 is covered with the protective film 10, the entire surface of the identification marking 9 can be protected by the protective film 10, so that the marking surface can be prevented from deteriorating. Further, since the marking surface is not exposed, it is possible to prevent erroneous connection to the identification marking 9 when performing wire bonding or terminal connection.

  In such a case, it is necessary to identify the identification marking 9 through the protective film 10. However, unlike the semiconductor material, the material of the protective film 10 can be appropriately selected. Therefore, the protective film 10 is formed of a visible light transmissive material without using a conventional method of transmission photography. Only by this, the identification mark 9 can be easily identified.

(Other embodiments)
In the first embodiment, the vertical power MOSFET is described as an example of the vertical semiconductor element. However, as described above, a semiconductor device provided with another element, for example, a vertical IGBT or a vertical diode, as the vertical semiconductor element. The present invention can also be applied to. In this case, for example, in the case of a vertical IGBT, the first electrode is an emitter electrode and the second electrode is a collector electrode, and in the case of a vertical diode, the first electrode is an anode electrode and the second electrode is a cathode electrode. The second electrode is an electrode connected to each element.

  Moreover, although the said 3rd Embodiment demonstrated the case where the structure where the identification marking 9 was covered with the protective film 10 with respect to 1st Embodiment was applied, as shown in FIG. The present invention can also be applied to a structure in which the number of stacked first electrodes 4 is increased as in the embodiment. In the case of such a structure, the height of the portion provided on the outer edge portion of the first electrode 4 in the protective film 10 is higher than the height of the portion provided on the surface of the identification marking 9. For this reason, when wire bonding or terminal connection is performed on the first electrode 4 in order to connect the semiconductor device to an external circuit, the identification marking 9 and the protective film 10 covering it can be prevented from getting in the way.

  Further, the identification marking 9 may be formed in any part on the main surface 1a side, and may be formed in the first electrode 4, for example.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Main surface 1b Back surface 2 Cell area | region 3 Outer periphery area | region 4 1st electrode 5 2nd electrode 6-8 Various pads 9 Identification marking 10 Protective film

Claims (3)

A cell region (2) formed using a semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface, in which a semiconductor element is formed, and the cell region And an outer peripheral region (3) formed on the outer periphery surrounding
On the main surface side, a first electrode (4) that constitutes a surface electrode connected to the semiconductor element is formed in the cell region, and any part on the main surface side is made of metal. An identification marking (9) is provided ,
The semiconductor device according to claim 1, wherein a height of the first electrode from the main surface is higher than a height of the identification marking from the main surface . The outer edge of the first electrode and at least the outer edge of the identification marking are covered with a protective film (10);
Of the protective film, the height from the main surface of the portion covering the outer edge of the first electrode is higher than the height from the main surface of the portion covering the outer edge of the identification marking. The semiconductor device according to claim 1. Metal layer located on the outermost surface of the first electrode and the identification marking, characterized in that the oxidation-reduction potential than the metal layer disposed beneath the metal layer (4c) is a material of the noble The semiconductor device according to claim 1 .

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