JP5265932B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5265932B2
JP5265932B2 JP2008012626A JP2008012626A JP5265932B2 JP 5265932 B2 JP5265932 B2 JP 5265932B2 JP 2008012626 A JP2008012626 A JP 2008012626A JP 2008012626 A JP2008012626 A JP 2008012626A JP 5265932 B2 JP5265932 B2 JP 5265932B2
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layer
conductivity type
bonding pad
concentration impurity
contact
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JP2009176869A (en
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伸二郎 加藤
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable protective diode strong against an impact upon bonding in a static electricity protective diode provided on the lower part of a bonding pad. <P>SOLUTION: A diode element for which an embedded layer 2 at the lower part of the bonding pad is a cathode and a low concentration impurity region 4 formed in a semiconductor substrate and a semiconductor epitaxial layer 3 and having the same conductivity type as the semiconductor substrate 1 is an anode is configured as the semiconductor device 100, and the contact of a high concentration impurity layer 6 and a wiring layer 8 is provided away from the contact of a bonding pad electrode layer 10 and the wiring layer 8. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、静電気から内部回路を保護する入力保護素子、出力保護素子、入出力保護素子を有する半導体装置に関する。   The present invention relates to a semiconductor device having an input protection element, an output protection element, and an input / output protection element for protecting an internal circuit from static electricity.

半導体装置は、静電気から内部回路を保護するために入力端子と接地端子、出力端子と接地端子の間に保護素子を挿入するが、より大きなサージに耐えうる保護素子をつくろうとすれば、より大きな面積が必要となり、チップ全体の面積が大きくなってしまう。これまで、チップ面積を大きくせずに、ボンディングの際の機械的な影響が抑えられた保護素子を作製する方法として、ボンディングパッドとボンディングパッド下部の保護素子がつくられた基板表面との間に配線層を置き、前記配線層とボンディングパッド、前記配線層と基板表面の保護素子をそれぞれ複数のコンタクトで接続する方法などが考えられた。（例えば、特許文献１参照）
特開２０００−１３３７７５号公報 In semiconductor devices, protective elements are inserted between the input terminal and the ground terminal and between the output terminal and the ground terminal to protect the internal circuit from static electricity. However, if a protective element that can withstand a greater surge is created, the semiconductor device is larger. An area is required, and the area of the entire chip becomes large. Up to now, as a method of manufacturing a protective element in which the mechanical influence during bonding is suppressed without increasing the chip area, between the bonding pad and the substrate surface on which the protective element under the bonding pad is formed. A method of placing a wiring layer and connecting the wiring layer and a bonding pad, and connecting the wiring layer and a protective element on the substrate surface with a plurality of contacts, etc., has been considered. (For example, see Patent Document 1)
JP 2000-133775 A

上述の方法では、保護素子とボンディングパッドの間に配線層及び層間絶縁膜を設けているとはいえ、保護素子をボンディングパッド下部の基板表面につくることになるので、ボンディングの際にボンダーからの圧力などの影響がボンディングパッド下部の保護素子に反映されることがありうる。また、ボンディングパッドと基板表面の保護素子の間に配線が無い場合には、上述の方法をとることが出来ない。本発明は、それらを解決し、より信頼性の高い半導体保護素子をボンディングパッド下部に設けることを目的としている。   In the above method, although the wiring layer and the interlayer insulating film are provided between the protective element and the bonding pad, the protective element is formed on the substrate surface below the bonding pad. An effect such as pressure may be reflected on the protective element below the bonding pad. In addition, when there is no wiring between the bonding pad and the protective element on the substrate surface, the above method cannot be taken. An object of the present invention is to solve these problems and to provide a semiconductor protection element with higher reliability under the bonding pad.

本発明では、ボンディングパッド下部に埋め込み層を設けて保護ダイオードのカソードとし、前記埋め込み層と配線との接続をボンディングパッド以外のところで行うことを特徴としている。   The present invention is characterized in that a buried layer is provided under the bonding pad to serve as a cathode of the protective diode, and the buried layer and the wiring are connected at a place other than the bonding pad.

埋め込み層を用いることにより、基板表面からより深いところにpn接合面を持つ保護ダイオードをつくることができ、また前記保護ダイオードと配線との接続がボンディングパッド下部に無いため、ボンディングの際の機械的な影響が前記保護ダイオードに伝わり難く、より信頼性の高い保護ダイオードをボンディングパッド下につくることが可能である。   By using the buried layer, a protection diode with a pn junction can be made deeper from the substrate surface, and there is no connection between the protection diode and the wiring at the bottom of the bonding pad. Therefore, it is difficult to transmit the influence to the protection diode, and it is possible to form a more reliable protection diode under the bonding pad.

以下、本発明を実施するための最良の形態について、図面に基づいて説明する。   The best mode for carrying out the present invention will be described below with reference to the drawings.

図１は、本発明の第１の実施形態に係る半導体装置の断面図である。半導体装置１００は、第１導電型の半導体基板１の上に第１導電型の半導体エピタキシャル層３を成長させ、その界面を中心として上下に第２導電型の埋め込み層２を配置してある。埋め込み層２の上に接するように第１導電型低濃度不純物領域４を設ける。第１導電型低濃度不純物領域４に隣接して第２導電型低濃度不純物領域５を配し、第２導電型低濃度不純物領域５の表面近傍には、第２導電型高濃度不純物領域６を設けている。半導体エピタキシャル層３上の第１導電型低濃度不純物層４の上には絶縁膜７が形成されており、絶縁膜７と第２導電型高濃度不純物領域を覆うように一般的には金属からなる配線層８が形成され、配線層８と第２導電型不純物領域６とはコンタクトを介して低抵抗となるように接触している。配線層８の上には層間絶縁膜９が形成されており、層間絶縁膜９の一部に開けられた開口部を介してボンディングパッド電極層１０が形成され、ボンディングパッド電極層１０の上には絶縁保護膜１１が被着され、部分的に開口されている。平面視的には、最表層の絶縁保護膜１１に設けられた開口部は第２導電型埋め込み層２の上に形成された第１導電型低濃度不純物領域４内に形成され、第２導電型低濃度不純物領域５は絶縁保護膜１１によって覆われた領域の下部に位置する構成である。   FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. In the semiconductor device 100, a first conductivity type semiconductor epitaxial layer 3 is grown on a first conductivity type semiconductor substrate 1, and a second conductivity type buried layer 2 is arranged vertically above and below the interface. A first conductivity type low concentration impurity region 4 is provided so as to be in contact with the buried layer 2. A second conductivity type low concentration impurity region 5 is disposed adjacent to the first conductivity type low concentration impurity region 4, and the second conductivity type high concentration impurity region 6 is located near the surface of the second conductivity type low concentration impurity region 5. Is provided. An insulating film 7 is formed on the first conductivity type low-concentration impurity layer 4 on the semiconductor epitaxial layer 3 and is generally made of metal so as to cover the insulating film 7 and the second conductivity type high-concentration impurity region. A wiring layer 8 is formed, and the wiring layer 8 and the second conductivity type impurity region 6 are in contact with each other through a contact so as to have a low resistance. An interlayer insulating film 9 is formed on the wiring layer 8, and a bonding pad electrode layer 10 is formed through an opening opened in a part of the interlayer insulating film 9, and on the bonding pad electrode layer 10. Is covered with an insulating protective film 11 and partially opened. In plan view, the opening provided in the outermost insulating protective film 11 is formed in the first conductivity type low-concentration impurity region 4 formed on the second conductivity type buried layer 2, and the second conductivity The type low-concentration impurity region 5 is configured to be located below the region covered with the insulating protective film 11.

半導体装置１００は、第２導電型埋め込み層２をカソード、第１導電型低濃度不純物領域４と第１導電型半導体基板１をアノードとする保護ダイオード素子を成している。高濃度不純物層６と配線層８とのコンタクトは、ボンディングの際に加わる圧力の影響が保護ダイオード素子に伝わらないように、配線層８とボンディングパッド電極層１０のコンタクトから３０μｍ〜４０μｍ離して設けられる。   The semiconductor device 100 forms a protective diode element having the second conductivity type buried layer 2 as a cathode, the first conductivity type low-concentration impurity region 4 and the first conductivity type semiconductor substrate 1 as an anode. The contact between the high-concentration impurity layer 6 and the wiring layer 8 is provided 30 μm to 40 μm away from the contact between the wiring layer 8 and the bonding pad electrode layer 10 so that the influence of the pressure applied during bonding is not transmitted to the protective diode element. It is done.

図１では、第２低濃度不純物領域５および第２導電型高濃度不純物層６と配線層８とのコンタクトはボンディングパッドの４辺のうち向き合う２辺に設けるように図示されているが、１辺から４辺までどのように設けても構わない。第２導電型埋め込み層２と第１導電型低濃度不純物領域４及び第２導電型高濃度不純物領域６と第１導電型半導体エピタキシャル層３の不純物濃度は、保護素子の降伏耐圧が内部回路を構成する素子の降伏電圧よりも５Ｖ〜１０Ｖ低くなるように設定される。ボンディングパッド電極層１０は、機械的にボンディングされない外部電極用のパッド電極層であってもよい。   In FIG. 1, the contact between the second low-concentration impurity region 5 and the second conductivity type high-concentration impurity layer 6 and the wiring layer 8 is shown to be provided on two opposite sides of the four sides of the bonding pad. Any number of sides to four sides may be provided. The impurity concentration of the second conductivity type buried layer 2, the first conductivity type low concentration impurity region 4, the second conductivity type high concentration impurity region 6, and the first conductivity type semiconductor epitaxial layer 3 depends on the breakdown voltage of the protection element. It is set to be 5 V to 10 V lower than the breakdown voltage of the constituent elements. The bonding pad electrode layer 10 may be a pad electrode layer for an external electrode that is not mechanically bonded.

図２は、本発明の第２の実施形態に係る半導体装置の断面図である。   FIG. 2 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention.

第２の実施形態は、配線層が一層の場合である。半導体装置１０１は、第１導電型の半導体基板１の上に第１導電型の半導体エピタキシャル層３を成長させ、その界面に第２導電型の埋め込み層２を配置してある。埋め込み層２の上に接するように第１導電型低濃度不純物領域４を設ける。第１導電型低濃度不純物領域４に隣接して第２導電型低濃度不純物領域５を配し、第２導電型低濃度不純物領域５の表面近傍には、第２導電型高濃度不純物領域６を設けている。半導体エピタキシャル層３上の第１導電型低濃度不純物層４の上には絶縁膜７が形成されており、絶縁膜７と第２導電型高濃度不純物領域６を覆うように一般的には金属からなるボンディングパッド電極層１０が形成され、ボンディングパッド電極層１０と第２導電型不純物領域６とは電気的に接触している。ボンディングパッド電極層１０の上には絶縁保護膜１１が形成されており、絶縁保護膜１１一部には開口部が形成されている。平面視的には、最表層の絶縁保護膜１１に設けられた開口部は第２導電型埋め込み層２の上に形成された第１導電型低濃度不純物領域４内に形成され、第２導電型低濃度不純物領域５は絶縁保護膜１１によって覆われた構成である。   In the second embodiment, the wiring layer is a single layer. In the semiconductor device 101, a first conductivity type semiconductor epitaxial layer 3 is grown on a first conductivity type semiconductor substrate 1, and a second conductivity type buried layer 2 is disposed at an interface thereof. A first conductivity type low concentration impurity region 4 is provided so as to be in contact with the buried layer 2. A second conductivity type low concentration impurity region 5 is disposed adjacent to the first conductivity type low concentration impurity region 4, and the second conductivity type high concentration impurity region 6 is located near the surface of the second conductivity type low concentration impurity region 5. Is provided. An insulating film 7 is formed on the first conductivity type low-concentration impurity layer 4 on the semiconductor epitaxial layer 3 and is generally made of metal so as to cover the insulating film 7 and the second conductivity type high-concentration impurity region 6. The bonding pad electrode layer 10 is formed, and the bonding pad electrode layer 10 and the second conductivity type impurity region 6 are in electrical contact. An insulating protective film 11 is formed on the bonding pad electrode layer 10, and an opening is formed in a part of the insulating protective film 11. In plan view, the opening provided in the outermost insulating protective film 11 is formed in the first conductivity type low-concentration impurity region 4 formed on the second conductivity type buried layer 2, and the second conductivity The type low concentration impurity region 5 is covered with an insulating protective film 11.

半導体装置１０１は、第２導電型埋め込み層２をカソード、第１導電型低濃度不純物層４と第１導電型半導体基板１をアノードとするダイオード素子を成している。第２導電型埋め込み層２は、第２導電型低濃度不純物領域５に接続され、第２導電型高濃度不純物層６を介してボンディングパッド電極層１０と電気的に接続され、第２導電型高濃度不純物層６とボンディングパッド電極層１０のコンタクトは、ボンディングの際に加わる圧力の影響が前記ダイオード素子に伝わらないように、絶縁保護膜１１の開孔部より３０um〜４０um内側に設けられる。   The semiconductor device 101 forms a diode element having the second conductivity type buried layer 2 as a cathode, the first conductivity type low-concentration impurity layer 4 and the first conductivity type semiconductor substrate 1 as an anode. The second conductivity type buried layer 2 is connected to the second conductivity type low concentration impurity region 5 and electrically connected to the bonding pad electrode layer 10 via the second conductivity type high concentration impurity layer 6. The contact between the high-concentration impurity layer 6 and the bonding pad electrode layer 10 is provided 30 μm to 40 μm inside the opening portion of the insulating protective film 11 so that the influence of pressure applied during bonding is not transmitted to the diode element.

図２では、第２導電型高濃度不純物層６とボンディングパッド電極層１０のコンタクト及び第２導電型低濃度不純物領域５はボンディングパッドの４辺のうち向き合う２辺に設けられているが、１辺から４辺までどのように設けても構わない。第２導電型埋め込み層２と第１導電型低濃度不純物領域４及び第２導電型高濃度不純物領域６と第１導電型半導体エピタキシャル層３の不純物濃度は、前記ダイオード素子の降伏耐圧が内部回路を構成する素子の降伏電圧よりも５Ｖ〜１０Ｖ低くなるように設定される。前記ボンディングパッド電極層１０は、機械的にボンディングされない外部電極用のパッド電極層であってもよい。   In FIG. 2, the contact between the second conductivity type high concentration impurity layer 6 and the bonding pad electrode layer 10 and the second conductivity type low concentration impurity region 5 are provided on two opposite sides of the four sides of the bonding pad. Any number of sides to four sides may be provided. The impurity concentration of the second conductive type buried layer 2, the first conductive type low concentration impurity region 4, the second conductive type high concentration impurity region 6, and the first conductive type semiconductor epitaxial layer 3 depends on the breakdown voltage of the diode element. Is set so as to be 5 V to 10 V lower than the breakdown voltage of the elements constituting the. The bonding pad electrode layer 10 may be a pad electrode layer for an external electrode that is not mechanically bonded.

上述したよう、埋め込み層を用いることにより、基板表面からより深いところにpn接合面を持つ保護ダイオードをつくることができ、また前記保護ダイオードと配線との接続がボンディングパッド下部に無いため、ボンディングの際の機械的な影響が前記保護ダイオードに伝わり難く、より信頼性の高い保護ダイオードをボンディングパッド下につくることができる。   As described above, by using the buried layer, a protection diode having a pn junction surface deeper from the substrate surface can be formed, and since there is no connection between the protection diode and the wiring under the bonding pad, It is difficult for a mechanical influence to be transmitted to the protection diode, and a more reliable protection diode can be formed under the bonding pad.

本発明の第１の実施形態に係る半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第２の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１ 第１導電型半導体基板
２ 第２導電型埋め込み層
３ 第１導電型半導体エピタキシャル層
４ 第１導電型低濃度不純物領域
５ 第２導電型低濃度不純物領域
６ 高濃度不純物領域
７ 絶縁膜
８ 配線層
９ 層間絶縁膜
１０ ボンディングパッド電極層
１１ 絶縁保護膜
１００ 半導体装置
１０１ 半導体装置 DESCRIPTION OF SYMBOLS 1 1st conductivity type semiconductor substrate 2 2nd conductivity type buried layer 3 1st conductivity type semiconductor epitaxial layer 4 1st conductivity type low concentration impurity region 5 2nd conductivity type low concentration impurity region 6 High concentration impurity region 7 Insulating film 8 Wiring Layer 9 Interlayer insulating film 10 Bonding pad electrode layer 11 Insulating protective film 100 Semiconductor device 101 Semiconductor device

Claims (2)

第１導電型の半導体基板と、
前記半導体基板の上に配置された第１導電型の半導体エピタキシャル層と、
前記半導体基板と前記半導体エピタキシャル層との界面にその上下に係り配置された第２導電型の埋め込み層と、
前記埋め込み層の上に接して配置された前記埋め込み層よりも小さい第１導電型の不純物層と、
前記不純物層に隣接するとともに前記埋め込み層にも接して配置された第２導電型の低濃度不純物領域と、
前記低濃度不純物領域の表面近傍に配置された第２導電型の高濃度不純物領域と、
前記不純物層の上に配置された絶縁膜の上に配置されるとともに前記高濃度不純物領域とは第１のコンタクトにおいて直接に接触している配線層と、
前記配線層の上に配置された層間絶縁膜を介して配置された、表面が絶縁保護膜で覆われ、前記絶縁保護膜の開口部はボンディングパッドを構成している、前記配線層とは前記ボンディングパッドの下部に設けられた第２のコンタクトにおいて接触しているボンディングパッド電極層と、を有し、
前記ボンディングパッドと前記第１のコンタクトとは上下方向から見た場合に重なりを有していない半導体装置。 A first conductivity type semiconductor substrate;
A semiconductor epitaxial layer of a first conductivity type disposed on the semiconductor substrate;
A second conductivity type buried layer disposed above and below the interface between the semiconductor substrate and the semiconductor epitaxial layer;
An impurity layer of a first conductivity type smaller than the buried layer disposed on and in contact with the buried layer;
A low-concentration impurity region of a second conductivity type disposed adjacent to the impurity layer and in contact with the buried layer;
A second conductivity type high concentration impurity region disposed in the vicinity of the surface of the low concentration impurity region;
A wiring layer disposed on an insulating film disposed on the impurity layer and in direct contact with the high-concentration impurity region in a first contact;
The surface is covered with an insulating protective film disposed via an interlayer insulating film disposed on the wiring layer, and the opening of the insulating protective film constitutes a bonding pad. A bonding pad electrode layer in contact with a second contact provided at a lower portion of the bonding pad,
The semiconductor device in which the bonding pad and the first contact do not overlap when viewed from above and below. 第１導電型の半導体基板と、
前記半導体基板の上に配置された第１導電型の半導体エピタキシャル層と、
前記半導体基板と前記半導体エピタキシャル層との界面にその上下に係り配置された第２導電型の埋め込み層と、
前記埋め込み層の上に接して配置された前記埋め込み層よりも小さい第１導電型の不純物層と、
前記不純物層に隣接するとともに前記埋め込み層にも接して配置された第２導電型の低濃度不純物領域と、
前記低濃度不純物領域の表面近傍に配置された第２導電型の高濃度不純物領域と、
前記不純物層の上に配置された絶縁膜の上に配置されるとともに前記高濃度不純物領域とはコンタクトにおいて直接に接触しているとともに表面が絶縁保護膜で覆われ、前記絶縁保護膜の開口部はボンディングパッドを構成している、ボンディングパッド配線層と、を有し、
前記ボンディングパッドと前記コンタクトとは上下方向から見た場合に重なりを有していない半導体装置。 A first conductivity type semiconductor substrate;
A semiconductor epitaxial layer of a first conductivity type disposed on the semiconductor substrate;
A second conductivity type buried layer disposed above and below the interface between the semiconductor substrate and the semiconductor epitaxial layer;
An impurity layer of a first conductivity type smaller than the buried layer disposed on and in contact with the buried layer;
A low-concentration impurity region of a second conductivity type disposed adjacent to the impurity layer and in contact with the buried layer;
A second conductivity type high concentration impurity region disposed in the vicinity of the surface of the low concentration impurity region;
An insulating film disposed on the impurity layer and in direct contact with the high-concentration impurity region and having a surface covered with an insulating protective film, the opening of the insulating protective film Comprises a bonding pad wiring layer constituting a bonding pad,
A semiconductor device in which the bonding pad and the contact do not overlap when viewed from above and below.
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