JP5102011B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP5102011B2
JP5102011B2 JP2007327297A JP2007327297A JP5102011B2 JP 5102011 B2 JP5102011 B2 JP 5102011B2 JP 2007327297 A JP2007327297 A JP 2007327297A JP 2007327297 A JP2007327297 A JP 2007327297A JP 5102011 B2 JP5102011 B2 JP 5102011B2
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internal circuit
electrode pad
semiconductor device
terminal
back electrode
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JP2007327297A
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JP2009152294A (en
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伸二郎 加藤
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Seiko Instruments Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

本発明は、入出力保護ダイオードを備えた半導体装置に関する。   The present invention relates to a semiconductor device including an input / output protection diode.

端子から入るサージから内部回路を保護するために入力端子と接地端子、出力端子と接地端子の間に保護ダイオードを備えた半導体装置において、より大きなサージに耐えうる半導体装置をつくろうとすれば、より大きな接合面積を持つ保護ダイオードが必要となり、チップ面積も大きくなってしまう。これまでチップ面積を大きくせずに保護ダイオードを作製する方法として、周囲を絶縁膜で囲まれた素子を用いてウエーハ表面に内部回路を構成し、ウエーハ表面がカソード、裏面がアノードとなるように、ウエーハ内部に保護ダイオードを設ける方法などが考えられた。（例えば、特許文献１参照）
特開平７−２９９７４号公報 If a semiconductor device with a protective diode between the input terminal and the ground terminal and the output terminal and the ground terminal to protect the internal circuit from the surge that enters from the terminal is intended to make a semiconductor device that can withstand a greater surge, A protection diode having a large junction area is required, and the chip area is also increased. As a method of manufacturing a protection diode without increasing the chip area, an internal circuit is formed on the wafer surface using an element surrounded by an insulating film so that the wafer surface becomes a cathode and the back surface becomes an anode. A method of providing a protective diode inside the wafer has been considered. (For example, see Patent Document 1)
Japanese Patent Laid-Open No. 7-29974

上記のような方法を用いる場合、表面の内部回路を構成する素子と基板とを絶縁させるために、ウエーハを張り合わせるなど前工程として複雑な工程が必要となる。本発明の目的は、より簡便に、チップ面積を大きくすることなく接合面積の大きな保護ダイオードを得ることにある。   When the above method is used, in order to insulate the element constituting the internal circuit on the surface from the substrate, a complicated process such as a wafer bonding is required. An object of the present invention is to obtain a protection diode having a large junction area more easily without increasing the chip area.

ウエーハと導電型が逆になるような不純物領域を裏面に複数作製し、ウエーハ表面に作られる内部回路の接地電極が保護ダイオードのアノード、裏面電極が前記保護ダイオードのカソードとなるように、チップをパッケージする際に前記内部回路の入力端子と出力端子をそれぞれ前記裏面電極に結線する。   A plurality of impurity regions are formed on the back surface so that the conductivity type is opposite to that of the wafer, and the chip is formed so that the ground electrode of the internal circuit formed on the wafer surface is the anode of the protection diode and the back electrode is the cathode of the protection diode. When packaging, the input terminal and output terminal of the internal circuit are respectively connected to the back electrode.

チップ表面から保護ダイオード分の面積が縮小でき、且つチップ面積を大きくせずに接合面積の大きな保護ダイオードを作製することができる。よって、小さな面積で大きなサージに耐える半導体装置をつくることができる。   The area of the protective diode can be reduced from the chip surface, and a protective diode having a large junction area can be manufactured without increasing the chip area. Therefore, a semiconductor device that can withstand a large surge in a small area can be manufactured.

以下、本発明を実施するための最良の形態について、図面に基づいて説明する。   The best mode for carrying out the present invention will be described below with reference to the drawings.

図１は、本発明の実施形態に係る半導体装置１００の断面図である。半導体装置１００は、第１導電型の半導体基板９の表面に作りこまれた内部回路を構成する素子領域１０と絶縁保護膜６と入力端子を構成するボンディングパッド１と接地端子および保護ダイオードのアノードを構成するボンディングパッド２と出力端子を構成するボンディングパッド３と第１導電型の高濃度不純物領域７と第２導電型の低濃度不純物領域８と第２導電型の高濃度不純物領域１２、入力端子用の保護ダイオードのカソードを構成する裏面電極４と出力端子用の保護ダイオードのカソードを形成する裏面電極５で構成されている。   FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes an element region 10 that forms an internal circuit formed on the surface of a semiconductor substrate 9 of a first conductivity type, an insulating protective film 6, a bonding pad 1 that forms an input terminal, a ground terminal, and an anode of a protective diode. Bonding pad 2 constituting the output terminal, bonding pad 3 constituting the output terminal, high-concentration impurity region 7 of the first conductivity type, low-concentration impurity region 8 of the second conductivity type, high-concentration impurity region 12 of the second conductivity type, input The back electrode 4 constitutes the cathode of the protective diode for the terminal and the back electrode 5 forms the cathode of the protective diode for the output terminal.

第１導電型半導体基板９と第２導電型の低濃度不純物領域８の界面は、保護ダイオードのｐｎ接合を成しており、第１導電型半導体基板９の不純物濃度と第２導電型の低濃度不純物領域８の不純物濃度は、上記保護ダイオードの降伏電圧が、内部回路の降伏電圧よりも５Ｖ〜１０Ｖ低くなるように選ばれる。また、基板と異なる導電型の低濃度不純物領域８の間隔１１は、裏面電極４と裏面電極５の間のパンチスルー耐圧が、上記保護ダイオードの降伏電圧よりも５Ｖ〜１０Ｖ高くなるように、間隔を設ける。内部回路を構成している素子は、ｎチャネルＭＯＳＦＥＴ、ｐチャネルＭＯＳＦＥＴ、ダイオード、キャパシター、バイポーラトランジスタ、ＬＤＭＯＳ、抵抗などである。入力端子を構成するボンディングパッド１と入力端子用の保護ダイオードのカソードを構成する裏面電極４、出力端子を構成するボンディングパッド３と出力の保護ダイオードのカソードを形成する裏面電極５をそれぞれ結線することにより、入力端子および出力端子に保護ダイオードを持つ半導体装置を構成することができる。   The interface between the first conductivity type semiconductor substrate 9 and the second conductivity type low-concentration impurity region 8 forms a pn junction of a protection diode, and the impurity concentration of the first conductivity type semiconductor substrate 9 and the second conductivity type low-concentration impurity region 8 are low. The impurity concentration of the concentration impurity region 8 is selected so that the breakdown voltage of the protection diode is 5 V to 10 V lower than the breakdown voltage of the internal circuit. Further, the interval 11 between the low-concentration impurity regions 8 having a conductivity type different from that of the substrate is such that the punch-through breakdown voltage between the back electrode 4 and the back electrode 5 is 5 V to 10 V higher than the breakdown voltage of the protection diode. Is provided. Elements constituting the internal circuit are an n-channel MOSFET, a p-channel MOSFET, a diode, a capacitor, a bipolar transistor, an LDMOS, a resistor, and the like. The bonding pad 1 constituting the input terminal and the back electrode 4 constituting the cathode of the protection diode for the input terminal, and the bonding pad 3 constituting the output terminal and the back electrode 5 forming the cathode of the output protection diode are respectively connected. Thus, a semiconductor device having protective diodes at the input terminal and the output terminal can be configured.

図１の実施例では、半導体装置の端子は入力端子と出力端子の２端子の構成であるが、２端子以上の場合も同様に、接地端子を除く半導体装置の端子の数と同数だけ、ウエーハ裏面に間隔１１だけ隔てて第２導電型の低濃度不純物領域８と裏面電極４、５を設け、ウエーハの表面と裏面の端子を結線すれば、それぞれの端子に保護ダイオードを設けることができる。   In the embodiment of FIG. 1, the terminal of the semiconductor device has a configuration of two terminals, that is, an input terminal and an output terminal. Similarly, when there are two or more terminals, the number of wafers is the same as the number of terminals of the semiconductor device excluding the ground terminal. If the second conductivity type low-concentration impurity region 8 and the back electrodes 4 and 5 are provided on the back surface with an interval 11 therebetween, and the front and back terminals of the wafer are connected, a protection diode can be provided at each terminal.

また、本実施例では、第１導電型がＰ型、第２導電型がＮ型の場合を示したが、すべての導電型を逆にした構成が可能であることは言うまでもない。   In the present embodiment, the first conductivity type is P-type and the second conductivity type is N-type, but it goes without saying that a configuration in which all conductivity types are reversed is possible.

表面電極と裏面電極とを結線するには、例えば、図２に示すようにチップをマウントする際に、ウエーハ表面の入力端子を構成するボンディングパッド１と入力端子を構成するリードフレーム１４、接地端子を構成するボンディングパッド２と接地端子を構成するリードフレーム１５、出力端子を構成するボンディングパッド３と出力端子を構成するリードフレーム１６をそれどれワイヤー１３でボンディングを行い、入力端子用の保護ダイオードのカソードを構成する裏面電極４と入力端子を構成するリードフレーム１４、出力端子用の保護ダイオードのカソードを構成する裏面電極５と出力端子を構成するリードフレーム１６をそれぞれバンプ１７で溶接する方法がある。これ以外にも公知の方法を用いて結線することができるのはいうまでもない。   In order to connect the surface electrode and the back electrode, for example, when the chip is mounted as shown in FIG. 2, the bonding pad 1 constituting the input terminal on the wafer surface, the lead frame 14 constituting the input terminal, and the ground terminal The bonding pad 2 constituting the ground and the lead frame 15 constituting the ground terminal, and the bonding pad 3 constituting the output terminal and the lead frame 16 constituting the output terminal are each bonded by the wire 13, and a protective diode for the input terminal is formed. There is a method in which the back electrode 4 constituting the cathode and the lead frame 14 constituting the input terminal, the back electrode 5 constituting the cathode of the protective diode for the output terminal, and the lead frame 16 constituting the output terminal are welded by bumps 17 respectively. . Needless to say, other known methods can be used for connection.

本発明の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の斜視図である。1 is a perspective view of a semiconductor device according to an embodiment of the present invention.

符号の説明Explanation of symbols

１ ボンディングパッド(内部回路の入力端子)
２ ボンディングパッド(内部回路の接地端子および保護ダイオードのアノード端子)
３ ボンディングパッド(内部回路の出力端子)
４ 裏面電極 (入力保護ダイオードのカソード端子)
５ 裏面電極 (出力保護 ダイオードのカソード端子)
６ 絶縁保護膜
７ 第１導電型高濃度不純物領域
８ 第２導電型低濃度不純物領域
９ 第１導電型半導体基板
１０ 内部素子回路の領域
１１ 第１導電型低濃度不純物領域間の間隔
１２ 第２導電型高濃度不純物領域
１３ ボンディングワイヤー
１４ リードフレーム(入力端子)
１５ リードフレーム(接地端子)
１６ リードフレーム(出力端子)
１７ バンプ
１００ 半導体装置 1 Bonding pad (internal circuit input terminal)
2 Bonding pads (Ground terminal of internal circuit and anode terminal of protective diode)
3 Bonding pads (internal circuit output terminals)
4 Back electrode (cathode terminal of input protection diode)
5 Back electrode (cathode terminal of output protection diode)
6 Insulating protective film 7 First conductivity type high concentration impurity region 8 Second conductivity type low concentration impurity region 9 First conductivity type semiconductor substrate 10 Internal element circuit region 11 Space between first conductivity type low concentration impurity regions 12 2nd Conductive type high concentration impurity region 13 Bonding wire 14 Lead frame (input terminal)
15 Lead frame (grounding terminal)
16 Lead frame (output terminal)
17 Bump 100 Semiconductor device

Claims (2)

端子から入るサージから内部回路を保護する保護ダイオードを有する半導体装置であって、
ウエーハと、
前記ウエーハの表面に配置された、接地電極パッドを含む電極パッドを有する内部回路と、
前記ウエーハの裏面に配置された、前記ウエーハと導電型が逆になるような不純物領域と前記不純物領域とオーミック接触する裏面電極パッドと、
前記裏面電極パッドと前記内部回路の接地電極パッド以外の電極パッドとを対として電気的に結線する配線とからなり、
前記不純物領域と前記裏面電極パッドが間隔を隔て、入力端子、出力端子、入出力端子、テスト端子の数だけ設けられており、前記裏面電極パッドと前記内部回路の接地電極パッド以外の電極パッドとが一対ずつ電気的に結線されていることを特徴とする半導体装置。 A semiconductor device having a protective diode for protecting an internal circuit from a surge entering from a terminal,
With wafers,
An internal circuit having electrode pads, including ground electrode pads, disposed on the surface of the wafer;
An impurity region disposed on the back surface of the wafer and having a conductivity type opposite to that of the wafer; and a back electrode pad in ohmic contact with the impurity region;
Ri Do from the electrically connected to the wiring and the electrode pad other than the ground electrode pads of the internal circuit and the back electrode pads as a pair,
The impurity region and the back electrode pad are spaced apart from each other by the number of input terminals, output terminals, input / output terminals, and test terminals, and the back electrode pad and electrode pads other than the ground electrode pad of the internal circuit are provided. Are electrically connected to each other in pairs . 前記内部回路の電極パッドがワイヤーボンデイングにより接続される電極パッドであり、前記裏面電極がバンプにより接続される電極パッドであることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1 , wherein the electrode pad of the internal circuit is an electrode pad connected by wire bonding, and the back electrode is an electrode pad connected by a bump .
JP2007327297A 2007-12-19 2007-12-19 Semiconductor device Expired - Fee Related JP5102011B2 (en)

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JP5102011B2 true JP5102011B2 (en) 2012-12-19

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