JP5835871B2 - Game machine - Google Patents

Description

The present invention includes a variable winning device that can be controlled in an open state in which a game medium can be won and a closed state in which a game cannot be won, and a gaming machine that gives value to the variable winning device based on the winning of the game medium About.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. If the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Therefore, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means.

  Further, in order to prevent illegally paying out game media as prizes due to fraudulent acts, the payout control means includes the number of winning game media actually detected by each of the winning switches provided for each winning area. There is a gaming machine that compares the number of detections by a safe sensor as a collective winning ball detector that detects all winning game media and determines that an abnormality has occurred in winning detection when they do not match (for example, , See Patent Document 1).

JP 2000-237436 A (paragraphs 0074, 0081)

  As a switch for detecting a game ball, a proximity switch for detecting a change in electric field or magnetic field due to the approach of a metal (for example, a game ball) is often used. Since the proximity switch detects a change in an electric field or a magnetic field, it may malfunction if it receives a strong electromagnetic wave (radio wave). In other words, there is room for fraudulent acts by radio waves. That is, by illegally emitting radio waves, a switch for detecting a game ball is caused to output a detection signal (false detection signal) indicating that a game ball has been detected even though the game ball is not actually detected. There is a possibility of cheating. In addition, as a switch for detecting a game ball, a light-emitting element and a light-receiving element are juxtaposed, and light from the light-emitting element reflected by the game ball is detected by the light-receiving element so that the light passes through the vicinity of the light-emitting element and the light-receiving element. In the case of using a reflection type photosensor that detects the game ball, the light of the light receiving element in the photosensor is irradiated by some means, so that the game ball is actually detected by the switch that detects the game ball. In spite of this, there is a possibility that a fraudulent act of outputting a detection signal (false detection signal) indicating that a game ball has been detected may be received.

  In the case where both the winning switch and the safe sensor described in Patent Document 1 receive an illegal act that outputs a false detection signal, the number of winning game media actually detected by each winning switch and the safe Since there is no discrepancy with the number detected by the sensor, it is not possible to detect fraud.

Accordingly, the present invention is to test known fraud against detection means for detecting a game medium, and an object thereof is to provide a gaming machine which can take fraud measures.

In order to solve the above-mentioned problem, a gaming machine according to claim 1 of the present invention provides:
A gaming machine (pachinko gaming machine) that gives value based on the winning of a game medium in a variable winning device (400 ) that can be controlled to an open state in which a game medium (game ball) can be won and a closed state in which a game cannot be won 1)
The specific detection means for detecting a game medium which has passed through the specific area (43) provided in the variable winning device (specific region switch 43a),
Based on the Yu technique medium is detected by the specific detector, in Yu Technical state means (gaming control microcomputer 560 to shift to an advantageous Yu TECHNICAL state for the player (jackpot gaming state), special symbols process Part for executing steps S305 to 307 in the process);
First detection means (upper count switch 24) for detecting a game medium and outputting a first detection signal;
Second detection means (fourth winning confirmation switch 24a) for detecting a game medium and outputting a second detection signal;
Abnormality determination means (game control microcomputer 560) for determining a winning abnormality based on the first detection signal output from the first detection means and the second detection signal output from the second detection means. In step S113 in the switch process),
Transition means (a part for executing step S139 in the switch process in the game control microcomputer 560) based on the fact that the abnormality determination means determines that the prize is abnormal.
The first detecting means and the second detecting means are provided at a position (upper ball path 406) for detecting a game medium won in the variable winning device (see FIGS. 23 and 24) and different detection methods. It is constituted by a sensor ( for example, the game medium detection method of the first detection means is electromagnetic, and the game medium detection method of the second detection means is optical),
The abnormality determining means determines that a difference between the number of game media detected by the first detection means and the number of game media detected by the second detection means is from the first detection means to the second detection means. It is characterized in that a winning abnormality is determined when the threshold value is greater than the number of game media corresponding to the length of the passage .
According to this feature, the detection known fraud against detection means for detecting a game medium, it is possible to take fraud measures.

A gaming machine according to claim 2 of the present invention is the gaming machine according to claim 1,
Giving means for giving value based on the output of the first detection signal from the first detection means (upper count switch 24) (for example, the part for executing step S32 in the game control microcomputer 560) With
The second detection signal output from the second detection means (fourth winning confirmation switch 24a) is used only for determination of a winning abnormality in the variable winning device by the abnormality determining means (for example, for game control). the microcomputer 560, a detection signal from the fourth prize confirmation switch 24 a confirmed only in the processing in step S136, used for the determination of the presence or absence of abnormality prize to the upper winning opening 24b in step S139),
It is characterized by that.
According to this feature, since the value is added based on the detection result of one of the detection means, it is possible to prevent an increase in processing burden accompanying the strengthening of countermeasures against fraud.

A gaming machine according to claim 3 of the present invention is the gaming machine according to claim 1 or 2,
A passing area (for example, a first start winning port 13a, a second starting winning port 13b, a lower large winning port 23b, etc.) provided separately from the variable winning device (400);
A gaming machine (pachinko gaming machine 1) that gives a value (prize ball) based on the passing of the gaming medium through the passing area,
The first detection means (first start port switch 14a, second start port switch 15a, lower count switch 23) and the second detection means (first winning confirmation switch 14b, second winning confirmation switch 15b, third winning confirmation) a switch 23a), but the position {first start hole switch 14a for detecting a game medium which has passed through the transmitting region first inlet prize passage 1306a, first winning confirmation switch 14b is first input prize passage 1306b, second start mouth switch 15a and the second prize confirmation switch 15b second inlet prize passage 1307, lower count switch 23 and the third prize confirmation switch 23a is provided on the lower major winning path 1308 (see FIG. 25 (a))},
It is characterized by that.
According to this feature, it is possible to detect fraud against the detecting means for detecting the game medium and take countermeasures against the fraud.

A gaming machine according to claim 4 of the present invention is the gaming machine according to any one of claims 1 to 3,
A collection road surface (bottom surface 1501) that is disposed below the second detection means (fourth winning confirmation switch 24a) and collects game media (game balls) that have passed through the second detection means;
A direction changing unit (a first changer in the upper ball path 406 is provided between the second detection means and the collection road surface so as to be able to change the flow direction of the game medium in contact with the game medium that has passed through the second detection means. 4 bent winning confirmation switch 24a and a bent portion formed at a lower position in the vicinity)
It is characterized by that.
According to this feature, the flow direction of the game medium that has passed through the second detection means is changed by the direction changing unit, thereby preventing the game medium that has fallen and jumped up from being detected again by the second detection means. Is done.

A gaming machine according to claim 5 of the present invention is the gaming machine according to any one of claims 1 to 4,
Provided separately from the variable winning device (400), provided with a predetermined passing area ( ordinary winning ports 29a-29d) through which game media (game balls) are less likely to pass than the open state of the variable winning device,
A gaming machine (pachinko gaming machine 1) that gives a value (prize ball) based on the passing of the gaming medium through the predetermined passing area,
Only the first detection means (winning port switches 30a and 30b) are provided at positions (winning passages 1450 and 1451) for detecting game media that have passed through the predetermined passing area.
It is characterized by that.
According to this feature, since the second detection means is not provided in a predetermined passing area that is not likely to be fraudulent, the manufacturing cost of the gaming machine can be reduced.

It is the front view which looked at the pachinko game machine from the front. It is a rear view which shows a game machine. (A) is a 1st start winning opening, (b) is a 2nd starting winning opening, (c) is a lower large winning opening, (d) is an explanatory view showing a specific example of a sectional structure in an upper large winning opening. It is a circuit diagram for demonstrating the system of the detection means which can detect a game ball. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which a serial communication circuit transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a circuit diagram which shows the internal structure of a terminal board | substrate. (A) is a front view which shows the closed state of a variable winning apparatus, (b) is a front view which shows the open state of a variable winning apparatus. (A) is a figure which shows the flow of the game ball induced | guided | derived to the lower stage from the upper sphere path | route, (b) is a figure which shows the flow of the game sphere induced | guided | derived from the upper ball path | route to the lower sphere path | route. . (A) is a rear view showing various winning aisles provided on the game board, (b) is a view showing the vicinity of the outlets of the second winning award passage and the upper grand award passage, and (c) is a first winning award. It is a figure which shows the discharge port vicinity of a channel | path, (d) is a figure which shows the discharge port vicinity of a lower big prize channel | path. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows a 4 ms timer interruption process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 10 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a winning ball operation cannot be executed immediately. FIG. 5 is a timing chart showing signal transmission and reception between a game control microcomputer and a payout control microcomputer during normal operation. FIG. 10 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when an error occurs during a winning ball. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during connection confirmation. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during award ball number notification. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which similarly shows an example of a special symbol normal process. It is a flowchart which shows an example of a special symbol stop process. It is a flowchart which shows an example of a small hit release pre-processing. It is a flowchart which shows an example of a process during small hit release. It is a flowchart which shows an example of a process at the time of an upper special winning opening entrance. It is a flowchart which shows an example of a small hit end process. It is a flowchart which shows an example of a specific winning determination process. It is a flowchart which shows an example of a jackpot end process. It is a flowchart which shows an example of a normal symbol process process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. (A) is when the game ball is clogged in the first start prize opening, (b) is when the game ball is clogged in the second start prize opening, (c) is in the upper big prize opening (D) is an explanatory view showing a case where the game ball is in a clogged state in the lower prize opening. It is a block diagram which shows the various signals output to a terminal board. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is explanatory drawing which shows the output timing of a security signal. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a main control transmission command conversion process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows the main process which CPU for production control performs. It is a flowchart which shows the specific example of a command analysis process. It is a flowchart which shows production control process processing. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the cross-section of the site | part to which the terminal board | substrate of a cover member is attached.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable winning device 400 having an effect display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol (effect symbol). ing. The effect display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The effect display device 9 variably displays the effect symbol as a decoration (effect) symbol during the variable display period of the special symbol by the first special symbol indicator 8a or the second special symbol indicator 8b. The effect display device 9 that performs variable display of effect symbols is controlled by an effect control microcomputer mounted on the effect control board.

  A first special symbol display (first variable display means) 8a for variably displaying a first special symbol as first identification information is provided at a lower right position on the game board 6. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. A second special symbol display (second variable display means) 8b for variably displaying the second special symbol as the second identification information is provided above the first special symbol display 8a. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. The first special symbol display 8a and the second special symbol display 8b each variably display a number (or a two-digit symbol) from 0 to 99 using, for example, two 7-segment LEDs. It may be configured.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b may be collectively referred to as a special symbol indicator.

  The variable display of the first special symbol is a variable display start condition (for example, after the game ball has won the first start winning opening 13a) after the first start condition, which is the variable display execution condition, is established (for example, When the number of reserved memories is not 0, the variable display of the first special symbol is not executed, and the variable display is started based on the fact that the big hit game is not executed) When time (fluctuation time) elapses, a display result (stop symbol) is derived and displayed. In addition, the variable display of the second special symbol is a variable display start condition (for example, that the game ball has won the second start winning opening 13b) after the second start condition, which is a variable display execution condition, is satisfied (for example, For example, when the number of reserved memories is not 0, the variable display of the second special symbol is not executed, and the big hit game is not executed) is started, When the variable display time (variation time) elapses, the display result (stop symbol) is derived and displayed. Note that winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  In the upper part of the second special symbol display 8b, the number of effective winning balls that have entered the first start winning opening 13a, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) is displayed. A first special symbol reserved memory display section and the first special symbol reserved memory display section are provided separately, and a second special special display for displaying the number of effective winning balls that have entered the second start winning slot 13b, that is, the second reserved memory number. For example, a special symbol storage memory display unit 18 including a 7-segment LED provided with a symbol storage memory display unit is provided. The first special symbol reserved memory display unit displays up to four first reserved memory numbers in the order of winning, and increases the number of indicators that are turned on by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one. The second special symbol reserved memory display unit displays up to four second reserved memory numbers in the order of winning, and increases the number of indicators that are turned on by 1 each time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one. In this example, the upper limit number (up to 4) is provided for the starting memory number by winning at the first starting winning port 13a and the starting memory number by winning at the second starting winning port 13b. May be four or more.

  On the display screen of the effect display device 9, a first reserved memory display unit (not shown) for displaying the first reserved memory number and a second reserved memory display unit (not shown) for displaying the second reserved memory number. And are provided. In addition, you may make it provide the area | region (sum total pending | holding memory display part) which displays the total number (sum total pending memory count) which is the sum total of the 1st pending memory count and the 2nd pending memory count. As described above, if the summation pending storage display section for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition.

  The effect display device 9 is for decoration (effect) during the variable display time of the first special symbol on the first special symbol display 8a and during the variable display time of the second special symbol on the second special symbol display 8b. Display design (also referred to as a decorative design) as a design. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Synchronous means that the start time and end time of variable display are substantially the same (may be exactly the same) and the variable display period is substantially the same (may be exactly the same). Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 reminds the jackpot The combination of is stopped and displayed.

  Below the variable winning device 400, there is provided a winning device having a first start winning port 13a that is always kept in a certain open state by a predetermined ball receiving member, for example. The game ball won in the first start winning opening 13a is guided to the back of the game board 6, and is detected by the first start opening switch 14a (for example, proximity switch) and the first winning confirmation switch 14b (for example, photo sensor). The

  Further, on the right side of the variable winning device 400, there is provided a variable winning ball device 15 having a second start winning port 13b through which a game ball can be won. The game ball that won the second start winning opening (second start opening) 13b is led to the back of the game board 6, and the second start opening switch 15a (for example, proximity switch) and the second winning confirmation switch 15b (for example, for example) It is detected by a photo sensor. The variable winning ball device 15 includes an electric tulip-shaped accessory (ordinary electric accessory) having a pair of movable wing pieces that are changed between an open state in a vertical position and an expanded open state in a tilt position by a solenoid 16. The 2 start winning opening 13b is formed to be openable and closable. When the variable winning ball apparatus 15 is in the open state, the game ball can be won in the second start winning opening 13b (it is easy to start winning), which is advantageous for the player. In the state where the variable winning ball device 15 is in the open state, it is easier for the game ball to win the second starting winning port 13b than the first starting winning port 13a. In addition, in a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning opening 13b. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Further, as will be described later, whether or not an abnormal winning has occurred is determined based on the detection results of the first start opening switch 14a and the first winning confirmation switch 14b and the detection results of the second starting opening switch 15a and the second winning confirmation switch 15b. A security signal is externally output based on the determination and the occurrence of an abnormal winning.

  Hereinafter, the first start winning opening 13a and the second start winning opening 13b may be collectively referred to as a start winning opening or a starting opening.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 13b. The first start winning opening 13a is provided immediately below the variable winning apparatus 400, but the interval between the lower end of the variable winning apparatus 400 and the first start winning opening 13a is further reduced, or the first start winning opening is set. The winning rate of the second starting winning port 13b is such that the nails are densely arranged around 13a, or the nail arrangement around the first starting winning port 13a is difficult to guide the game ball to the first starting winning port 13a. You may make it make higher than the winning rate of the 1st start winning opening 13a.

  In this embodiment, as shown in FIG. 1, the variable winning ball device 15 that opens and closes only the second starting winning opening 13b is provided. However, the first starting winning opening 13a and the second starting winning opening 13a are provided. Any of the start winning openings 13b may be provided with a variable winning ball apparatus that performs an opening / closing operation.

  Below the first start winning opening 13a, there is a door type combination having a lower big winning opening door 23c that is changed by the solenoid 21 into an open state that is tilted and an open state that is a vertical position by a specific game state (big hit state). There is provided a special variable winning ball apparatus 20 that is configured to be able to open and close a lower large winning opening 23b formed in a horizontally long rectangular shape. The special variable winning ball apparatus 20 is means for opening and closing the lower large winning opening 23b. The winning ball that has won the special variable winning ball device 20 and led to the back of the game board 6 is detected by a lower count switch 23 (for example, a proximity switch) and a third winning confirmation switch 23a (for example, a photo sensor).

A normal symbol display device 10 is provided on the right side of the first special symbol indicator 8a. The normal symbol display device 10 includes, for example, two lamps. When the game ball passes through the passage gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display device 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when turned on). For example, if the lower lamp is turned on at the end of the variable display, it is a hit. . When the lamp on the lower side of the normal symbol display device 10 is turned on and it is a win, the variable winning ball device 15 is opened for a predetermined number of times. That is, the state of the variable winning ball device 15 is a state that is advantageous from a disadvantageous state for the player when the lower lamp is lit (a state in which a game ball can win the second start winning opening 13b). ). On the upper part of the special symbol storage memory display 18, there is a normal symbol storage memory display 41 having four display parts (for example, four segments out of 7 segment LEDs) for displaying the number of winning balls that have passed through the passing gate 32. Is provided. Each time there is a game ball passing through the passing gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol hold storage display 41 increases the number of display units to be turned on by one. Then, each time the variable display of the normal symbol display device 10 is started, the number of display units that are lit is reduced by one.

In addition, the normal symbol storage memory display 41 composed of 7-segment LEDs has four display units (segments) for displaying the number of winning balls that have passed through the passing gate 32, and the special variable winning ball device 20 is opened at the time of a big hit, for example. Two display parts (segments) indicating the number of times (number of big hit rounds) and two display parts (segments) indicating the gaming state are provided, but these display parts are displayed separately from the normal symbol hold storage display part. You may comprise with a vessel. Further, the normal symbol display device 10 may be configured by a segment LED or the like that can variably display a plurality of types of identification information called “normal symbols” (for example, “◯” and “x”).

The game area 7 is provided with a plurality of normal winning holes 29a to 29d that are always kept in a certain open state by a predetermined ball receiving member, for example. The winning of the game balls to the winning openings 29c and 29d is detected by the winning opening switch 30b. Each of the normal winning holes 29a to 29d constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winnings, and nails are densely arranged around each of the normal winning holes 29a to 29d. The game balls are harder to be guided to the respective normal winning ports 29a to 29d than the first starting winning port 13a and the second starting winning port 13b, and the winning rates of the respective normal winning ports 29a to 29d are set to the first starting winning port. 13a, lower than the winning rate of the second start winning opening 13b. The first start winning opening 13a, the second start winning opening 13b, and the lower large winning opening 23b also constitute a winning area that accepts game media and allows winning. In addition, it is good also as a structure which detects with a detection switch that the game ball passed through the predetermined area | region (for example, gate) instead of the structure which detects the game ball won to each normal winning opening 29a-29d with a winning switch.

  Next, the variable winning device 400 will be described with reference to FIGS. FIG. 23A is a front view showing the closed state of the variable winning device, and FIG. 23B is a front view showing the open state of the variable winning device. FIG. 24A is a diagram showing the flow of a game ball guided from the upper ball path to the lower stage, and FIG. 24B is a flow of the game ball guided from the upper ball path to the lower ball path. FIG.

The variable winning device 400, on the right upper position in the variable winning device 400, upper winning opening door 24c as the movable member made of a closing member is provided changeable slide. The upper prize winning door 24c is connected to a plunger or the like built in a coil of the solenoid 17 (see FIG. 5) via a predetermined link mechanism such as a linkage arm. When the solenoid 17 is in the on state, the upper special prize opening door 24c brings the upper special prize opening 24b into the open state as the first state. On the other hand, when the solenoid 17 is in the OFF state, the upper special prize opening door 24c puts the upper special prize opening 24b in the closed state as the second state. Note that the upper special winning opening door 24c is not limited to one configured to be slidable, and for example, is configured to be rotatable so that the upper special winning opening 24b is in an open state that is the first state. As long as it can be changed to the open state which is the second state. As described above, the variable winning device 400 can execute the starting operation that changes between the first state (open state) advantageous to the player and the second state (closed state) disadvantageous to the player. It is configured.

  Inside the variable winning device 400, there is provided an upper ball path 406 through which game balls that have entered from the upper large winning opening 24b can flow down and pass. A doll model 401 including a foot model 402 is provided on the left side of the variable winning device 400. The game ball that has entered the variable winning device 400 passes through the upper ball path 406 and then enters one of a plurality of areas such as the specific area 43 and the normal area 44, and then is guided to the back of the game board 6. And discharged to the outside of the variable winning device 400. At this time, the game ball that has entered the specific area 43 is detected by the specific area switch 43a. In other words, the specific area switch 43a detects a game ball that has entered the specific area 43 among a plurality of areas provided in the variable winning device 400. In the present embodiment, a game ball that has entered the variable prize winning device 400 through the upper prize winning opening 24b opened by the upper prize winning opening door 24c in the start operation in the small hit gaming state enters the specific area 43. Then, in response to the detection by the specific area switch 43a, the big hit gaming state as the specific gaming state is controlled.

  The upper big prize opening 24b is an opening that allows the inside and outside of the variable prize-winning device 400 to communicate with each other. When the upper prize-winning port 24b is in an open state as shown in FIG. Can enter inside. A game ball that has entered the variable winning device 400 from the upper prize winning opening 24 b is detected by the upper count switch 24 provided at the inlet to the upper ball path 406 and then the upper ball path 406 from the inlet. Flow into. Based on the detection of game balls by the upper count switch 24, a predetermined number (for example, 10) of game balls are paid out as prize balls and are detected by the fourth winning confirmation switch 24a. In the present embodiment, a winning ball is given according to the detection by the upper count switch 24, but the present invention is not limited to this, and the fourth winning confirmation switch 24a and a later-described A prize ball may be given according to the detection of the game ball by the discharge port switch 45 to be performed.

  As shown in FIGS. 23A and 24A and 24B, a doll model 401 is provided in the vicinity of the upper sphere path 406 as an example of a decorative model. A foot model 402 is attached to the doll model 401 as an example of a movable member serving as a sorting member. The foot model 402 is connected to a plunger or the like built in a coil of the solenoid 18 (see FIG. 5) via a predetermined link mechanism or the like. The solenoid 18 may be connected to a mouth decoration model attached to the doll model 401 and operated in conjunction with the foot model 402.

  When the solenoid 18 is in the OFF state, the foot model 402 is held above the path of the game ball so as not to contact the game ball flowing down the upper ball path 406 as shown in FIG. At this time, the game ball flowing down the upper ball path 406 is guided so as to be distributed to the lower stage 407 without contacting the foot model 402. On the other hand, when the solenoid 18 is in the ON state, as shown in FIG. 24B, the foot model 402 moves downward and comes into contact with the game ball flowing down the upper ball path 406. At this time, the game ball that has flowed down the upper ball path 406 is guided so as to contact the foot model 402 and be distributed to the lower ball path 408.

  The game ball that has entered the normal area 44 is not detected by the specific area switch 43a, but is detected by the discharge port switch 45 after being discharged from the variable winning device 400 to the back side of the game board 6. On the other hand, the game ball that has entered the specific area 43 is detected by the specific area switch 43a and then discharged from the variable winning device 400 to the back side of the game board 6 and then detected by the discharge port switch 45.

  In the prize winning space of the variable prize winning device 400, for example, an effect display device 9 is arranged on the back side of the variable prize winning device 400 or the like. The effect display device 9 may be any device that performs screen display by a dot matrix method using a large number of pixels (pixels) such as a liquid crystal display (LCD). In the effect display device 9, a display area for displaying an effect image is formed. In the display area of the effect display device 9, for example, the effect symbol variable display divided into three in correspondence with the variable symbol special symbol display in the special symbol game by the first special symbol indicator 8 a and the second special symbol indicator 8 b. The display unit variably displays a plurality of types of effect symbols (also referred to as decoration symbols) that can be identified, and the first reserved memory number or the second start as the number of effective approaching balls that have entered the first start winning opening 13a. The number of second reserved memories as the number of effective approaching balls that have entered the winning opening 13b is displayed. This variable display of the effect symbols is also included in the variable display game performed based on the start condition being satisfied.

  As an example, in the display area of the effect display device 9, “left”, “middle”, and “right” effect symbol variable display portions are arranged, and the first special symbol display 8 a and the second special symbol display 8 b Corresponding to the execution of any of the special symbol games, the variable display of the effect symbols is started in each effect symbol variable display section. That is, when the variable display of the special symbol is started by any one of the first special symbol display 8a and the second special symbol display 8b, each of the effect symbol variable display portions “left”, “middle”, and “right” is displayed. When starting the variable display (for example, switching display or scroll display) of the effect symbols at, and then when the confirmed special symbol is stopped and displayed as a variable display result in the special game, "left", "middle", "right" In each effect symbol variable display section of "", the finalized effect symbol that is the result of variable display of the effect symbol is stopped and displayed (derived display). In addition, each of the “left”, “middle”, and “right” effect symbol variable display portions can be moved within the display area of the effect display device 9 so that the effect symbols can be displayed in a reduced or enlarged manner. It may be.

  In each of the “left”, “middle”, and “right” effect variable display portions in the display area of the effect display device 9, for example, eight kinds of symbols (alphanumeric characters “1” to “8” or Chinese numerals “one” to “8”, English letters “A” to “H”, eight character images related to a predetermined motif, a combination of numbers, letters or symbols and character images, etc. An effect image showing an object other than these, a symbol such as a character, or any other graphic) may be displayed as a changeable design pattern. A corresponding symbol number is attached to each of the effect symbols. For example, symbol numbers “1” to “8” may be assigned to alphanumeric characters indicating “1” to “8”, respectively.

  When the variable display of the effect symbol is started in the display area of the effect display device 9, in each of the effect symbol variable display portions of “left”, “middle”, and “right”, for example, from the smallest symbol number to the larger symbol. When switching display or scroll display is performed and the effect symbol with the maximum symbol number “8” is displayed, the effect symbol with the minimum symbol number “1” is then displayed. Alternatively, when the effect symbol with the smallest symbol number “1” is displayed by switching display or scrolling from the largest symbol number to the smallest symbol number, the next largest symbol number is “8”. A certain effect design may be displayed. During the variable display of the effect symbol, for example, an image for performing various effect displays such as a notice effect image for notifying that the variable display result is “big hit” or “small hit” is displayed on the effect display device 9. It may be displayed in the area.

  A decorative member 25 provided with a decorative lamp 25a that blinks and displays during the game is provided around the left and right sides of the game area 7, and an out port 26 that absorbs a game ball that has not won a prize is provided below. In addition, two speakers 27 that emit sound effects are provided on the left, right, top, and bottom of the outside of the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine. In this embodiment, the case where the light emitter provided in the gaming machine is configured by using a lamp or an LED is shown. However, the present invention is not limited to the mode shown in this embodiment. You may make it comprise all the provided light-emitting bodies using LED.

  Although not shown in FIGS. 1 and 2, a prize ball lamp that is turned on during the prize ball payout is provided in the vicinity of the left frame lamp 28b, and a supply ball is provided in the vicinity of the top frame lamp 28a. There is a ball-out lamp that illuminates when it runs out. Note that the award ball lamp and the out-of-ball lamp are controlled to be turned on by the effect control microcomputer mounted on the effect control board when the award ball is being paid out or when the out-of-ball is detected. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the first start winning port 13a and is detected by the first start port switch 14a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the first special symbol display 8a starts variable display (variation) of the first special symbol, and the effect display device 9 starts variable display of the effect symbol (decoration symbol). Is done. In other words, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13a. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning port 13b and is detected by the second start port switch 15a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the effect display device 9 starts variable display of the effect symbol (decoration symbol). Is done. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 13b. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  The variable display of the first special symbol on the first special symbol display 8a and the variable display of the second special symbol on the second special symbol display 8b are stopped when a certain time has elapsed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. The opening of the special variable winning ball apparatus 20 is allowed until the last round of the determined number of rounds (for example, up to 15 rounds). In addition, when the special symbol (stop symbol) at the time of stoppage is the small hit symbol (small hit display result), it shifts to the small hit game state. That is, the variable winning device 400 is opened until a predetermined time has elapsed.

When the game ball passes the passing gate 32, the normal symbol display device 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol in the normal symbol display device 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  A special symbol game (also referred to as a first special symbol game) by the first special symbol display 8a is a variable special symbol by the first special symbol indicator 8a, such as a game ball entering the first start winning opening 13a. After the first start condition for executing the display is established, the first start condition for starting the variable display of the special symbol, for example, the end of the previous special figure game or the end of the big hit game state is, for example, It starts based on the establishment. The special symbol game (also referred to as the second special symbol game) by the second special symbol display 8b is a variable special symbol by the second special symbol display 8b, such as a game ball entering the second start winning opening 13b. After the second starting condition for executing the display is established, for example, to start variable display of special symbols such as the end of the previous special figure game, the end of the big hit game state, or the small hit game state The process is started on the basis that the second start condition is satisfied. As described above, the first special symbol display 8a variably displays the first special symbol serving as the first identification information based on the fact that the first start condition is satisfied after the first start condition is satisfied. Variable display means is configured. Further, the second special symbol display 8b variably displays the second special symbol serving as the second identification information based on the fact that the second start condition is satisfied after the second start condition is satisfied. Configure the means. In the present embodiment, for example, after both the first start condition and the second start condition are satisfied, the first start condition and the second start condition corresponding to each are not satisfied. When both the first start condition and the second start condition can be established, the second start condition is established with priority over the first start condition. In addition, winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  In the special symbol game by the first special symbol indicator 8a or the second special symbol indicator 8b, after the special symbol variable display is started, when a predetermined time elapses, a fixed special symbol which becomes a variable symbol variable display result is displayed. Stop display (derived display). At this time, if a specific special symbol (big hit symbol) is stopped and displayed as a confirmed special symbol, it becomes a “big hit” as the specific display result, and a predetermined special symbol (small bonus symbol) different from the big hit symbol is stopped and displayed. Then, “small hit” is obtained as a predetermined display result, and if a special symbol other than the big hit symbol or the small hit symbol is stopped and displayed, “off” is obtained. When the variable display result in the special figure game is “big hit”, it is controlled to the big hit gaming state as the specific gaming state. In addition, when the variable display result in the special game is “small hit”, the game state is controlled to a small hit game state different from the big hit game state. In the pachinko gaming machine 1 in the present embodiment, as an example, in the first special symbol display 8a, the numbers indicating “1”, “2”, “3”, “4”, “5” The symbol of 5 big hits is used, and the symbol indicating “−” is used as a symbol. In the second special symbol display 8b, the number indicating “7” is a big hit symbol, and the numbers indicating “1”, “2”, “3”, “4”, “5” are small hit symbols. Yes. In the present embodiment, the second special symbol display 8b does not necessarily have a deviation symbol because there is no deviation because it is a big hit or a small hit, but in the case of providing a deviation, the first special symbol indicator Similarly to 8a, the symbol indicating “−” may be removed and used as a symbol. In the first special symbol game by the first special symbol display 8a, the jackpot symbol that is stopped and displayed as the confirmed special symbol that is the variable symbol display result of the special symbol becomes the first specific display result. Further, in the second special symbol game by the second special symbol display 8b, the big hit symbol that is stopped and displayed as the fixed special symbol which is the variable display result of the special symbol becomes the second specific display result, and the small hit symbol is the second predetermined symbol. Display result.

  In the display area of the effect display device 9, in response to the variable display of the special symbol being performed in the special symbol game by the first special symbol display device 8a or the second special symbol display device 8b, Done. Then, when the confirmed special symbol in the special symbol game becomes a big hit symbol, as the variable symbol display result of the special symbol game, for example, a predetermined symbol variable display unit of “left”, “middle”, “right” The finalized design symbols constituting the big hit combination are stopped and displayed. For example, the same effect design such as an alphanumeric character indicating “7” is arranged in each of the effect design variable display sections of “left”, “middle”, and “right”. What is derived and displayed may be included. In addition, when the confirmed special symbol in the second special symbol game is a small hit symbol, as a variable display result of the effect symbol, for example, in each effect symbol variable display portion of “left”, “middle”, “right” Thus, the definite effect symbols constituting the predetermined small hit combination are stopped and displayed. In such a small winning combination finalized design symbol, for example, “1”, “3”, and “5” alphanumeric characters indicating “left”, “middle”, and “right” in the production symbol variable display portion are stopped. As in the case of displaying, it is only necessary to include one in which a predetermined combination of effect symbols is derived and displayed.

  In the small hit game state based on the fact that the confirmed special symbol in the special symbol game by the second special symbol display 8b becomes the small hit symbol, the variable winning device can be obtained by switching the solenoid 17 from the OFF state to the ON state, for example. The upper special prize opening door 24c at 400 is slid to change the upper special prize opening 24b from the closed state to the open state in a predetermined starting manner. Thereafter, when a predetermined time elapses, the upper special winning opening 24b is returned to the closed state, for example, by switching the solenoid 17 from the on state to the off state. The opening / closing operation of the upper special winning opening 24b performed in such a small hit gaming state is referred to as a starting operation. For example, in the small hit gaming state, the starting operation for opening and closing the upper special winning opening 24b is performed a plurality of times such as once or twice. As described above, the starting operation is based on the fact that the game ball that has entered the second starting winning port 13b is detected by the second starting port switch 15a, and the variable display result in the special game by the second special symbol display 8b. Corresponding to the second predetermined display result “small hit”, the upper big winning opening 24b in the variable winning device 400 is changed from the closed state, which is a disadvantageous state for the player, to the player. After the open state, which is an advantageous first state, is changed to the closed state, which is the second state.

  When a game ball that has entered the variable prize-winning device 400 from the upper big prize opening 24b opened by the start operation enters the specific area 43 and is detected by the specific area switch 43a, the big hit gaming state ( 7th big hit). As described above, when the confirmed special symbol in the special symbol game by the second special symbol indicator 8b becomes a small hit symbol, the variable prize winning device 400 from the upper big prize opening 24b opened in the starting operation. In response to the game ball entering the inside being detected by the specific area switch 43a, control for setting the big hit gaming state is performed. On the other hand, when the confirmed special symbol in the special symbol game by the first special symbol indicator 8a or the second special symbol indicator 8b becomes a big hit symbol, it is related to whether or not the game ball has entered the specific area 43. However, control is performed to achieve a big hit gaming state (first to sixth big hits). In this case, the lower big prize opening 23b is opened by the lower big prize opening door 23c provided in the special variable prize ball apparatus 20 without opening the upper big prize opening 24b provided in the variable prize winning device 400. A specific action to enter a state is started.

  In the big hit game state, it becomes possible to execute a specific operation of a predetermined operation unit as a round game, and the lower big prize opening 23b formed in the special variable winning ball device 20 is changed from the closed state as the second state to the first state. It becomes an open state as a state of. As an example, in the special variable winning ball apparatus 20, a predetermined time (for example, 29 seconds) has elapsed after the lower big prize opening door 23 c changes the lower big prize opening 23 b from the closed state to the opened state, or In response to the occurrence of the number (for example, 10) of winning balls, the operation unit until the lower large winning opening 23b is changed from the open state to the closed state is defined as one round game. In addition, the round maximum value as the maximum number of times that the round game can be repeatedly executed (can be continued) in the big hit game state is determined to be “15” (in the case of the seventh big hit via the small hit, it is substantially 14 times as will be described later). In the present embodiment, the round maximum value for all jackpot types is set to 15. However, the round maximum value may be varied depending on the jackpot type.

  In the big hit game state, the next round game can be executed after the end of each round game other than the final round game that has reached the maximum round value. At this time, the condition for enabling the next round game to be executed is that the game ball has been detected by the lower count switch 23 during the execution of the round game or the V winning detection has been detected by the continuous winning detector. (Round continuation condition) may be used. On the other hand, until the maximum round value is reached, the next round game can be executed after the end of the round game regardless of whether or not the game ball is detected by the lower count switch 23 or the continuous winning detector. Good.

  After the big hit gaming state is ended, depending on the type of the big hit, unlike the normal gaming state or the big hit gaming state, it is controlled to a short time state (advantageous state) as an advantageous state advantageous to the player compared to the normal gaming state. The The normal game state is a specific game state such as a big hit game state, an advantageous state such as a short time (advantage) state, or a game state other than the small hit game state. The probability of “per figure” is controlled to be the same as the initial setting state of the pachinko gaming machine 1 (for example, when a predetermined return process is not executed after power-on as in the case of a system reset). .

  In the short-time (advantageous) state, for example, the probability that the variable display result in the ordinary game is “per normal” is higher than the normal game state, or the variable display result in the ordinary game is “per normal”. When the movable wing piece in the second start winning opening 13b makes the second start winning opening 13b in the expanded open state as the first guiding state, the period and the number of times increase from the normal gaming state. The variable display time from the start of variable display of normal symbols until the variable display result is stopped and displayed is shorter than the normal game state, any one of these, or all of these combined For example, the second start condition for executing the special figure game by the second special symbol display 8b may be more easily established than in the normal gaming state. In this embodiment, in the short time (advantageous) state, the probability of “per game” is the same as in the normal game state, but the variable display time of the normal game is longer than the normal game state (30 seconds). Is shortened (1 second), and when the period during which the movable blade piece is in the expanded open state is extended from 0.1 second to 5 seconds, the second start winning opening 13b can be easily won. This is advantageous to the player.

  In the present embodiment, when it is determined that the short-time (advantageous) state is set after the big hit gaming state, the special-time game by the second special symbol display 8b is controlled to the above-mentioned short-time state during the period of 100 times. Is done. In the first special symbol display 8a, the advantageous state after the big hit gaming state is ended, based on the presence or absence of the short time (advantageous) state when controlled to the big hit gaming state and the type of the big hit (first to fifth) generated. In the case where it is determined whether or not to be in the short-time (advantageous) state, control of the short-time (advantageous) state is started. Further, in the second special symbol display 8b, when the big hit type (sixth) that has occurred or the small hit game state is controlled and the game ball flows into the specific area 43, the big hit game state is controlled. When it is decided to make the short-time (advantageous) state after the end of the big-hit gaming state based on the winning type (first to fifth) At this time, the control of the short time (advantageous) state is started. The short time (advantageous) state that has been started is controlled to the big hit game state when it is the short time (advantageous) state, or the special figure game by the second special symbol display 8b is the upper limit number of times (for example, 100 times). ), The control of the short time (advantageous) state ends.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as viewed from the back. As shown in FIG. 2, on the back side of the pachinko gaming machine 1, there are a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, and the like. Various boards such as a mounted game control board (main board) 31, an audio output board 70, a lamp driver board 35, and a payout control board 37 mounted with a payout control microcomputer for performing ball payout control are installed. Yes. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, there are provided a power supply substrate 910 and a touch sensor substrate (not shown) on which power supply circuits for creating various power supply voltages such as DC30V, DC21V, DC12V and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided. ing. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. The number-of-payout counting switch 301 (see FIG. 6) for counting prize balls and rental balls is also configured as a part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 includes, for example, an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state (a start port signal shown in FIG. 58, one symbol determination signal, one jackpot signal, two jackpot signals, three jackpot signals, hour An information output terminal for externally outputting a short signal, security signal, prize ball signal 1, gaming machine error state signal) is provided. Note that the gaming machine error status signal does not necessarily have to be output to the outside of the pachinko gaming machine 1, and a door indicating that the gaming frame is open from the information output terminal instead of the gaming machine error status signal. An open signal or the like may be output.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. When the ball break switch 187 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIGS. 3A and 3B illustrate a specific example of a cross-sectional structure in the first start winning opening, (b) the second starting winning opening, (c) the lower large winning opening, and (d) the upper large winning opening. FIG. As shown in FIG. 3A, in the first start winning opening 13a, two switches (a first start opening switch 14a and a first winning confirmation switch 14b) capable of detecting a game ball won in the start winning opening. Is provided. In this embodiment, a first start opening switch 14a and a first winning confirmation switch 14b are vertically arranged in the first start winning opening 13a (in this example, the first start opening switch 14a is on the upper side). And the first winning confirmation switch 14b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the first start winning opening 13a is guided to the back of the game board 6, first detected by the first start opening switch 14a, and then by the first winning confirmation switch 14b. Detected.

  Further, as shown in FIG. 3B, in the second start winning opening 13b, there are two switches (a second start opening switch 15a and a second winning confirmation switch) capable of detecting a game ball won in the start winning opening. 15b) is provided. In this embodiment, the second start opening switch 15a and the second winning confirmation switch 15b are arranged vertically in the second start winning opening 13b (in this example, the second start opening switch 15a is on the upper side). And the second winning confirmation switch 15b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the second start winning opening 13b is guided to the back of the game board 6, first detected by the second start opening switch 15a, and then by the second winning confirmation switch 15b. Detected.

  Further, as shown in FIG. 3 (c), in the lower big prize opening 23b, there are two switches (a lower count switch 23 and a third prize confirmation switch that can detect a game ball won in the lower big prize opening 23b. 23a) is provided. In this embodiment, a lower count switch 23 and a third winning confirmation switch 23a are arranged up and down in the lower big prize opening 23b (in this example, the lower count switch 23 is arranged on the upper side, The winning confirmation switch 23a is arranged on the lower side). Therefore, in this embodiment, the game ball won in the lower big prize opening 23b is guided to the back of the game board 6, first detected by the lower count switch 23, and then detected by the third winning confirmation switch 23a. .

  Further, as shown in FIG. 3 (d), in the upper special winning opening 24b, there are two switches (upper count switch 24 and fourth winning confirmation switch that can detect a game ball won in the upper special winning opening 24b. 24a) is provided. In this embodiment, the upper count switch 24 and the fourth winning confirmation switch 24a are arranged vertically in the upper special winning opening 24b (in this example, the upper count switch 24 is arranged on the upper side, The winning confirmation switch 24a is arranged on the lower side). Therefore, in this embodiment, the game ball won in the upper special winning opening 24b is first detected by the upper count switch 24 and then detected by the fourth winning confirmation switch 24a.

  In addition, the first start opening switch 14a, the first winning confirmation switch 14b, the second starting opening switch 15a, the second winning confirmation switch 15b, the lower count switch 23, the third winning confirmation switch 23a, the upper count switch 24, and the fourth. As the winning confirmation switch 24a, switches of different detection methods are used. In this embodiment, proximity switches are used as the first start port switch 14a, the second start port switch 15a, the lower count switch 23, and the upper count switch 24, and the first winning confirmation switch 14b, the second winning confirmation switch 15b, A case is shown in which a photo sensor is used as the third winning confirmation switch 23a and the fourth winning confirmation switch 24a.

Further, in this embodiment, as will be described later, based on the detection of the game ball by the first start port switch 14a, the first special symbol variation display is started and the prize ball payout is executed. Further, based on the fact that the game ball is detected by the second start port switch 15a, the display of the variation of the second special symbol is started, and a prize ball payout is executed. Further, based on the detection of the game ball by the lower count switch 23 and the upper count switch 24, a prize ball payout is executed. Further, as will be described later, it is determined whether or not an abnormal winning has occurred based on the detection result of the first winning confirmation switch 14b in addition to the detection result by the first start opening switch 14a, and the occurrence of the abnormal winning is detected. A security signal is output externally. In addition to the detection result of the second start opening switch 15a, the presence / absence of an abnormal winning is determined based on the detection result of the second winning confirmation switch 15b, and the security signal is generated based on the detection of the abnormal winning. Output externally. In addition to the detection result of the lower count switch 23, whether or not an abnormal winning has occurred is determined based on the detection result of the third winning confirmation switch 23a, and a security signal is externally output based on the detection of the abnormal winning. Is done. In addition to the detection result by the upper count switch 24, whether or not an abnormal winning has occurred is determined based on the detection result of the fourth winning confirmation switch 24a, and a security signal is externally output based on the detection of the abnormal winning. Is done. Thus, in this embodiment, the first prize confirmation switch 14b, the second prize confirmation switch 1 5 b, third prize confirmation switch 23a, a fourth prize confirmation switch 24a is used only to determine the abnormal winning.

  Thus, in this embodiment, in addition to the first start opening switch 14a, the first start winning opening 13a includes the first winning confirmation switch 14b, and the second start winning opening 13b includes the second start opening switch 15a. In addition to the second winning confirmation switch 15b, the lower large winning opening 23b is added to the lower counting switch 23, the third winning confirmation switch 23a is added to the upper large winning opening 24b, and the upper counting switch 24 is added to the second counting switch 23b. A 4-winning confirmation switch 24a is provided. The first start winning port 13a, the second start winning port 13b, the lower count switch 23, and the upper count switch 24 are configured using proximity switches, and the first winning check switch 14b, the second winning check switch 15b, and the third winning switch. Although the confirmation switch 23a and the fourth winning confirmation switch 24a use photo sensors, the first starting opening switch 14a and the first winning confirmation switch 14b, the second starting opening switch 15a and the second winning confirmation switch 15b, and the lower count switch 23, the third winning confirmation switch 23a, the upper count switch 24, and the fourth winning confirmation switch 24a are not limited to those shown in this embodiment. For example, the first and second start opening switches 14a, 15a and Lower count switch 23, upper count switch 24, and first to fourth winning confirmation switches If the detection method differs between 4b, 15b, 23a, and 24a, the first and second start opening switches 14a and 15a, the lower count switch 23, and the upper count switch 24 use photo sensors, and the first to fourth prize confirmation Proximity switches may be used as the switches 14b, 15b, 23a, and 24a. In this case, the special symbol variation display and prize ball payout processing are executed based on the detection results of the first and second start port switches 14a and 15a, the lower count switch 23, and the upper count switch 24, which are photosensors. The detection results of certain first to fourth winning confirmation switches 14b, 15b, 23a, and 24a are used only for the determination of abnormal winning of the first and second start port switches 14a and 15a, the lower count switch 23, and the upper count switch 24. become. Also, for example, instead of a proximity switch or an optical photosensor that is an electromagnetic switch, the first and second start port switches 14a and 15a, the lower count switch 23, the upper count switch 24, or the first to fourth winning confirmation switches Mechanical switches (such as microswitches) may be used as 14b, 15b, 23a, and 24a.

  FIG. 4 is a circuit diagram for explaining a method of detection means capable of detecting a game ball. In FIG. 4, the first start opening switch 14a and the first winning confirmation switch 14b will be described as an example. However, the second starting opening switch 15a and the third winning confirmation switch 14b, the lower count switch 23, and the third winning confirmation switch Since the 23a, the upper count switch 24 and the fourth winning confirmation switch 24a are the same as the first start opening switch 14a and the first winning confirmation switch 14b, detailed description thereof is omitted here.

Further, in this embodiment, the first and second start opening switches 14a and 15a, the lower count switch 23, and the upper count switch 24, which trigger the execution of the special symbol change display and the winning ball payout process, are determined as abnormal winnings. The first to fourth winning confirmation switches 14b, 15b, 23a, and 24a used in the above are provided on the upstream side, but may be provided on the downstream side of the switch used for determining the abnormal winning.

  FIG. 4A shows a first start port switch 14a (second start port switch 15a, lower count switch 23, upper count switch 24) which is a proximity switch. One terminal of the first start port switch 14a (second start port switch 15a, lower count switch 23, upper count switch 24) is supplied with + 12V power supply voltage from the power supply board 910. A detection signal that is the voltage level of the other terminal of the first start port switch 14 a is input to the main board 31. In the main board 31, the detection signal is input from the input driver circuit to the input port of the game control microcomputer. A resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the first start port switch 14a.

  When a metal game ball passes through a hole provided in the first start port switch 14a that is a proximity switch, a counter electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Accordingly, the output of the first start port switch 14a becomes a low level close to 0V. That is, the detection signal is at a low level. When the metal game ball does not pass through the hole provided in the first starter switch 14a, the output of the first starter switch 14a is divided by + 12V by the resistance value of the coil L and the resistor R. Exceeding a threshold level that is considered high. That is, the detection signal is at a high level. Therefore, in this embodiment, the game control microcomputer can determine that the first start port switch 14a is in the OFF state if the output from the first start port switch 14a is at a high level. If the output from the start port switch 14a is at a low level, it can be determined that the first start port switch 14a is in an ON state (that is, the output of the first start port switch 14a is negative logic). The detection signal level may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  FIG. 4B shows a first winning confirmation switch 14b (second winning confirmation switch 15b, third winning confirmation switch 23a, and fourth winning confirmation switch 24a) which is a photosensor. The photosensor illustrated in FIG. 4B includes a light-emitting diode (LED) 341 that emits light and a phototransistor 342 that receives light and outputs current. When the game ball passes in the vicinity of the light-emitting diode 341 and the phototransistor 342, the phototransistor 342 receives light from the light-emitting diode 341 reflected by the game ball and causes a current to flow to the output side. In this case, since a current flows from the collector terminal of the phototransistor 342 toward the emitter terminal, the detection signal of the photosensor is negative logic as in the proximity switch. The output side of the photosensor is connected to the main board 31, and the detection signal of the photosensor is input from the input driver circuit to the input port of the game control microcomputer. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer. As with the proximity switch, the level of the detection signal may be logically inverted by an input driver circuit and then input to the game control microcomputer 560.

  The game control microcomputer can determine that the game ball has passed through the photosensor when the detection signal from the input driver circuit is at a low level.

  In this embodiment, a reflective photosensor is used as a photosensor. As shown in the upper part of FIG. 4C, a light emitting element (LED 341) and a light receiving element (phototransistor 342) are used as winning balls. The game balls that have been installed so as to face each other and the game ball blocks light from the light emitting element and the light receiving element does not detect the light, thereby detecting the game ball that has passed between the light emitting element and the light receiving element. A transmissive photosensor may be used. When a transmissive photosensor is used, as shown in the lower part of FIG. 4C, the optical axis of the light emitting element (illustrated by a black circle in FIG. 4C) is a game ball path (winning ball). It is preferable to install the light emitting element and the light receiving element so as to deviate from the center of the game ball passing through the route. Compared to the case where the optical axis corresponds to the central portion of the game ball, a portion where the interval between two game balls passing through is relatively wide (the portion of “void” in FIG. 4C) This is because the game ball can be detected at, and the two game balls can be easily detected separately. For the same reason, when using the reflective photosensor illustrated in FIG. 4B, the light emitting element and the light receiving element are installed so that the reflection point of the light from the light emitting element is shifted from the center of the game ball. It is preferable to do.

  FIG. 5 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 5 also shows the payout control board 37, the effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads the numerical data as random R from the random number circuit 503 when a start winning to the first start port switch 14a or the second start port switch 15a occurs, and starts to change the special symbol and the effect symbol Sometimes it is determined whether or not to make a big hit display result as a specific display result based on the random R, that is, whether or not to make a big hit. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  Further, the game control microcomputer 560 inputs / outputs (transmits / receives) signals to / from the payout control board 37 (the payout control microcomputer 370) and the effect control board 80 (the effect control microcomputer) by serial communication. Serial communication circuit 505 is incorporated. The payout control microcomputer 370 and the effect control microcomputer also incorporate a serial communication circuit for inputting / outputting signals to / from the game control microcomputer 560 through serial communication (the payout control microcomputer 370 includes (See FIG. 6 for the built-in serial communication circuit). The game control microcomputer 560 includes a two-channel serial communication circuit 505, and can perform serial communication with the payout control microcomputer 370 and also performs serial communication with the effect control microcomputer 100. It is possible. However, in this embodiment, for serial communication with the production control microcomputer 100, a signal is output only from the game control microcomputer 560 to the production control microcomputer, and the production control microcomputer 100 No signal is output to the game control microcomputer 560. Note that the communication between the game control microcomputer 560 and the effect control microcomputer is not limited to the serial communication configuration, and may be configured to perform parallel communication.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as the value of the special symbol process flag and the pending storage number counter) and data indicating the number of unpaid prize balls (specifically, prize balls described later) The value of the command output counter) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid winning balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). Instead of mounting the power monitoring circuit on the power supply board, it may be mounted on a board that is backed up by a backup power supply (for example, the main board 31). A clear signal (see FIG. 5) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  In addition, the gate switch 32a, the first start opening switch 14a, the first winning confirmation switch 14b, the second starting opening switch 15a, the second winning confirmation switch 15b, the lower count switch 23, the third winning confirmation switch 23a, and the upper count switch 24. Also, an input driver circuit 58 for supplying a detection signal from the fourth winning confirmation switch 24a, the specific area switch 43a, the discharge opening switch 45 and the winning opening switches 30a and 30b to the basic circuit 53 is also mounted on the main board 31, and the variable winning ball is mounted. An output circuit 59 for driving the solenoid 16 for opening / closing the device 15, the solenoid 17 for opening / closing the variable winning device 400, the solenoid 18 for driving the foot model 402, and the solenoid 21 for opening / closing the special variable winning ball device according to a command from the basic circuit 53. Is also mounted on the main board 31 and controls the game when the power is turned on. A system reset circuit (not shown) for resetting the microcomputer 560 and information output signals such as jackpot information indicating the occurrence of a jackpot gaming state are sent to an external device such as a hall computer via the terminal board 160. An information output circuit 64 for outputting is also mounted on the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  FIG. 6 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 6, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. The predetermined payout conditions are a winning area provided in the game area (normal winning holes 29a to 29d, lower large winning hole 23b, upper large winning hole 24b, first starting winning hole 13a, second starting winning hole 13b). It is established when a game ball is won or a rental ball request is made. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Further, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560. Note that specific signal exchange by serial communication between the game control microcomputer 560 and the payout control microcomputer 370 will be described later.

Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from the error release switch 375 for releasing the error state is input to the I / O port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the I / O port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the I / O port 372a, it is not shown in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( (PRDY signal) is transmitted / received via the I / O port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, when a BRDY signal from the card unit 50 is not in an ON state, a prize ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 7 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 7, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control microcomputer 101 including an effect control CPU 101a and a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). The effect control microcomputer 100 has a built-in serial communication circuit 101b that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication. In addition, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101a. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. In addition, the production control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies current to a light emitter provided on the frame side such as the frame lamp 28 based on a signal for driving the LED. Further, an electric current is supplied to the decorative lamp 25a provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 8 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 8, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses a single signal line for transmission of an effect control signal to produce an effect control command (effect control signal). Is transmitted to the effect control board 80.

  As shown in FIG. 8, wiring from the first start opening switch 14a, the first winning check switch 14b, the second starting opening switch 15a, and the second winning check switch 15b is connected to the main board 31. Further, on the main board 31, the lower count switch 23 of the special variable winning ball apparatus 20 which is the lower big winning opening 23b, the third winning confirmation switch 23a, and the upper count switch 24 of the variable winning apparatus 400 which is the upper big winning opening 24b. Also, wiring from various switches 43a, 45, 30a, 30b for detecting the fourth winning confirmation switch 24a and the winning of the game ball to the other winning opening is connected. Further, the main board 31 includes a solenoid 16 for opening and closing the variable winning ball apparatus 15, a solenoid 17 for opening and closing the upper large winning opening door 24c, a solenoid 18 for driving the foot model 402, and a solenoid for opening and closing the special variable winning ball apparatus 20. The wiring to 21 is connected.

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with microcomputers provided in payout control board 37 and effect control board 80, and I / O An O port unit 57 is incorporated.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where the serial communication circuit 505 is used for communication will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  In this embodiment, as shown in FIG. 8, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full-duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, and a microcomputer on each control board (for example, the payout control board 37 and the effect control board 80). Perform serial communication. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 9 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 10 is a block diagram illustrating a configuration example of a receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 9, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 10, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 11 is an explanatory diagram showing an example of a data format of data transmitted / received by the serial communication circuit 505 to / from a microcomputer mounted on each control board. As shown in FIG. 11, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 11A shows an example of a data format when the data length is set to 8 bits. FIG. 11B shows an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 11, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made so that a parity bit is added, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).
Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 12 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 13A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 13A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 13B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 13B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 13B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 505) in the standby state. Is set. As shown in FIG. 13 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 13B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 13B, by setting bit 1 to “0”, the parity function is set not to be used. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 13B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 14A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 14A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 14B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 14B, in the bit 7 (bit name “TIE”) of the control register B708, setting data indicating whether or not a transmission interrupt request that is an interrupt request to be performed at the time of data transmission is permitted is set. Is done. As shown in FIG. 14B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 14B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request performed when data is received, is permitted. As shown in FIG. 14B, the reception interrupt request is set to be prohibited by setting bit 5 to “0”. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B708 is set with setting data indicating whether or not an idle line interrupt request that is an interrupt request to be performed when an idle line of received data is detected is permitted. As shown in FIG. 14B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 14B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 14B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used. In this embodiment, setting to use the receiving circuit is performed by setting bit 2 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 14B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 14B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 causes the microcomputer on which the control board (the payout control board 37 and the effect control board 80) is mounted with a break code (for example, a signal continuously including “0”). Send to.

  FIG. 15A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 15A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  In this embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 15B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 15B, transmission data indicating that transmission data is not stored in transmission data register 710 (transmission data empty) in bit 7 (bit name “TDRE”) of status register A705. Stores an empty flag. As shown in FIG. 15B, when “0” is stored in the bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. In addition, when “0” is stored in bit 7, data is not written to the transmission data register. For example, in steps S5211, S52305, transmission data is set on condition that “0” is not stored in bit 7. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 15B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that. When the command storage area is in the ring buffer format, if “1” is stored in bit 6, the command read pointer is updated.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 15B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full). Whether or not the command from the payout control microcomputer 370 has been received is confirmed by whether or not “1” is stored in bit 5. For example, in steps S5221, S52401, and S52501, it is determined that the command is received on condition that “0” is not stored in bit 5. In this embodiment, bit 5 (RDRF) of status register A 705 is cleared when reception data is read from reception data register 711 by game control microcomputer 560. If the bit 5 (RDRF) of the status register A 705 is not automatically cleared when the received data is read, the game control microcomputer 560 reads the received data from the received data register 711. Every time reception data is read, it is necessary to perform processing for clearing bit 5 (RDRF) of the status register A705.

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the reception interrupt is set, the serial communication circuit 505 sets the bit 5 of the status register A 705 to “1” when reception data full is detected, and enables reception processing. As an example, an interrupt request is made to the CPU 56 (referred to as an interrupt request upon reception).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 15B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 15B, when “0” is stored in bit 3, it indicates that the receiving circuit is not detecting an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It will not be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 15B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 15B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 15B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 16A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 16B, the status register B706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 16B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 16B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 16B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. Even when “1” is stored in bit 0, command data is not written or command data cannot be written. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 17A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 17A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if a control for writing a value to bits 4 and 5 of the control register C709 is performed, it is invalid, and all the values read from the bits 4 and 5 are “0 (= 0000b)”.

  FIG. 17B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 17B, bit 7 (bit name “R8”) of the control register C709 stores the 9th bit data of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the 9th bit data of the transmission data when the data length is set to 9 bits.

  Bit 3 (bit name “ORIE”) of the control register C709 is set with setting data indicating whether or not to permit an overrun flag interrupt request that is an interrupt request to be performed when an overrun is detected. As shown in FIG. 17B, by setting bit 3 to “0”, an overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 17B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 17B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 17B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 18 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 18, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of communication error is permitted, the interrupt control circuit 714 interrupts the CPU 56 with the occurrence of the communication error as a cause of interruption when detecting a parity error. Make a request.

  FIG. 19A is an explanatory diagram showing a hit determination table. The hit determination table is a collection of data stored in the ROM 54 and is a table in which a big hit determination value to be compared with random 0 is set. In the hit determination table, the special symbol pointer to be described later is the first, that is, the first special symbol is the variable display target, and the special symbol pointer to be described later is the second, that is, the second special symbol. For each of the cases where the symbol is a variable display target, a determination value for big hit and a determination value for small hit are set. The numerical value described in FIG. 19A is the hit determination value.

  As shown in FIG. 19 (a), when the special symbol pointer is the first, the determination value corresponding to the big hit is set, but the determination value corresponding to the big hit is not set. When the first special symbol is subject to variable display, only the big win can be won, and no small win is generated.

  When the special symbol pointer is second, the same determination value as that when the special symbol pointer is first is set as the determination value corresponding to the big hit, and the second special symbol is variably displayed. Even if it is a target, a big hit (sixth big hit; so-called direct hit big hit) will occur with the same probability as when the first special symbol is subject to variable display, and other than the judgment value corresponding to these big hits Since all the judgment values are set as judgment values corresponding to the small hits, when the second special symbol is subject to variable display, there is no losing and all but the big hits are won for the small hits. It is like that.

  That is, the CPU 106 extracts the count value of the random number circuit 503 at a predetermined time and uses the extracted value as the value of the random number for random determination (random 0). If it matches any one of the hit determination values corresponding to the jackpot shown in FIG. Further, if the hit determination random number (random 0) matches any hit determination value corresponding to the small hit shown in FIG. 19A, the special symbol is set to the small hit (small hits 1 to 5 described later). To decide. Note that the “probability” shown in FIG. 19A indicates the probability (ratio) of being a big hit and the probability (ratio) of being a big hit. Further, deciding whether or not to win a jackpot means deciding whether or not to shift to the jackpot gaming state, but the stop symbol in the first special symbol display 8a or the second special symbol display 8b is determined. It also means deciding whether or not to make a jackpot symbol. Further, determining whether or not to make a small hit means determining whether or not to shift to the small hit gaming state, but stopping in the first special symbol display 8a or the second special symbol display 8b. It also means determining whether or not the symbol is to be a small hit symbol.

  FIGS. 19B and 19C are explanatory diagrams showing a jackpot type determination table (for the first special symbol) and a jackpot type determination table (for the second special symbol) stored in the ROM 54. Among these, FIG. 19 (b) determines the jackpot type using the holding memory based on the fact that the game ball has won the first start winning opening 13a (that is, when the variable display of the first special symbol is performed). Table. FIG. 19 (c) shows a case where the jackpot type is determined by using the stored memory based on the fact that the game ball has won the second start winning opening (that is, when the second special symbol is displayed in a variable manner). It is a table.

  The big hit type determination table indicates that when the variable display result is determined to be a big hit symbol, the big hit type is selected from the first big hit to the sixth big hit based on a random number (random 1) for the hit type determination. It is a table that is referred to in order to determine any of the above. In this embodiment, as shown in FIGS. 19B and 19C, the big hit type determination table (for the first special symbol) includes five types of big hits from the first big hit to the fifth big hit. On the other hand, in the big hit type determination table (for the second special symbol), only one type of big hit for the sixth big hit is provided. That is, the big hit that occurs when the first special symbol is displayed is one of five types of big hits from the first big hit to the fifth big hit, while the second special symbol is displayed in a variable manner. The only big hit that occurs when the player is hit is the sixth big hit.

  In the big hit type determination table (for the first special symbol), for each of the first big hit to the fifth big hit, the determination value of the random number for random hit type (random 1) and the fixed special symbol ("1" to "5") ) Data, round number (15R) data, and data indicating whether to enter the normal gaming state or the short time (advantageous) state after big hit depending on whether the advantageous state flag is off or on ing.

  Also, in the normal gaming state in which the advantageous state flag is in the off state (not set), only when the third and fifth big hits are made, the short time (advantageous) state is set after the big hit, The 2,4 big hits are in the normal gaming state, and in the advantageous state where the advantageous state flag is on (set state), only the second big hit is in the normal gaming state, all other big hits are The time is shortened (advantageous).

  The number of determination values in the present embodiment is 60 for all the first to fifth jackpots, and the occurrence probability is the same, but the present invention is not limited to this, and the number of determination values is as follows: What is necessary is just to set suitably in consideration of game property.

  Thus, in the first special figure game, in the normal game state, the ratio of winning the first, second, and fourth jackpots controlled to the normal game state after the end of the jackpot game state is 3/5. The ratio of winning the third and fifth jackpots controlled to the advantageous state after the end is 2/5. On the other hand, in the advantageous state, the ratio of winning the second big hit which is controlled to the normal gaming state after the end of the big hit gaming state is 1/5, and the first, third, third which is controlled to the advantageous state after the big hit gaming state is finished. The winning ratio for winning 4 or 5 is 4/5. Therefore, after the big hit in the advantageous state is finished, the advantageous state is controlled to the advantageous state at a higher rate (4/5) than after the big hit in the normal gaming state (1/5). Is more advantageous for the player.

  In the big hit type determination table (for the second special symbol), for the sixth big hit, the determination values “0” to “299” of the random number (random 1) for the hit type determination, the definite special symbol (“7”) data, The number of rounds (15R) data and data indicating the advantageous state are set regardless of whether the advantageous state flag is in the off state or the on state. That is, if the second special symbol is a direct hit big hit, it will be all the sixth big hit, and a big hit game of 15R will be given as the number of rounds, and it will be in an advantageous state after the big hit.

  In this embodiment, when the sixth big hit is made in the second special figure game, even if the gaming state at that time is either the normal gaming state or the advantageous state, the big hit gaming state must be performed. Although it was controlled to the advantageous state, it is controlled to either the normal gaming state or the advantageous state after the big hit gaming state is ended according to the type of gaming state when the sixth big hit is reached. May be. In this case, it is preferable that after the end of the big hit in the advantageous state, the advantageous state is controlled at a higher rate than after the end of the big hit gaming state in the normal gaming state.

  FIG. 19D is an explanatory diagram showing a small hit type determination table (for the second special symbol) stored in the ROM 54. This small hit type determination table (for the second special symbol) uses the holding memory based on the game ball having won the second start winning opening 13b (that is, when the variation display of the second special symbol is performed). It is a table | surface in the case of determining the type of a small hit when the occurrence of a small hit is determined. That is, when it is determined that the small hit type determination table (for the second special symbol) and the variable display result is the small hit symbol, the small hit type is determined based on the random number (random 1) for determining the hit type. It is a table referred to in order to determine a classification in any one of the 1st small hit-the 5th small hit.

  In the small hit type determination table (for the second special symbol), for each of the first small hit to the fifth small hit, a determination value of random number (random 1) for determining the hit type, a fixed special symbol (“1” to “1”) “5”) data, big hit round number data generated when a game ball flows into the specific area 43 by small hit, normal game state after big hit depending on whether the advantageous state flag is off or on Or data indicating whether or not to be advantageous.

  Specifically, for all the small hits, when the seventh big hit that is 15 round number data (actually 14 rounds) is set, the game ball flows into the specific area 43 by the small hit Is a seventh big hit, and 15 rounds (substantially 14 rounds) of big hit games are awarded.

  Further, in the normal gaming state in which the advantageous state flag is in the off state (the state where it is not set), when the third small hit and the fourth small hit are made, the time is shortened (advantageous) after the seventh big hit. When the first small hit, the second small hit, and the fifth small hit, the normal gaming state is set after the seventh big hit, and the advantageous state flag is turned on (set state). In the short time (advantageous) state, when the first small hit, the third small hit, the fourth small hit, and the fifth small hit, the short time (advantageous) state is established after the seventh big hit. In the case of a small hit, the game is set to the normal gaming state after the seventh big hit.

  In the present embodiment, the driving control patterns (for example, the driving timing and driving time of the solenoid 18) of the foot model 402 in the first to fifth small hits are all the same, and the game ball to the specific area 43 is the same. The ease of winning is set to be the same, but the driving control pattern of the foot model 402 (for example, the driving timing and driving time of the solenoid 18) is changed according to the type of the small hit, and the game to the specific area 43 The ease of winning the ball may be different.

  In the second special game, in the normal gaming state, the winning ratio for the first, second and fifth small jacks controlled to the normal gaming state after the end of the big hit gaming state is 3/5, and after the big hit gaming state ends The winning ratio per 3rd and 4th small controlled to the advantageous state is 2/5. On the other hand, in the advantageous gaming state, the ratio of winning the second small hit, which is controlled to the normal gaming state after the end of the big hit gaming state, is 1/5. The winning percentage per 3, 4, 5 small is 4/5. Therefore, after the end of the big hit in the advantageous state, the small hit which is controlled to the advantageous state after the end of the big hit gaming state at a higher rate (4/5) than after the end of the big hit in the normal gaming state (1/5) Is won, the advantageous state is more advantageous to the player than the normal gaming state.

  In addition, after the end of the jackpot in the advantageous state in the second special figure game, at a higher rate (4/5) than after the jackpot in the normal game state in the first special figure game (2/5), After winning the big hit gaming state, the small hit that is controlled to the advantageous state is won, so it is highly likely that the big hit will be again after the advantageous state ends, and also likely to become the advantageous state even after the end of the big hit gaming state That is, since the continuation rate of the advantageous state is high, it can be expected that the big hits are continuously generated.

  In this embodiment, in the second special game in the normal gaming state, the third and fourth small hits controlled to be in an advantageous state after the end of the big hit may be won, but the second in the normal gaming state may be won. In the special figure game, any small hit may be controlled to the normal gaming state after the big hit ends.

  In the advantageous state, the second special game is 100 times, that is, there is 100 chances to be in the small hit game state. Actually, the game ball does not necessarily enter due to a harmful nail or a hit ball, but the 100 game In addition, an opening / closing operation control pattern of the upper big prize opening door 24c and a driving operation control pattern of the foot model 402 are set and an obstacle nail is arranged so as to be a big hit within.

  In the present embodiment, when the special figure game is executed 100 times in the advantageous state, the maximum number of the second reserved memory numbers may be stored, so that even after the advantageous state ends. If the second reserved memory number has a reserved memory at that time, the second special game based on the reserved memory is executed, and therefore, when controlled to the advantageous state, there are 104 chances at maximum.

  That is, the advantageous state ends when the second special figure game of the 100th time is finished without a big hit in the advantageous state, but when the second reserved memory number is 1 or more at this time, the second reserved memory number Minutes of the second special figure game is executed after the advantageous state ends. However, since the advantageous state ends, the number of reserved memories hardly increases during the execution period of the second special figure game based on one reserved memory.

  In this embodiment, small hits are generated only for the second special symbol. However, the present invention is not limited to this, and small hits are also generated for the first special symbol. In addition, by making the advantageous state after the small hit according to the type of occurrence of the small hit, it may be possible to suddenly enter the advantageous state without making a big hit.

FIG. 20 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 20, a payout control signal (a connection signal in this example) transmitted to the payout control board 37 is output from the output port 0. In addition, a solenoid (large winning port door solenoid) 21 for opening and closing the special variable winning ball device 20 for opening and closing the lower big winning port 23b, and a solenoid (normal electric accessory solenoid) for opening and closing the variable winning ball device 15 The drive signal for 16 is also output from output port 0.

  Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 20 may be used. In particular, for the connection signal, the main board 31 and the payout control board. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  Then, from the output port 1 to the external device (for example, hall computer) via the terminal board 160, a seed information output signal, that is, information related to the control (for example, start port signal, symbol determination number 1 signal, jackpot 1 signal, 2 jackpots, 3 jackpots, short time signal, security signal) are output. In this embodiment, a prize ball signal 1 (a signal that is output every time one prize ball payout is detected) or a gaming machine error status signal (a gaming machine is in an error status (in this example, a ball is out of ball). An error state or a full tank error state) is also output to the external device via the terminal board 160. In this case, on the payout control board 37 side, a prize ball payout or an error state of the gaming machine is detected, and a prize ball signal 1 or a gaming machine error state signal is input to the main board 31. The prize ball signal 1 and the gaming machine error status signal input to the main board 31 are output via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. Is done. The prize ball signal 1 and the gaming machine error state signal input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the gaming control microcomputer 560.

  In addition, since the pachinko gaming machine 1 in this embodiment has two start winning ports, a first start winning port 13a and a second start winning port 13b, a game ball wins the first start winning port 13a. The start port 1 signal for notifying that the game ball has been won and the start port 2 signal for notifying that the game ball has won the second start winning port 13b are individually output to the outside via the terminal board 160. You may do it.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, a door opening signal indicating that the game frame is in an open state and prize ball information output every time ten prize balls are paid out are also output to an external device via the terminal board 160. May be. In this case, on the payout control board 37 side, it is detected that the game frame is in the open state and the payout of the winning ball is detected, and a door opening signal and winning ball information are input to the main board 31. The door opening signal and prize ball information input to the main board 31 are output to the outside via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. However, it is assumed that the door opening signal and the prize ball information are branched on the main board 31 and input to the game control microcomputer 560. In this case as well, the door opening signal and prize ball information input to the main board 31 may be output to the outside via the terminal board 160 after passing through the game control microcomputer 560 once. .

  In addition, for example, the gaming machine has two start winning ports, a first start winning port and a second starting winning port, and is configured to be capable of variably displaying two special symbols, a first special symbol and a second special symbol. If it is, a start port 1 signal for notifying that the game ball has won the first start winning port 13a and a start port for notifying that the game ball has won the second start winning port 13b. 2 signals are individually output via the terminal board 160, and the symbol determination number 2 signal in addition to the symbol determination frequency 1 signal as a symbol determination frequency signal for notifying the number of times the special symbol fluctuates You may make it output externally via the board | substrate 160. FIG. In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 21 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 21, bits 1 to 7 of input port 0 (bit 0 is not used) are gate switch 32a, winning port switches 30a and 30b, magnet sensor signal 1, magnet sensor signal 2, and door open, respectively. Signals and prize ball information are input. In this embodiment, two magnet sensors (not shown) for detecting fraud using a magnet are provided, and detection signals from the respective magnet sensors are also input from the input port 0. . Also, the detection signal of the first start port switch 14a is input to bit 0 of the input port 1, and the detection signal of the first winning confirmation switch 14b is input to bit 1 of the input port 1, The detection signal of the second start port switch 15 a is input to bit 2, the detection signal of the second winning confirmation switch 15 b is input to bit 3 of the input port 1, and the lower signal is input to bit 4 of the input port 1 The detection signal of the count switch 23 is input, the detection signal of the third winning confirmation switch 23 a is input to bit 5 of the input port 1, and the detection signal of the upper count switch 24 is input to bit 6 of the input port 1. Then, the detection signal of the fourth winning confirmation switch 24 a is input to bit 7 of the input port 1. In addition, a power-off signal and a clear switch detection signal are input to bits 0 and 1 (bits 2 to 7 are not used) of the input port 2.

  FIG. 22 is a circuit diagram showing the internal configuration of the terminal board 160. In the terminal board 160 shown in FIG. 22, the upper left connector CN-1 is a connector for connecting a cable for transmitting a signal from the main board 31, and the lower left connector CN-2 is a payout control board 37. This is a connector for connecting a cable for transmitting a signal from the main board 31 via the main board 31. The right connectors CN1 to CN9 are connectors for connecting cables that transmit signals to external devices such as hall computers. The terminal board 160 is mounted with semiconductor relays (PhotoMOS relays) PC1 to PC9 as driver circuits.

  When the cable from the main board 31 is connected to the connector CN-1, various signals are input from the main board 31 (game control microcomputer 560) to the terminal board 160. Specifically, the start port signal is input to the terminal “2” of the connector CN-1, the symbol determination number 1 signal is input to the terminal “3” of the connector CN-1, and the terminal “5” of the connector CN-1 is input. 1 jackpot signal is input, 2 jackpot signals are input to terminal “6” of connector CN-1, 3 jackpot signals are input to terminal “7” of connector CN-1, and terminal “8” of connector CN-1 is input. The time reduction signal is input to “”, and the security signal is input to the terminal “9” of the connector CN-1.

  In addition, when the cable from the payout control board 37 is connected to the connector CN-2 via the main board 31, various signals from the payout control board 37 (the payout control microcomputer 370) are input to the terminal board 160. Is done. Specifically, the prize ball signal 1 is input to the terminal “2” of the connector CN-2, and the gaming machine error state signal is input to the terminal “3” of the connector CN-2.

  As shown in FIG. 22, in the terminal board 160, the signal line of the reference potential is connected to the terminal “1” of the connector CN-1 and the connector CN-2, and the signal line branches to each of the semiconductor relays PC1 to PC1. It is connected to the input terminal “1” of the PC 9. Further, the signal lines connected to the terminals “2”, “3”, “5” to “9” of the connector CN-1 and the connectors “2” and “3” of the connector CN-2 are 1 KΩ resistances, respectively. It is connected to the input terminals “2” of the semiconductor relays PC1 to PC9 via R1 to R9. The signal lines connected to the output terminals “4” of the semiconductor relays PC1 to PC9 are connected to the terminals “1” of the connectors CN1 to CN9, respectively. The signal lines connected to the output terminals “3” of the semiconductor relays PC1 to PC9 are connected to the terminals “2” of the connectors CN1 to CN9, respectively.

  In the semiconductor relays PC1 to PC9, when a signal current flows through the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is applied to the photoelectric element (solar cell) provided opposite to the LED through the transparent silicon. The photoelectric element that has received the light is exchanged for voltage according to the amount of light, and this voltage passes through the control circuit to charge the MOSFET gate of the output section. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive and turns on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the gate load of the MOSFET is rapidly discharged by the control circuit. With this control circuit, the MOSFET is turned off and the load is turned off.

  By the operation of the semiconductor relays PC1 to PC9 as described above, the signals input from the connectors CN-1 and CN-2 on the input side are transmitted to the connectors CN1 to CN9 on the output side to the external device such as a hall computer. Is output. Specifically, the start signal is output from the connector CN1, the symbol determination number 1 signal is output from the connector CN2, the jackpot signal is output from the connector CN3, the jackpot signal is output from the connector CN4, and the connector CN5 is output. Three jackpot signals are output, a time reduction signal is output from the connector CN6, a security signal is output from the connector CN7, a prize ball signal 1 is output from the connector CN8, and a gaming machine error state signal is output from the connector CN9. The assignment of connectors to each external output signal on terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the end connector (for example, connector CN9) provided on the terminal board 160. Further, the gaming machine error status signal does not necessarily have to be output to the outside of the pachinko gaming machine 1. For example, from the connector CN9, a door opening indicating that the gaming frame is in an opened state instead of the gaming machine error status signal is opened. A signal or the like may be output.

  The security signal output from the connector CN7 is a signal indicating the security state of the gaming machine. Specifically, as described later, the detection result of the first start opening switch 14a and the detection result of the first winning confirmation switch 14b, the detection result of the second start opening switch 15a and the detection result of the second winning confirmation switch 15b, Based on the detection result of the lower count switch 23 and the detection result of the third winning confirmation switch 23a, the detection result of the upper count switch 24 and the detection result of the fourth winning confirmation switch 24a, respectively, the first start winning opening 13a and the second start A security signal is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes) when it is determined that an abnormal winning has occurred in the winning opening 13b, the lower winning opening 23b, or the upper winning opening 24b. . With such a configuration, the number of winnings at the first starting winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b using radio waves or the like is larger than the actual number of winnings. It is possible to make it possible for an external device such as a hall computer to recognize that an illegal act that causes the user to be recognized.

  In this embodiment, even when the gaming machine is turned on and the initialization process is executed, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds). . By configuring as such, it is recognized that the initialization process has been executed at an unnatural timing (for example, even after all the gaming machine power reset operations have been completed when the amusement store is opened). By making it possible, the external device such as a hall computer can recognize the possibility that an unauthorized act of illegally resetting the power of the gaming machine and aiming for a big hit at the power reset timing is performed. it can.

  In this embodiment, as described above, when the abnormal winning is detected and the initialization process (for example, the operation of the clear switch is performed when the power to the gaming machine is turned on) A common security signal is output from the common connector CN7 of the terminal board 160 to the outside when the process (such as clearing the stored contents) is executed. This is because the initialization process is usually performed only when the game machine power is reset when the amusement store is opened, so the terminal is used for a signal that is output only once a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, a signal for external output is configured by outputting a security signal from the common connector CN7 when an abnormal winning is detected and when an initialization process is executed. The waste of lines and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and complication of wiring work.

  The signal output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only abnormal winning to the first starting winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, the upper large winning opening 24b, but abnormal winning to the normal winning openings 29a to 29d is detected, You may comprise so that it can output externally as a security signal from the common connector CN7 of the terminal board 160. FIG. In this case, for example, as for the first prize winning opening 13a, the second starting prize winning opening 13b, the lower major prize winning opening 23b, and the upper major prize winning opening 24b, the winning of the game ball is also detected for the normal winning prize winning holes 29a to 29d. Two types of switches (proximity switches and photosensors) having different detection methods are provided as switches for the first start winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b. The presence / absence of an abnormal prize may be determined according to a similar determination method.

  Further, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, a security signal is output from the common connector CN7 of the terminal board 160. You may comprise so that external output is possible. In addition, for example, when an abnormality of various switches provided in the gaming machine is detected (for example, when occurrence of a short circuit is detected by determining that the input value has exceeded the threshold value), a common terminal board 160 is used. The connector CN7 may be configured so that it can be output externally as a security signal.

  As described above, an abnormal winning, abnormal magnetic error, and abnormal radio wave error at the lower special winning opening 23b and the upper special winning opening 24b can be externally output as a security signal from the common connector CN7 of the terminal board 160. For example, if only one signal line is connected, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  When detecting an abnormal winning at the lower big prize opening 23b, the number detected by the lower count switch 23 and the number detected by the third winning confirmation switch 23a are equal to or greater than a predetermined value (for example, 20). In addition to the case where the determination is based on the case, the value of the special symbol process flag is not a value indicating that a big hit game is being played (for example, the value of the special symbol process flag is not 4 or more. FIG. 65). Also, when a game ball is detected by the lower count switch 23, it may be determined that an abnormal winning to the lower big prize opening 23b has occurred. In addition, even when it is determined that an abnormal winning to the lower special winning opening 23b has occurred based on the value of the special symbol process flag as described above, the security signal information timer is similar to the step S127 in the switch normal / abnormal check processing. A security signal may be output to the outside by setting a predetermined time (for example, 4 minutes) to.

  In addition, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the security signal can be externally output from the common connector CN7 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN7 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN7 of the terminal board 160.

  In addition to the signal line and connector CN7 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  In addition to the signal line for security signal output, detection of execution of initialization processing and abnormal winning to the first starting winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b. Detection, abnormal magnetic error detection, abnormal radio wave error detection, and communication error detection are provided with separate signal lines, respectively, and an external output signal corresponding to each error is also sent from the terminal board 160 together with the security signal. Alternatively, the data may be output to an external device such as a hall computer. With such a configuration, it is possible to recognize that an error has occurred by checking the security signal, and further, by checking the signal output for each type of error, the type of error can be determined on the amusement store side. Can be confirmed. Therefore, when an amusement store requires a confirmation of the type of error, an external output signal for each error type is provided separately from the security signal, so that an external output that better meets the needs of the amusement store can be provided. Can be done. On the other hand, in the case of a game shop that only requests confirmation that some kind of error has occurred, only the security signal out of the externally output signals is connected to an external device such as a hall computer. Check it.

  As described above, by providing the semiconductor relays PC1 to PC9 on the terminal board 160, signal input from the outside to the inside of the gaming machine can be prevented, and as a result, illegal acts can be reliably prevented. In the above example, the semiconductor relays PC1 to PC9 are provided on the terminal board 160. However, other relay elements such as mechanical relays may be used instead of the semiconductor relays PC1 to PC9.

Next, winning (entry) to each winning device and each winning opening constituting the first starting winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, the upper large winning opening 24b, and the normal winning openings 29a to 29d. The structure of the game ball passage through which the game balls flow down will be described with reference to FIG. 25A is a rear view showing various winning paths provided in the game board, and FIG. 25B is a view showing the vicinity of the outlets of the second winning path and the upper grand prize path, and FIG. FIG. 6 is a view showing the vicinity of the discharge opening of the first winning passage, and FIG. 6D is a view showing the vicinity of the discharge opening of the lower large winning passage.

  As shown in FIG. 25 (a), the game board 6 is provided with a first opening 451 to which the variable winning device 400 for forming the upper big winning opening 24b is attached and a winning device for forming the first start winning opening 13a. The second opening 452, the third opening 453 to which the variable winning ball device 15 that forms the second starting winning hole 13b is attached, and the fourth opening to which the special variable winning ball device 20 that forms the lower big winning port 23b is attached. 454, a fifth opening 455 to which the decorative member 25 provided with the decorative lamp 25a is attached, and a sixth opening 456 constituting the out port 26 are formed.

  From the lower back of the variable winning device 400 attached to the first opening 451 from the front side, the game ball guided to the back of the game board 6 flows down after winning the upper large winning opening 24b of the variable winning device 400. An upper prize winning passage 1309 is extended downward. The upper prize winning passage 1309 is formed in a cylindrical shape by a transparent synthetic resin material (not shown in detail), and is distributed to the lower stage 407 from the upper spherical path 406 at the upper end portion and detected by the specific area switch 43a. A game ball guided to the back side of the game board 6 and a game ball distributed to the lower ball path 408 from the upper ball path 406 and guided to the back side of the game board 6 without being detected by the specific area switch 43a. And a receiving port 1309a is formed.

  The upper grand prize winning passage 1309 is bent to the left side when the game board 6 is viewed from the rear side below the receiving port 1309a, and then bent downward and dropped again. A discharge port switch 45 is provided at the lower part of the receiving port 1309a, and a game ball won in the upper big winning port 24b is detected by the discharge port switch 45 and then discharged from the discharge port 1454 (see FIG. 25B). It is discharged and discharged into a collection basket 1500 described later.

  A first winning path 1306a through which a game ball that has won a prize at the first starting winning opening 13a flows down from the lower back of the starting winning unit having the first starting winning opening 13a attached to the second opening 452 from the front side. It is extended toward. The first winning path 1306a is formed in a cylindrical shape from a transparent synthetic resin material (not shown in detail), and is suspended downward from the second opening 452. In addition, on the back surface of the special variable winning ball apparatus 20 disposed below the first start winning opening 13a, a first winning path 1306b disposed immediately below the first winning path 1306a extends downward. The first winning path 1306a, 1306b constitutes a first winning path.

  A first start opening switch 14a is provided in the upstream first winning passage 1306a, and a first winning confirmation switch 14b is provided in the downstream first winning passage 1306b to win the first start winning opening 13a. The game ball is detected by the first start port switch 14a and the first winning confirmation switch 14b disposed downstream thereof, and then released from the discharge port 1452 and discharged into a collection basket 1500 described later.

  From the lower back of the variable winning ball apparatus 15 attached to the third opening 453 from the front side, a second winning path 1307 through which a game ball that has won a prize at the second start winning opening 13b flows downward is extended downward. Yes. Although not shown in detail, the second winning path 1307 is formed in a cylindrical shape by a transparent synthetic resin material, and is suspended downward from the third opening 453, and then left when the game board 6 is viewed from the back. And bent downward again and suspended.

  A second start opening switch 15a is provided in the upper vertical portion of the second winning passage 1307, and a second winning confirmation switch 15b is provided in the lower vertical portion, so that the game ball won in the second start winning opening 13b. Is detected by the second start port switch 15a and the second winning confirmation switch 15b arranged downstream thereof, and then discharged from the discharge port 1453 (see FIG. 25 (b)), and inside the collection basket 1500 described later. To be discharged.

  From the lower back side of the special variable winning ball apparatus 20 attached to the fourth opening 454 from the front side, a lower big prize passage 1308 is provided extending downwards for a game ball that has flowed into the lower big prize opening 23b to flow down. Yes. Although not shown in detail in detail, the lower prize winning passage 1308 is formed in a cylindrical shape by a transparent synthetic resin material, and is suspended downward from the fourth opening 454.

  The lower prize winning passage 1308 is provided with a third prize confirmation switch 23a, and a game ball that has won a prize passage provided in the special variable prize winning ball device 20 from the lower prize winning opening 23b is placed on the game board 6 from the back. After being guided to the right side and being detected by the lower count switch 23, it is guided to the back side of the game board 6 and flows into the lower big prize passage 1308, and is then provided in the lower big prize passage 1308. After being detected by the 3-winning confirmation switch 23a, it is discharged from the discharge port 1455 (see FIG. 25 (d)) and discharged into a collection basket 1500 described later.

  From the back of the decorative members 25, 25 provided with decorative lamps 25a attached to the left and right fifth openings 455, 455 from the front side, a winning path 1450 and a winning opening through which the game balls won in the winning holes 29a, 29b flow down. A winning path 1451 through which game balls that have won 29c and 29d flow down is extended downward. Although not shown in detail, the winning paths 1450 and 1451 are formed in a cylindrical shape from a transparent synthetic resin material, and are suspended downward from the back surfaces of the decorative members 25 and 25.

  The winning passages 1450 and 1451 are provided with winning opening switches 30a and 30b, respectively, and the game balls that have won the winning openings 29a and 29b are detected by the winning opening switch 30a and then discharged from the discharge opening 1457 to be described later. It is discharged into the tub 1500. Further, the game balls won in the winning openings 29c and 29d are detected by the winning opening switch 30b, and then released from the discharge opening 1458 and discharged into a collection basket 1500 described later.

  In addition, as shown in FIGS. 25B, 25C, and 25D, the game balls that have dropped in the vertical direction are discharged to the lower positions of the discharge ports 1452 to 1455 of the winning paths 1306b, 1307, 1308, and 1309. Discharge direction changing surfaces 1460 to 1463 for changing the direction to the left diagonally downward and right diagonally downward directions are respectively provided.

  A game ball released from each of the discharge ports 1452 to 1455 falls into a collection basket 1500 provided in a game frame (not shown) of the game machine, and is finally discharged from the game machine and is not shown. It is collected in the collection path. The recovery basket 1500 is formed in a funnel shape, and a bottom surface 1501 as a recovery path surface is formed in an inclined surface shape that is inclined downward toward the central discharge path 1502, and is discharged from each of the discharge ports 1452 to 1455. The game ball is guided toward the discharge path 1502 and discharged.

  In a state in which the game board 6 is attached to the game frame, the bottom ball 1501 is disposed in the left-right direction directly below each of the outlets 1452 to 1455, so that the game ball released from the outlets 1452 to 1455 and dropped on the bottom surface 1501. Is expected to jump, but since each of the outlets 1452 to 1455 is provided with a discharge direction changing surface 1460 to 1463, the first winning confirmation switch 14b, the second winning confirmation switch 15b, and the third winning confirmation The game balls that have passed through the switch 23a and the fourth winning confirmation switch 24a are not released in the vertical direction. In other words, it is possible to prevent the game ball falling on the bottom surface 1501 from jumping and being detected again by the first winning confirmation switch 14b, the second winning confirmation switch 15b, the third winning confirmation switch 23a, and the fourth winning confirmation switch 24a. The

  The fourth winning confirmation switch 24a is provided in the variable winning device 400, and each of the winning passages 407, 408, and 1309 from the fourth winning confirmation switch 24a to the discharge port 1454 is provided with a plurality of bent portions. Therefore, even if the game ball released from the discharge port 1454 and falling on the bottom surface 1501 jumps, backflow is prevented at the bent portion, so that the game ball that has passed through the fourth winning confirmation switch 24a is detected again. There is nothing.

  In particular, as shown in FIG. 24, a fourth winning confirmation switch 24a is provided in the vertical portion of the upper ball path 406, and the upper ball path 406 is a bent formed at a position below the fourth winning confirmation switch 24a. It extends so as to incline downward from the portion toward the front side, and communicates with the lower stage 407. That is, the game ball that has passed through the fourth winning confirmation switch 24a is not detected again by the fourth winning confirmation switch 24a.

  As described above, in the present embodiment, the start winning unit having the first start winning opening 13a and the special variable winning ball device 20 are arranged close to each other in the lower part of the game area 7, The display area of the effect display device 9 provided in the game area 7 and the arrangement space for the accessory and decoration member arranged on the right side of the display area 9 can be secured over a wide range, thereby producing effects in the limited game area 7 It is possible to enlarge the display unit, the accessory, the decorative member, and the like of the display device 9 as much as possible.

  A first start winning opening 13a is arranged close to the upper part of the special variable winning ball apparatus 20, and the first winning paths 1306a and 1306b through which the game balls won from the first starting winning opening 13a pass are the first. A first start port switch 14a as detection means and a first winning confirmation switch 14b as second detection means are attached. However, if the first winning passages 1306a and 1306b are shortened, the first start port switch 14a and the first winning prize switch are installed. It is difficult to dispose the confirmation switch 14b at a predetermined distance. Therefore, the downstream first winning path 1306b is provided on the back surface of the special variable winning ball apparatus 20, and the first winning confirmation switch 14b is attached to the first winning path 1306b without being limited to the first winning path 1306b. Since the start winning unit that forms the first start winning opening 13a and the special variable winning ball apparatus 20 can be arranged with the smallest possible interval, the display unit of the effect display device 9 provided in the game area 7 and the right side thereof It is possible to ensure a wide range of arrangement space for the accessory and the decorative member arranged in the above.

  In this embodiment, the electromagnetic second start opening switch 15a and the optical second winning confirmation are detected in the second winning passage 1307 through which the game ball won from the second starting winning opening 13b passes. By attaching the switch 15b, the game ball can be normally detected without being affected by fraudulent acts caused by radio waves or light, so that the second special figure game is illegally executed in addition to illegally paying out a prize ball. Thus, illegal actions such as illegally opening the upper big prize opening 24b of the variable prize-winning device 400 can be prevented by generating many small hits.

The upper ball path 406 in which the upper count switch 24 and the fourth winning confirmation switch 24a are provided is not particularly shown in detail, but is disposed at a deeper position on the back side than the lower stage 407 and the like in the variable winning device 400. Has been. More specifically, the upper ball path 406 is disposed inside the variable winning device 400 that opens to the front side, but the variable winning device 400 is fitted to the opening formed in the game board 6 from the front side. Thus, the upper sphere path 406 is disposed substantially on the back side with respect to the back side of the game board 6. Therefore, like the other switches 14a, 14b, 15a, 15b, 23, 23a, etc. provided on the back of the gaming board 6, the upper count switch 24 and the fourth winning confirmation switch 24a are easily provided from the front side of the gaming machine. Since it is arranged at a position where it is difficult to access, it is possible to make the illegal act in the variable winning device 400 opened to the front side as difficult as possible.

  Further, in this embodiment, the first special symbol display 8a starts the variable display of the first special symbol based on the winning of the game ball in the first starting winning port 13a, and the second starting winning port 13b. The second special symbol display unit 8b starts to display the variation of the second special symbol based on the winning of the game ball in the first, but the first starting winning port 13a or the second starting winning port 13b. Based on the winning of a game ball, the special symbol display may be started with one special symbol display. That is, you may provide two or more start winning openings corresponding to a single special symbol display.

  Further, in the present embodiment, the second special figure game is easily executed by winning the third big hit or the fifth big hit in the first special figure game and shifting to the advantageous state after the big hit state ends. The variable winning device 400 was opened by winning the small win in this second special figure game, but it is executed on the basis that the game ball has won the predetermined start winning opening provided in the game area 7. It is not limited to the one in which the variable winning device 400 is opened by winning the small win in the special figure game. For example, in the normal game state, the game ball is detected by the gate switch 32a and the variable symbol is displayed in a variable manner. The variable prize-winning device 400 may be opened when it is started and hits the usual figure. Furthermore, the variable winning device 400 may be opened without making a small hit determination in a special game by winning a game ball at a predetermined start winning opening provided in the game area 7.

  Next, the operation of the gaming machine will be described. FIG. 26 is a flowchart showing main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output is impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed when the power is turned on, not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15. In addition, after setting in step S93, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above.

  Further, the CPU 56 sets the head address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  The CPU 56 sets a predetermined time (in this example, 30 seconds) in the security signal information timer (step S14a). The security signal information timer is a timer for measuring the ON time of the security signal output from the terminal board 160. In this embodiment, an initialization process is performed when the gaming machine is turned on by executing an information output process (see S31), which will be described later, based on the fact that a predetermined time is set in the security signal information timer in step S14a. Is executed, a security signal is externally output for a predetermined time (in this example, 30 seconds).

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs settings in accordance with the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 in accordance with the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of the interrupt process by executing the process according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs initialization according to the interrupt processing priority table so as to preferentially execute an interrupt process whose cause is the occurrence of a communication error in the serial communication circuit 505. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15 to S15b, a part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also executed in the process of step S5. For example, in step S5, an initial value is set in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  For example, in setting the internal device register, the CPU 56 sets the baud rate of the serial communication circuit 505. In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  For example, the CPU 56 sets the data format of data transmitted and received by the serial communication circuit 505. In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the presence / absence of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  Further, for example, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505. In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the game control microcomputer 560 stores in advance a designation information for designating values of each bit of the control register B 708 and the control register C 709 set by a user (for example, a manufacturer of the gaming machine) in a predetermined storage area of the ROM 54. I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  In the initialization process of the main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. Note that the process of setting the initial value to the prize ball number counter may be executed, for example, in the process of sequentially setting each initial value in the work area of steps S92 and S12, until the process proceeds to steps S15 to S17. It only has to be executed during

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the first special symbol display 8a and the second special symbol display 8b. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same process is executed in steps S26 and S27 of the interrupt process), so as to avoid conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process or reception Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

Next, the timer interrupt process will be described. FIG. 27 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Then, the CPU 56 via the input driver circuit 58, the gate switch 32a, the first start opening switch 14a, the first winning confirmation switch 14b, the second starting opening switch 15a, the second winning confirmation switch 15b, the lower count switch 23, Input detection signals of switches such as the third winning confirmation switch 23a, the upper count switch 24, the fourth winning confirmation switch 24a, the specific area switch 43a, the discharge port switch 45, the winning port switches 30a and 30b, and the like. It detects (switch process: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

Next, the CPU 56 performs display control for performing display control of the first special symbol display 8a, the second special symbol display 8b, the normal symbol display device 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41. Processing is executed (step S22). About the 1st special symbol display 8a, the 2nd special symbol display 8b, and the normal symbol display apparatus 10, a drive signal is output with respect to each indicator according to the content of the output buffer set by step S36, S37. Execute control.

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating a random number for determination such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the effect symbol synchronized with the variation of the special symbol in the transmission data register of the serial communication circuit 505 and sending the effect control command (effect symbol command control process: step S30). . It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 performs an information output process for outputting data such as a start port signal supplied to the hall management computer, a symbol determination number 1 signal, a jackpot 1 to 3 signal, a time reduction signal, a security signal, and the like (step S31). ).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, detection of the winning opening switches 30a, 30b, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switches 30a, 30b being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). Further, in this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs frame state output processing for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to display the error state of the gaming machine to the production control microcomputer 100. Execute (Step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

  Next, the prize ball process (step S32) in the main process will be described. First, payout control signals (connection signals, prize ball information) and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described.

FIG. 28 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 28, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. This is a signal (connection signal for the main board 31). The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, payout controlled via the input circuit 373A and I / O ports 372e payout control microcomputer 370 To the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, in step S34). Although it is output by processing, it may be output at the timing of step S4). The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time one prize ball has been detected on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game is played via the input circuit 67B and the I / O port unit 57 of the game control microcomputer 560. The data is input to the control microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 29 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined contents depending on the contents of the set 8-bit data.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with respect to “xxxx” in the second byte of the connection OK command, as shown in FIG. 30, a prize ball error (a prize ball payout operation based on winning or a ball rental payout operation based on a ball rental request cannot be performed normally). An abnormal state that has become a state: Specifically, when the main control unconnected error shown in FIG. 94, the dispensing switch abnormality detection error 1, the dispensing switch abnormality detection error 2, the dispensing case error, or the main control communication error) occurs. In this case, “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified. In the example shown in FIG. 30, the connection OK command shows a case where a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) is set as a control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, when a game ball is detected by the first start port switch 14a and the second start port switch 15a, three prize balls are paid out, and the game ball is detected by one of the winning port switches 30a and 30b. Then, 10 prize balls are paid out. When a game ball is detected by the lower count switch 23 and the upper count switch 24, 15 prize balls are paid out. Therefore, when a game ball is detected by the first start port switch 14a and the second start port switch 15a, a prize ball number command “01010011” for notifying three prize balls is transmitted, and the prize opening switches 30a, 30a, When a game ball is detected in any of 30b, a prize ball number command “01011010” for notifying 10 prize balls is transmitted, and a game ball is detected by the lower count switch 23 and the upper count switch 24. In this case, a prize ball number command “0101111” for notifying 15 prize balls is transmitted. In this embodiment, a game ball is detected by the lower count switch 23 and the upper count switch 24, so that fewer than 15 (for example, 3 or 5) prize balls are paid out. Also good.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball quantity command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball quantity command. It is a control command transmitted as a signal. The content of the prize ball number reception command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The contents of the data of the winning ball preparation command are “4x (H)”, that is, “0100xxxx”. Here, with respect to “xxxx” in the second byte of the command for preparing a prize ball, as shown in FIG. 30, when a prize ball error occurs, “1” is set to “x” in the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. The game control microcomputer 560 can be notified that the operation has not ended, and the contents of the error can also be notified to the game control microcomputer 560. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). Note that the command for preparing a prize ball is not only in a state where an error occurs and the prize ball operation cannot be executed, but also in a state where the prize ball payout operation cannot be started immediately because the ball rental operation is in progress, This command (signal) is output even in the running state (the state in which the payout operation for the number of prize balls specified by the prize ball number command has not been completed). The example shown in FIG. 30 shows a case where a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) is set as a control state in the command for preparing a prize ball. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that the prize ball payout operation or the lending ball payout operation is in the control state in the award ball preparation command, and the game control microcomputer 560. You may make it transmit to.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control commands, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number reception command, a payout end signal is realized by a prize ball end command, and a payout in progress signal is realized by a prize ball preparation command.

  FIG. 31 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 28 and the control command shown in FIG. As shown in FIG. 31, the connection signal is output by the game control microcomputer 560 via the output circuit 67A and input to the payout control microcomputer 370 via the input circuit 373A. The prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and input to the game control microcomputer 560 via the input circuit 67B. A prize ball signal 1 and a gaming machine error state signal, which will be described later, are also output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B. May be. The door opening signal may also be output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B.

Of the control commands, the connection confirmation command and the prize ball number command are output from the serial communication circuit 505 built in the game control microcomputer 560 and input to the serial communication circuit 380 built in the payout control microcomputer 370. The Of the control commands, the connection OK command, the winning ball number acceptance command, the winning ball end command, and the winning ball preparation command are output from the serial communication circuit 380 built in the payout control microcomputer 370, and the gaming control microcomputer 560. Is input to the serial communication circuit 505 incorporated therein. In FIG. 31, two signal lines (signal lines for sending commands from the game control microcomputer 560 to the payout control microcomputer 370 side and payout control microcomputers) are used as signal lines for serial communication. 370 shows a signal line for transmitting a command from 370 to the game control microcomputer 560 side, but actually, the payout control command is transmitted and received through one signal line. A signal line for transmitting a command from the game control microcomputer 560 to the payout control microcomputer 370 side, and a signal line for transmitting a command from the payout control microcomputer 370 to the game control microcomputer 560 side. May be configured as separate signal lines.

  Next, transmission / reception of a payout control command between the game control microcomputer and the payout control microcomputer during normal operation will be described. In this embodiment, a connection confirmation command and a prize ball number command are transmitted from the game control microcomputer 560 to the payout control microcomputer 370, and the payout control microcomputer 370 is connected to the game control microcomputer 560. An OK command, a prize ball number reception command, a prize ball end command, and a prize ball preparation command are transmitted.

  FIG. 32 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 32, the game control microcomputer 560 is connected via the serial communication circuit 505 in order to confirm whether or not the signal line connection with the payout control microcomputer 370 is disconnected. A confirmation command is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives the connection confirmation command via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  FIG. 33 and FIG. 34 are sequence diagrams showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during the prize ball operation. As shown in FIGS. 33 and 34, when a winning occurs and a prize ball payout operation is executed, the game control microcomputer 560 is set with data indicating the number of prize balls via the serial communication circuit 505. The prize ball number command is transmitted to the payout control microcomputer 370. In this case, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the received connection OK command with respect to the previously transmitted connection confirmation command (see FIG. 30), and A winning ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received after the connection OK signal is received until 1 second elapses.

  Next, when the payout control microcomputer 370 receives the award ball number command, if the award ball operation can be executed immediately (that is, if the lending ball is not being dispensed and no error has occurred), the award A prize ball number reception command indicating that the number of balls has been received is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  Next, when the game control microcomputer 560 receives the prize ball end command, as shown in FIG. 33, if the number of prize balls to be paid out is not yet stored, the game ball control command 560 issues a prize ball end command. Transmission of a new connection confirmation command is resumed after 1 s (1 second) has elapsed from the time of reception. On the other hand, as shown in FIG. 34, when the number of prize balls to be paid out has already been stored, a prize ball number command for immediately specifying the next prize ball number is issued without waiting for 1 s (1 second). This is sent to the payout control microcomputer 370. In this case as well, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 30), and The award ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received from the reception of the ball end command until 1 second elapses. Thereafter, transmission and reception of control commands are repeated according to the same sequence.

  FIG. 35 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when the winning ball operation cannot be executed immediately. Even if the payout control microcomputer 370 receives the award ball number command, if the lending ball is being paid out or is in an error state, the award ball number specified by the received award ball number command. Unable to start the prize ball payout operation. In such a case, as shown in FIG. 35, even if the payout control microcomputer 370 receives the award ball number command, it does not immediately transmit the award ball number acceptance command, and the award ball payout operation ends. A command for preparing a prize ball for notifying that the game has not been sent is transmitted to the game control microcomputer 560. In this case, the payout control microcomputer 370 is in a state of preparing a prize ball at regular intervals (every 1 s) unless the payout operation of the lending ball is completed and the award ball action can be started or the error is not canceled. The command is transmitted to the game control microcomputer 560.

  Next, the payout control microcomputer 370 finishes the lending ball payout operation and becomes ready to start the next prize ball operation, or when the error is canceled, the prize indicating that the number of prize balls has been received is received. The ball number acceptance command is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  FIG. 36 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 36, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits the connection confirmation command again after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  If there is a prize when the connection confirmation communication process is not executed (between receiving the connection OK command and transmitting the next connection confirmation command), the game control microcomputer 560 The control for repeatedly transmitting the confirmation command is interrupted, data indicating the number of winning balls is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number acceptance command to the game control microcomputer 560. In this case, the game control microcomputer 560 performs a process of subtracting the prize ball number storage based on the reception of the prize ball number reception command (specifically, 1 is subtracted from a prize ball command output counter described later). (See step S52404). Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command, and when the prize ball payout (prize ball payout operation) is completed, the prize ball end command is sent to the game control microcomputer. Send to computer 560. As described above, when the winning ball payout operation takes a long time, the payout control microcomputer 370 waits for 1 s (1 second) until the winning ball payout operation is completed. Is sent repeatedly. When the game control microcomputer 560 receives the prize ball end command, if the number of prize balls to be paid out is not yet stored, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. To do.

  If there is a prize during the execution of the connection confirmation communication process (between sending the connection confirmation command and receiving the connection OK command), the game control microcomputer 560 and the payout control microcomputer 370 Since the connection state is not confirmed, the award ball number command is not immediately transmitted, but the process waits until the connection OK command can be confirmed. When the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 sets data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and sets the set number of winning balls. The command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number acceptance command to the game control microcomputer 560. Then, the payout control microcomputer 370 performs the same processing, pays out the number of prize balls designated by the prize ball number command, and when the prize ball is paid out (prize ball payout operation), The ball end command is transmitted to the game control microcomputer 560.

  After receiving the winning ball end command, the game control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 30). In addition, even when the start winning prize is received from the reception of the winning ball end command until 1 second elapses, the winning ball number command is transmitted to the payout control microcomputer 370. In other words, in this embodiment, the game control microcomputer 560 receives a prize ball end command from when a connection OK signal in which a value indicating an error is not set until one second elapses. The award ball number command can be transmitted until 1 second has passed.

  FIG. 37 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when an error occurs in the winning ball. As shown in FIG. 37, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. If there is a win when the communication process for confirming the connection is not executed, the game control microcomputer 560 sets the data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and the set winning prize is set. The ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number acceptance command to the game control microcomputer 560. Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command. When executing the payout operation for the number of prize balls specified by the prize ball number command, a predetermined error (for example, an abnormal payout number error, a ball lending, a full tank, or an out of ball error) occurs. When the ball payout operation cannot be performed (abnormal state, error state), the payout control microcomputer 370 issues a prize ball preparing command for notifying that an error has occurred and the prize ball payout operation has not ended. It transmits to the game control microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. When the predetermined error state is canceled (resolved) and the winning ball payout operation ends, the payout control microcomputer 370 transmits a winning ball end command to the game control microcomputer 560. The award ball preparation command is transmitted from the payout control microcomputer 370 to the game control microcomputer 560 every 1 s after the award ball number acceptance command is transmitted. Further, while the game control microcomputer 560 is receiving a command for preparing a prize ball, the game control microcomputer 560 is controlled not to transmit a connection confirmation command. Specifically, the payout control microcomputer 370 outputs a prize ball end command based on the completion of the prize ball payout operation, and the game control microcomputer 560 receives the prize ball end command. Based on this, control is performed so as to return to a state in which a connection confirmation command is output every predetermined period (1S).

  FIG. 38 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during connection confirmation. As shown in FIG. 38, the game control microcomputer 560 has transmitted the connection confirmation command to the payout control microcomputer 370, but has not received the connection OK command from the payout control microcomputer 370, that is, When a connection state abnormality (communication error) occurs, the connection confirmation command is transmitted again after 10 s (10 seconds) have elapsed since the connection confirmation command was transmitted. In other words, if the process of transmitting the connection confirmation command every 1 s (1 second) when the connection OK command cannot be received is continued, the number of connection confirmation command transmissions is increased even though the communication state is unstable. Since it increases in vain, the transmission interval of the connection confirmation command is extended to 10 s (10 seconds), and the control is switched to transmitting the connection confirmation command with the minimum necessary number of transmissions until the communication state is recovered. If a winning occurs when a communication error has occurred, the game control microcomputer 560 will receive a connection OK command from the payout controlling microcomputer 370, even if a new winning occurs. Without transmitting the award ball number command, the connection confirmation command is continuously transmitted at regular intervals (10 s). When the communication error is canceled (resolved) and a connection OK command is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a prize ball number command.

  FIG. 39 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during the award ball number notification. As shown in FIG. 39, the game control microcomputer 560 has transmitted a prize ball number command based on the occurrence of a win, but has not received a prize ball number acceptance command from the payout control microcomputer 370. In this case, that is, when a connection state abnormality (communication error) occurs, a connection confirmation command is transmitted to the payout control microcomputer 370 after 10 seconds (10 seconds) have elapsed since the prize ball number command was transmitted. Then, the connection confirmation command is repeatedly transmitted every 10 s (10 seconds) until the communication state is recovered. After that, when the communication error is canceled (resolved) and the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 returns to the normal (normal) operation, and the prize ball number command Is retransmitted (retryed) to the payout control microcomputer 370. Specifically, the game control microcomputer 560 does not subtract the prize ball number storage if it does not receive the prize ball number acceptance command even after sending the prize ball number command (described later). If N in step S52403, the value of the prize ball command output counter in step S52404 is not subtracted by 1), and the value of the prize ball command output counter is maintained as it is when the prize ball number command is transmitted next time. The prize ball number command is retransmitted based on that (see steps S52301 to S52035 described later).

  Next, the prize ball process (step S32) will be described. FIG. 40 is a flowchart showing an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 41 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the prize ball command output counter, and the prize ball designation for designating the number of prize balls Data is set sequentially. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2, 3 (2) corresponding to the prize ball number “10”. Corresponding to the normal winning ports 29 and 30) and a prize ball command output counter 4 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15) based on the prize ball designation data for designating the number of prize balls (15). The data is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0. Based on the prize ball designation data for designating the number of prize balls (3), data indicating the number of prize balls (3) is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is issued. It transmits to the control microcomputer 370. In FIG. 41, the switch-on buffer 1 corresponds to the input port 0, and the switch-on buffer 2 corresponds to the input port 2.

  FIG. 42 is a flowchart showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded in the register and the prize ball designation data pointed to by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not on, the number of processes is reduced by 1 (step S5114), and if the number of processes is 0 The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer. (Step S111). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5112, S5113). Then, the process proceeds to step S5113.

  FIG. 43 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 44 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). . If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the processing of steps S5227 and S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and Y in step S5227. When the determination is made, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integral multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal 1 output timer.

  FIG. 45 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S5221). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S5227.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 30) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the processing of steps S52313 and S52315, which will be described later, and one second elapses without sending a prize ball number command, and Y in step S52313. If it is determined, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 46 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 4 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 4 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the process does not proceed to step S52303 and subsequent steps. And control to suspend transmission of the prize ball number command.

  If the content of the frame state display buffer is 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count value of the prize ball command output counters 2 and 3 is also 0, the CPU 56 checks whether the count value of the prize ball command output counter 4 is 0 or not. If the count value of the prize ball command output counter 4 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls to 3 in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs processing for outputting a prize ball number command in which the number of prize balls is set to the transmission data register of the serial communication circuit 505.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds have elapsed without receiving a prize ball number acceptance command or a prize ball preparation command. If it is timed out and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. Connection (without returning to the prize ball transmission process 1) by repeating the prize ball receipt confirmation process (see steps S52403 to S52405) or by receiving the prize ball preparation command (see steps S52406 to S52408). In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out in excess of the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. Cases are also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the award ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the winning ball shortage error command transmission table is set in the pointer in step S52312, the serial communication circuit of the transmission / reception channel with the effect control board 80 in the effect symbol command control processing in step S30. A prize ball shortage error command is output to the transmission data register 505, and the prize ball shortage error command is transmitted to the production control microcomputer 100. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around. Therefore, the game control microcomputer 560 may be equipped with a transmission-only serial communication circuit for communication with the effect control microcomputer 100.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command described later, the effect control microcomputer 100 performs an error notification of prize ball shortage or prize ball excess. However, the error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed from the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, on the contrary, 10 may be added to the value of the winning ball counter based on the input of winning ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. If the value of the prize ball number counter is 501 or more in the process of step S5312 described later, What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 47 is a flowchart showing a prize ball reception confirmation process (step S524) executed when the value of the prize ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first checks whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52402). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S52409.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 30) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. When the time-out occurs and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 48 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S52502). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S52509.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the prize ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a winning ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorized number of prize balls, and a new prize is also generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 30) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the processing of steps S52509 and S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time is out and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 49 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the input of the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the winning ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the winning ball information input invalid timer (step S5310) and sets the value of the winning ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the prize ball information has been inputted on the condition that the prize ball information has been inputted 6 times or more out of the 8 confirmation processes, and 10 pieces of prize ball information are entered. The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the winning ball excess error command transmission table is set in the pointer in step S5315, in the effect symbol command control process in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. The award ball excessive error command is output to the transmission data register 505, and the award ball excessive error command is transmitted to the production control microcomputer 100.

  Next, the frame state output process (step S39) will be described. FIG. 50 is a flowchart illustrating an example of the frame state output process in step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the contents of the input port 0 (step S392) and logically ANDs the input contents of the input port 0 with a predetermined door opening signal confirmation mask value (specifically 01000000). (Step S393). Further, the CPU 56 calculates the logical product of the operation result obtained by the logical product and the contents of the frame state display buffer loaded in step S391 (step S394). By executing the above processing, a calculation result is obtained in which the door opening signal input state is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the contents of the previous frame state display buffer (step S395). The previous frame state display buffer stores the calculation result of step S394 calculated when the frame state output processing is executed by the previous timer interrupt. When the calculation result is different from the content of the previous frame state display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame state display buffer and updates the previous frame state display buffer. Along with (Step S397), the calculation result calculated in Step S394 is set as it is to the frame state display command, and control is performed to transmit the frame state display command to the effect control microcomputer 100 (Step S398). Specifically, the CPU 56 performs processing for setting the address of the frame state display command transmission table in the pointer. Then, based on the fact that the address of the frame state display command transmission table is set in the pointer in step S398, in the effect symbol command control processing in step S30, the serial communication circuit 505 for the channel for transmission / reception with the effect control board 80 is performed. The frame state display command is output to the transmission data register, and the frame state display command is transmitted to the production control microcomputer 100.

By executing the above processing, error information set by the connection OK command or the winning ball preparation command from the payout control microcomputer 370 (paid-out number error error, out of ball error, full tank error, winning ball error) And the input state of the door opening signal are set in the frame state display command and transmitted to the production control microcomputer 100.

  FIG. 51 is a flowchart showing an example of a program of special symbol process (step S28) executed by the game control microcomputer 560. As described above, in the special symbol process, the first special symbol display 8a or the second special symbol display 8b, the special variable winning ball device 20, and the variable winning device 400 are controlled. In the special symbol process, if the first start opening switch 14a for detecting that the game ball has won the first start winning opening 13a is turned on, that is, the start to the first starting winning opening 13a. If a winning has occurred, a first start port switch passage process is executed (steps S311 and S312). If the second start port switch 15a for detecting that the game ball has won the second start winning port 13b is turned on, that is, the start winning to the second start winning port 13b has occurred. Then, the second start port switch passage process is executed (steps S313, S314). Then, any one of steps S300 to S310 is performed. If the first start port switch 14a or the second start port switch 15a is not turned on, any one of steps S300 to S310 is performed according to the internal state. Note that the determinations in step S311 and step S313 may be made based on whether or not the switch-on buffer corresponding to the first start port switch 14a or the switch-on buffer corresponding to the second start port switch 15a is “0”. Good.

  The processes in steps S300 to S310 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is in a state where variable display of the special symbol can be started, the game control microcomputer 560 checks the number of numerical data stored in the reserved storage number buffer (total number of reserved storage). The stored number of numerical data stored in the pending storage number buffer can be confirmed by the count value of the total pending storage number counter. Further, if the count value of the total pending storage number counter is not 0, it is determined whether or not the display result of the variable display of the first special symbol or the second special symbol is a big hit or a small hit. . In case of big hit, set big hit flag. If it is a small hit, the small hit flag is set. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The big hit flag is reset when the big hit game ends, and the small hit flag is reset in the pre-start process for the small hit.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is defined as the variation display variation time of the special symbol. Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result designation command transmission process (step S302): This process is executed when the value of the special symbol process flag is 2. Control for transmitting a display result designation command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the internal state (special symbol process flag) is stepped. Update to a value corresponding to S304 (4 in this example).

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. The variable display on the first special symbol display 8a or the second special symbol display 8b is stopped, and the stop symbol is derived and displayed. In addition, control for transmitting a symbol confirmation designation command to the effect control microcomputer 100 is performed. If the big hit flag is set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. If the small hit flag is set, the internal state (special symbol process flag) is updated to a value (8 in this example) corresponding to step S308. If neither the big hit flag nor the small hit flag is set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (in this example, 0). The effect control microcomputer 100 controls the effect display device 9 to stop the effect symbol when receiving the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the big prize opening pre-processing, the lower big prize opening 23b is controlled to be opened. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the lower big prize opening 23b) is initialized, and the solenoid 17 is driven to open the lower big prize opening 23b. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting a round display effect control command during the big hit gaming state to the effect control microcomputer 100, a process for confirming that the closing condition of the lower big prize opening 23b is satisfied, and the like are performed. If the closing condition for the lower big prize opening 23b is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended. Also, a process for setting a flag indicating the gaming state (for example, an advantageous state flag) is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  Small hit release pre-processing (step S308): This process is executed when the value of the special symbol process flag is 8. In the small hit release pre-processing, a small hit start command corresponding to the small hit type is transmitted, and a counter (for example, a remaining ball count counter that counts game balls that have entered the variable winning device 400) is initialized. In addition, by setting a small hitting control pattern including a timing for opening the upper special winning opening 24b, a timing for closing the upper big winning opening 24b, and a timing for operating the foot model 402, the operation setting of these small hitting gaming states is performed. The internal state (special symbol process flag) is updated to a value (9 in this example) corresponding to step S309.

  Small hit release processing (step S309): executed when the value of the special symbol process flag is 9. In the small hit opening process, control is performed to open the upper special winning opening 24b. Specifically, the solenoid 17 is driven to open the upper special winning opening 24b. Further, the end of the small hit gaming state is determined by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Small hit end process (step S310): executed when the value of the special symbol process flag is 10. Control is performed to cause the display control microcomputer 100 to perform display control for transmitting the small hit end designation command to notify the player that the small hit gaming state has ended, and the game is performed in the specific area 43 by small hit. It is determined whether or not a ball has entered (specific winning determination process). When a game ball enters the specific area 43 in the small hit, the internal state (special symbol process flag) is updated to a value corresponding to step S305 (5 in this example), while the game ball enters the specific area 43. If not, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 52 is a flowchart showing the start-port switch passing process in steps S312 and S314. Among these, FIG. 52 (A) is a flowchart showing the first start port switch passing process of step S312. FIG. 52B is a flowchart showing the second start port switch passing process in step S314.

  First, the first start port switch passing process will be described with reference to FIG. In the first start port switch passing process executed when the first start port switch 14a is in the on state, the CPU 56 of the game control microcomputer 560 displays the first start winning memorized number (or the first start winning memorized counter) (or It is confirmed whether or not the first start winning memory number stored in the first special figure reservation memory has reached the maximum value of 4 (step S321A). If the first start winning memorized number has not reached 4, the CPU 56 reads the random R value stored as the random number value from the random number value memory circuit of the random number circuit 503 (step S322A). In addition, the CPU 56 stores the read random R value in a storage area (first special symbol determination buffer (first special diagram holding memory)) corresponding to the value of the number of start winning memories (step S323A). In this embodiment, the random number circuit 503 inputs an input signal from the first start port switch 14a as a latch signal. In this case, the random number circuit 503 latches the counter value of the counter built in the random number circuit 503 in the random value storage circuit (latch circuit) at the timing when the input signal is input from the first start port switch 14a. Then, the CPU 56 reads the value latched in the random value storage circuit of the random number circuit 503 as a random R in step S322A.

  When the random number circuit 503 is configured so that a new count value cannot be latched in the latch circuit even if a latch signal is output unless the count value latched in the random number value storage circuit (latch circuit) is read. As long as it is determined in step S321A that the starting prize storage number has reached the maximum value 4, the count value is not read from the latch circuit, and the new count value is not latched by the latch circuit. Therefore, even if the start winning memorized number is less than 4 and step S322A is executed and the count value is read out from the latch circuit, the old count value latched at a timing other than the original latch timing is read out. Thus, there is a risk that processing such as jackpot determination will be performed using a random number value based on the old count value. Therefore, when the random number circuit 503 is configured so that a new count value cannot be latched unless the count value latched by the latch circuit is read, even if it is determined as Y in step S321A (start winning memory) Even if the number is 4 or more), the process of step S322A may be executed to read the count value latched by the latch circuit (however, steps S323A to S325A are not executed). By doing so, it is possible to prevent a situation in which processing such as jackpot determination is performed using a random number value based on an old count value latched at a timing other than the original latch timing.

  Next, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the first special figure reservation memory (step S324A), and adds 1 to the count number of the first start winning counter. The first start winning memory number is increased by 1 (step S325A).

  Note that if the first start winning memory has reached the maximum value of 4 in step S321A, the first start port switch passing process is terminated as it is.

  Next, the second start port switch passing process will be described with reference to FIG. In the second start port switch passing process executed when the second start port switch 15a is in the ON state, the CPU 56 of the game control microcomputer 560 has a second start winning memorize number (or a second start memorizing memory counter). It is confirmed whether or not the second starting prize storage number stored in the second special figure holding memory has reached the maximum value of 4 (step S321B). If the second start winning storage number has not reached 4, the CPU 56 reads the random R value stored as the random value from the random value storage circuit of the random number circuit 503 (step S322B). Further, the CPU 56 stores the read random R value in a storage area (second special symbol determination buffer (second special symbol holding memory)) corresponding to the value of the number of start winning memories (step S323B). In this embodiment, the random number circuit 503 inputs an input signal from the second start port switch 15a as a latch signal. In this case, the random number circuit 503 latches the counter value of the counter built in the random number circuit 503 in the random value storage circuit (latch circuit) at the timing when the input signal is input from the second start port switch 15a. Then, the CPU 56 reads the value latched in the random value storage circuit of the random number circuit 503 as a random R in step S322B.

  Next, the CPU 56 sets the value of the random R stored in the predetermined buffer area at the head of the empty entry in the second special figure reservation memory (step S324B), and adds 1 to the count number of the second start winning counter. The second start winning memory number is increased by 1 (step S325B).

  If the second start winning memory has reached the maximum value of 4 in step S321B, the second start port switch passing process is terminated as it is.

  53 and 54 are flowcharts showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 confirms the value of the total pending storage number (step S51). Specifically, the count value of the total pending storage number counter is confirmed. If the total pending storage number is 0, the process is terminated.

  If the total reserved memory number is not 0, the CPU 56 checks whether or not the second reserved memory number is 0 (step S52). Specifically, it is confirmed whether or not the value of the second reserved memory number counter is zero. If the second reserved memory number is not 0, the CPU 56 has a special symbol pointer (a flag indicating whether the special symbol process is being performed for the first special symbol or the special symbol process is being performed for the second special symbol). Is set to data indicating “second” (step S53). If the second reserved memory number is 0 (that is, only the first reserved memory number is accumulated), the CPU 56 sets data indicating “first” in the special symbol pointer (step S54).

  In this embodiment, by executing the processing of steps S52 to S54, the variation display of the second special symbol is executed with priority over the variation display of the first special symbol.

  Next, the CPU 56 reads out each random number value stored in the storage area corresponding to the reserved storage number = 1 indicated by the special symbol pointer in the RAM 55 and stores it in the random number buffer area of the RAM 55 (step S55). Specifically, when the special symbol pointer indicates “first”, the CPU 56 determines each disturbance stored in the storage area corresponding to the first reserved memory number = 1 in the first reserved memory number buffer. The numerical value is read and stored in the random number buffer area of the RAM 55. In addition, when the special symbol pointer indicates “second”, the CPU 56 reads each random number value stored in the storage area corresponding to the second reserved memory number = 1 in the second reserved memory number buffer. And stored in the random number buffer area of the RAM 55.

  Then, the CPU 56 decrements the count value of the reserved storage number counter indicated by the special symbol pointer, and shifts the contents of each storage area (step S56). Specifically, when the special symbol pointer indicates “first”, the CPU 56 decrements the count value of the first reserved memory number counter by 1 and saves each storage area in the first reserved memory number buffer. Shift the contents of. When the special symbol pointer indicates “second”, the count value of the second reserved memory number counter is decremented by 1, and the contents of each storage area in the second reserved memory number buffer are shifted.

  That is, when the special symbol pointer indicates “first”, the CPU 56 saves the first reserved memory number = n (n = 2, 3, 4) in the first reserved memory number buffer of the RAM 55. Are stored in a storage area corresponding to the first reserved memory number = n−1. Further, when the special symbol pointer indicates “second”, it is stored in the storage area corresponding to the second reserved memory number = n (n = 2, 3, 4) in the second reserved memory number buffer of the RAM 55. Each random number value is stored in a storage area corresponding to the second reserved memory number = n−1.

  Therefore, the order in which each random value stored in each storage area corresponding to each first reserved memory number (or each second reserved memory number) is extracted is always the first reserved memory number (or (Second reserved storage number) = 1, 2, 3, 4 in order.

  Then, the CPU 56 stores the count value of the total pending storage number counter in a predetermined area of the RAM 55 (step S57), and then decreases the value of the total pending storage number by one. That is, 1 is subtracted from the count value of the total pending storage number counter (step S58). The CPU 56 stores the value of the total pending storage number counter before the count value is decremented by 1 in a predetermined area of the RAM 55.

  Further, the CPU 56 performs control to transmit the reserved memory number designation command indicated by the special symbol pointer to the effect control microcomputer 100 based on the value of the reserved memory number counter indicated by the special symbol pointer after the subtraction. (Step S59). In this case, when a value indicating “first” is set in the special symbol pointer, the CPU 56 performs control to transmit the first reserved storage number designation command. When a value indicating “second” is set in the special symbol pointer, the CPU 56 performs control to transmit a second reserved memory number designation command.

  In the special symbol normal process, first, data indicating “first” indicating that the process is executed with respect to the first start winning opening 13a, that is, “first” indicating that the process is executed with respect to the first special symbol. ”Or“ second ”indicating that the process is performed on the second special symbol, that is,“ second ”indicating that the process is performed on the second start winning opening 13b. Data is set in the special symbol pointer. In the subsequent processing in the special symbol process, processing corresponding to the data set in the special symbol pointer is executed. Therefore, the process of steps S300 to S310 can be made common between the case of targeting the first special symbol and the case of targeting the second special symbol.

  Next, the CPU 56 reads random 0 (a random number for hit determination) from the random number buffer area, and executes the hit determination module. In this case, the CPU 56 determines the hits that have been extracted in step S312A of the first start port switch passing process or step S314B of the second start port switch passing process and stored in advance in the first hold memory buffer or the second hold memory buffer. A random number is read out and hit determination is performed. The hit determination module is a program that compares a predetermined big hit determination value or small hit determination value with a random number for hit determination, and executes a process of determining a big hit or a small hit if they match. That is, it is a program that executes a big hit determination or a small hit determination process.

  That is, when the value of the random number for random determination (random 0) matches one of the big hit determination values shown in FIG. When it is determined to be a big hit (step S61), the process proceeds to step S71. Note that deciding whether to win or not is to decide whether or not to shift to the big win gaming state, but to decide whether or not to stop the special symbol display device as a big hit symbol. But there is.

  If the value of the hit determination random number (random 0) does not match any of the big hit determination values (No in step S61), the CPU 56 uses the hit determination table (see FIG. 19A) to calculate the small hit value. Perform the determination process. That is, when the value of the random number for random determination (random 0) matches one of the small hit determination values shown in FIG. In this case, the CPU 56 confirms the data indicated by the special symbol pointer. If the data indicated by the special symbol pointer is “first”, the CPU 56 stores the data in association with the small hit corresponding to the first special symbol. It is determined whether or not to make a small hit using the judgment value. Further, when the data indicated by the special symbol pointer is “second”, it is determined whether or not to make a small hit using a determination value stored in association with the small hit corresponding to the second special symbol. To do. If it is determined to be a small hit (step S62; Yes), the CPU 56 sets a small hit flag indicating a small hit (step S63) and reads random 1 from the random number buffer area. The small hit type is specified based on the read random 1 and the small hit type determination table (see FIG. 19D) (step S64), and the specified small hit type (first to fifth) is stored in the RAM 55. The small hit type buffer is set (stored) (step S65). For example, when the small hit type is the first small hit type, “01” is set as data indicating the small hit type, and when the small hit type is the second small hit type, “01” is set as the data indicating the small hit type. “02” is set, and when the small hit type is the third small hit type, “03” is set as data indicating the small hit type, and when the small hit type is the fourth small hit type, the small hit type is selected. “04” is set as the data indicating, and when the small hit type is the fifth small hit, “05” is set as the data indicating the small hit type. On the other hand, when it is not decided to make a small hit (step S62; No), the process proceeds to step S66 without going through steps S63 to S64.

  Next, the CPU 56 determines whether or not the advantageous state end flag is turned on (set) (step S66). At this time, if the advantageous state end flag is off (not set) (step S66; No), it is further determined whether or not the advantageous state flag is on (set) (step S67).

  If the advantageous state flag is off (not set) (step S67; No), there is no need to update the time count count value, so that the process proceeds to step S75 without performing steps S67 + to S70. If the advantageous state flag is on (set) (step S67; Yes), it is determined whether or not the special symbol pointer is the second, that is, whether or not the target of the special symbol game is the second special symbol. Determine (step S67 +). If the special symbol pointer is not the second (step S67 +; No), the process proceeds to step S75. On the other hand, if the special symbol pointer is the second (step S67 +; Yes), it is counted by the short-time counter. 1 is subtracted and updated from the time count count value (step S68), and after the subtraction update command is transmitted to notify the effect control microcomputer 100 of the time count after the subtraction update (step S68 +), the subtraction is performed. It is determined whether or not the short-time count value is 0, that is, whether or not the advantageous state has reached a predetermined upper limit value for the second special figure game, for example, 100 (step S69).

  At this time, if the time reduction count value is 0 (step S69; Yes), after clearing the advantageous state flag and setting the advantageous state end flag for ending the advantageous state in the next special figure game (step S70). On the other hand, if the advantageous state count value is not 0 (step S69; No), the process proceeds to step S75 without setting the advantageous state end flag. That is, the advantageous state end flag is set in response to the advantageous state reaching a predetermined upper limit value for the second special figure game, for example, 100 times.

  When the advantageous state end flag is turned on (set) in step S66 (step S66; Yes), the advantageous state end flag is cleared (reset), and the advantageous state flag is cleared (reset). The state is ended (step S77), and after the normal game state designation command is transmitted, the process proceeds to step S75. That is, when the advantageous state is ended in the next special figure game in which the advantageous state end flag is set in response to reaching the upper limit number (for example, 100 times) for the second special figure game, the upper limit number of times (for example, Even if a big win is triggered by the special game that has reached (100 times), it can be judged as a big hit that occurred in a short time (advantageous) state.

  In this embodiment, it is determined in step S66 whether or not the advantageous state end flag is turned on (set). However, this determination may be performed in the special symbol stop process. For example, after determining whether or not the advantageous state end flag is turned on (set), the advantageous state end flag may be cleared (reset). In addition, the normal gaming state designation command may be determined by determining whether or not it is in an advantageous state in the special symbol stop process and not in the advantageous state.

  In step S71, the CPU 56 sets a big hit flag indicating that it is a big hit. Then, the jackpot type determination table indicated by the special symbol pointer is selected as a table used to determine the jackpot type as one of a plurality of types (step S72). Specifically, when the special symbol pointer indicates “first”, the CPU 56 selects the jackpot type determination table for the first special symbol shown in FIG. Further, when the special symbol pointer indicates “second”, the CPU 56 selects a big hit type determination table for the second special symbol shown in FIG.

  Next, the CPU 56 uses the selected jackpot type determination table to select a type (first to sixth jackpots) corresponding to a value that matches the value of the random number for random determination (random 1) stored in the random number buffer area. Is determined as the type of jackpot (step S73). In this case, the CPU 56 determines the jackpot type extracted in step S214A of the first start port switch passing process or step S214B of the second start port switch passing process and stored in advance in the first hold memory buffer or the second hold memory buffer. The random number is read and the jackpot type is determined.

  In addition, the CPU 56 sets (stores) data indicating the determined jackpot type in the jackpot type buffer in the RAM 55 (step S74). For example, when the jackpot type is the first jackpot type, “01” is set as data indicating the jackpot type, and when the jackpot type is the second jackpot type, “02” is set as the data indicating the jackpot type. When the jackpot type is the third jackpot, “03” is set as data indicating the jackpot type, and when the jackpot type is the fourth jackpot, “04” is set as the data indicating the jackpot type. Is set as data indicating the big hit type, “06” is set as the data indicating the big hit type, and “06” is set as the data indicating the big hit type when the big hit type is the sixth big hit.

  Next, the CPU 56 determines a special symbol stop symbol (step S75). Specifically, when neither the big hit flag nor the small hit flag is set, “−” which is a loss symbol is determined as a special symbol stop symbol. When the jackpot flag is set, according to the determination result of the jackpot type, any one of “1” to “5” or “7” corresponding to the jackpot type is determined as a special symbol stop symbol (see FIG. 19 (b) and (c)). When the small hit flag is set, “1” to “5”, which are the small hit symbols corresponding to the small hit types, are determined as the special symbol stop symbols.

  Then, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S301) (step S76).

  FIG. 55 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 sets an end flag referred to in the special symbol display control process in step S32 to end the variation of the special symbol, and the first special symbol display 8a or the second special symbol display 8b. Then, a control for deriving and displaying the stop symbol is performed (step S131). If data indicating “first” is set in the special symbol pointer, the variation of the first special symbol on the first special symbol display 8a is terminated, and “second” is indicated in the special symbol pointer. When data is set, the variation of the second special symbol on the second special symbol display 8b is terminated. Moreover, control which transmits the symbol determination designation | designated command to the microcomputer 100 for production control is performed (step S132). When the big hit flag is not set, the process proceeds to step S147 (step S133).

  If the big hit flag is set, the CPU 56 performs control to send a big hit start designation command to the effect control microcomputer 100 (step S134). Whether the big hit type is the first big hit to the sixth big hit is determined based on the data indicating the big hit type stored in the RAM 55 (data stored in the big hit type buffer).

  Further, the CPU 56 performs control to transmit a normal state designation command to the effect control microcomputer 100 (step S135). A value corresponding to a jackpot display time (a time for which the effect display device 9 notifies that the jackpot has occurred, for example) is set in the jackpot display time timer (step S136). In addition, the number of times of opening (for example, 15 times in the case of a big hit of 15 rounds) is set in the number-of-opening counter of the lower big prize opening 23b (step S137).

  It should be noted that the control for transmitting the normal state designation command to the production control microcomputer 100 in step S135 may be transmitted in the big hit ending process when the short hit (advantageous) state is not controlled after the big hit ending.

  Further, the CPU 56 determines whether or not an advantageous state flag indicating that the time is short (advantageous) is turned on (set). If the advantageous state flag indicating the short-time (advantageous) state is turned on (set) (step S138; Yes), the big hit hour advantageous flag is set to the on state (step S139), and the advantageous The state flag is cleared (reset) to be turned off (not set) (step S140). The time reduction counter is cleared and the time reduction count value is initialized to “0” (step S141). When the advantageous state flag is ON in step S138 (step S138; Yes), the time reduction ( Advantage) Since the advantage state end flag may have been directly hit after being set in the second special figure game that reaches the upper limit number of states, if it is set, the advantage state end flag is reset. (Clear) to turn it off (not set) (step S142). As described above, by setting the big hit advantage flag in the step S139, it is memorized that the gaming state was the short time (advantageous) state before being controlled to the big hit gaming state. Can do.

  After the process of step S142 or when the advantageous state flag is OFF (not set) in step S138 (step S138; No), the value of the special symbol process flag corresponds to the pre-opening process for the big prize opening (step S305). The updated value is updated (step S143).

  In step S147, it is determined whether the small hit flag is set. If the small hit flag is not set (No in step S147), the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300) (step S149). On the other hand, if the small hit flag is set (Yes in step S147), the CPU 56 updates the value of the special symbol process flag to a value corresponding to the small hit release pre-processing (step S308) (step S148).

  FIG. 56 is a flowchart showing the small hit release pre-processing (step S308) in the special symbol process. In the small hit release pre-processing, the CPU 56 first transmits a small hit start designation command (step S152) and sets a small hit game control time (step S153). For example, in the process of step S153, the CPU 56 resets the game control process timer to set the timer value to “0”, and sets a small hit game end reference value predetermined corresponding to the small hit game control time, Set as a comparison target with the game control process timer value. The small hit game end reference value set at this time is compared with the game control process timer value in the small hit releasing process executed in step S309 shown in FIG. For example, the small hit game end reference value is that the game ball that has entered the variable winning device 400 from the upper big prize opening 24b opened by the start operation after starting the small hit game state is entered into the specific area 43. Any timer reference value corresponding to a sufficient time until the vehicle enters may be used. That is, the small hit game end reference value is effective by the specific area switch 43a when a game ball that has entered the upper special winning opening 24b that has been opened by the start operation in the small hit game state enters the specific area 43. An effective winning detection period, which is a grace period until detection, is shown. In addition, in the process of step S153, the game stop determination value corresponding to the grace period until the game is stopped may be initialized.

  After the small hit game control time is set in step S153, the small hit flag is cleared (reset) to be turned off (not set) (step S154), and the game balls that have entered the variable winning device 400 are counted. After the counter such as the remaining ball number counter is initialized (step S155), the value of the special figure process flag is updated to a value corresponding to the small hit releasing process (step S156).

  FIG. 57 is a flowchart showing the small hit releasing process (step S309) in the special symbol process. In the small hit release process, the CPU 56 first updates the game control process timer value by adding 1 for example (step S161). The game control process timer value is set to “0” by the process of step S153 shown in FIG. 56, for example, and then updated every time the process of step S271 is executed, so that the elapsed time in the small hit gaming state is obtained. Corresponding values can be shown. Subsequent to the processing in step S161, various settings and controls corresponding to the updated game control process timer value are performed.

  For example, the CPU 56 determines whether or not the game control process timer value matches the upper prize winning opening release determination value (step S162). When the game control process timer value matches the upper big prize opening opening determination value in step S162 (step S162; Yes), the solenoid 17 is driven to set the upper big prize opening provided in the variable prize winning device 400. A start operation start setting is performed to bring 24b into an open state by the upper prize winning door 24c (step S163). In the process of step S163, a drive control signal for starting the drive of the solenoid 17 is generated according to the drive pattern indicated by the upper special winning opening opening control data. When the game control process timer value does not match the upper big prize opening opening determination value in step S162 (step S162; No), the process of step S163 is skipped.

  Thereafter, the CPU 56 determines whether or not the game control process timer value matches the model solenoid drive determination value (step S164). If the game control process timer value matches the model solenoid drive determination value in step S164 (step S164; Yes), a setting is made to start driving the solenoid 18 provided corresponding to the foot model 402 ( Step S165). In the process of step S165, a drive control signal for starting driving of the solenoid 18 is generated in accordance with the drive pattern indicated by the model solenoid drive control data. If the game control process timer value does not match the model solenoid drive determination value in step S164 (step S164; No), the process of step S165 is skipped.

  Then, the CPU 56 performs various settings and control when the game ball enters the variable winning device 400 from the upper special winning opening 24b by executing the upper special winning opening entry process (step S166). .

  After executing the process at the time of entering the upper prize opening in step S166, it is determined whether or not the game control process timer value matches the model solenoid stop determination value (step S167). When the game control process timer value matches the model solenoid stop determination value in step S167 (step S167; Yes), the setting for stopping the driving of the solenoid 18 is performed (step S168). In the process of step S168, a drive control signal for stopping the drive of the solenoid 18 is generated according to the drive pattern indicated by the model solenoid stop control data. When the game control process timer value does not coincide with the model solenoid stop determination value in step S167 (step S167; No), the process of step S168 is skipped.

  Thereafter, the CPU 56 determines whether or not the game control process timer value matches the upper special winning opening release determination value (step S169). When the game control process timer value matches the upper big prize opening opening determination value in step S169 (step S169; Yes), the driving of the solenoid 17 is stopped and the upper big prize opening 24b is set to the upper big prize opening door. The operation for making the closed state is set by 24c (step S170). In the process of step S170, a drive control signal for stopping the drive of the solenoid 17 is generated according to the drive pattern indicated by the upper special winning opening opening control data. If the game control process timer value does not match the upper big prize opening release determination value in step S169 (step S169; No), the process of step S170 is skipped.

  Then, the CPU 56 compares the game control process timer value with the small hit game end reference value to determine whether or not the game control process timer value has reached the small hit game end reference value (step S175). At this time, if the game control process timer value has reached the small hit game end reference value (step S175; Yes), the special figure process flag value is updated to a value corresponding to the small hit end processing (step S175). S176) If the game control process timer value has not reached the small hit game end reference value (step S175; No), the value of the special figure process flag is not changed.

  FIG. 58 is a flowchart showing the process when entering the upper special winning opening in the small hit opening process (step S309). 58, first, the CPU 56 determines whether any of the detection signals from the upper count switch 24 is in an on state (step S501). At this time, if any of the detection signals from the upper count switch 24 is in an on state (step S501; Yes), 1 is added to the remaining ball count value (step S502). On the other hand, when all the detection signals from the upper count switch 24 are in the off state (step S501; No), the process of step S502 is skipped.

  Thereafter, it is determined whether or not the detection signal from the specific area switch 43a is in an ON state (step S503). At this time, if the detection signal from the specific area switch 43a is on (step S503; Yes), the specific ball detection flag (V winning flag) is set to the on state (step S504). On the other hand, when the detection signal from the specific area switch 43a is in the off state (step S503; No), the process of step S504 is skipped.

  Subsequently, it is determined whether or not the detection signal from the discharge port switch 45 is on (step S505). At this time, if the detection signal from the discharge port switch 45 is in an off state (step S505; No), the upper special winning opening entry process is terminated. On the other hand, when the detection signal from the discharge port switch 45 is in the ON state (step S505; Yes), the remaining ball number count value is decremented by 1 (step S506), and then the upper prize winning opening is entered. The process ends.

  FIG. 59 is a flowchart showing the small hit end process (step S310) in the special symbol process. In the small hitting end process, the CPU 56 first transmits a small hitting end designation command (step S180) and determines whether the remaining ball count value is “0” (step S181). Note that the remaining ball count value is updated by executing the processing of steps S502 and S506 shown in FIG. 58 in the upper special winning opening entry processing of step S166 shown in FIG.

  If the remaining ball count value is “0” in step S181 (step S181; Yes), the drive of the solenoid 18 is stopped, for example, by generating a drive control signal for stopping the drive of the solenoid 18. For this purpose (step S182). Thereafter, the game control process timer is reset to clear the timer value (step S183), and by executing the specific winning determination process, the game ball enters the specific area 43 in the effective winning detection period in the small hit gaming state. It is determined whether or not it has been performed (step S184).

  If the remaining ball count value is not “0” in step S181 (step S181; No), it is determined whether or not the game control process timer value has reached the game stop determination value (step S186). At this time, if the game stop determination value has not been reached (step S186; No), the small hit release process is terminated. On the other hand, when the game stop determination value is reached in step S186 (step S186; Yes), the abnormality notification process for notifying that the state is abnormal is repeatedly executed (step S187). As a result, the progress of the game can be stopped, and an illegal act performed by generating an abnormal state can be prevented. In the abnormality notification process in step S187, a predetermined notification screen is displayed on the display area of the effect display device 9, a predetermined warning lamp is turned on, a predetermined warning sound is output from the speaker 27, or these What is necessary is just to be able to alert | report abnormality by combining.

  The abnormality notification process executed in step S187 may be repeatedly performed when the power supply from the power supply board is stopped, that is, until the power is turned off. In this case, when the power is cut off, if the clear switch is pressed when the power is turned on again, the initial setting process is executed after the RAM 55 is cleared, and the abnormal state is cleared (released). Good. On the other hand, when the power is cut off, the notification of abnormality may be ended even if the pressing operation of the clear switch is not performed when the power is turned on again. Thereby, since it is not necessary to input a special signal to the main board 31 in order to clear (cancel) the abnormal state, it is possible to reduce the possibility that an illegal signal is input.

  In addition, the abnormality notification process executed in step S187 is repeatedly performed until a predetermined time (for example, 30 seconds) elapses, and can automatically recover from the abnormal state after the predetermined time elapses. It may be. As a result, it is possible to reliably notify an amusement hall clerk or the like that an abnormal state has occurred, but from the abnormal state without clearing the RAM 55 by pressing the clear switch or turning on the power again. Since it is restored, it is possible to reduce the disadvantage given to the player when it is determined to be abnormal due to noise or the like. Alternatively, in the abnormality notification process in step S187, for example, after an effect control command that is an error command is transmitted to the effect control board 80 to notify the occurrence of an error, the small hit release process is performed without entering the loop process. May be terminated. Alternatively, even when the game control process timer value reaches the game stop determination value in step S186, the CPU 56 detects the elapse of a predetermined time on the side of the effect control board 80 without executing the abnormality notification process, You may make it alert | report an abnormality. As an example, when a game ball is detected by any of the upper count switches 24 from the main board 31 to the effect control board 80, an upper count detection command as an effect control command indicating the detection of the game ball is issued. Send. On the side of the effect control board 80, the elapsed time after receiving the upper count detection command is measured, and the measured elapsed time is predetermined without receiving the small hit end command or the big hit start command from the main board 31. When the error determination time is reached, a process for notifying the occurrence of abnormality may be executed. In this case, for example, with respect to an abnormal winning corresponding to the detection of a game ball by one of the upper count switches 24, only the operation of paying out the winning ball and notifying the occurrence of the abnormality may be executed. Thereby, for example, at the time of closing the store where the pachinko gaming machine 1 is installed, it is possible to easily perform the ball exit compensation.

  FIG. 60 is a flowchart showing the specific winning determination process in the small hit end process (step S310). In the specific winning determination process, the CPU 56 first determines whether or not the specific ball detection flag (V winning flag) is set to the on state (step S510). At this time, if the specific ball detection flag (V winning flag) is on (step S510; Yes), the big hit flag is set to the on state (step S511), and the big hit type buffer corresponds to the seventh big hit as the big hit type. “07” is set (stored) (step S512), and a big hit start designation command is transmitted to the production control microcomputer 100 (step S513). Further, the CPU 56 performs control to transmit a normal state designation command to the effect control microcomputer 100 (step S514). It should be noted that the control for transmitting the normal state designation command to the effect control microcomputer 100 in step S514 may be transmitted in the big hit end process when the short win (end) state is not controlled after the big hit.

  Next, a value corresponding to the jackpot display time timer (time for notifying in the effect display device 9 that the jackpot has been generated by the V winning) is set in the jackpot display time timer (step S515). In addition, after setting the number of times of opening corresponding to the seventh big hit to 14 times in the lower big winning opening opening number counter (step S516), the specific ball detection flag (V winning flag) is reset (cleared) and turned off ( (Not set) state (step S517).

  Next, the CPU 56 determines whether or not an advantageous state flag indicating that the time is short (advantageous) is turned on (set).

  When the advantageous state flag indicating that the time is short (advantageous) is turned on (set) (step S518; Yes), the big hit hour advantageous flag is set to the on state (step S519). The state flag is cleared (reset) to be turned off (not set) (step S520). Further, the time reduction counter is cleared and the time reduction count value is initialized to “0” (step S521), and when the advantageous state flag is on in step S518 (step S518; Yes), the time reduction ( Since the advantageous state end flag is set in the second special figure game that reaches the upper limit of the number of states, it may be a big hit by winning a small area and winning in the specific area 43. If yes, the advantageous state end flag is reset (cleared) to be in an off (non-set) state (step S522). In this manner, by setting the big hit advantage flag in the step S519, it is possible to store that the gaming state was in an advantageous state before being controlled to the big hit gaming state. After the process of step S522, the value of the special symbol process flag is updated to a value corresponding to the pre-opening process for the special winning opening (step S305) (step S523).

  On the other hand, if the specific ball detection flag (V winning flag) is not set to ON in step S510 (step S510; No), the small hit type set (stored) in the small hit type buffer is cleared. After (step S524), the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S525).

  FIG. 61 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the jackpot end process, the CPU 56 checks whether or not the jackpot end display timer is set (step S190). If the jackpot end display timer is set, the process proceeds to step S206. If the big hit end display timer is not set, the big hit flag is reset (step S191), and then the processing from step S192 to step S205 is performed to determine whether there is a big hit advantageous state flag and the big hit type buffer. Based on the stored big hit type, it is determined whether the gaming state after the big hit is a normal gaming state or a short-time (advantageous) state, and the number of time reductions corresponding to the normal gaming state or the short-time (advantageous) state is determined. Set and send jackpot end designation command.

  In step S192, first, it is determined whether or not the big hit advantageous state flag is set to the on state. If the big hit advantageous state flag is not set to the on state, the process proceeds to step S200, whereas if the big hit advantageous state flag is set to the on state, the process proceeds to step S193 and is set. Reset (clear) the big hit advantageous state flag.

  Then, the CPU 56 determines whether or not the jackpot type data stored in the jackpot type buffer is “7” corresponding to the seventh jackpot, that is, whether or not the finished jackpot is the seventh jackpot ( Step S194).

  If the ended big hit is not the seventh big hit, the process proceeds to step S195, and further, whether or not the big hit type data stored in the big hit type buffer is “2” corresponding to the second big hit, that is, ended. It is determined whether or not the big hit is the second big hit.

  When the finished big hit is the second big hit, the process proceeds to step S196, and the big hit end display timer corresponds to the display time corresponding to the time during which the big hit end display is performed on the effect display device 9 (big hit end display time). After the value to be set is set (step S196), it is determined that the gaming state after the big hit is the normal gaming state, and the big hit end 1 designation command corresponding to the normal gaming state is transmitted to the effect control microcomputer 100. This is performed (step S197).

  On the other hand, if the big hit ended in step S195 is not the second big hit, the process proceeds to step S204, and the big hit end display timer corresponds to the time that the big hit end display is performed on the effect display device 9 (big hit end display time). After the value corresponding to the display time to be set is set (step S204), it is determined that the gaming state after the big hit is the short time (advantageous) state, and the initial value of the short time count value is set to 100 times. A control for transmitting a jackpot end 2 designation command corresponding to the state to the effect control microcomputer 100 is performed (step S205).

  If the big hit ended in step S194 is the seventh big hit, the process proceeds to step S203, and the small hit type data stored in the small hit type buffer is “2” corresponding to the second small hit. In other words, it is determined whether or not the small hit where the completed seventh big hit has occurred is the second big hit generated in the short time (advantageous) state.

  If the small hit that the seventh big hit that has been completed is the first, third, and fifth small hits other than the second small hit that occurred in the short-time (advantageous) state, the process proceeds to step S204. In addition, when the small hit where the seventh big hit is completed is the second small hit generated in the short-time (advantageous) state, that is, the second small hit generated in the short-time (advantageous) state, The process proceeds to step S196.

  On the other hand, in step S200, the CPU 56 determines whether or not the big hit type data stored in the big hit type buffer is “7” corresponding to the seventh big hit, that is, the seventh big hit generated in the normal gaming state. It is determined whether or not.

  If the completed big hit is not the seventh big hit, the process proceeds to step S201, and the big hit type data stored in the big hit type buffer is “3” corresponding to the third big hit and “5” corresponding to the fifth big hit. It is determined whether the jackpot is “6” corresponding to the sixth jackpot, that is, whether the finished jackpot is any of the third jackpot, the fifth jackpot or the sixth jackpot generated in the normal gaming state.

  If the finished big hit is any of the third big hit, the fifth big hit and the sixth big hit generated in the normal gaming state, the process proceeds to step S204. In addition, when the big hit that has ended is not any of the third big hit, the fifth big hit, or the sixth big hit that occurred in the normal gaming state, that is, the first big hit, the second big hit, If it is 4 big hits, the process proceeds to step S196.

  On the other hand, if the big hit ended in step S200 is the seventh big hit, the process proceeds to step S202, where the small hit type data stored in the small hit type buffer is “3” corresponding to the third small hit, or Whether or not it is “4” corresponding to the fourth small hit, that is, whether or not the small hit where the seventh big hit ended is the third small hit or the fourth small hit generated in the normal gaming state. Determine.

  When the completed small hit is the third small hit or the fourth small hit generated in the normal gaming state, the process proceeds to step S204. In addition, when the small hit where the seventh big hit that has ended is not the third small hit or the fourth small hit that occurred in the normal gaming state, that is, the first small hit or the second small hit that occurred in the normal gaming state or If it is the fifth small hit, the process proceeds to step S196.

  Then, after the process of step S197 or the process of step S205 is completed, the big hit type and the small hit type set (stored) in the big hit type buffer and the small hit type buffer are cleared (step S198), and the process ends.

  In step S206, 1 is subtracted from the value of the jackpot end display timer. Then, the CPU 56 checks whether or not the value of the jackpot end display timer is 0, that is, whether or not the jackpot end display time has elapsed (step S207). If not, the process ends.

  If the jackpot end display time has elapsed, the process proceeds to step 208, and the CPU 56 determines whether or not the jackpot end 1 designation command has been transmitted, that is, whether or not the gaming state after the jackpot is a short time (advantageous) state. (Step S208). If it is determined that the gaming state after the big hit is the short-time (advantageous) state, 100 is set as the initial value of the short-time count value (step S209), and after the advantageous state flag is set (step S210) Then, control is performed to transmit a time-short state designation command corresponding to the time-short (advantageous) state to the production control microcomputer 100 (step S211). On the other hand, if it is determined in step S208 that the gaming state after the big hit is not the short-time (advantageous) state, the process directly proceeds to step S212. Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S212).

  FIG. 62 is a flowchart showing an example of the normal symbol process executed in step S28 of FIG. In this normal symbol process, the CPU 56 first checks whether or not the detection signal from the gate switch 32a provided in the passage gate 32 is in the on state, so that the game ball has passed through the passage gate 32. It is determined whether or not (step S401). When the game ball passes through the passing gate 32 and the detection signal from the gate switch 32a is turned on (step S401; Yes), the process at the time of passing the gate is executed (step S402). On the other hand, when the detection signal from the gate switch 32a is in the off state (step S401; No), the process of step S402 is skipped.

  In the process at the time of passing through the gate executed in step S402, first, the number of reserved maps stored as the number of reserved data stored in the reserved map buffer of the RAM 55 is a predetermined upper limit value (for example, “4”). It is determined whether or not. At this time, if the number of stored customary drawings is an upper limit value, the current game ball detection is invalidated and the process at the time of passing the gate is terminated as it is. On the other hand, when the number of stored customary drawings is less than the upper limit value, for example, the CPU 56 displays numerical data indicating the random number value 4 for determining the normal display result from numerical data updated by the random counter. To extract. Then, the numerical data indicating the extracted random number value random 4 is set at the head of the empty entry in the ordinary reserved storage buffer. At this time, for example, it may be updated so that 1 is added to the common figure reserved memory number count value which is the count value in the common figure reserved memory number counter provided in the game control counter setting unit. After the above-described processing at the time of passing the gate, or after it is determined in step S401 that the detection signal from the gate switch 32a is in the off state, the following processing is performed according to the value of the usual process flag. Each process of steps S410 to S414 is executed.

The normal symbol normal process in step S410 is executed when the value of the normal symbol process flag is “0”. In this normal symbol normal process, it is determined whether or not the normal symbol display device 10 starts the normal symbol game based on the presence / absence of reserved data stored in the normal symbol storage buffer. At this time, for example, if there is pending data stored in the usual figure storage buffer, the value of the usual figure process flag is updated to “1”.

  The normal symbol determination process in step S411 is executed when the value of the normal symbol process flag is “1”. In this normal symbol determination processing, based on the numerical data indicating the random value random number 4 for determining the normal symbol display result, the normal symbol display result as the variable symbol display result of the normal symbol in the normal symbol game is set to “per normal symbol”. Or “unusual” is determined. Also, in the normal symbol determination process, the universal symbol change pattern corresponding to the universal symbol display result and the presence / absence of the advantageous state is also determined.

The normal symbol variation process in step S412 is executed when the value of the normal symbol process flag is “2”. In this normal symbol variation process, the normal symbol display device 10 is set to vary the normal symbol. The normal symbol that changes based on these settings is displayed in the normal symbol display result, which is a variable symbol display result of the normal symbol, when the normal symbol stop process in step S413 is executed. In the normal symbol variation process, the elapsed time from the start of variation of the normal symbol is measured. At this time, a determination is made as to whether or not the measured elapsed time has reached the normal time fluctuation time determined in accordance with the normal time fluctuation pattern. Then, when the usual figure change time is reached, the value of the usual figure process flag is updated to “3”.

The normal symbol stop process in step S413 is executed when the value of the normal symbol process flag is “3”. In this normal symbol stop process, the normal symbol display device 10 is set to stop and display the variable symbol display result of the normal symbol. Note that the setting for stopping and displaying the variable symbol display result of the normal symbol is the normal symbol process flag value when the measured elapsed time reaches the normal symbol variation time in the normal symbol variation process of step S412. It may be performed before updating to “3”. Further, in the normal symbol stop process, when the normal symbol display result is “per normal symbol”, a setting is made to drive the solenoid 16 provided corresponding to the second start winning opening 13b. The value of the process flag is updated to “5”. On the other hand, when the normal map display result is “out of normal map”, the value of the general map process flag is updated to “0”.

  The ordinary electric accessory actuating process of step S414 is executed when the value of the usual process flag is “4”. In this ordinary electric accessory actuating process, the movable wing piece provided in the second start winning port 13b is moved from the vertical position to the tilt position in response to the variable display result in the normal game being "per normal game". Thus, setting for changing the second start winning opening from the normal open state to the expanded open state is performed. For example, in the normal electric accessory operation process, a drive control signal for driving the solenoid 16 is generated in accordance with the setting of the normal electric operation pattern set in the normal symbol stop process in step S413. That's fine. Further, in the ordinary electric accessory actuating process, the elapsed time after the solenoid 16 is driven and the second start winning opening is set in the expanded open state is measured, and the elapsed time reaches the expanded open time corresponding to the normal operation pattern. A determination is made whether or not. When the elapsed time reaches the expansion opening period, the driving of the solenoid 16 is stopped, and the movable blade piece is returned from the tilting position to the vertical position, so that the second start winning opening is changed from the expansion opening state to the normal opening state. Set to change to. At this time, the value of the normal process flag may be updated to “0”.

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. FIG. 63 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of the ports 0, 1, and 2 input this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. The previous port buffer, port buffer, and switch-on buffer shown in FIG. 63 are prepared for each of the input ports 0, 1, and 2. For example, in this embodiment, two switch-on buffers 1, 2, and 3 are prepared, the switch state of the input port 0 is set to the switch-on buffer 1, and the switch state of the input port 1 is switched on. The buffer 2 is set, and the switch state of the input port 2 is set to the switch-on buffer 3.

  FIG. 64 is a flowchart showing a processing example of the switch processing in step S21 in the game control processing. In the switch process, the game control microcomputer 560 first inputs the data input to the input ports 0, 1, 2 (see FIG. 21) (step S101), and sets the input data in the port buffer (step S101). Step S102).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input ports 0, 1, and 2 are input again (step S106), and the logical product is performed bit by bit between the input data and the data set in the port buffer. (Step S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs a switch normal / abnormal check process (step S113).

  FIG. 65 is a flowchart showing a switch normal / abnormal check process. In the switch normal / abnormal check process shown in FIG. 65, the CPU 56 reads the contents of the switch-on buffer corresponding to the input port 1 (step S121). Then, it is confirmed whether or not the value of bit 0 corresponding to the first start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (step S122). That is, it is confirmed whether or not the first start port switch 14a (proximity switch) provided in the first winning path 1306a of the first start winning port 13a is turned on (detects a game ball).

  When the value of bit 0 corresponding to the first start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first start port switch 14a is in the on state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S123).

  Further, the CPU 56 checks whether or not the value of bit 1 corresponding to the first winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (step S124). That is, it is confirmed whether or not the first winning confirmation switch 14b (photo sensor) provided in the first winning passage 1306b of the first start winning opening 13a is turned on (detects a game ball).

  When the value of bit 1 corresponding to the first winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first winning confirmation switch 14b is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S125).

  Further, the CPU 56 checks whether or not the value of bit 2 corresponding to the second start port switch 15a in the switch-on buffer corresponding to the input port 1 is 0 (step S126). That is, it is confirmed whether or not the second start port switch 15a (proximity switch) provided in the second winning path 1307 of the second start winning port 13b is turned on (a game ball is detected).

  When the value of bit 2 corresponding to the second start port switch 15a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second start port switch 15a is in the ON state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S127).

  Further, the CPU 56 checks whether or not the value of bit 3 corresponding to the second winning confirmation switch 15b in the switch-on buffer corresponding to the input port 1 is 0 (step S128). That is, it is confirmed whether or not the second winning confirmation switch 15b (photo sensor) provided in the second winning passage 1307 of the second start winning opening 13b is turned on (detects a game ball).

  When the value of bit 3 corresponding to the second winning confirmation switch 15b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second winning confirmation switch 15b is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S129).

  Further, the CPU 56 checks whether or not the value of bit 4 corresponding to the lower count switch 23 in the switch-on buffer corresponding to the input port 1 is 0 (step S130). That is, it is confirmed whether or not the lower count switch 23 (proximity switch) provided in the lower big prize passage 1308 of the lower big prize opening 23b is turned on (detects a game ball).

  When the value of bit 4 corresponding to the lower count switch 23 in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the lower count switch 23 is in the ON state), the switch formed in the RAM 55 The counter value is incremented by 1 (step S131).

  Further, the CPU 56 checks whether or not the value of bit 5 corresponding to the third winning confirmation switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (step S132). That is, it is confirmed whether or not the third winning confirmation switch 23a (photo sensor) provided in the lower large winning passage 1308 of the lower large winning opening 23b is turned on (detects a game ball).

  When the value of bit 5 corresponding to the third winning confirmation switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the third winning confirmation switch 23a is in the ON state), it is formed in the RAM 55. The value of the switch counter that has been set is decremented by 1 (step S133).

  Further, the CPU 56 checks whether or not the value of the bit 6 corresponding to the upper count switch 24 in the switch-on buffer corresponding to the input port 1 is 0 (step S134). That is, it is confirmed whether or not the upper count switch 24 (proximity switch) provided in the upper big prize passage 1309 of the upper big prize opening 24b is turned on (detects a game ball).

  When the value of bit 6 corresponding to the upper count switch 24 in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the upper count switch 24 is in the ON state), the switch formed in the RAM 55 The counter value is incremented by 1 (step S135).

  Further, the CPU 56 confirms whether or not the value of the bit 7 corresponding to the fourth winning confirmation switch 24a in the switch-on buffer corresponding to the input port 1 is 0 (step S136). That is, it is confirmed whether or not the fourth winning confirmation switch 24a (photo sensor) provided in the upper large winning path 1309 of the upper large winning opening 24b is turned on (detects a game ball).

  When the value of the bit 7 corresponding to the fourth winning confirmation switch 24a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the fourth winning confirmation switch 24a is in the ON state), it is formed in the RAM 55. The value of the switch counter that has been set is decremented by 1 (step S137).

  Then, the CPU 56 checks whether or not the value of the switch counter is equal to or greater than a predetermined value (step S138). When the value of the switch counter is equal to or greater than a predetermined value, the CPU 56 goes to any one of the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b. Is determined to have occurred, and a predetermined time (in this example, 4 minutes) is set in the security signal information timer (step S139). In this embodiment, the CPU 56 sets a predetermined time (4 minutes in this example) to the security signal information timer based on the fact that the value of the switch counter is 20 or more as a predetermined value. To do. In this embodiment, the information output process (see S31) is executed based on the predetermined time set in the security signal information timer in step S138, whereby the first start winning opening 13a and the second start winning prize are obtained. When an abnormal winning is detected at the mouth 13b, the lower special winning opening 23b, and the upper special winning opening 24b, a security signal is externally output for a predetermined time (four minutes in this example).

  In the process of step S138, the CPU 56, for example, based on the fact that the value of the switch counter is 20 or more, the first start winning port 13a, the second starting winning port 13b, the lower large winning port 23b, the upper portion In addition to determining that an abnormal winning at the big winning opening 24b has occurred, conversely, even if the value of the switch counter is -20 or less, the first starting winning opening 13a and the second starting winning are also obtained. You may make it determine with the abnormal winning to the opening | mouth 13b, the lower large winning opening 23b, and the upper large winning opening 24b having generate | occur | produced. In this case, if the switch counter value is determined not to be a negative value, for example, 20 is set as the default value of the switch counter value. Based on the fact that the counter value becomes 0 or 40 or more, an abnormal winning occurs at the first starting winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b. You may make it determine.

  In this embodiment, even when a value is already set in the security signal information timer and the security signal is being output to the outside, if a new abnormal winning is detected, the process of step S139 is executed again. The security signal information timer is overwritten with a predetermined time (in this example, 4 minutes). Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example) from the time when the new abnormal winning is detected. 4 minutes) The output of the security signal is continued.

In this embodiment, when only one switch counter is used to detect an abnormal winning to the first starting winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b. The number of detections of the first start opening switch 14a and the number of detections of the first winning confirmation switch 14b or the number of detections of the second starting opening switch 15a and the number of detections of the second winning confirmation switch 15b or the lower count switch 23 Different switch counters may be used for the number of detections and the number of detections of the third winning confirmation switch 23a or the number of detections of the upper count switch 24 and the number of detections of the fourth winning confirmation switch 24a . In this case, for example, the value of the first switch counter is incremented by 1 each time the on state of the first start port switch 14a is detected, and every time the on state of the first winning confirmation switch 14b is detected. What is necessary is just to add 1 to the value of the counter for two switches. In step S138, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is equal to or greater than a predetermined value (for example, 20), the first start winning award 13a is entered. It may be determined that an abnormal winning has occurred and the process of step S139 is executed to output the security signal to the outside.

  If it is detected that an abnormal winning at the first start winning opening 13a has occurred, the process of step S139 is executed to output a security signal to the outside, and a predetermined error notification command is sent to the effect control microcomputer. It is desirable that error notification can be performed by displaying a predetermined error screen on the effect display device 9 on the effect control microcomputer 100 side.

  Further, for example, in addition to the abnormal winning at the first start winning opening 13a, the security signal is also detected when an abnormal winning at the other winning openings 29a, 29b, an abnormal magnetic error, an abnormal radio wave error, or a communication error is detected. When configured to output, a different error notification command for each type of error may be transmitted to the effect control microcomputer 100. Then, on the effect control microcomputer 100 side, error notification may be performed by causing the effect display device 9 to display different error screens for each type of error.

  In the above configuration, when power supply is resumed after the power supply to the gaming machine is stopped, an error notification is being issued before the power supply is stopped. The error notification command may be transmitted again to the effect control microcomputer 100. In other words, since the storage content such as RAM is not backed up by the backup power source on the production control microcomputer 100 side, if a power failure occurs, it is not possible to execute the production such as error notification that has been executed until then. However, the error notification can be resumed when the power failure is recovered by configuring the predetermined error notification command to be transmitted again when the power failure is recovered. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM. If the security signal is being output before the power supply is stopped, it is backed up when the power failure is restored. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent an illegal act such as turning off the error notification or stopping the output of the security signal by intentionally turning off the power to the gaming machine.

  66 and 67 are explanatory diagrams for explaining the switch normality / abnormality check processing. Among these, FIG. 66 shows an example of the switch normality / abnormality check process in a normal state, and FIG. 67 shows an example of the switch normality / abnormality check process when an illegal act leading to an abnormal winning is performed. Show.

  As shown in FIG. 66 and FIG. 67, for example, bit 0 of the switch-on buffer corresponding to input port 1 is “ 0 ”. The bit 1 of the switch-on buffer corresponding to the input port 1 becomes “0” when a game ball is detected by the first winning confirmation switch 14 b (photo sensor) corresponding to the bit 1. If the switch is operating normally and has not received any fraudulent activity (an act of illegally turning on a detection signal from the switch or illegally turning on an on-state detection signal), the first Since the start opening switch 14a is disposed upstream of the first winning confirmation switch 14b, the first starting opening switch 14a (proximity switch) is first turned on, and then the first winning confirmation switch 14b (photo sensor). ) Should turn on. Accordingly, the value of the switch counter is first incremented to 1 based on the first start port switch 14a being turned on (see step S123), and then the switch is based on the first winning confirmation switch 14b being turned on. The counter value is decremented by 1 and returned to 0 (see step S125). Therefore, when the game ball passes through the switch, both the bit 0 and the bit 1 of the switch-on buffer corresponding to the input port 1 are “0”, and if it is in a normal operation state, the count up timing is shifted ( As shown in FIG. 66, the value of the switch counter should be kept at 0, although this corresponds to a shift in the passing timing of game balls.

  However, when a fraudulent act by radio waves is performed, as shown in FIG. 67, the off state is illegally interrupted by radio waves during the period when the first start switch 14a is turned on once. There is a possibility that an illegal act of recognizing the starter switch 14a as if it has been turned on twice is performed. Therefore, although the first start port switch 14a is turned on only once, it is misrecognized that the first start port switch 14a is turned on twice, and the value of the switch counter is 2 in total. It is added to 2 (step S123 is executed twice). On the other hand, the first winning confirmation switch 14b arranged on the downstream side is different in detection method from the electromagnetic first start port switch 14a, and uses an optical photosensor. Unaffected by actions. Therefore, as shown in FIG. 67, when one game ball is detected by the first start opening switch 14a, when the game ball is detected on the first winning confirmation switch 14b side with a slight delay, the first winning game is normally completed. The ON state of the confirmation switch 14b is detected only once, and the value of the switch counter is decremented by 1 to 1 (see step S125). Therefore, when a fraudulent act by radio waves is performed, there is a difference in the number of detections between the first start opening switch 14a and the first winning confirmation switch 14b having different detection methods, as shown in FIG. On the other hand, based on the fact that the value of the switch counter is not kept at 0 and the value of the switch counter is equal to or greater than a predetermined value (20 in this example) (the first start port switch 14a and the first winning confirmation switch 14b). Based on the fact that the cumulative value of the detection error between the first and second winning prizes is equal to or greater than a predetermined value (20 in this example), it is possible to detect the occurrence of an abnormal winning at the first start winning opening 13a.

Here, an example is shown in which an abnormal winning to the first starting winning opening 13a is detected based on the detection result of the first starting opening switch 14a and the detection result of the first winning confirmation switch 14b. Based on the detection result of the switch 15a and the detection result of the second winning confirmation switch 15b, it is possible to detect an abnormal winning to the second start winning opening 13b. Further, it is possible to detect an abnormal winning to the lower large winning opening 23b based on the detection result of the lower count switch 23 and the detection result of the third winning confirmation switch 23a. Further, it is possible to detect an abnormal winning to the upper special winning opening 24b based on the detection result of the upper count switch 24 and the detection result of the fourth winning confirmation switch 24a .

  In addition, it is also conceivable that a similar illegal act is performed by an act of illegally irradiating light. In this case, during the period when the first winning confirmation switch 14b is turned on once, an illegal act that causes the off state to be illegally interrupted by light and to recognize that the first winning confirmation switch 14b is turned on twice. May be done. However, in this case, on the contrary, since the electromagnetic first start port switch 14a side can normally detect the game ball without being affected by the illegal act of light, the value of the switch counter is kept at 0 similarly. The accumulated value of the detection error between the first start port switch 14a and the first winning confirmation switch 14b is a predetermined value based on the fact that the value of the switch counter is not less than a predetermined value (20 in this example). It is possible to detect that an abnormal winning to the first start winning opening 13a has occurred (based on 20 in this example).

  In this embodiment, the outputs of the first start opening switch 14a and the first winning confirmation switch 14b are negative logic, but the outputs of the first starting opening switch 14a and the first winning confirmation switch 14b are shown. May be configured to be positive logic. In this case, for example, the output levels of the first start port switch 14a and the first winning confirmation switch 14b are logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  Further, in this embodiment, the value of the switch counter is not kept at 0 (a detection error has occurred between the first start port switch 14a and the first winning confirmation switch 14b) and immediately. It is not determined that an abnormal winning has occurred, but it is determined that an abnormal winning has occurred based on the value of the switch counter being equal to or greater than a predetermined value (20 in this example). Such a configuration prevents, for example, a case where a game ball has become clogged in the first start winning opening 13a from being determined as an abnormal winning due to an illegal act.

  FIG. 68 (a) is an explanatory diagram showing a case where a game ball is in a clogged state in the first winning paths 1306a and 1306b through which the game ball won in the first start winning opening 13a passes. As shown in FIG. 68 (a), in the first winning paths 1306a and 1306b, the first start port switch 14a and the first winning confirmation switch 14b are arranged at a certain distance in the vertical direction. Therefore, the game ball won in the first start winning opening 13a is first detected by the first start opening switch 14a, and then detected by the first winning check switch 14b on the downstream side after a while. Therefore, when the game balls are jammed in the first winning passages 1306a and 1306b, the number of detections is increased depending on the physical distance difference between the first start opening switch 14a and the first winning confirmation switch 14b. A difference occurs. In the first winning passages 1306a and 1306b, a maximum of five detection errors occur between the first start port switch 14a and the first winning confirmation switch 14b.

  FIG. 68 (b) is an explanatory diagram showing a case where the game ball is jammed in the second winning path 1307 through which the game ball won in the second start winning opening 13 b passes. As shown in FIG. 68 (b), in the second winning path 1307, the second start opening switch 15a and the second winning confirmation switch 15b are arranged at a certain distance in the vertical direction. Therefore, the game ball won in the second start winning opening 13b is first detected by the second start opening switch 15a, and then detected by the second winning check switch 15b on the downstream side after a while. Therefore, when a game ball is jammed in the second winning path 1307, there is a difference in the number of detections due to the physical distance difference between the second start port switch 15a and the second winning confirmation switch 15b. It occurs. In the second winning path 1307, a maximum of 14 detection errors occur between the second start port switch 15a and the second winning confirmation switch 15b.

  FIG. 68 (c) is an explanatory diagram showing a case where a game ball has become clogged in the lower big prize passage 1308 through which the game ball won in the lower big prize opening 23b passes. As shown in FIG. 68 (c), the lower count switch 23 and the third winning confirmation switch 23 a are arranged at a certain distance in the left and right and front and rear directions in the lower big prize passage 1308. Therefore, the game ball won in the lower big prize opening 23b is first detected by the lower count switch 23, and then detected by the third winning confirmation switch 23a on the downstream side after a while. Therefore, when the game ball is clogged in the lower big prize passage 1308, a difference in the number of detection is caused by a physical distance difference between the lower count switch 23 and the third prize confirmation switch 23a. It becomes a state. It is assumed that a maximum of four detection errors occur between the lower count switch 23 and the third winning confirmation switch 23a in the lower large winning path 1308.

  FIG. 68 (d) is an explanatory diagram showing a case where a game ball is in a clogged state in the upper ball path 406 through which the game ball won in the upper special winning opening 24 b passes. As shown in FIG. 68 (d), in the upper ball path 406, the upper count switch 24 and the fourth winning confirmation switch 24a are arranged at a fixed distance from side to side and up and down. Therefore, the game ball that has won the upper big winning opening 24b is first detected by the upper count switch 24, and then detected by the fourth winning confirmation switch 24a on the downstream side after a while. Therefore, when the game ball is clogged in the upper ball path 406, the difference in the number of detections is caused by the physical distance difference between the upper count switch 24 and the fourth winning confirmation switch 24a. It becomes. In the upper ball path 406, a maximum of 12 detection errors occur between the upper count switch 24 and the fourth winning confirmation switch 24a.

  In the present embodiment, the value of the switch counter is the upstream proximity of the plurality of winning paths (first winning paths 1306a, 1306b, second winning path 1307, lower large winning path 1308, upper ball path 406). Ball clogged state in the second winning path 1307 which is the winning path having the largest physical distance difference between the switch (14a, 15a, 23, 24) and the downstream photosensor (14b, 15b, 23a, 24a). An abnormal prize occurred based on the fact that the detection error of the second start opening switch 15a and the second prize confirmation switch 15b at the time became equal to or greater than a predetermined value (20 in this example) with a sufficient margin. Is determined, any one of the first prize paths 1306a and 1306b, the second prize path 1307, the lower large prize path 1308, and the upper ball path 406 is selected. Etc. If the game ball caused the ball clogging state is prevented from being determined as abnormal winning Fraud.

  In this embodiment, the predetermined detection value (20 in this example) is greater than or equal to 14 detection errors between the second start opening switch 15a and the second winning confirmation switch 15b in the ball jammed state. Although the case where it is determined that an abnormal winning has occurred based on the above is shown, the predetermined value used for determining the abnormal winning is not limited to that shown in this embodiment. For example, it is possible to prevent erroneous determination of an abnormal winning if the number is more than 14 detection errors between the second start opening switch 15a and the second winning confirmation switch 15b in the ball jammed state. Alternatively, it may be determined that an abnormal winning has occurred based on the value of the switch counter being 15 or more.

  In addition, when the detection errors in the ball clogged state in a plurality of winning paths are the same number (for example, 3), the detection error has become a predetermined value (for example, 10) or more with a sufficient margin for the three detection errors. Based on the above, it may be determined that an abnormal winning has occurred.

  In addition, when it is configured to be able to detect abnormal winnings in a plurality of winning paths, the total number of detection errors in the ball clogging state in all these winning paths (5 + 14 + 4 + 12 = 35) If an abnormal prize is determined by using a larger number (for example, 40) as a predetermined value, it is possible to prevent an abnormal prize from being erroneously determined.

  In the present embodiment, the detection error in the ball clogged state in the plurality of winning paths can be detected by one switch counter, so that no switching counter corresponding to each winning path is provided. However, it was possible to detect abnormal winnings in each winning path, but provided a switch counter corresponding to each winning path, set a predetermined value corresponding to the detection error for each winning path, The detection error in the switch counter may be monitored to determine whether or not there is an abnormal prize. By doing in this way, it becomes possible to specify in which winning path the winning abnormality has occurred.

  FIG. 69 is a block diagram showing various signals output to the terminal board 160. As shown in FIG. 69, in this embodiment, from the game control microcomputer 560 mounted on the main board 31 to the terminal board 160, the start port signal, the symbol determination number of times 1 signal, the jackpot 1 signal, the jackpot Two signals, three jackpot signals, a time reduction signal, and a security signal are output by information output processing (see step S31) on the game control microcomputer 560 side. In this embodiment, a prize ball signal 1 and a gaming machine error status signal are sent from the payout control microcomputer 370 mounted on the payout control board 37 to the terminal board 160 via the main board 31. Is output by the information output process (see step S759) on the payout control microcomputer 370 side.

  The starting port signal is a signal for notifying the number of winnings to the first starting winning port 13a and the second starting winning port 13b. The symbol determination number 1 signal is a signal for notifying the number of changes in the special symbol. The jackpot 1 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) is in progress. The jackpot 2 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) or that the special symbol variation time reduction function is being operated (during the short-time state). The jackpot 3 signal is a signal for notifying that a 15-round jackpot game is in progress. The time reduction signal is a signal for notifying that the special symbol variation time reduction function is operating (in the time reduction state).

  The security signal is a signal indicating the security state of the gaming machine. Specifically, based on the detection result of the first start opening switch 14a and the detection result of the first winning confirmation switch 14b, it is determined that an abnormal winning to the first start winning opening 13a has occurred, or the first 2 When it is determined that an abnormal winning to the second starting winning opening 13b has occurred based on the detection result of the starting opening switch 15a and the detection result of the second winning confirmation switch 15b, or the detection result of the lower count switch 23 And the detection result of the third winning confirmation switch 23a when it is determined that an abnormal winning to the lower large winning opening 23b has occurred, or the detection result of the upper count switch 24 and the detection of the fourth winning confirmation switch 24a. Based on the result, when it is determined that an abnormal winning to the upper special winning opening 24b has occurred, the security signal is displayed for a predetermined period (for example, 4 minutes). It is output to an external device such as a Le computer. Also, when the gaming machine is turned on and the initialization process is executed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  It should be noted that the signal output externally as the security signal is not limited to that shown in this embodiment. For example, not only abnormal winning to the first starting winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, the upper large winning opening 24b, but abnormal winning to the normal winning openings 29, 30 is detected, You may comprise so that external output is possible as a security signal. Also, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine, or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, the security signal can be output externally Also good. In addition, for example, when an abnormality of various switches provided in a gaming machine is detected (for example, when an occurrence of a short circuit is detected by determining that an input value exceeds a threshold value), it can be externally output as a security signal. You may comprise as follows. As such, if the abnormal winning, the abnormal magnetic error, and the abnormal radio wave error in the upper special winning opening 24b and the lower special winning opening 23b are configured to be externally output as security signals from the common connector CN7 of the terminal board 160. If only one signal line is connected, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In addition, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the security signal can be externally output from the common connector CN7 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN7 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN7 of the terminal board 160.

  In addition to the signal line and connector CN7 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  The prize ball signal 1 is a signal that is output every time one prize ball payout is detected. Further, the gaming machine error state signal is a signal indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). Instead of outputting the prize ball signal 1 to the outside every time one prize ball is detected, a certain prize ball signal is outputted every time a predetermined number (for example, 10) of prize balls is detected. Also good.

  70 to 73 are flowcharts showing the information output process of step S31. Of the processes shown in FIGS. 70 to 73, steps S1002 to S1030 are processes for outputting the start port signal, and steps S1031 to S1036 are processes for outputting the symbol determination number 1 signal. S1050 to S1068 are processes for outputting one jackpot signal, two jackpot signals, three jackpot signals and a short time signal. Steps S1069 to S1074 are processes for outputting a security signal.

  In the information output process, the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1001). Then, the address of the start port information setting table is set in the pointer (step S1002), and the number of processes pointed to by the pointer is loaded (step S1003). The number of processes (= 1) and the start port switch input bit (start port switch input bit determination value (01 (H)) are set in the start port information setting table. In step S1003, the pointer is set to the start port information setting. Since the address of the number of processes in the table is indicated, the data of the number of processes (= 1) in the start port information setting table is loaded.If the gaming machine has two start winning ports, In the start port information setting table, 2 may be set as the number of processes, and start port switch input bits for the two start winning ports may be set respectively.

  Next, the CPU 56 loads the contents of the switch-on buffer into the register (step S1004), and sets the switch-on buffer as switch input data (step S1005). The pointer is incremented by 1 (step S1006), the start port switch input bit pointed to by the pointer is loaded into the register (step S1007), and the logical product of the start port switch input bit and the switch input data is obtained (step S1008). When the content of the switch-on buffer is 01 (H), that is, when the first start port switch 14a or the second start port switch 15a is on, the logical product operation result is 01 (H). When the first start port switch 14a or the second start port switch 15a is not turned on, the operation result of the logical product is 00 (H).

  If the logical operation result is 0 (Y in step S1009), the process proceeds to step S1015. If the result of the logical product is not 0 (N in step S1009), it is determined that a winning has occurred in the first starting winning port 13a or the second starting winning port 13b, and the starting port information storage counter is loaded into the register. (Step S1010). The start port information storage counter is a counter that counts the number of remaining outputs of the start port signal (that is, the remaining number of start winnings that have not been output from the start port signal). Next, the CPU 56 adds 1 to the start port information storage counter (step S1011). Then, it is confirmed whether the calculation result (added result) is not 0 (step S1012). When the calculation result is 0 (N in step S1012), 1 is subtracted from the calculation result (step S1013). Then, the calculation result is stored in the start port information storage counter (step S1014).

  Next, the CPU 56 subtracts 1 from the number of processes (step S1015), and determines whether the number of processes is not 0 (step S1016). When the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine has only one first start winning opening 13a, 1 is set as the initial value of the processing number, and it is always determined that the processing number is 0 in step S1016. Will be.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 loads the start port information storage timer (step S1017), and reflects the state of the start port information storage timer in the flag register. (Step S1018), it is determined whether or not the start port signal is being output (step S1019). The start port information storage timer is a timer for measuring an on time and an off time (for example, an on time of 200 ms and an off time of 200 ms) of the start port signal. If the value of the start port information storage timer is not 0, it is determined that the start port signal is being output. If the value of the start port information storage timer is 0, it is determined that the start port signal is not being output.

  If the start port signal is being output (Y in step S1019), the process proceeds to step S1026. If the start port signal is not being output (N in step S1019), the CPU 56 loads the start port information storage counter (step S1020), and reflects the state of the start port information storage counter in the flag register (step S1021). Then, it is determined whether there is a remaining number of output times of the start port signal (step S1022). When the first start port switch 14a or the second start port switch 15a is turned on (N in step S1009), the start port information storage counter is incremented by 1, so there is a remaining number of output times of the start port signal. It will be determined.

  If there is no remaining number of output times of the start port signal (Y in step S1022), the process proceeds to step S1031. If there is a remaining number of output times of the start port signal (N in Step S1023), the CPU 56 subtracts 1 from the start port information storage counter (Step S1023), and the calculation result (the result of subtracting 1) is the start port information storage counter. (Step S1024). Then, the winning information operating time (100) is set in the register (step S1025). The winning information operating time (100) is a time for which a 4 ms timer interruption is executed 100 times, that is, a time of 0.400 seconds (400 ms).

  Next, if the winning information operating time is not set in step S1025, the CPU 56 subtracts 1 from the start port information storage timer, and if the winning information operating time is set in step S1025, the CPU 56 subtracts 1 from the winning information operating time. (Step S1026). Then, the calculation result (result obtained by subtracting 1) is stored in the start port information storage timer (step S1027).

  The CPU 56 compares the calculation result with the winning information on time (50) (step S1029), and determines whether the calculation result is shorter than the winning information on time (step S1030). The winning information on time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms).

  When the calculation result is not shorter than the winning information on time, that is, when the calculation result (remaining time of the start port 1 information storage timer) is longer than the winning information on time (200 ms) (N in step S1029). The CPU 56 sets the start port output bit position of the information buffer (bit 0 of the output port 1 in the example shown in FIG. 20) (step S1030). When the start port output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Will be output.

  By the processing of steps S1001 to S1030 described above, winning to the first start winning opening 13a (turning on the first start opening switch 14a) or winning to the second starting winning opening 13b (turning on the second start opening switch 15a) ) Occurs, a start port signal is output. That is, after the start port signal is turned on for 200 ms, it is turned off for 200 ms. By inputting this start port signal to the hall computer, it is possible to recognize the number of winnings to the first start winning port 13a or the second starting winning port 13b.

  Since the start port signal is turned on for 200 ms and then turned off for 200 ms, the next start port is turned off after the 200 ms off state even when a start winning is continuously generated in a short time. A signal is output. That is, the start port signals are output at intervals of at least 200 ms.

  Thus, since the start port signals are output at intervals of at least 200 ms, the hall computer can reliably grasp the total number of start winnings.

  Next, the CPU 56 loads the symbol determination number 1 information timer into the register (step S1031), reflects the state of the symbol determination number 1 information timer in the flag register (step S1032), and the symbol determination number 1 information timer times out. It is determined whether or not (step S1033). In this embodiment, in the special symbol variation process (see step S302), when the variation time times out, when the variation of the special symbol is stopped, the symbol determination number 1 information timer outputs the symbol determination number output time (in this example, 0). .500 seconds) is set, and when the symbol determination count output time has not elapsed, it is determined that the symbol determination count 1 information timer has not timed out, and when the symbol determination count output time has elapsed (symbol determination count) When the value of the 1 information timer is 0), it is determined that the 1 symbol information timer has timed out.

  If the symbol determination count 1 information timer has not timed out (N in step S1033), the symbol determination count 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination count 1 information timer (step S1035). . Then, the design buffer count 1 output bit position of the information buffer (bit 1 of output port 1 in the example shown in FIG. 20) is set (step S1036). When the symbol determination number 1 output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Is output from the output port 1 (becomes ON state). If the symbol determination number 1 information timer times out (Y in step S1033), the process of step S1036 is not executed, and as a result, the symbol determination number 1 signal is turned off.

  By the processing of steps S1031 to S1036 described above, every time the change of the special symbol is stopped (stopped symbol is fixed), the symbol determination number 1 signal is turned on.

  Next, the CPU 56 loads the special symbol process flag (step S1050), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1051), and the special symbol process flag. It is determined whether the value of is less than 4 (step S1052). When the value of the special symbol process flag is less than 4 (Y in step S1052), the process proceeds to step S1058. When the value of the special symbol process flag is 4 or more (N in step S1052), the output bit position of the big hit in the information buffer is set (step S1053). Further, the big output 2 output bit position of the information buffer is set (step S1054). When one output bit position of jackpot and two output bit positions of jackpot of the information buffer are set, the information buffer is set to an output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. One signal and two jackpot signals are output from the output port 1 (become turned on).

  Further, the CPU 56 executes a time reduction check process for confirming whether or not it is in the time reduction state (step S1058), and determines whether or not it is in the time reduction state (step S1059). Specifically, the CPU 56 determines whether or not it is in the time reduction state by checking whether or not the time reduction flag that is set when shifting to the time reduction state is set. If the time-short state is set (Y in step S1059), the time-short output bit position of the information buffer is set (step S1060). When the time-short output bit position is set, the time buffer signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102 and outputting the output value to the output port 1 in step S1103. (Turns on) Also, the big output 2 output bit position of the information buffer is set (step S1061). When the jackpot 2 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, whereby the jackpot 2 signal is output from the output port 1. (Turns on).

  In addition, the CPU 56 loads the special symbol process flag (step S1062), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1063), and sets the special symbol process flag. It is determined whether or not the value is less than 4 (step S1064). When the value of the special symbol process flag is less than 4 (Y in step S1064), the process proceeds to step S1069. When the value of the special symbol process flag is 4 or more (N in step S1064), the contents of the big hit symbol determination buffer are loaded (step S1065), and it is confirmed whether or not it is a big hit of 15 rounds (step S1067). . Whether or not it is a big hit of 15 rounds can be determined, for example, by confirming the contents of the big hit symbol determination buffer set in the special symbol normal process. For example, the jackpot symbol determination buffer stores the contents of the jackpot type determined by the special symbol normal processing and the contents indicating the jackpot determination result. For example, “1” is a normal jackpot, “2” is a probable bonus jackpot, “3” is suddenly a big hit. If the contents of the big hit symbol determination buffer are “1” or “2”, it is determined that the number of rounds at the big hit is 15 rounds. In this case, the big output 3 output bit position of the information buffer is set (step S1068). When the jackpot 3 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, so that the jackpot 3 signal is output from the output port 1. (Turns on).

  By the processing of steps S1050 to S1068 described above, one big hit signal, two big hit signals, three big hit signals, and a short time signal are output (turned on) according to the type of big hit and the gaming state.

Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070). S1071). In this embodiment, the detection difference between the start opening switches 14a and 15a and the lower count switch 23, the upper large winning opening 24b and the first to fourth winning confirmation switches 14b, 15b, 23a and 24a is a predetermined value (in this example). 20) When it is determined that the above has been reached and it is determined that an abnormal winning at the start winning prize opening or the big winning prize has occurred, a predetermined time (4 minutes in this example) is set in the security signal information timer ( In steps S126 and S127 in the switch normality / abnormality check process), when the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (security signal information timer) When the value of is 0), it is determined that the security signal information timer has timed out.

  In this embodiment, when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer (in the main process). When the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the calculation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position of the information buffer (bit 7 of output port 1 in the example shown in FIG. 20) is set (step S1074). When the security signal output bit position of the information buffer is set, the security signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102, and outputting the output value to the output port 1 in the step S1103. Is output (turns on). If the security signal information timer times out (Y in step S1071), the security signal is turned off as a result of not executing the process in step S1074.

  4 minutes have elapsed since the abnormal winnings to the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b are detected by the processing of steps S1069 to S1074 described above. The security signal is output using the common connector CN7 of the terminal board 160 until 30 seconds have elapsed since the initialization process was executed at the start of power supply to the gaming machine. If a new abnormal prize is detected during the output of the security signal, the output of the security signal is continued until 4 minutes have elapsed since the last abnormal prize was detected.

Next, the security signal output timing will be described. FIG. 74 is an explanatory diagram showing the output timing of the security signal. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 to S14), a predetermined time (in this example, 30 seconds) is set in the security signal information timer. Based on the above (see step S14a), the processing of steps S1069 to S1103 is executed in the information output process (see step S31). As shown in FIG. 74A, from the connector CN7 of the terminal board 160, the hall computer or the like A security signal is output to the external device. In addition, after the power supply to the gaming machine is started, the number of detections of the start port switches 14a, 15a and the lower count switch 23, the upper count switch 24 and the first to fourth winning confirmation switches 14b, 15b, 23a, 24a Based on the fact that the detection error with respect to the number of detections is equal to or greater than a predetermined value (20 in this example), to the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b. Even when it is determined that an abnormal prize has occurred (see steps S121 to S126), based on the fact that a predetermined time (4 minutes in this example) is set in the security signal information timer (see step S127), In the information output process (see step S31), the processes of steps S1069 to S1103 are executed, and as shown in FIG. The connector CN7 outputs a security signal to an external device such as a hall computer. As described above, in this embodiment, when the initialization process is executed when power supply to the gaming machine is started, the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, the upper large winning opening A security signal is externally output from the common connector CN7 of the terminal board 160 when an abnormal winning to the winning opening 24b is detected.

Further, in this embodiment, when the security signal is being output externally, a new abnormal winning to the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b is newly performed. Is detected, the security signal output period is substantially extended, and finally, the first prize winning opening 13a, the second starting prize opening 13b, the lower big prize opening 23b, and the upper big prize opening 24b are abnormally awarded. The output of the security signal is continued until a predetermined time (in this example, 4 minutes) elapses from the time point at which is detected. For example, in the case where the output of the security signal is started based on the fact that the initialization process is executed when the power supply to the gaming machine is started, as shown in FIG. 74 (A), until 30 seconds have elapsed in principle. Security signal output should continue. However, as shown in FIG. 74 (B), even before 30 seconds have elapsed, the detected numbers of the start port switches 14a and 15a, the lower count switch 23, and the upper count switch 24 and the first to fourth winning prizes. The detection error with the number of detection of the confirmation switches 14b, 15b, 23a , 24a becomes equal to or greater than a predetermined value (20 in this example), and the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, the upper part There is a possibility that it is determined that an abnormal winning to the big winning opening 24b has occurred. In this case, a predetermined time (in this example, 4 minutes) is overwritten and written in the security signal information timer based on the detection of the occurrence of the abnormal winning (see step S127), and the information output process (step S31). Step S1069 to S1103 are executed, and the output of the security signal is continued as shown in FIG. 74B. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 74 (B), the first start winning opening 13a, the second starting winning opening 13b, and the lower grand prize are received. The output of the security signal is continued until 4 minutes have elapsed from the time when the abnormal winning to the mouth 23b and the upper special winning opening 24b is detected, and the output of the security signal is substantially extended.

Also, for example, when the output of the security signal is started based on the detection of the abnormal winning to the first starting winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b. As shown in FIG. 74A, in principle, the output of the security signal should be continued until 4 minutes have passed. However, as shown in FIG. 74 (C), even before the lapse of 4 minutes, the detected numbers of the start port switches 14a and 15a, the lower count switch 23, and the upper count switch 24 and the first to fourth winning prizes. The detection error with the number of detections of the confirmation switches 14b, 15b, 23a , 24a becomes equal to or greater than a predetermined value (20 in this example), and the first start winning opening 13a, the second starting winning opening 13b, and the lower large winning opening 23b, there is a possibility that it is determined that an abnormal winning to the upper big winning opening 24b has occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the newly detected occurrence of an abnormal winning (see step S127), and information output processing ( In step S31), the processing of steps S1069 to S1103 is executed, and the output of the security signal is continued as shown in FIG. 74C. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 74 (C), the first start winning port 13a, the second starting winning port 13b, and the lower portion are newly added. The output of the security signal will be continued until 4 minutes have elapsed since the time of detecting the abnormal winning at the big prize opening 23b and the upper big prize opening 24b, and the output of the security signal is substantially extended. Become.

  If an abnormal winning is detected at the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b while the security signal is already being output, Although it is conceivable that the output of the next security signal is started again after the output of the security signal is finished, in this embodiment, as shown in FIGS. 74 (B) and 74 (C). In addition, by extending the output time of the security signal being output as it is, the processing load for the security signal output process is reduced and the program capacity for the security signal output process is reduced. In other words, when it is configured to start the output of the next security signal after the output of the security signal being output is completed, the output of the next security signal is started after the output of the security signal is completed. For example, a process for measuring the interval time until completion is required, which increases the processing load and the program capacity. In contrast, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S14a and S127), the security signal is output. It is possible to prevent the increase in processing load and program capacity.

  In this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, a security signal is output for 30 seconds, and the first start winning opening 13a and the second starting winning opening 13b are output. In the present embodiment, the case where the security signal is output for 4 minutes when the abnormal winning to the lower big winning opening 23b and the upper big winning opening 24b is detected is shown. It is not limited to what is shown. That is, whether the initialization process has been executed or whether an abnormal winning is detected in the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, or the upper large winning opening 24b. Recognizable, the case where the initialization process is executed is different from the case where abnormal winning is detected in the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b. What is necessary is just to output a security signal over an output time.

  In this embodiment, the output period of the security signal when an abnormal winning to the first starting winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b is detected is 4 minutes. In the case of abnormal winning at the first starting winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b, a security signal is output for as long as possible. Therefore, it is a substantially maximum time that can be set. That is, in this embodiment, since the game control microcomputer 560 can set a 2-byte value as the value of the security signal information timer, the maximum value is set to “FFFF (H) = 65535 in the security signal information timer. "Can be set. Therefore, in this embodiment, “60000”, which is almost the maximum value, is set in the security signal information timer, and the timer interruption period is 4 ms. Therefore, security is performed for 4 ms × 60000 = 4 minutes. A signal is output.

Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 75 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 75, the output port 0 outputs a signal of each phase supplied to the payout motor 289 by the stepping motor. In addition, a PRDY signal or an EXS signal is output from the output port 0 to the card unit 50, and a game indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). A machine error state signal and a prize ball signal 1 indicating that a prize ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by 7 segment LED is output. The output port 1 also outputs prize ball information indicating that ten prize ball payouts have been detected.

  FIG. 76 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 76, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 77 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 380. In this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. Further, in the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for Further, as described above, a part of the initial setting of the serial communication circuit 380 is executed in the built-in device register setting process in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 78 is a flowchart showing an example of timer interruption processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process of detecting the state of bits 0 to 7 (see FIG. 76) of the input port 0 and reflecting the detection result in a predetermined 1 byte of the RAM (referred to as a sensor input state flag). The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S754). Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. A payout control process to be executed is executed (step S755).

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

Next, the payout control CPU 371 executes error processing for detecting various errors (step S757). Next, the payout control CPU 371 executes a prepaid card unit error control process for performing error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes information output processing for outputting prize ball information to the main board 31 and outputting the prize ball signal 1 and the gaming machine error state signal to the outside (step S759). Further, a display control process for performing a predetermined display on the error display LED 374 according to the result of the error process is executed (step S760).

In the present embodiment, when various errors (for example, a payout number error error, a full tank error, a ball shortage error, a prepaid card unit unconnected error) are detected in error processing to be described later, an error corresponding to the detected error is detected. Bit is set. Then, in the display control process in step S760, it had One that error bit is set, the payout control CPU371 performs predetermined display in the error display LED 374.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer include a payout motor control process (step S756), a prepaid card control process (step S753), a main control communication process (step S754), an information output process (step S759), and a display control process ( It is updated in step S760).

  FIG. 79 is a flowchart showing the main control communication process in step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 80 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command reception process, the payout control CPU 371 first checks whether or not a connection signal is input (step S7401). If no connection signal is input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S7402). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is under an abnormal state. It is possible to prevent a situation where data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S7403), and checks whether or not the value of the main control communication control code is a value “0” indicating the main control connection confirmation process. (Step S7404).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S7404, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, when the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S7404, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S7405). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. Then, the payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S7406). If it is determined in step S7404 that the value of the main control communication control code is “0” indicating the main control connection confirmation process, the process proceeds to step S7406).

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that a connection signal is not input in step S7401, if the main control connection confirmation process is not being executed in step S7404, the connection signal is not displayed after power is turned on to the gaming machine. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S7406), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this example) has elapsed since the connection OK command was transmitted, the connection confirmation command and the prize ball number command are received from the game control microcomputer 560. If not, it is determined that some communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and the connection state with the game control microcomputer 560 is confirmed again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S7407). For example, the payout control CPU 371 receives the serial communication circuit 380 if a flag indicating a parity error, framing error, noise error, overrun error, or idle line error is set in the status register of the serial communication circuit 380. It is determined that there is an error state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S7408). In this way, by initializing the receiving circuit of the serial communication circuit 380 in the case of a reception error state, it is possible to prevent a situation in which a reception command is stored in the reception data register even though some reception abnormality has occurred. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S7409).

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S7410) and checks whether or not a connection confirmation command is received (step S7411). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 29). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S7414.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 29, the contents of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is greater than or equal to the prize ball number command minimum value “51 (H)” (step S7412). Next, if the prize ball number command minimum determination value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum determination value “60 (H)”. It is confirmed whether or not (step S7413). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S7414.

  In step S7414, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interrupt period (1 ms in this example) in the payout control microcomputer 370 is equal to the timer interrupt period (in this example, the game control microcomputer 560). 4 ms), a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and the main control communication normal process cannot be performed. Can be prevented.

  FIG. 81 is a flowchart showing a main control connection confirmation process (step S741) executed when the value of the main control communication control code is 0. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) to the main control communication control timer (step S7417).

  82 and 83 are flowcharts showing the main control communication normal process (step S742) executed when the value of the main control communication control code is 1. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, the fact that the main control communication control timer has timed out in step S7402 means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S7409) elapses well after 1 second from the transmission of the connection OK command. This is a case where reception was not possible. For this reason, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S7403), and returns to the main control connection confirmation process to wait for the recovery of the communication state. To do.

  The payout control CPU 371 clears the main control communication reception buffer if the main control communication control timer has timed out in step S74202. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the connection OK command in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If no BRDY signal is input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. In other words, in this case, any error condition has occurred, or during the winning ball payout operation, the ball lending payout operation, or the ball lending preparation, so the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a command for preparing a prize ball (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  FIG. 84 and FIG. 85 are flowcharts showing the main control communication in-process (step S743) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a winning ball preparing command in order to transmit the next winning ball preparing command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, the command for preparing the next prize ball is not yet ready if the prize ball payout operation cannot be started after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal has been input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, and the processing is ended as it is. In this embodiment, since the next award ball number command is transmitted after the award ball payout operation is finished and the award ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer. This is to prevent inconvenience in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparation command is transmitted.

  FIG. 86 is a flowchart showing a main control communication end process (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process that is executed after receiving a prize ball number command and starting a prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74414). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74414, the command for preparing the next prize ball is transmitted if the prize ball payout operation is not yet completed after one second has passed. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 87 is a flowchart showing main control transmission command conversion processing executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets a main control communication payout number error error output bit (specifically, bit 3) in the conversion buffer (step S732).

  Next, the payout control CPU 371 checks whether or not the ball break error designation bit is set (step S733). If the ball-out error designation bit is set, the payout control CPU 371 sets the main control communication ball-out output bit (specifically bit 2) in the conversion buffer (step S734).

  Next, the payout control CPU 371 checks whether or not the full error designation bit is set (step S735). If the full error specification bit is set, the payout control CPU 371 sets the full output bit for main control communication (specifically bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 checks whether or not other prize ball error designation bits are set (step S737). Specifically, the payout control CPU 371 includes a main control communication error designation bit, a main control unconnected error designation bit, a withdrawal switch abnormality detection error 1 designation bit, a withdrawal switch abnormality detection error 2 designation bit, a withdrawal in the error flag. Check if the case error specification bit is set. If any other prize ball error designation bit is set, the payout control CPU 371 sets a main control communication ball out output bit (specifically bit 0) in the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or prize ball preparing command) set for transmission (step S739).

  FIG. 88 is a flowchart showing the payout control process in step S755. In the payout control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S7501), and checks whether the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid number counter is 0, the payout control CPU 371 adds 1 to the value of the payout number abnormality counter for counting the cumulative number of abnormal payouts (step S7503). In other words, Y in step S7502 means that the unpaid number to be paid out is not set in the unpaid-out number counter, so that the payout operation is performed even though the game ball should not be paid out. And the payout count switch 301 detects the payout of the game ball. For this reason, there is a possibility that the payout operation has been performed by some kind of fraud, so the payout control CPU 101 cumulatively adds 1 to the value of the payout number abnormality counter.

  The payout number abnormality counter indicates the number of payouts exceeding the number of unpaid game balls to be paid out and the number of payout shortages that did not meet the number of unpaid game balls to be paid out. This is a counter for cumulatively counting. As will be described later, in this embodiment, when the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), it is determined that a payout number error has occurred and the payout is stopped. Processing to control the state is performed. Note that the process of step S7503 corresponds to a process of cumulatively counting the excess payout in the payout number abnormality counter.

  In this embodiment, without distinguishing whether the ball is a winning ball or a lending ball, the payout excess number and the payout shortage number are cumulatively counted in the payout number abnormality counter. For only one of the rented balls, the excessive payout and the shortage payout may be cumulatively counted in the payout number abnormality counter. Further, for example, with respect to prize balls and lending balls, it is possible to cumulatively count the excess payout and the shortage payout using separate counters. In this case, it may be determined that a payout number error occurs when the value of one of the counters reaches a predetermined threshold value, or a payout number error error when the total value of both counters reaches a predetermined threshold value. May be determined.

  Further, in this embodiment, the case where the value of the payout number abnormality counter is incremented by 1 when an excessive payout is detected in step S7503 has been shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excessive payout number may be subtracted from the value of the payout number abnormality counter, and the insufficient payout number may be added to the value of the payout number abnormality counter. In this case, for example, the payout control CPU 371 sets “2000” as the initial value in the payout number abnormality counter in the initial setting process when the power is turned on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. In steps S75320, S75325, and S75335, which will be described later, a value corresponding to the insufficient payout number may be added to the value of the payout number abnormality counter. For example, in the processing of steps S7504, S75321, and S7725 described later, it may be determined that a payout number error has occurred based on the value of the payout number error counter being 2000 or less.

  Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7504). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payouts detected is cumulatively managed on the payout control microcomputer 370 side, and if the accumulated value is equal to or greater than a predetermined payout number abnormal error determination value (for example, 2000), It is determined that there is an extremely high possibility that a payout operation is being performed due to some sort of fraud, and it is determined that a payout number abnormality error (an error indicating that the number of game balls paid out is abnormal) has occurred. In addition, there are not a few cases where game balls are paid out excessively or insufficient due to malfunctions, etc., so when an abnormality in the number of payouts is detected, it is immediately determined as a payout number error. The frequency determined to be a payout number abnormality error becomes higher than necessary, and the game is hindered. Therefore, in this embodiment, the number of abnormal payouts detected is cumulatively managed, and the payout number abnormality error is determined on the condition that the accumulated value is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000). By determining, it is prevented that it is determined that the payout number abnormality error is more than necessary.

  In this embodiment, if it is determined that there is a payout number error and the payout number error error flag is set once, the payout number error error flag is not cleared until the power is reset. When the payout number abnormality error flag is set, the processes in steps S7504 and S7505 and the processes in S75321, S75322, S7725, and S7726 described later may not be executed. By doing so, it is possible to prevent useless processing after it is once determined that the payout number abnormality error has occurred, and to reduce the processing burden.

  Further, in this embodiment, “2000” corresponding to the number of game balls that can be stored in a game ball storage box (so-called dollar box) generally used in a game store is set as a predetermined payout number abnormality error determination value. Although the case where it uses is shown, other values (for example, 1000 or 3000) may be used as the predetermined payout number abnormality error determination value.

  In this embodiment, the payout control process shown in FIG. 88 is a process that is commonly executed when the prize ball payout operation is executed and when the lending ball payout operation is executed. This counter is used in common when counting the number of game balls that have not been paid out with prize balls and when counting the number of game balls that have not been paid out with lending balls. When an abnormality in the number of payouts is detected, the value of the payout number abnormality counter is incremented without distinguishing between payout with a prize ball and payout with a lending ball, and whether or not a payout number abnormality error has occurred. A determination is made.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid-out number counter (step S7506), and a payout ball detection designation bit (game ball payout) is added to the flag of the payout control state. A bit indicating detection) is set (step S7507). The payout ball detection designation bit is a bit that is set when the payout number count switch 301 is turned on, and indicates that the payout number count switch 301 has detected at least one game ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes any one of steps S7511 to S7513 according to the value of the payout control code.

  FIG. 89 is a flowchart showing the payout start waiting process (step S7511) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first checks whether or not the value of the error flag is 0 (step S75101). If an error bit (one or more of all error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, by executing the process of step S75101, it is determined that there is a payout number abnormal error, and the payout number abnormal error designation bit of the error bit is set, so that the steps after step S75102 are set. Control is performed so as not to shift to processing, and the payout is stopped.

  If the value of the error flag is 0, the payout control CPU 371 checks whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and checks whether or not a ball lending request is being made (step S75104). Specifically, the payout control CPU 371 checks whether or not a ball lending request specifying bit (a bit indicating that a ball lending request is being made) is set in the payout control state flag. The payout control CPU 371 may determine whether or not a ball lending request is being made by confirming whether or not a BRQ signal is input. If a ball lending request is being made (that is, when a ball lending payout operation is started), the payout control CPU 371 resets the ball lending request specifying bit in the payout control state flag (step S75105) and at the same time a payout control state flag. The designated bit during the ball lending / dispensing operation is set (step S75016). Next, the payout control CPU 371 sets a predetermined ball lending number (25 in this example) in the unpaid number counter (step S75107) and a predetermined ball lending number (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, control goes to a step S75113.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  If the BRDY signal is not input, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S75109). If the value of the unpaid number counter is not 0 (that is, when the prize ball payout operation is started), the payout control CPU 371 sets the value of the unpaid number counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of prize balls designated by the received prize ball number command should be set in the unpaid quantity counter (see steps S74214 and S74319), the prize ball dispensing operation is started. Then, a process of setting the number of winning balls in the payout motor rotation frequency buffer is performed. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball paying-out operation designation bit in the payout control state flag (step S75112). Then, control goes to a step S75113.

  In step S75113, the payout control CPU 371 sets a value in the payout motor control code for selecting a process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process in step S756, a payout motor starting process for starting the payout motor 289 is executed, and a lending ball payout operation or a prize ball payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 90 is a flowchart showing a payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether or not the payout operation is completed (step S7522). Specifically, the payout control CPU 371 checks whether or not a payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake process and the payout motor ball biting release process in the payout motor control process in step S756 shown in FIG.

  In the payout motor control processing, the payout control CPU 371 performs payout motor normal processing (processing such as setting the pointer at the head address of the table stored in the ROM), payout, according to the value of the payout motor control code. Motor start-up processing (processing such as setting the initial value of the excitation pattern in bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), payout motor slow-up processing (starting the rotation of the payout motor 289 smoothly) Therefore, the output state of the output port 0 is read out by reading the contents of the payout motor excitation pattern table at intervals longer than those in the case of constant speed processing and gradually approaching the time intervals in the case of constant speed processing. , Processing of setting bits 4 to 7 in the port 0 buffer corresponding to), payout motor constant speed processing (periodic payout motor excitation pattern) The process of reading the contents of the table and setting the bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), the dispensing motor brake process (the constant speed process to smoothly stop the dispensing motor 289) Port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at intervals longer than those in the case of, and gradually away from the time interval in the case of constant speed processing Processing of setting the bits 4 to 7), the payout motor ball biting process (when the ball biting state is detected, in order to release the ball biting, the contents of the payout motor excitation pattern table are read and the output port 0 is set. Processing to set bits 4 to 7 in the port 0 buffer corresponding to the output state), and the payout motor ball biting release processing (ball biting state is released) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the payout operation has been completed, the payout control CPU 371 resets the payout operation end designation bit of the payout control state flag (step S7523) and stops the payout motor used for setting a payout passage monitoring time to be described later. The waiting process setting table 2 is set (step S7524).

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S7525). The designated number of paid-out balls inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). If the payout ball number inspected designation bit is set, the process proceeds to step S7527. If the payout ball number inspected designation bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S7524 with a payout motor stop waiting process setting table. Then, control goes to a step S7527.

  In step S7527, the payout control CPU 371 sets a value “2” indicating payout passing waiting processing in the payout control code. The payout control CPU 371 sets the payout passing monitoring time in the payout control timer based on the table set in steps S7524 and S7526 (step S7527). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. In this embodiment, when the payout ball number inspected bit is set in step S7525, 1 second is set as the payout passing monitoring time based on the payout motor stop waiting process setting table 2 set in step S7524. To do. If the paid ball number inspected bit is not set in step S7525, 0.6 seconds is set as the payout passing monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  91 to 93 are flowcharts showing the payout passing waiting process (step S7513) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first checks the value of the payout control timer (step S75301). If the value is 0, the process proceeds to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). If the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the payout control CPU 371 loads the error flag, and sets the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit. It is confirmed whether or not (step S75304). If any one of the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit is set, it is determined that the dispensing operation cannot be continued any more, and the process proceeds to step S75306. Transition. If none of the payout number error error specification bit, the payout switch error detection error 1 specification bit, and the payout switch error detection error 2 specification bit is set, the payout control CPU 371 sets the value of the unpaid number counter to 0. It is confirmed whether or not (step S75305). If the value of the unpaid-out counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads a payout control state flag (step S75306), and is requesting a ballot for the payout control state flag. Bits other than the designated bit and the payout operation end designation bit are reset (step S75307). Then, the payout control CPU 371 sets a value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 loads an error flag and confirms whether or not the ball breakage error designation bit or the full tank error designation bit is set (step S75309). . If the ball breakage error designation bit or the full tank error designation bit is set, the processing is terminated as it is. If neither the ball breakage error designation bit nor the full tank error designation bit is set, the payout control CPU 371 checks whether or not the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designation bit in the payout control status flag (step S75312). . The payout control CPU 371 also includes a 1 designation bit during re-payout operation (bit indicating execution of the first re-payout operation) and a 2 designation bit during re-payout operation (execution of the second re-payout operation). Is reset (step S75313), and the process is terminated.

  Note that the designated number of paid-out balls has been inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). Note that, when the value of the unpaid-out number counter remains two or more despite the end of the payout operation, the remaining number is added to the payout number abnormality counter. Further, the detection determination by the payout number count switch 301 at the end of the payout operation is executed only once every time the payout operation is executed, and the payout motor ball biting process or the payout motor ball bite releasing process is executed. It is not executed when the biting operation is finished (specifically, since the payout case error designation bit is set in the ball biting state, the ball biting operation is performed by setting the payout ball number checked designation bit in advance in step S75312. Even if the operation is finished, the detection by the payout number count switch 301 is not determined). It should be noted that the payout ball number inspected designation bit is also set when the payout motor constant speed process in the payout motor control process becomes full.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314) and performs processing for executing re-payout processing after step S75315.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the 2 designation bit during re-payout operation of the payout control state flag is set (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1 designation bit during re-payout operation of the payout control state flag is set (step S75316). If the 1 designation bit during re-payout operation is not set, the payout control CPU 371 sets the 1 designation bit during re-payout operation in the payout control state flag in order to execute the first re-payout operation (step S75317). .

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S75318). If the specified number of paid-out balls is inspected, the process proceeds to step S75326. If the specified number of paid-out balls has been inspected, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 2 or more (step S75319). If the value of the unpaid-out number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid number counter is 2 or more, the payout control CPU 371 adds the value of the unpaid number counter to the payout number abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S75321). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S75322).

  In this embodiment, the payout is performed on condition that the value of the unpaid-out number counter remains at a predetermined reference number (2 in this example) even though the payout operation is finished by the process of step S75319. The value of the unpaid number counter is added to the number abnormality counter. That is, since the payout operation is terminated due to a malfunction or the like, the value of the unpaid-out number counter remains in a small number (1 in this example). If even one unsettled number counter value remains, the accumulated number is immediately counted as a cumulative number in the payout number abnormality counter, and the frequency determined as a payout number abnormality error is increased more than necessary, causing problems to the game. End up. Therefore, in this embodiment, on the condition that the value of the unpaid-out number counter remains 2 or more with a little allowance, the accumulated number is counted in the payout number abnormality counter, and it is determined that there is an unnecessarily large number of payout errors. Is prevented. The process of step S75319 shows a case where the payout number abnormality counter is cumulatively counted up on condition that the payout shortage number is equal to or greater than a predetermined reference number (2 in this example). Alternatively, the payout number abnormality counter may be counted up cumulatively on condition that the number is a predetermined reference number (2 in this example) or more. In this case, for example, on the condition that the number of times determined as Y in step S7502 shown in FIG. Count up. In the processing of steps S75319 and S75320, the value of the unpaid number counter is always used as it is in the payout number abnormality counter regardless of whether or not the value of the unpaid number counter remains at a predetermined reference number (2 in this example). You may make it add.

  If the 1 designation bit during re-payout operation is set in step S75316, the payout control CPU 371 checks whether or not the dispensed ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during re-payout operation in the payout control state flag to execute the second re-payout operation (step S75324). Then, 1 is added to the value of the payout number abnormality counter (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Then, control goes to a step S75326. Note that by executing the processing of step S75325, the value of the payout number abnormality counter is incremented by 1 when the re-payout operation is not performed normally despite the execution of the first re-payout operation. The Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repaid operations in order to execute the first repaid operation. Next, the payout control CPU 371 sets the number of re-payout operations (1 in this example) in the payout motor rotation frequency buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value in the payout motor control code for selecting a process executed in the payout motor control process in accordance with the payout motor activation process (step S75330). Thereby, in the payout motor control process of step S756, the payout motor starting process for starting the payout motor 289 is executed, and the re-payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If the 2 designation bit during re-payout operation is set in step S75315, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75332). Next, the payout control CPU 371 checks whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter (step S75334). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Also, by executing the process of step S75335, even if the second re-payout operation is executed, if the re-payout operation is not performed normally, the value of the payout number abnormality counter is incremented by one. Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the re-payout waiting timer (step S75337) and ends the process. The re-payout waiting timer set in step S57337 is measured by an error process described later (see step S7710), and the payout case error designation bit in the error flag is reset based on the time-out of the re-payout timer. (See steps S7711 and S7712). By executing such processing, in this embodiment, after the payout case error is detected, the error state is automatically recovered based on the fact that two minutes have passed.

  Next, error processing will be described. FIG. 94 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 94, when no error has occurred, “−” is displayed on the error display LED 374. When the cumulative count value of the payout number abnormality counter is 2000 or more and a payout number error is detected, the payout control CPU 371 of the payout control microcomputer 370 detects an error display LED 374 as a payout number error. Control to display “A” on the screen. If a payout number abnormality error occurs, the error state is continued until the power supply of the gaming machine is reset.

  When the connection signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 performs control to display “1” on the error display LED 374 as a main board non-connection error. Do.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  When a serial communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, control is performed to display “5” on the error display LED 374 as a main control communication error. .

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S758).

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, or a main control communication error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes ON state) The payout control means returns to the state before the error occurred.

As described above, the payout control CPU 371 specifically displays an error on the error display LED 374 according to the relationship shown in FIG. 94 in the display control process of the timer interrupt process (see step S760). . For example, the payout control CPU 371 generates a prepaid card unit unconnected error in the display control process based on the setting of the prepaid card unit unconnected state designation bit in the error process described later (see step S7729). An error display “8” indicating that is displayed on the error display LED 374 is controlled. Further, for example, based on the fact that the full error specification bit is set in the error processing (see step S7714), an error display “6” indicating that a full error has occurred in the display control processing is displayed on the error display LED 374. Control the display.

  95 and 96 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the error flag payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. Other error bits are reset (step S7701). Next, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch abnormality detection error 2 designation bit, the withdrawal case error designation bit, the main control communication error designation bit, or the withdrawal number abnormality error designation bit is set) The control CPU 371 checks whether or not the operation signal is turned on from the error release switch 375 (step S7703). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S7709). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S7705). If the pre-error recovery timer value becomes 0 (step S7706), the payout switch of the error flags The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the re-payout waiting timer is reset (step S7708). Then, control goes to a step S7710. If the pre-error recovery timer has not timed out, the process proceeds to step S7713.

  When the processing of step S7707 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem even if the error bit that is not in the set state is reset. As described above, in this embodiment, when an error (see FIG. 94) that causes the setting of the payout switch abnormality detection error 2, the payout case error, and the main control communication error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  In step S7710, if set, the payout control CPU 371 subtracts 1 from the value of the re-payout waiting timer, and checks whether the re-payout wait timer after the subtraction has timed out (step S7711). If the re-payout waiting timer has timed out, the payout control CPU 371 resets the payout case error designation bit of the error flag (step S7712). Then, control goes to a step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processes of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error has been canceled (more precisely, the time before error recovery has passed) and on the condition that a predetermined time (2 minutes in this example) has passed after detection of the payout case error The error may be automatically canceled. In this embodiment, regarding the payout number abnormality error, once detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing of steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 91 to 93). Then, the game ball payout retry operation is started. That is, when the payout control process in step S755 is executed next, if the payout passing waiting process in step S7513 is executed, the repayout process is performed again. For example, if the prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is in the reset state in step S75310. Therefore, the process for starting the re-payout process after step S75314 is executed again, and the re-payout process is executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When detected (see step S75314 and subsequent steps in FIGS. 91 to 93), the control state related to payout is shifted to an error state, and an error release signal is output from the error release switch 375 in the error state, or a payout case Corrected payout that makes correction payout control again on condition that a predetermined time (2 minutes in this example) has passed since the error was detected To run the control restart processing.

  Further, even during execution of the re-payout process in the error state (specifically, during the re-payout process before setting the payout case error and during the re-payout process after the error release switch 375 is pressed), step S7501, FIG. S7502 and S7506 are executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the unpaid-off number counter is subtracted. Accordingly, the value of the unpaid-out number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  In addition, even when it is confirmed that the game ball has been paid out as a result of the re-payout process in the payout passing waiting process shown in FIGS. 91 to 93, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) or when a payout case error is detected for a predetermined time. (2 minutes in this example) has elapsed (steps S7707, S7712). That is, until a predetermined time (in this example, 2 minutes) has passed since the detection of the payout case error, the payout case error (insufficient payout) is automatically determined based on the fact that the game ball has passed through the payout number count switch 301. The error) state is not canceled, and the payout case error is not canceled without an artificial operation. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred. However, in this embodiment, at least a long time (2 minutes in this example) after the occurrence of the payout case error is configured to automatically cancel the payout case error so that the payout case error is generated. Prevents continued for longer than necessary.

  In some cases, a gaming machine may be configured such that a hardware reset (reset to the payout control CPU 371) is performed by operating the error release switch 375. However, when such a gaming machine is configured, When the error release switch 375 is operated, for example, the value of the unpaid number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S7713, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit in the error flag is set (step S7714).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S7715). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 checks the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), sets the main board unconnected error designation bit. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S7720). It should be noted that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S752, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371 loads the payout control state flag when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “4”) (step S7721). In step S7722), it is confirmed whether the winning ball payout operation or the ball lending payout operation is in progress (step S7723). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit or a ball lending payout operation specifying bit is set in the payout control state flag. If the designated bit during the winning ball payout operation and the designated bit during the ball lending payout operation are both in the reset state, the payout control CPU 371 determines that the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, an error flag. Among these, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 checks whether or not the value of the payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7725). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred and sets a payout number error error flag (step S7726).

  Next, the payout control CPU 371 resets the prepaid card unit error flag for setting the error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S7728), and if the VL signal is not input (if it is in the off state), the prepaid card unit error flag The prepaid card unit unconnected error designation bit is set (step S7729).

  In the display control process of step S760, the error display LED 374 performs notification by display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board unconnected error is automatically canceled when the connection signal is turned on (see steps S7701, S7717, and S7718), but the condition that the error cancel switch 375 is further operated is set. In addition, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit non-connection error and a prepaid card unit communication error) and other errors (see FIG. 94). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  In this embodiment, in error processing, first of the error flags, other than the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, and the withdrawal number abnormality error designation bit. After the bit is reset once (see step S7701), it is checked every time error processing is executed whether a full error, a ball break error, or a main control unconnected error has occurred. The payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 has been operated. However, the payout number abnormality error is not canceled once it is set. Therefore, in this embodiment, when a payout number error occurs, the payout number error is canceled as a condition that the power supply is reset.

  97 and 98 are flowcharts showing the information output processing in step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 checks whether or not the designated bit during the ball lending payout operation of the payout control state flag is set. If the ball lending / dispensing operation is in progress, the process proceeds to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 checks whether or not the payout number count switch 301 is in the on state (step S7903). If the payout number count switch 301 is in the ON state (in this case, the payout by the winning ball is detected), the payout control CPU 371 adds 1 to the value of the winning ball signal 1 output number counter (step S7904). At the same time, 1 is added to the value of the prize ball payout number counter (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the condition for outputting the prize ball signal 1 is satisfied. The prize ball payout number counter is a counter for counting the number of game balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the added prize ball payout counter is equal to or greater than a predetermined prize ball information output determination value (10 in this example) (step S7906). If it is equal to or greater than the predetermined prize ball information output determination value (10 in this example), the payout control CPU 371 resets the prize ball payout number counter (step S7907) and sets the value of the prize ball information output number counter. 1 is added (step S7908). The prize ball information output count counter is a counter for counting the number of times that the condition for outputting prize ball information is satisfied.

  Next, if it is set, the payout control CPU 371 decrements the prize ball information output timer by 1 (step S7909), and checks whether the prize ball information output timer after the subtraction has timed out (step S7910). The prize ball information output timer is a timer for measuring the output duration time of prize ball information. If not timed out, the process proceeds to step S7914. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball information output number counter is 0 (step S7911). If the value of the prize ball information output number counter is 0, the process proceeds to step S7915. If the value of the winning ball information output number counter is not 0 (that is, if the number of winning ball information output conditions is still satisfied), the payout control CPU 371 subtracts 1 from the value of the winning ball information output number counter. (Step S7912). Next, the payout control CPU 371 sets a prize ball information output timer in order to start outputting the next prize ball information (step S7913). Then, the payout control CPU 371 performs control to output the prize ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 performs a process of setting output data in a prize ball information output bit (bit 7, see FIG. 75) of the output port 1.

Next, if the payout control CPU 371 is set, the prize ball signal 1 output timer is decremented by 1 (step S7915), and it is confirmed whether or not the prize ball signal 1 output timer after the subtraction has timed out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If not timed out, the process proceeds to step S7920. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output number counter is not 0 (that is, if the number of established conditions for the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output number counter. 1 is subtracted (step S7918). Next, the payout control CPU 371 sets a prize ball signal 1 output timer to start outputting the next prize ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to output the prize ball signal 1 to the outside (step S7920). Specifically, the payout control CPU 371 performs processing for setting output data in the prize ball signal 1 output bit (bit 0; see FIG. 75) of the output port 0. In this embodiment, the winning ball signal 1 is not directly input from the payout control board 37 to the terminal board 160 and externally output, but is input to the terminal board 160 once through the main board 31. Is output externally.

Next, the payout control CPU 371 performs processing for setting output data in the gaming machine error state signal output bit (bit 1, see FIG. 75) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the ball breakage error designation bit or the full tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of the output port 0 remains set. The process ends. In this case, the gaming machine error status signal is output to the outside based on the fact that the gaming machine error status signal output bit of the output port 0 is set in step S7921. In this embodiment, the gaming machine error state signal is not directly input from the payout control board 37 to the terminal board 160 but externally output, but is input to the terminal board 160 once through the main board 31. And output externally. On the other hand, if neither the ball breakage error designation bit nor the full tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error state signal output bit of the output port 0 (step S7925), and processing Exit.

  By executing the above processing, in this embodiment, the prize ball signal 1 is output to the outside every time one prize ball payout is detected on the payout control means side. Further, prize ball information is output to the game control means side every time ten payout balls are detected on the payout control means side. Further, when a ball break error or a full tank error is detected on the payout control means side, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 99 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, effect control CPU 101a) as effect control means mounted on the effect control board 80. The effect control CPU 101a starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) (step S781). . Thereafter, the effect control CPU 101a proceeds to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101a clears the flag (step S783) and executes the following effect control process.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S784).

  Next, the effect control CPU 101a performs effect control process processing (step S785). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S786). Thereafter, the process proceeds to step S782.

  FIG. 100 is a flowchart illustrating a specific example of command analysis processing (step S784). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101a checks the content of the command stored in the command reception buffer.

  In addition, in FIG. 100, although it shows about the process at the time of receiving the command which shows the error regarding payout control especially among the effect control commands transmitted from the microcomputer 560 for game control, Various effect control commands such as a variation pattern command indicating a variation pattern and a display result specifying command indicating a display result indicating whether or not to win are transmitted from the game control microcomputer 560.

  In the command analysis process, the effect control CPU 101a first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101a sets a prize ball error bit (bit 0, see FIG. 30) among the lower 4 bits of the frame state display command. It is confirmed whether it has been done (step S615). If set, the effect control CPU 101a performs control to superimpose and display predetermined prize ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the full error bit (bit 1, see FIG. 30) in the lower 4 bits of the frame state display command is set (step S617). If set, the effect control CPU 101a performs control to superimpose and display predetermined full tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 a performs control to display a character string such as “a full tank error has occurred” on the display screen of the effect display device 9.

  In addition, the effect control CPU 101a checks whether or not the ball break error bit (bit 2, see FIG. 30) in the lower 4 bits of the frame state display command is set (step S619). If set, the effect control CPU 101a performs control to superimpose and display predetermined ball-out error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 a performs control to display a character string such as “A ball break error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the payout number abnormality error bit (bit 3; see FIG. 30) in the lower 4 bits of the frame state display command is set (step S621). If set, the effect control CPU 101a performs control to superimpose and display predetermined payout number abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 a performs control to display a character string such as “A payout number error has occurred” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball shortage error command (step S623), the effect control CPU 101a performs control to superimpose and display predetermined prize ball shortage error notification information on the display screen of the effect display device 9 (step S623). S624). For example, the effect control CPU 101 a performs control to display a character string such as “There was a shortage of prize balls” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball excess error command (step S625), the effect control CPU 101a performs control to superimpose and display predetermined prize ball excess error notification information on the display screen of the effect display device 9 (step S625). S626). For example, the effect control CPU 101 a performs control to display a character string such as “There was an excessive prize ball error” on the display screen of the effect display device 9.

  In addition, each error display may not be simply displayed in a superimposed manner, but may be prioritized and notified of an error having a high priority by ranking from the viewpoint of fraud importance. For example, a payout number abnormality error may be preferentially notified with the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  If the received effect control command is another command, the effect control CPU 101a sets a flag corresponding to the received effect control command (step S627). Then, control goes to a step S611. For example, when a variation pattern command or a display result designation command is received, the effect control CPU 101a also performs processing for storing the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  FIG. 101 is a flowchart showing the effect control process (step S785) in the main process shown in FIG. In the effect control process, the effect control CPU 101a performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of the effect symbol is realized. However, control related to variable display of the effect symbol synchronized with the change of the first special symbol is also the second. Control related to the variable display of the effect symbol synchronized with the change of the special symbol is also executed in one effect control process. It should be noted that the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Production symbol variation start processing (step S801): Control is performed so that the variation of the production symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Effect symbol variation stop processing (step S803): Control is performed to stop the variation of the effect symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): When the big hit is reached, after the variation time is over, the effect display device 9 is controlled to display a screen for notifying the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805).

  Big hit game processing (step S805): Control during big hit game is performed. For example, when a special winning opening opening designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot end effect process (step S806).

  Big hit end effect processing (step S806): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  As described above, according to this embodiment, the gaming control microcomputer 560 is informed that the initialization process has been executed when the gaming machine is powered on and that a predetermined error (in this example, the first That a predetermined signal output condition is satisfied, including that it is determined that the start winning port 13a, the second starting winning port 13b, the lower large winning port 23b, and the upper large winning port 24b are abnormal). First, a security signal is output to the outside of the gaming machine. In this case, the game control microcomputer 560 has a common output terminal (a terminal board of the terminal board) provided in the gaming machine when the initialization process is executed and when it is determined that a predetermined error has occurred. A security signal is output from the common connector CN7). Further, a predetermined signal output condition is newly established when the security signal is output (in this example, the first start winning opening 13a, the second starting winning opening 13b, the lower big winning opening 23b, the upper big winning prize are newly established). If an abnormal winning is detected in the mouth 24b), the output time for outputting the security signal is extended. Therefore, by outputting a security signal based on the execution of the initialization process, it is possible to prevent an illegal act performed when the gaming machine is powered on. In addition, since the security signal is output to the common output terminal when the initialization process is executed and when it is determined that a predetermined error has occurred, the waste of the signal line for external output is reduced. Can do. Therefore, it is possible to reduce the waste of the signal line for external output while preventing an illegal act performed when the power to the gaming machine is turned on.

  Further, Patent Document 1 describes that an illegal act (radio wave or the like) input to the winning switch is prevented from operating a safe sensor so that an illegal act can be detected. Specifically, the use of a pass-type safe sensor is described. However, Patent Document 1 shows that the winning switch and the safe sensor are operated simultaneously by strong radio waves, so that the winning switch and the safe sensor have different detection performances. The same type of safe sensor is used. Patent Document 1 shows that all winning switches and safe sensors are operated at the same time, and that it is determined that an illegal act has been received. The winning switch and the safe sensor do not always operate simultaneously. Depending on the strength of the radio wave, it is assumed that all winning switches and safe sensors may or may not operate simultaneously. That is, the method disclosed in Patent Document 1 is insufficient for detecting fraud.

  According to this embodiment, the game control microcomputer 560 includes the detection signal input from the first start port switch 14a (proximity switch), the detection signal input from the first winning confirmation switch 14b (photosensor), the second The detection signal input from the start port switch 15a (proximity switch), the detection signal input from the second winning confirmation switch 15b (photo sensor), the detection signal input from the lower count switch 23 (proximity switch) and the third winning confirmation switch 23a Based on the detection signal input from the (photo sensor), the detection signal input from the upper count switch 24 (proximity switch), and the detection signal input from the fourth winning confirmation switch 24a (photo sensor), the first start port switch 14a. , Second start port switch 15a, lower count switch 23, upper cap The difference between the number of game balls detected by the game switch 24 and the number of game balls detected by the first to fourth winning confirmation switches 14b, 15b, 23a, 24a exceeds a predetermined threshold (in this example, 20 If it is determined that the above is determined), it is determined that a predetermined error has occurred in the first start winning opening 13a, the second starting winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b. Further, in this embodiment, the first start opening switch 14a and the first winning confirmation switch 14b, the second starting opening switch 15a and the second winning confirmation switch 15b, the lower count switch 23 and the third winning confirmation switch 23a, the upper count The switch 24 and the fourth winning confirmation switch 24a are configured by sensors of different detection methods (in this example, a proximity switch and a photo sensor). For this reason, it is possible to more reliably detect fraudulent acts with respect to the switch that detects the game ball, and to take certain measures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 executes the special symbol variation display based on only the input of the detection signal from the first start port switch 14a and performs the winning ball payout process. The detection signal that is executed and input from the first winning confirmation switch 14b is used only to determine whether or not an abnormal winning has occurred in the first start winning opening 13a. The detection signal input from the second winning confirmation switch 15b is executed based on only the detection signal input from the second start opening switch 15a, and the special symbol variation display is executed and the winning ball payout process is executed. It is used only for determining whether or not an abnormal winning has occurred in the second start winning opening 13b. Therefore, since the special symbol variation display and the prize ball payout process are performed based on the detection result of one of the switches, it is possible to prevent an increase in the processing burden accompanying the strengthening of countermeasures against fraud.

Further, in particular, by allowing the second start opening switch 15a and the second winning confirmation switch 15b to detect an abnormal winning at the second start winning opening 13b, the second start opening using radio waves or the like in an advantageous state, for example. It is possible to recognize that the number of winnings for the switch 15a is larger than the actual number of winnings, thereby preventing frequent occurrence of small hits and illegally opening the upper large winning opening door 24c.

  In addition, according to this embodiment, the game control microcomputer 560 opens and closes the lower large winning opening door 23c based on only the detection signal input from the lower count switch 23, and the winning ball payout process. And the detection signal input from the third winning confirmation switch 23a is used only for determining whether or not an abnormal winning has occurred in the lower large winning opening 23b. Further, based on only the detection signal input from the upper count switch 24, the upper large winning opening door 24c is opened and closed and the prize ball payout process is executed. The detection signal input from the fourth winning confirmation switch 24a is It is used only to determine whether or not an abnormal winning has occurred in the upper special winning opening 24b. For this reason, the opening / closing of each of the big prize opening doors 23c, 24c and the prize ball payout process are performed based on the detection result of one of the switches, so that it is possible to prevent an increase in the processing burden associated with strengthening countermeasures against fraud. it can.

  Further, according to this embodiment, the game control microcomputer 560 includes the number of game balls detected by the first start port switch 14a, the second start port switch 15a, the lower count switch 23, and the upper count switch 24. Second start when the inside of the second winning path 1307 is in a clogged state with the difference from the number of game balls detected by the first to fourth winning confirmation switches 14b, 15b, 23a, 24a as a predetermined threshold It is determined whether or not a value (20 in this example) greater than the difference (for example, 14) between the detected number of game balls in the mouth switch 15a and the detected number of game balls in the second winning confirmation switch 15b. For this reason, when the first start port switch 14a, the second start port switch 15a, the lower count switch 23, and the upper count switch 24 become clogged, the first start port switch 14a and the second start port switch are erroneously made. It can be prevented that an abnormal winning to the mouth switch 15a, the lower count switch 23, and the upper count switch 24 has occurred. Accordingly, it is possible to prevent erroneous determinations associated with strengthening countermeasures against fraud.

  Further, according to this embodiment, the gaming control microcomputer 560 has a predetermined error (in this example, the first start winning award 13a, the first number) when the initialization process is executed when the gaming machine is turned on. 2) When it is determined that an abnormal winning to the start winning port 13b, the lower large winning port 23b, and the upper large winning port 24b has occurred, a security signal is output over different times. Specifically, in this embodiment, when the initialization process is executed when the power to the gaming machine is turned on, a security signal is output to the outside for 30 seconds, and the first start winning opening 13a, the second start When an abnormal winning is detected in the winning opening 13b, the lower large winning opening 23b, and the upper large winning opening 24b, a security signal is output to the outside for four minutes. Therefore, by determining the output time of the security signal, it is possible to determine whether the initialization process has been performed or a predetermined error has occurred in an external device such as a hall computer. It becomes.

Further, according to this embodiment, the game area 7 is provided separately from the variable winning device 400, and the normal winning holes 29a to 29d are less likely to pass the game ball than the open state of the variable winning device 400. It is not only inherently difficult to win the game ball, based on the fact that the prize to the normal winning openings 29a~29d, is and the upper winning opening door 24c that the variation display of the special symbols of that game balls are paid out is performed open It is not likely to be a target of fraud. Therefore, in the winning paths 1450 and 1451 through which the game balls that have entered the normal winning holes 29a to 29d pass, only the winning opening switches 30a and 30b including proximity switches are provided, and the detection method is different from that of the proximity switches. By not providing a winning confirmation switch such as the 1-4 winning confirmation switch, the manufacturing cost of the pachinko gaming machine 1 can be reduced.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. Further, the game control microcomputer 560 sends a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370 every time a predetermined period (1 second in this example) elapses. To 370. The payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using a serial communication method, it is possible to facilitate wiring between the game control microcomputer 560 and the payout control microcomputer 370. In addition, the control state signal (response signal to which the control state is added) is transmitted by placing the control state on the connection OK command that the payout control microcomputer 370 periodically outputs based on the reception of the connection confirmation command. Can do. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the cycle (interval) for transmitting the connection confirmation command is 1 second, but it may be 0.5 seconds or the like.

  Further, according to this embodiment, the game control microcomputer 560 resets a predetermined period (1 second in this example) to the prize ball process timer when the execution of the payout control is finished, and the prize ball process. Measurement control by the timer is started (see step S52505). If the number of prize balls is not stored (specifically, if no prize ball command output counter has a count value of 1 or more in step S52301), the game control microcomputer 560 resets the game. A new connection confirmation command is transmitted to the payout control microcomputer 370 based on the time-out of the prize ball process timer. For this reason, an interval period can be provided between the end of execution of payout control and the transmission of a new connection confirmation command, and processing at the end of execution of payout control is concentrated, and a new connection check command is overwritten. Can be prevented.

Further, according to this embodiment, the game control microcomputer 560 transmits a winning ball number command to the payout control microcomputer 370 based on the detection of a winning regardless of the transmission timing of the connection confirmation command. To do. The payout control microcomputer 370 transmits a prize ball number reception command based on the reception of the prize ball number command, and outputs a prize ball preparation command during execution of the payout control. It is transmitted to the game control microcomputer 560 every period (1 second in this example). In this case, the payout control microcomputer 370 receives the prize ball in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, an out of ball error, and a payout number error error). The preparing command is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the prize ball number reception command. Therefore, it is possible to reduce the control burden of the game control microcomputer 560 by not performing connection control command transmission control unnecessarily during execution of payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the award ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, the game control microcomputer 560 receives the award ball end command and then stores the number of award balls (specifically, the prize ball command output counter in step S52301). If the count value is 1 or more), a new prize ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to speed up the execution process of the payout control.

In addition, according to this embodiment, the game control microcomputer 560 determines whether a predetermined error (in this example, a prize ball error, a full tank error, a full ball error, based on the control state indicated by the received connection OK command. , And a payout quantity abnormality error). Then, the game control microcomputer 560 transmits a prize ball number command to the payout control microcomputer 370 on the condition that it is determined that a predetermined error has not occurred. Therefore, it is possible to prevent the inconvenience of sending a prize ball number command when the payout control cannot be normally performed due to an error state. In particular, in this embodiment, since the RAM provided in the payout control microcomputer 370 is not backed up by the backup power supply, if a prize ball number command is transmitted when there is an abnormality in the payout control, the power is reset. For example, the memorized number of prize balls may be lost, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the prize ball number command is transmitted while the memory of the prize ball number is retained on the game control microcomputer 560 side backed up by the backup power source. It is possible to prevent such a disadvantage from occurring by controlling to hold.

  Further, according to this embodiment, the game control microcomputer 560 increases the time interval for transmitting the connection confirmation command when the connection OK command cannot be received after transmitting the connection confirmation command. Whenever a specific period (10 seconds in this example) elapses, the control is switched to the connection confirmation command transmission. Therefore, in a state where the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. Can be performed less frequently, and a wasteful processing load can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 causes the game to occur when a predetermined error (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error) occurs. Information that allows the control microcomputer 560 to recognize a predetermined error is set by changing a specific bit of the connection OK command, and the connection OK command in which the setting has been made is transmitted to the game control microcomputer 560. The game control microcomputer 560 transmits a frame state display command in which information capable of recognizing a predetermined error set in the received connection OK command is set as it is to the effect control microcomputer 100. Then, based on the reception of the frame state display command, the production control microcomputer 100 controls the production device (the production display device 9 in this example) to notify that a predetermined error has occurred. Do. Therefore, it is possible to notify that a predetermined error has occurred using the effect device, and to reduce the processing load on the game control microcomputer 560.

  In addition, according to this embodiment, the payout control microcomputer 370 has a payout excess exceeding the number of unpaid game balls to be paid out and the number of unpaid games to be paid out. The number of shortage payouts that did not reach the ball is cumulatively counted using a payout number abnormality counter. When the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), the payout control is stopped and the payout stop state is controlled. Therefore, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under an abnormal condition based on the value of the payout number abnormality counter counted up cumulatively. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out the game ball.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout number abnormality counter when a payout shortage number equal to or greater than a predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary. In other words, since there are not a few small numbers (1 in this example) of insufficient payouts in the operating state of the gaming machine, the number of insufficient payouts exceeding the predetermined reference number (2 in this example) has occurred. By counting up on the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes re-payout control for driving and controlling the ball payout device 97 to pay out only one game ball when a payout shortage occurs. . If the payout of the game ball is not detected even after the re-payout control is executed, the value of the payout number abnormality counter is counted up. Therefore, even if the number of payout shortages is small, it is possible to appropriately stop the execution of payout control by reflecting it in the count value of the payout number abnormality counter, and to take illegal measures to prevent the act of illegally paying out game balls. Can be strengthened.

  Further, according to this embodiment, when the payout number abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on condition that the power supply of the gaming machine is reset. Therefore, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and the game is continued in the abnormal state. This can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can retain the stored contents for a predetermined period by the backup power supply even when the power supply to the gaming machine is stopped. In addition, when the game control microcomputer 560 is controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a winning occurs. For this reason, the number of prize balls stored in the RAM 55 (specifically, the value of the prize ball command output counter) is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that is not caused by fraud. It is possible to prevent such a situation from occurring, and it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the prize ball number to the prize ball number counter at the timing of sending the prize ball number command, and receives the prize ball information based on the received prize ball information. Subtract 10 from the value of the ball counter. Then, based on the fact that the value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (501 in this example), it is determined that there is a prize ball shortage error. Based on the fact that it is less than the determination value (0 in this example), it is determined that there is an excessive prize ball error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game ball.

Further, according to this embodiment, the game control microcomputer 560 sends a connection signal indicating a connection state of communication with the payout control microcomputer 370 via the I / O port unit 57. Since the connection state of communication can be confirmed at any timing on the payout control microcomputer 370 side, the payout of the winning ball is made when the communication connection state is abnormal. Can be reliably prevented.

  In the above embodiment, the game control microcomputer 560 normally transmits a connection confirmation command 1 second after the connection OK command is received, and when a communication error occurs (for example, connection When the OK command cannot be received), the connection confirmation command is transmitted 10 seconds after the connection confirmation command is transmitted, and the period of 1 second or 10 seconds is measured by a timer (a counter configured by software). However, the connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the connection OK command, or the counter may be cleared if an internal interrupt is generated with a predetermined value.

  Next, a modified example of the physical configuration of the terminal board 160 mounted on the gaming machine will be described. 102 and 103 are explanatory views showing modifications of the physical configuration of the terminal board 160. FIG. The gaming machine is provided with a cover member 800 for covering and protecting each board such as the main board 31, the effect control board 80, and the payout control board 37, for example, as shown in FIGS. As described above, the terminal board 160 may be embedded in the cover member 800. Also, a terminal board cover 801 for covering and protecting the terminal board 160 is attached to a portion of the cover member 800 where the terminal board 160 is attached. Here, FIG. 102 shows a state where the terminal board cover 801 is attached to the cover member 800, and FIG. 103 shows a state where the terminal board cover 801 is removed from the cover member 800. As shown in FIG. 103, two terminal claws 801a are provided on the upper part of the terminal board cover 801, and the terminal board is secured by inserting the claws 801a and fastening them with screws 801b. A cover 801 can be attached.

  As shown in FIGS. 102 and 103, a plurality of terminals 96a, 96b, 98a, 98b,... Are provided on the terminal board 160 for connecting cables with external devices such as hall computers. A terminal board 900 is provided. Further, the terminal board 900 has a two-stage configuration including a terminal row including terminals 96a, 96b,... And a terminal row including terminals 98a, 98b,. One set (set of signal line and ground line). For example, in the example shown in FIGS. 102 and 103, there is one set of the terminals 96a and 96b arranged in the horizontal direction among the terminals in the upper terminal row, and the horizontal direction among the terminals in the lower terminal row. One set of the terminal 98a and the terminal 98b arranged in a row. Further, the terminals 96a, 96b, 98a, 98b,... Provided on the terminal board 900 are respectively provided with knobs 95a, 95b, 99a, 99b, and the knobs 95a, 95b,. The terminals 96a, 96b, 98a, 98b... Are opened by performing operations such as pressing 99a, 99b. For example, when the upper knob 95a is pressed, the cable can be connected to the terminal 96a, and when the lower knob 99a is pressed, the cable can be connected to the terminal 98a. For example, when the upper knob 95b is pressed, the cable can be connected to the terminal 96b, and when the lower knob 99b is pressed, the cable can be connected to the terminal 98b.

  102 and 103, the knobs 95a, 95b, 99a, 99b,... Provided for each of the terminals 96a, 96b, 98a, 98b,. Has been. With such a configuration, it is possible to prevent inconveniences such as accidentally operating the knob for the adjacent terminal, and improve workability when performing the work of connecting the cable to the terminal board 900. be able to.

  FIG. 104 is an explanatory view showing a cross-sectional structure of a portion of the cover member 800 where the terminal board 160 is attached. As shown in FIG. 104, the terminal board 160 is sufficiently placed so that the terminal board 900 provided on the terminal board 160 is located inside the surface of the cover member 800 (the X plane shown in FIG. 104). The cover member 800 is attached to the back side. As described above, the terminal board 900 provided on the terminal board 160 is configured to be inside the surface of the cover member 800 (the X surface shown in FIG. 104). It is possible to prevent the occurrence of inconvenience such as contact with the terminal board 900.

  As shown in FIG. 104, the terminal board cover 801 is inclined so that the side wall 801c gradually narrows. Since the side wall 801c is inclined as described above, even when the terminal board cover 801 is attached, it is easy for a finger or the like to enter, and when connecting the cable to the terminal board 900, Workability can be improved.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines, arrange ball gaming machines, and sparrow ball gaming machines.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 13a 1st start winning opening 13b 2nd starting winning opening 14a 1st starting opening switch 14b 1st winning check switch 15a 2nd starting check switch 15b 2nd winning check switch 15 Variable winning ball apparatus 20 Special variable winning ball Device 23 Lower count switch 23a Third prize confirmation switch 23b Lower big prize opening 24 Upper count switch 24a Fourth prize confirmation switch 24b Upper big prize opening 43 Specific area 43a Specific area switch 44 Normal area 45 Outlet switch 400 Variable prize apparatus 406 Upper ball path 407 Lower stage 408 Lower ball path 560 Microcomputer for game control

Claims (5)

A game machine imparting valuable game media game media controllable variable winning equipment in an open state and a winning impossible closed state capable winning is based on the fact that the prize,
And specific detection means for detecting a game medium which has passed through the specific area provided in said variable winning device,
Based on the Yu technique medium is detected by the specific detector, and Yu Technical state shift means for shifting to an advantageous Yu TECHNICAL state for the player,
First detection means for detecting a game medium and outputting a first detection signal;
Second detection means for detecting a game medium and outputting a second detection signal;
An abnormality determining means for determining a prize abnormality based on the first detection signal output from the first detection means and the second detection signal output from the second detection means;
Transition means for shifting to a predetermined error state based on the fact that the abnormality determination means has determined that a winning abnormality has occurred,
The first detection means and the second detection means are provided at positions for detecting game media won in the variable winning device, and are configured by sensors of different detection methods ,
The abnormality determining means determines that a difference between the number of game media detected by the first detection means and the number of game media detected by the second detection means is from the first detection means to the second detection means. A gaming machine characterized in that a winning abnormality is determined when a threshold value greater than the number of game media corresponding to the length of the passage is reached . Based on said first detection signal is outputted from the first detecting means comprises assigning means for assigning values,
The second detection signal output from the second detection means is used only for determination of a winning abnormality to the variable winning device by the abnormality determination means.
The gaming machine according to claim 1. A passing area provided separately from the variable prize device,
A gaming machine that gives value based on the fact that a game medium has passed through the passing area,
The first detection means and the second detection means are provided at a position for detecting a game medium that has passed through the passage area.
The gaming machine according to claim 1 or 2, characterized in that. A collection road surface disposed at a position below the second detection means and for collecting the game medium that has passed through the second detection means;
A direction changing portion provided between the second detection means and the recovery road surface so as to be in contact with the game medium that has passed through the second detection means and capable of changing the flow direction of the game medium;
A gaming machine according to any one of claims 1 to 3. Provided separately from the variable winning device, provided with a predetermined passage area through which game media is less likely to pass than the open state of the variable winning device,
A gaming machine that gives value based on the fact that a game medium has passed through the predetermined passing area,
Only the first detection means is provided at a position where the game medium that has passed through the predetermined passage area is detected.
The gaming machine according to any one of claims 1 to 4, characterized in that.

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