JP6121500B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that controls a specific gaming state advantageous to a player based on establishment of a predetermined condition.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be done.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. If the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Therefore, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means.

  Further, in order to prevent illegally paying out game media as prizes due to fraudulent acts, the payout control means includes the number of winning game media actually detected by each of the winning switches provided for each winning area. There is a gaming machine that compares the number of detections by a safe sensor as a collective winning ball detector that detects all winning game media and determines that an abnormality has occurred if they do not match (for example, Patent Literature 1).

JP 2000-237436 A (paragraphs 0074, 0081)

  In Japanese Patent Laid-Open No. 2004-26883, fraud countermeasures are taken by determining whether or not an abnormality due to winning has occurred, but because of an initialization signal that is output only once a day outside the gaming machine. There is a problem that providing a dedicated signal line is not efficient and wasteful.

  In view of the above, an object of the present invention is to provide a gaming machine that can prevent illegal acts more reliably and reduce the waste of signal lines for external output.

In order to solve the above-mentioned problem, a gaming machine according to claim 1 of the present invention provides:
A gaming machine that controls a specific gaming state advantageous to a player based on establishment of a predetermined condition,
A special variable winning device that can change to an open state in which the prize can be won in the specific gaming state;
Storage means capable of holding stored contents for a predetermined period even when power supply to the gaming machine is stopped;
Initialization operation means for outputting an operation signal in response to an operation;
Initialization processing execution means for executing initialization processing for initializing the storage contents of the storage means based on the input of the operation signal from the initialization operation means when power supply is started; ,
Error determination means for determining whether or not an abnormal winning error has occurred in the special variable winning device;
Based on the establishment of a signal output condition that includes at least that the initialization process has been executed by the initialization process execution means and that the error determination means has determined that the abnormal winning error has occurred. Security signal external output means for outputting a security signal to the outside of the gaming machine, abnormal winning error notification means for notifying that an abnormal winning error has occurred in the special variable winning device,
With
The security signal external output means includes:
A common output terminal provided in the gaming machine when the initialization process is executed by the initialization process execution means and when the abnormal determination error is determined by the error determination means To output the security signal to the outside of the gaming machine,
When the abnormal winning error is generated by the error determination means during the output of the security signal based on the initialization process being executed or the determination that the abnormal winning error has occurred, a new one is newly generated. When determined, extend the output period of the security signal being output,
When the initialization process is executed, the security signal is output for a predetermined time,
When it is determined that the abnormal winning error has occurred, the security signal is output for a time different from the predetermined time.
According to this feature, illegal acts can be prevented more reliably, and waste of signal lines for external output can be reduced.

The gaming machine according to means 1 of the present invention is:
A first variable winning device (first special variable winning ball device 20A) that can be controlled to an open state in which a game medium (game ball) can win and a closed state in which a game cannot be won; and an open state in which a game medium can win A second variable winning device (second special variable winning ball device 20B) that can be controlled to a closed state in which a prize cannot be won, and a game medium has won a prize in the first variable winning device or the second variable winning device. A gaming machine (pachinko gaming machine 1) that pays out a prize gaming medium (prize ball) as a prize based on that,
Based on the fact that the predetermined condition is satisfied (the big hit display result is derived and displayed), the specific game state transition means (in the game control microcomputer 560) for shifting to the specific game state (big hit game state) advantageous to the player , A part for executing steps S304 to S307 in the special symbol process processing),
In the specific gaming state, an opening control means for controlling the first variable winning device or the second variable winning device to an open state (in the game control microcomputer 560, the steps for executing steps S304 to S306 in the special symbol process) )When,
First detection means (first count switch 23, second count switch 24) for detecting a game medium and outputting a first detection signal;
Second detection means (third winning confirmation switch 23a, fourth winning confirmation switch 24a) for detecting a game medium and outputting a second detection signal;
Abnormality determination means (game control microcomputer 560) for determining a winning abnormality based on the first detection signal output from the first detection means and the second detection signal output from the second detection means. In step S113 in the switch process),
Transition means (a part for executing step S139 in the switch process in the game control microcomputer 560) based on the fact that the abnormality determination means determines that the prize is abnormal.
The first detection means and the second detection means are positions for detecting game media that have won the first variable winning device (the first count switch 23 and the third winning confirmation switch 23a are the first big winning path 1380). And a position for detecting a game medium won in the second variable winning device (the second count switch 24 and the fourth winning confirmation switch 24a are respectively provided in the second big winning path 1390) (see FIG. 26A). ,
The first detection means and the second detection means are constituted by sensors of different detection methods (for example, the game medium detection method of the first detection means is electromagnetic, and the game medium of the second detection means is The detection method is optical),
It is characterized by that.
According to this feature, it is possible to more reliably detect fraudulent acts against the detecting means for detecting the game medium, and to take measures against certain fraudulent acts, and to each of the first variable winning device and the second variable winning device. By providing the first detection means and the second detection means, it is possible to reliably prevent an illegal act in both cases even when the first variable winning device and the second variable winning device are individually arranged.

The gaming machine according to means 2 of the present invention is the gaming machine according to means 1,
Payout for performing control for paying out a prize game medium (prize ball) as a prize based on the output of the first detection signal from the first detection means (first count switch 23, second count switch 24). Control execution means (for example, a part for executing step S32 in the game control microcomputer 560);
The second detection signals output from the second detection means (the third winning confirmation switch 23a and the fourth winning confirmation switch 24a) are the first variable winning device and the second variable winning device by the abnormality determining means. (For example, the game control microcomputer 560 confirms the detection signal from the third winning confirmation switch 23a only in the process of step S132 and detects from the fourth winning confirmation switch 24a. The signal is confirmed only in the process of step S136, and is used to determine whether or not there is an abnormal winning in the first big prize opening 23b and the second big prize opening 24b in step S139).
It is characterized by that.
According to this feature, the payout of prize game media is processed based on the detection result of one of the detection means, so that it is possible to prevent an increase in processing burden associated with strengthening countermeasures against fraud.

The gaming machine according to means 3 of the present invention is the gaming machine according to means 1 or 2,
A passing area (for example, a first start winning opening 13a) provided separately from the first variable winning device (first special variable winning ball device 20A) and the second variable winning device (second special variable winning ball device 20B). The second start winning opening 13b)
A gaming machine (pachinko gaming machine 1) that pays out a prize gaming medium (prize ball) as a prize based on the passing of the gaming medium through the passing area,
The first detection means (first start opening switch 14a, second start opening switch 15a) and the second detection means (first winning confirmation switch 14b, second winning confirmation switch 15b) have passed through the passage area. Provided at a position for detecting the game medium {the first start opening switch 14a and the first winning confirmation switch 14b are the first winning passage 1360, the second starting opening switch 15a is the second winning passage 1370a, and the second winning confirmation switch 15b is Second winning path 1370b (see FIG. 26A)},
It is characterized by that.
According to this feature, it is possible to more reliably detect fraudulent acts against the detecting means for detecting the game medium, and to take reliable measures against fraud.

A gaming machine according to means 4 of the present invention is the gaming machine according to any one of means 1 to 3,
A collection road surface (collection ball) for collecting game media (game balls) disposed below (downstream) the second detection means (third winning confirmation switch 23a, fourth winning confirmation switch 24a) and passing through the second detection means ( Bottom 1501),
Direction changing portions (release direction changing surfaces 1462, 1463) provided between the second detecting means and the collection road surface so as to be able to change the flow direction of the game medium in contact with the game medium that has passed through the second detecting means. And),
It is characterized by that.
According to this feature, the direction of flow of the game medium that has passed through the second detection means is changed by the direction changing unit, so that the game medium that has fallen and jumped up on the collection road surface is detected again by the second detection means. It is prevented.

The gaming machine according to means 5 of the present invention is the gaming machine according to any one of means 1 to 4,
The first variable winning device (first special variable winning ball device 20A) and the second variable winning device (second special variable winning ball device 20B) are provided separately from the first variable winning device and the second variable winning device. A predetermined passing area (winning openings 29a, 29b) through which game media (game balls) are less likely to pass than the open state of the variable winning device;
A gaming machine (pachinko gaming machine 1) that pays out a prize gaming medium (prize ball) as a prize based on the passing of the gaming medium through the predetermined passing area,
Only the first detection means (winning port switches 30a and 30b) are provided at positions (winning passages 1450 and 1451) for detecting game media that have passed through the predetermined passing area.
It is characterized by that.
According to this feature, since the second detection means is not provided in a predetermined passing area that is not likely to be fraudulent, the manufacturing cost of the gaming machine can be reduced.

It is the front view which looked at the pachinko game machine from the front. It is a rear view which shows a game machine. (A) is the first start winning opening, (b) is the second starting winning opening, (c) is the first large winning opening 23b, and (d) is a specific example of the cross-sectional structure in the second large winning opening 24b. It is explanatory drawing. It is a circuit diagram for demonstrating the system of the detection means which can detect a game ball. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which a serial communication circuit transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a circuit diagram which shows the internal structure of a terminal board. (A) is an internal structure figure which shows the closed state of a 1st special variable winning ball apparatus, (b) is an internal structure figure which shows an open state, (c) is a principal part expanded sectional view. (A) is a longitudinal cross-sectional view which shows the closed state of a 2nd special variable winning device, (b) is a longitudinal cross-sectional view which shows the open state of a 2nd special variable winning device. (A) is a perspective view which shows the closed state of a 2nd special variable winning device, (b) is a perspective view which shows the open state of a 2nd special variable winning device. (A) is a rear view showing various winning paths provided in the game board, (b) is a view showing the vicinity of the outlet of the second winning path, and (c) is the outlet of the first big winning path. It is a figure which shows the vicinity, (d) is a figure which shows the discharge outlet vicinity of a 1st winning path, (e) is a figure which shows the discharge opening vicinity of a 2nd big winning path. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows a 4 ms timer interruption process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 10 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a winning ball operation cannot be executed immediately. FIG. 5 is a timing chart showing signal transmission and reception between a game control microcomputer and a payout control microcomputer during normal operation. FIG. 10 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when an error occurs during a winning ball. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during connection confirmation. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during award ball number notification. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of a start winning determination process. It is a flowchart which shows an example of a start winning determination process. It is a flowchart which shows an example of a special symbol normal process. It is a flowchart which shows an example of a special symbol normal process. It is a figure which shows the example of a setting of the number of times of winning a big winning opening. It is a flowchart which shows an example of a special symbol stop process. It is a flowchart which shows an example of a jackpot end process. It is a flowchart which shows an example of a normal symbol process process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. (A) is when the game ball is clogged in the first start prize opening, (b) is when the game ball is clogged in the second start prize opening, (c) is the first big prize. When the game ball is jammed in the mouth, (d) is an explanatory view showing the case where the game ball is jammed in the second prize winning mouth. It is a block diagram which shows the various signals output to a terminal board. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is explanatory drawing which shows the output timing of a security signal. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a main control transmission command conversion process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows the main process which CPU for production control performs. It is a flowchart which shows the specific example of a command analysis process. It is a flowchart which shows production control process processing. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the cross-section of the site | part to which the terminal board | substrate of a cover member is attached.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, there is provided an effect display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol (effect symbol). The effect display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The effect display device 9 variably displays the effect symbol as a decoration (effect) symbol during the variable display period of the special symbol by the first special symbol indicator 8a or the second special symbol indicator 8b. The effect display device 9 that performs variable display of effect symbols is controlled by an effect control microcomputer mounted on the effect control board.

  A first special symbol display (first variable display means) 8a for variably displaying a first special symbol as first identification information is provided at a lower right position on the game board 6. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. A second special symbol display (second variable display means) 8b for variably displaying the second special symbol as the second identification information is provided above the first special symbol display 8a. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. The first special symbol display 8a and the second special symbol display 8b each variably display a number (or a two-digit symbol) from 0 to 99 using, for example, two 7-segment LEDs. It may be configured.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b may be collectively referred to as a special symbol indicator.

  The variable display of the first special symbol is a variable display start condition (for example, after the game ball has won the first start winning opening 13a) after the first start condition, which is the variable display execution condition, is established (for example, When the number of reserved memories is not 0, the variable display of the first special symbol is not executed, and the variable display is started based on the fact that the big hit game is not executed) When time (fluctuation time) elapses, a display result (stop symbol) is derived and displayed. In addition, the variable display of the second special symbol is a variable display start condition (for example, that the game ball has won the second start winning opening 13b) after the second start condition, which is a variable display execution condition, is satisfied (for example, For example, when the number of reserved memories is not 0, the variable display of the second special symbol is not executed, and the big hit game is not executed) is started, When the variable display time (variation time) elapses, the display result (stop symbol) is derived and displayed. Note that winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  The effect display device 9 is for decoration (effect) during the variable display time of the first special symbol on the first special symbol display 8a and during the variable display time of the second special symbol on the second special symbol display 8b. Display design (also referred to as a decorative design) as a design. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Synchronous means that the start time and end time of variable display are substantially the same (may be exactly the same) and the variable display period is substantially the same (may be exactly the same). Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 reminds the jackpot The combination of is stopped and displayed.

  Below the effect display device 9, a winning device having a first start winning port 13a is provided. The game ball won in the first start winning opening 13a is guided to the back of the game board 6, and is detected by the first start opening switch 14a (for example, proximity switch) and the first winning confirmation switch 14b (for example, photo sensor). The

  A variable winning ball device 15 having a second starting winning port 13b through which a game ball can be won is provided on the right side of the winning device having the first starting winning port (first starting port) 13a. The game ball that has won the second start winning opening (second start opening) 13b is guided to the back of the game board 6 and detected by the second start opening switch 15a and the second winning confirmation switch 15b. The variable winning ball device 15 is opened by a solenoid 16. When the variable winning ball apparatus 15 is in the open state, the game ball can be won in the second start winning opening 13b (it is easy to start winning), which is advantageous for the player. In a state where the variable winning ball device 15 is in the open state, it is easier for the game ball to win the second starting winning port 13b than the first starting winning port 13a. In addition, in a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning opening 13b. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Further, as will be described later, whether or not an abnormal winning has occurred is determined based on the detection results of the first start opening switch 14a and the first winning confirmation switch 14b and the detection results of the second starting opening switch 15a and the second winning confirmation switch 15b. A security signal is externally output based on the determination and the occurrence of an abnormal winning. The variable winning ball device 15 is opened by a solenoid 16.

  Hereinafter, the first start winning opening 13a and the second start winning opening 13b may be collectively referred to as a start winning opening or a starting opening. Further, in the present embodiment, the game board 6 in a state in which the winning device having the first starting winning port 13a and the variable winning ball device 15 having the second starting winning port 13b are integrated into the starting winning unit 12. However, the game device 6 may be provided with the winning device and the variable winning ball device 15 separately.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 13b. The first start winning opening 13a is provided directly below the effect display device 9, but the interval between the lower end of the effect display device 9 and the first start winning port 13a is further reduced, or the first start winning port is set. The winning rate of the second starting winning port 13b is such that the nails are densely arranged around 13a, or the nail arrangement around the first starting winning port 13a is difficult to guide the game ball to the first starting winning port 13a. You may make it make higher than the winning rate of the 1st start winning opening 13a.

  In the upper part of the second special symbol display 8b, the number of effective winning balls that have entered the first start winning opening 13a, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) is displayed. A first special symbol reserved memory display section and the first special symbol reserved memory display section are provided separately, and a second special special display for displaying the number of effective winning balls that have entered the second start winning slot 13b, that is, the second reserved memory number. For example, a special symbol storage memory display unit 18 including a 7-segment LED provided with a symbol storage memory display unit is provided. The first special symbol reserved memory display unit displays up to four first reserved memory numbers in the order of winning, and increases the number of indicators that are turned on by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one. The second special symbol reserved memory display unit displays up to four second reserved memory numbers in the order of winning, and increases the number of indicators that are turned on by 1 each time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one. In this example, the upper limit number (up to 4) is provided for the starting memory number by winning at the first starting winning port 13a and the starting memory number by winning at the second starting winning port 13b. May be four or more.

  On the display screen of the effect display device 9, a first reserved memory display unit (not shown) for displaying the first reserved memory number and a second reserved memory display unit (not shown) for displaying the second reserved memory number. And are provided. In addition, you may make it provide the area | region (sum total pending | holding memory display part) which displays the total number (sum total pending memory count) which is the sum total of the 1st pending memory count and the 2nd pending memory count. As described above, if the summation pending storage display section for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition.

  In this embodiment, as shown in FIG. 1, the variable winning ball device 15 that opens and closes only the second start winning opening 13b is provided. Any of the start winning openings 13b may be provided with a variable winning ball device that performs opening and closing operations.

  A first special variable winning ball apparatus 20A using a first big winning opening door 1406 that is controlled to be opened by a solenoid 21A in a specific gaming state (big hit state) is provided at the lower right position of the gaming area 7. . The first special variable winning ball apparatus 20A is means for opening and closing the first big winning opening 23b. The winning ball that has won the first special variable winning ball device 20 </ b> A and led to the back of the game board 6 is detected by the first count switch 23.

  Based on the detection of game balls by the first count switch 23, a predetermined number (for example, 15) of game balls are paid out as prize balls. Thus, when the game ball passes (enters) the first special winning opening 23b that has been opened in the first special variable winning ball apparatus 20A, for example, the first starting winning opening 13a, the second starting winning opening 13b, etc. More prize balls are paid out than when a game ball passes (enters) through the prize opening. Therefore, if the first special winning opening 23b is opened in the first special variable winning ball apparatus 20A, the first state is advantageous for the player. On the other hand, if the first special winning opening 23b is closed in the first special variable winning ball apparatus 20A, the game ball cannot pass through (enter) the first large winning opening 23b and a prize ball cannot be obtained. The second state is disadvantageous for the player.

  Further, a second special variable winning ball apparatus 20B using an opening / closing plate 24c that is controlled to be opened by a solenoid 21B in a specific gaming state (big hit state) is provided at a lower left position of the gaming area 7. The second special variable winning ball apparatus 20B is means for opening and closing the second large winning opening 24b. The winning ball that has won the second special variable winning ball device 20 </ b> B and led to the back of the game board 6 is detected by the second count switch 24.

  Based on the detection of game balls by the second count switch 24, a predetermined number (for example, 15) of game balls are paid out as prize balls. Thus, when the game ball passes (enters) the second big prize opening 24b that has been opened in the second special variable prize ball apparatus 20B, for example, the first start prize opening 13a, the second start prize opening 13b, etc. More prize balls are paid out than when a game ball passes (enters) through the prize opening. Therefore, if the second special winning opening 24b is opened in the second special variable winning ball apparatus 20B, the first state advantageous to the player is obtained. On the other hand, if the second special prize opening 24b is closed in the second special variable prize-winning ball apparatus 20B, the game ball cannot pass through (enter) the second big prize opening 24b to obtain a prize ball. The second state is disadvantageous for the player.

  The normal symbol display 10 is provided on the right side of the first special symbol display 8a. The normal symbol display 10 is composed of, for example, two lamps. When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when turned on). For example, if the lower lamp is turned on at the end of the variable display, it is a hit. When the lamp on the lower side of the normal symbol display 10 is turned on and it is a win, the variable winning ball device 15 is opened for a predetermined number of times. That is, the state of the variable winning ball device 15 is a state that is advantageous from a disadvantageous state for the player when the lower lamp is turned on (a state in which a game ball can win a prize at the second start winning opening 14). ). An upper part of the special symbol storage memory display 18 is provided with a normal symbol storage memory display 41 having four display portions (for example, four segments among seven segment LEDs) for displaying the number of winning balls that have passed through the gate 32. It has been. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of display units to be turned on by one. Then, each time the variable display of the normal symbol display 10 is started, the number of display units that are lit is reduced by one.

  In addition, the normal symbol holding memory display 41 composed of 7 segment LEDs has four display units (segments) for displaying the number of winning balls that have passed through the gate 32, and the first special variable winning ball device 20A at the time of a big hit, for example, There are provided two display parts (segments) indicating the number of times the second special variable winning ball apparatus 20B is opened (number of big hit rounds) and two display parts (segments) indicating the gaming state. You may comprise by the indicator different from a symbol reservation memory | storage display part. Further, the normal symbol display 10 may be configured by a segment LED or the like that can variably display a plurality of types of identification information (for example, “◯” and “x”) called normal symbols.

  A winning opening 29a is provided on the left side of the second special variable winning ball apparatus 20B, and a game ball that has won the winning opening 29a is detected by a winning opening switch 30a. In addition, a winning opening 29b is provided on the left side of the first special variable winning ball apparatus 20A, and a game ball won in the winning opening 29b is detected by the winning opening switch 30b. Each winning opening 29a, 29b constitutes a winning area provided in the game board 6 as an area for accepting game balls and allowing winning. The first start winning opening 13a, the second start winning opening 13b, and the first big winning opening 23b also constitute a winning area that accepts a game ball and allows winning. In addition, it may be configured to detect with a detection switch that a game ball has passed a predetermined area (for example, a gate) instead of the configuration in which the game ball won in each winning opening 29a, 29b is detected with a prize switch. A decorative member 25 having a decorative lamp 25a blinking and displayed during the game is provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided below. In addition, two speakers 27 that emit sound effects are provided on the left, right, top, and bottom of the outside of the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration lamp 25a are examples of a decoration light-emitting body provided in the gaming machine. In this embodiment, the case where the light emitter provided in the gaming machine is configured by using a lamp or an LED is shown. However, the present invention is not limited to the mode shown in this embodiment. You may make it comprise all the provided light-emitting bodies using LED.

  Although not shown in FIGS. 1 and 2, a prize ball lamp that is turned on during the prize ball payout is provided in the vicinity of the left frame lamp 28b, and a supply ball is provided in the vicinity of the top frame lamp 28a. There is a ball-out lamp that illuminates when it runs out. Note that the award ball lamp and the out-of-ball lamp are controlled to be turned on by the effect control microcomputer mounted on the effect control board when the award ball is being paid out or when the out-of-ball is detected. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the first start winning port 13a and is detected by the first start port switch 14a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the first special symbol display 8a starts variable display (variation) of the first special symbol, and the effect display device 9 starts variable display of the effect symbol (decoration symbol). Is done. In other words, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13a. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning port 13b and is detected by the second start port switch 15a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the effect display device 9 starts variable display of the effect symbol (decoration symbol). Is done. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 13b. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  The variable display of the first special symbol on the first special symbol display 8a and the variable display of the second special symbol on the second special symbol display 8b are stopped when a certain time has elapsed. If the special symbol at the time of stop (stop symbol) is a big hit symbol (specific display result), it will be “big hit”, and the special symbol at the time of stop (stop symbol) will be different from the big hit symbol (predetermined display result) Is “small hit”, and if the special symbol at the time of stoppage (stop symbol) is stopped and displayed, a special symbol different from the big hit symbol and the small hit symbol is “lost”.

  After the variable display result in the special figure game becomes “big hit”, the game is controlled to the big hit gaming state as a specific gaming state in which a round advantageous to the player (also referred to as “round game”) is executed a predetermined number of times. Further, after the variable display result in the special figure game becomes “small hit”, the game is controlled to the small hit game state different from the big hit game state.

  In this embodiment, when the big win symbol corresponding to “non-probability change” or “probability change A” in the special figure game is stopped and displayed, the first big win state (15 It shifts to the round big hit state). In the big hit gaming state (usually 15 round big hit state), the first big winning opening door 1406 (see FIG. 23) of the first special variable winning ball apparatus 20A is set to a predetermined period (for example, 29.5 seconds) or the first period. In a period until a predetermined number (for example, 8) of winning balls is generated, the first special variable winning ball device 20A is in a first state advantageous to the player by opening the first big winning opening 23b ( A round to change to (open state) is executed. In this way, the first grand prize opening door 1406 which opened the first big prize opening 23b during the execution of the round receives the game ball falling on the surface of the game board 6, and then the first big prize opening 23b is closed. Thus, the first special variable winning ball apparatus 20A is changed to the second state (closed state) disadvantageous to the player, and one round is completed. In the 15 round big hit state, the number of executions of the round which is the opening cycle of the first big winning opening 23b becomes the first round number (for example, “15”). A game in the 15 round big hit state in which the number of round executions is “15” is also referred to as a 15-time open game. In such a 15 round big hit state, every time a game ball wins the first big winning opening 23b, 15 balls (prize balls) are obtained. The 15 round round big hit state is also referred to as a first specific gaming state.

  When the big hit symbol corresponding to “probability change B” is stopped and displayed as the confirmed special symbol in the special figure game, the state shifts to the second big hit state (high-speed 15 round big hit state) as the multi-round specific gaming state. In the second big hit state (high-speed 15 round big hit state), the movable portion 1163 (see FIGS. 24 and 25) of the second special variable winning ball device 20B has a second period (for example, shorter than the first period in the first big hit state). 0.5 second) or a period until a predetermined number (for example, three) of winning balls are generated, the second special winning ball device 20B is opened to the player by opening the second large winning opening 24b. A round to change to an advantageous first state (open state) is performed. In this way, the movable portion 1163 that opens the second grand prize opening 24b during the execution of the round receives the game ball falling on the surface of the game board 6, and then closes the second big prize opening 24b. Then, the second special variable winning ball apparatus 20B is changed to the second state (closed state) which is disadvantageous for the player, and one round is completed. In the second big hit state, the number of executions of the round that is the opening cycle of the second big winning opening 24b is the second round number (for example, “15”).

  In such a second big hit state, 15 game balls (prize balls) are obtained if a game ball wins the second big winning opening 24b, but the opening period of the second big winning opening 24b is the second period ( 0.5 seconds) and very short. For this reason, the second big hit state is a big hit gaming state in which a ball (prize ball) cannot be obtained substantially. The second big hit state is also referred to as a second specific gaming state. Further, the second big hit state may be one in which the number of round executions is smaller than that in the first big hit state. That is, in the second big hit state, the period during which the second big prize opening 24b is changed to the open state in each round is a second period shorter than the first period in the first big hit state, and the number of executions of the round is the first. It may be at least one of the second round numbers less than the first round number in the big hit state.

  In addition, after the first jackpot state is ended based on the fact that the jackpot symbol corresponding to “non-probable change” is stopped and displayed as a confirmed special symbol in the special figure game, it is compared with the normal state as one of the special gaming states. The time is controlled to be in a time-short state in which time-shortening control (short-time control) is performed in which the variable symbol display time (special-figure variation time) is shortened in the special figure game. Here, the normal state is a normal gaming state as a gaming state different from a specific gaming state such as a big hit gaming state, a probability variation state, and a short-time state, and an initial setting state of the pachinko gaming machine 1 (for example, a system reset is performed). As in the case where the initialization process is performed after the power is turned on, the same control is performed. If the time-short state is terminated when any of the conditions of the special game is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit” is satisfied first, Good. Thus, like the big hit symbol special symbol corresponding to “non-probable change”, the big hit symbol controlled to the short-time state after the first big hit state based on being stopped and displayed as the confirmed special symbol in the special symbol game is This is called a non-probable big hit symbol (also referred to as “normal big hit symbol”). Further, the fact that the non-probable variable big hit symbol among the big hit symbols is stopped and displayed and the variable display result becomes “big hit” is called “non-probable big hit” (also referred to as “normal big hit”).

  The jackpot symbol corresponding to “probability variation B” is displayed after the first big hit state is ended based on the fact that the jackpot symbol corresponding to “probability variation A” is stopped and displayed as a confirmed special symbol in the special symbol game. After the second big hit state is ended based on the fact that it is stopped and displayed as a confirmed special symbol in the game, the special figure variation time is shortened as one of the special game states different from the short-time state, for example, compared with the normal state. Along with the time-shortening control, the state is controlled to a probability variation state (high probability state) in which probability variation control (probability variation control) is continuously performed. In this probabilistic state, the variable display result of each special figure game and decorative design is improved so that the probability that the variable display result will be “big hit” and further controlled to the big hit gaming state will be higher than in the normal state and the short-time state. To do. Such a probability change state continues until the next variable display result is a “big hit”, regardless of the number of executions of the special game.

  Like the jackpot symbol corresponding to such “probability change A”, the jackpot symbol controlled to the probability change state after the first jackpot state based on being stopped and displayed as the confirmed special symbol in the special figure game is the probability change jackpot symbol. It is called. In addition, like the jackpot symbol corresponding to “probability change B”, the jackpot symbol controlled to the probability change state after the jackpot game state based on being stopped and displayed as the confirmed special symbol in the special figure game is the sudden hit bonus symbol. It is called. In addition, the probability variation big hit symbol out of the big hit symbol is stopped and displayed and the variable display result becomes “big hit” is called “probable big hit”. The fact that the sudden hit symbol is stopped and displayed and the variable display result is “big hit” is called “surprise big hit” (also referred to as “surprise big hit”). These jackpot symbols are arbitrary. For example, in order to prevent the player from recognizing the jackpot type, the jackpot symbol may not be a number but may be a predetermined symbol. .

  After the special symbol corresponding to “small hit” is stopped and displayed as the confirmed special symbol in the special symbol game, the small hit game state is controlled. In this small hit game state, a variable winning operation for changing the second big winning port 24b to the first state (open state) advantageous to the player is performed in the second special variable winning ball apparatus 20B as in the second big hit state. Is called. That is, in the small hit gaming state, for example, the operation of setting the second special variable winning ball device 20B to the first state (open state) over the second period is the second number {the number of executions equal to the second round number (in this example, , 15 times)}. In the small hit game state, as in the second big hit state, the period during which the second special variable winning ball apparatus 20B is in the first state is the second period, and the number of times of the operation to be set in the first state is Control may be performed so that at least one of the second times is performed. After the small hit gaming state ends, the gaming state is not changed, and the game state before the variable display result becomes “small hit” is continuously controlled. However, if the number of executions of the special figure game in the special gaming state has reached a predetermined number when the special figure game with the variable display result of “small hit” is executed, after the end of the small hit gaming state, The special gaming state may end and return to the normal state. A game in the small hit gaming state in which the number of times that the second special variable winning ball apparatus 20B is set to the first state by the variable winning operation is “15” is also referred to as a 15-time open game, similar to the game in the second big hit state. The When the winning ball apparatus provided separately from the second special variable winning ball apparatus 20B in each round in the second big hit state is changed to the first state, even in the small hit gaming state, In the same manner, the winning ball apparatus may be changed to the first state.

  In the probabilistic state and the short time state, the normal symbol display unit 10 controls the normal symbol in the normal symbol game so that the variation time of the normal symbol (ordinary symbol variation time) is shorter than that in the normal state. Control to improve the probability that the display result is “per normal figure” than in the normal state, and tilt control of the movable blade piece in the variable winning ball apparatus 15 based on the fact that the variable display result is “per normal figure”. The game ball can easily pass (enter) the second start winning opening 13b, such as control for making the tilt control time to be performed longer than that in the normal state, and control for increasing the number of tilts than in the normal state. Control that is advantageous to the player is performed by increasing the possibility that the start condition is satisfied. It should be noted that any one of these controls may be performed in the probability variation state or the short time state, or a plurality of controls may be performed in combination. As described above, the control that facilitates the entry of the game ball into the second start winning opening 13b in the probability change state or the short time state is also referred to as high release control. When the high opening control is performed, the frequency at which the second start winning opening 13b is in the expanded opening state is higher than when the high opening control is not performed. As a result, the second start condition for executing the special figure game using the second special figure in the second special symbol display 8b is easily established, and the special figure game can be executed frequently. In addition, the time until the variable display result becomes “big hit” is shortened. Therefore, in the probability variation state and the short time state, it becomes easier to enter the big hit gaming state than in the normal state. The period during which the high opening control can be executed is also referred to as a high opening control period, and this period may be the same as the period during which the gaming state in the pachinko gaming machine 1 is controlled to either the certain change state or the short-time state. . Further, it is also said that the gaming state is in the high base during the high opening control period. On the other hand, when it is not the high opening control period, it is said that the gaming state is in the low base. The time-short state in this embodiment is a gaming state that is also referred to as a low-probability high-base state, and the normal state is a gaming state that is also referred to as a low-probability low-base state. The latent probability changing state which is a state is a gaming state which is also referred to as a high probability low base state.

  Further, in this embodiment, after the end of the second big hit state based on the fact that the “probable big hit” corresponding to “probability change B” in the normal state, only the probability change control is performed, and the time-shortening control or the high opening control is performed. Shifts to the second probability variation control (latent probability variation state) in which no is performed. Further, after the end of the second big hit state based on the fact that the “probable big hit” is made in the probability change state, the state shifts to the first probability change state where the time-shortening control and the high opening control are performed together with the probability change control.

  As described above, the probability variation state includes not only the time variation control and the high release control are performed together with the probability variation control but also the probability variation control only and the time reduction control and the high release control are not performed (latency probability variation). It may be. In addition, for example, after the first big hit state based on the fact that the variable display result in the special figure game is “probable big hit”, the first positive change state (high-speed control and high-open control are performed together with the positive change control (high When the number of executions of the special figure game reaches a predetermined number of times (for example, 100 times) without the special figure display result being “big hit”, the probability variation control is continued. However, the control may be performed in a second certain change state (also referred to as a highly accurate low base state) that is not performed after the time-shortening control or the high opening control is finished.

  Further, in this embodiment, after the second big hit state is ended based on the fact that the variable display result in the special game is “abrupt big hit” when in the probability changing state, the second probability changing state (latency probability changing state) is reached. However, not only in the probability change state but also in the short time state, the variable display result in the special game is “surprise big hit”, and even after the end of the second big hit state. You may make it transfer to a probability change state. Alternatively, after the first big hit state based on the “probable big hit” is finished, it is controlled to the first positive change state until the special figure display result becomes “big hit” again, while the second big hit state based on the “surprise big hit” is controlled. After the completion, the process shifts to the first certain change state, and when the number of executions of the special figure game reaches a predetermined number without causing the special figure display result to be “big hit”, the second certain change state is entered. Also good. While the short-time control and the high-open control are started and ended simultaneously (interlocked), the start and end of the probability variation control is not necessarily linked to the start and end of the short-time control and high-open control. May be.

  In the “left”, “middle”, and “right” decorative symbol display areas provided in the effect display device 9, the special symbol game using the first special symbol and the second special symbol in the first special symbol display 8a. Corresponding to the start of one of the special figure games using the second special figure on the display unit 8b, the variable display (variation display) of the decorative symbols is started. In the period from the start of variable display of decorative symbols to the end of variable display due to the stop display of the fixed decorative symbols in the “left”, “middle”, and “right” decorative symbol display areas, The variable display state may be a predetermined reach state. Here, the reach state means a decorative symbol (“reach” which is not yet temporarily stopped when the decorative symbol temporarily stopped displayed in the display area of the effect display device 9 forms a part of the jackpot combination. "Varying symbol") is a display state in which the variation continues, or a display state in which all or part of the decorative symbols change synchronously while constituting all or part of the jackpot combination is there. Specifically, a part of the “left”, “middle”, and “right” decorative symbol display areas (for example, “left” and “right” decorative symbol display areas) constitutes a predetermined jackpot combination. In a remaining decorative symbol display area (for example, a “medium” decorative symbol display area, etc.) that has not yet been temporarily stopped when a decorative symbol (for example, a decorative symbol indicating the alphanumeric character “7”) is temporarily stopped. The display state in which the decorative symbols are fluctuating, or all or part of the “left”, “middle”, and “right” decorative symbol display areas are synchronized while the decorative symbols constitute all or part of the jackpot combination. The display state is fluctuating.

  Further, in response to the reach state, the variation speed of the decorative symbol is reduced, or a character image (an effect image simulating a person) different from the decorative symbol is displayed in the display area of the effect display device 9. Or changing the display mode of the background image, playing and displaying a moving image that is different from the decorative design, or changing the variation mode of the decorative design, performing a different rendering operation than before reaching the reach state May be. Such effect operations such as display of the character image, change of the display mode of the background image, reproduction display of the moving image, and change of the decorative pattern change mode are referred to as reach effect display (or simply reach effect). In the reach effect, not only the display operation in the effect display device 9, but also the sound output operation by the speaker 27, the lighting operation (flashing operation) in the light emitter such as the decorative lamp 25a, and a movable object (not shown) are in the reach state. It may be included that the operation mode is different from the previous operation mode. As an effect operation in the reach effect, a plurality of types of effect patterns (also referred to as “reach patterns”) having different operation modes (reach modes) may be prepared in advance. Each reach mode has a different possibility of “big hit” (also referred to as “reliability” or “big hit reliability”). That is, it is possible to vary the possibility that the variable display result will be a “hit” depending on which of the multiple types of reach effects is executed.

  During the variable display of decorative designs, unlike the reach production, the decorative display variable display state may become the reach state and the variable display result may be a “hit”. There may be a case where a variable display effect for notifying the player is given by a variable display mode of the symbol or the like. In this embodiment, variable display effects such as “slip” and “pseudo ream” can be executed, and each effect operation is executed in response to the fact that the variation pattern is determined on the main board 31 side. Or not is determined.

  In the variable display effect of “slip”, two or more decorative symbol display areas (for example, “left”) are displayed after the decorative symbols are changed in all of the “left”, “middle”, and “right” decorative symbol display areas. In addition, after a decorative symbol is temporarily stopped and displayed in the “right” decorative symbol display area, etc., a predetermined number (for example, “1” or “2”) of decorative symbols are displayed in the temporarily stopped decorative symbol display area. Change the decorative pattern to be stopped and displayed by changing the decorative pattern again in the area (for example, one or both of the “left” decorative symbol display area and the “right” decorative symbol display area). An effect display is performed.

  In the “pseudo-ream” variable display effect, the variable display of the decorative symbol is started in response to one of the first start condition and the second start condition of the special figure game being satisfied once. Before the final confirmed decorative symbol is derived and displayed, all decorative symbols are temporarily displayed in the “left”, “middle”, and “right” decorative symbol display areas, and then all decorative symbols are displayed. It is possible to perform an effect display for changing the decorative design again (pseudo-variable) in the area a predetermined number of times (for example, up to three times). The number of quasi-continuous fluctuations is displayed for the left, middle, and right decorative symbols, excluding the first variation after all decorative symbols are temporarily suspended after the decorative symbol variable display starts. This is the number of times that the decorative symbol re-varies in all areas. As an example, in the variable display effect of “pseudo-continuous”, a plurality of types of lost combinations predetermined as pseudo-continuous chances of special combinations are displayed in the “left”, “middle”, and “right” decorative symbol display areas. Any of the decorative symbols is temporarily stopped and displayed. In the temporary stop display, while the decorative symbol is stopped and displayed, the decorative symbol is displayed to the player by, for example, performing a fluctuation display or changing the decorative symbol again immediately after stopping for a short time. What is necessary is just to alert | report that the decoration design which is not decided. Alternatively, even in the temporary stop display, the decorative symbol may be re-fluctuated after the decorative symbol is stopped to such an extent that the player recognizes that the decorative symbol once displayed is confirmed.

  In the “pseudo-continuous” variable display effect, the variable display result may be set so that the possibility that the variable display result becomes “big hit” increases as the number of pseudo-continuous changes (re-changes) increases. As a result, the player can recognize that the “pseudo-ream” variable display effect is performed when any of the pseudo-ream chances is temporarily stopped and displayed. The expectation that the display result will be “big hit” is enhanced. In this embodiment, in the variable display effect of “pseudo-continuous”, the first start condition or the second start condition is satisfied once by performing the pseudo-continuous change (re-change) once to three times. Based on this, it is possible to make it appear as if the variable display of the decorative symbols has been started 2 to 4 times in succession. Note that the number of pseudo-continuous fluctuations (re-variations) in the “pseudo-continuous” variable display effect may be executed more than one to three times, for example, four or five times.

  The production operation executed as the re-variation production may include any production operation such as sound output from the speaker 27 and lighting operation of another light emitter such as the decoration lamp 25a. Further, for example, a difference in output of sound or sound effect from the speaker 27, a difference in movement of a production target object (for example, a production model, etc.) (difference in operating speed, difference in operating distance, difference in operating direction, etc.), presentation display Depending on the movement of the character image displayed on the device 9 (difference in movement speed, difference in movement distance, difference in movement direction, etc.) Alternatively, the character display may be changed or the display of the background image may be changed to change the effect mode in the re-change effect. Further, apart from the re-variation effect executed during the variation of the decorative symbol, for example, when the decorative symbol which is one of the pseudo-continuous chances is temporarily stopped, for example, sound output from the speaker 27 or light emission from the decorative lamp 25a or the like The player may be able to recognize that the chance eye has been temporarily stopped and displayed by an arbitrary production operation such as a body lighting operation.

  In addition to “slip” and “pseudo ream”, variable display effects using the variable display operation of such decorative patterns include, for example, “Development chance eyes”, “Development chance eyes end”, “Slip after chance eyes stop” Various production operations such as these may be executed. Here, in the variable display effect of “Development Opportunity”, “Left”, “Middle”, “Right” from the start of the variable display of the decorative pattern to the display of the fixed decorative pattern resulting in the variable display result. ”In the decorative symbol display area of“ ”, temporarily display the decorative symbols constituting the development opportunity included in the predetermined special combination, and then set the variable symbol display state of the decorative symbols as the reach state to achieve a predetermined reach. Is started. As a result, when the decorative symbol constituting the development opportunity is temporarily stopped, the variable display state of the decorative symbol becomes the reach state, and the variable display result becomes “big hit” after the reach state is reached. Expectation is enhanced.

  During variable display of decorative designs, unlike reach display or variable display effects such as “slip” and “pseudo-run”, for example, displaying a predetermined effect image, displaying a message as an image, outputting sound, etc. As described above, there is a possibility that the variable display state of the decorative design may reach a reach state due to a presentation operation different from the variable display operation of the decorative design, and that the variable display result may be a “hit”. A notice effect may be executed to notify the player. The effect operation that becomes the notice effect is the variable display state of the decorative symbol after the decorative symbol variable display is started in all of the “left”, “middle”, and “right” decorative symbol display areas 5L, 5C, and 5R. May be executed (started) prior to the reach state (before the decorative symbols are temporarily displayed in the “left” and “right” decorative symbol display areas 5L and 5R). In addition, the notice effect that notifies that the variable display result may be a “big hit” may include one that is executed after the variable display state of the decorative symbol becomes the reach state.

  If a special symbol that will be a lost symbol is stopped and displayed as a special symbol to be confirmed in the special symbol game, the decorative symbol variable display state will not reach the reach state after the variable symbol variable display starts. There are cases in which a fixed decorative symbol that is a non-reach combination is stopped and displayed. Such a decorative display variable display mode is referred to as “non-reach” (also referred to as “unreach loss”) variable display mode when the variable display result is “losing”.

  When a special symbol that becomes a losing symbol is stopped and displayed as a confirmed special symbol in the special symbol game, it corresponds to the fact that the decorative symbol variable display state has reached the reach state after the decorative symbol variable display has started. Then, after the reach effect is executed, a fixed decorative pattern that becomes a predetermined reach combination (also referred to as reach lose combination) may be stopped and displayed. Such a variable display result of the decorative design is referred to as a variable display mode of “reach” (also referred to as “reach lose”) when the variable display result is “losing”. It should be noted that the fixed decorative pattern that is a non-reach combination and the fixed decorative pattern that is a reach combination are collectively referred to as a fixed decorative pattern of a lost combination (non-specific combination).

  When a non-probable big hit symbol is stopped and displayed as a confirmed special symbol in a special figure game, after a predetermined reach effect is executed in response to the variable display state of the decorative symbol reaching the reach state, etc. In addition, a fixed decorative symbol that is a predetermined non-probable variation jackpot combination (also referred to as “normal jackpot combination”) is stopped and displayed. Here, the confirmed decorative symbols that are non-probable big hit combinations are, for example, symbol numbers “1” to “1” that are variably displayed in the decorative symbol display areas of “left”, “middle”, and “right” in the effect display device 9. Among the decorative patterns of “8”, any one of the decorative patterns with the even numbers “2”, “4”, “6”, “8” is the decoration of “left”, “middle”, “right” What is necessary is just to be able to be stopped and displayed on a predetermined effective line in the symbol display area. In this way, the decorative symbols having the even number “2”, “4”, “6”, and “8” constituting the non-probable variation big hit combination are referred to as non-probable variation symbols (also referred to as “normal symbols”). .

  Then, in response to the confirmed special symbol in the special figure game becoming an uncertain variable big hit symbol, after the predetermined reach effect is executed, the fixed decorative symbol of the non-probable big hit combination is stopped and displayed. The variable display mode is referred to as a variable display mode (also referred to as a jackpot type) of “non-probable change” (also referred to as “normal jackpot”) when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “non-probable change”, the game is controlled to the first big hit gaming state, and when the first big hit state is finished, it is controlled to the time reduction state.

  When the jackpot symbol corresponding to “probability change A” is stopped and displayed as a confirmed special symbol in the special figure game, the jackpot type is set to “Non-corresponding to the fact that the variable display state of the decorative symbol has reached the reach state. After a reach effect similar to the case of “probability change” is executed, or after a reach effect is executed that is different from the case where the jackpot type is “non-probability change”, a predetermined probability change big hit combination is obtained. The fixed decorative pattern may be stopped and displayed. Here, the confirmed decorative symbols that are probable big hit combinations are, for example, symbol numbers “1” to “8” that are variably displayed in the “left”, “middle”, and “right” decorative symbol display areas in the effect display device 9. Among the decorative symbols with the odd numbers “1”, “3”, “5”, “7”, the decorative symbols with “left”, “middle”, “right” What is necessary is just to stop and display on a predetermined effective line in the display area. In this way, the decorative symbols having odd numbers “1”, “3”, “5”, and “7” constituting the probability variation big hit combination are referred to as probability variation symbols. Then, in response to the confirmed special symbol in the special figure game becoming a probable big hit symbol, after the reach effect is executed, the decorative display variable display mode in which the definite decorative combination of the probable big hit combination is stopped is displayed. This is referred to as “probability change” variable display mode (also referred to as a big hit type) when the variable display result is “big hit”.

  When the probability variable big hit symbol is stopped and displayed as a fixed special symbol in the special figure game, the fixed decorative symbol that is a non-probable variable big hit combination may be stopped and displayed as a variable display result of the decorative symbol. In this way, even when the fixed decorative symbol that is a non-probable big hit combination is stopped and displayed, if the probable big hit symbol is stopped and displayed as a fixed special symbol in the special figure game, it is included in the variable display mode of “probable change”. . Thus, after the variable display result is “big hit” by the variable display mode of “probability change”, the first big hit state is controlled, and when the first big hit state ends, the probability change state is controlled. The confirmed decorative symbol that is a non-probable big hit combination and the definite decorative symbol that is a probable big hit combination are also collectively referred to as a definitive decorative symbol of a big winning combination (specific combination).

  During the variable display of the decorative symbol in which the confirmed decorative symbol is a non-probable variation jackpot combination or a certain variation jackpot combination, a re-lottery effect may be executed as a kind of certain variation promotion effect. In the re-lottery effect, after the decorative symbols that are non-probable big hit combinations are temporarily stopped and displayed in the “left”, “middle”, and “right” decorative symbol display areas on the effect display device 9, for example, “left”, “middle” ”And“ Right ”in the decorative symbol display area, the same decorative symbols are arranged again, and then fluctuated again, and the decorative symbol (probable variation symbol) that becomes the probability variation jackpot combination and the decorative symbol (non-probability variation) that becomes the non-probability variation jackpot combination One of the symbols) is stopped and displayed as a final decorative symbol (final stop display). Here, when the re-lottery effect is executed when the big hit type is “non-probable change”, as the re-lottery effect, the confirmed decoration that becomes the non-probable big hit combination after re-changing the temporarily stopped display decorative pattern A change promotion promotion effect that derives and displays a symbol is performed. On the other hand, when the re-lottery effect is executed when the big hit type is “probable change”, as the re-lottery effect, the definite decoration that becomes the probable big hit combination after re-variation of the temporarily stopped decorative pattern The changing promotion success effect during the stop display of the symbol may be executed, or the changing promotion failure effect during the change may be executed. Such a re-lottery effect including the changing promotion failure effect and the changing promotion success effect is also referred to as a changing promotion effect.

  After the definitive decorative symbol that is a non-probable jackpot combination is derived and displayed, at the start of the jackpot gaming state or during execution of the round in the jackpot gaming state, the next round will start after any round ends in the jackpot gaming state During the big hit, which is a notification effect on whether or not to control to the probable change state in the period until the start, the period from the end of the last round in the big hit gaming state to the start of the next variable display game, etc. A promotion effect may be executed. Note that a notification effect similar to the jackpot promotion effect may be executed during the first variable display game after the end of the jackpot gaming state. The jackpot promotion effect that is executed after the final round in the jackpot game state is particularly called “ending promotion effect”. Such a jackpot promotion effect is also a kind of probable promotion effect.

  In the jackpot promotion effect, there is no jackpot promotion success effect that notifies that there is a promotion that the game state becomes a probabilistic state even though the confirmed decorative pattern is a non-probable big hit combination, and there is no promotion that becomes a promiscuous state There is a promotion promotion failure during jackpot. For example, in the jackpot promotion effect, the decorative symbol is variably displayed in the display area of the effect display device 9 and either the non-probable variable symbol or the probable variable symbol is stopped and displayed as the effect display result, or the decorative symbol variable display What is necessary is just to alert | report so that a player can recognize the presence or absence of the promotion which will be in a probability change state by displaying the effect image different from.

  When the big hit symbol corresponding to “probability change B” is stopped or displayed as a special symbol in the special game, the variable display state of the decorative symbol does not reach the reach state. In addition, for example, any of a combination of a plurality of types of determined decorative symbols that are predetermined as a predetermined chance may be displayed in a stopped state. In addition, when the jackpot symbol corresponding to “probability variation B” is stopped and displayed as the special symbol for finalization in the special symbol game, the predetermined reach is determined in response to the variable display state of the decorative symbol being in the reach state. After the performance is executed, the confirmed decorative pattern that becomes a predetermined reach combination may be stopped and displayed. Corresponding to the fact that the confirmed special symbol in the special figure game becomes an abrupt big hit symbol, the variable display mode of the decorative symbol in which the various fixed ornament symbols are stopped and displayed is “surprise” when the variable display result is “big hit”. ”(Also referred to as“ sudden probability big hit ”or“ suddenly probable big hit ”) is referred to as a variable display mode (also called big hit type). Thus, after the variable display result is “big hit” by the variable display mode of “probability”, it is controlled to the second big hit state, and when the second big hit state is finished, it is controlled to the probability changing state or the latent probability changing state. become.

  When the variable display result is “big hit” and the big hit type is “accuracy”, the accuracy mode start effect may be executed during variable display of the decorative symbols. In the surprise mode start effect, a predetermined effect operation is performed in response to the big hit type being “Accuracy”. After the surprise mode start effect is performed, an effect mode different from the normal effect mode called the accuracy mode may be started. Further, the sudden start mode start effect is not limited to the effect operation executed during the variable display of the special symbol or the decoration symbol, and continues from the variable display during part or all of the period of the second big hit state. An effect operation may be performed. When the suddenness mode start effect is started, the decorative symbol that is variably displayed may be erased, and after the suddenness mode start effect is executed, the confirmed decorative symbol may not be derived and displayed. In the sudden accuracy mode, for example, until the variable display result is “big hit” and the probability variation state ends, the effect in the sudden accuracy mode is performed. In the effect during the surprise mode, the display mode of the background image in the display area of the effect display device 9 is different from the display mode in the normal effect mode, and the sound output from the speaker 27 with the variable display of the decorative pattern By making the lighting pattern of the decoration lamp 25a different from the lighting pattern in the normal production mode, or by combining some or all of them. What is necessary is just to alert | report so that a player can recognize that it is a sudden mode.

  In the probability change state, for example, an effect image for notifying that the probability change state is “currently being changed” is displayed in the display area of the effect display device 9, and a background image or a decorative pattern display mode in the display area of the effect display device 9 is displayed. May be different from the display mode in the normal effect mode, for example, so that the player can recognize that the player is in the probability change state. Alternatively, in the probability variation state, for example, the player may be unable to recognize or difficult to recognize that it is in the probability variation state due to the same effect mode as in the normal state or the short time state (so-called latent probability variation state). ). It can be said that during the period in which such a latent probability change is performed, the gaming state is in the latent probability change.

  In the latent probability changing state and the normal state, for example, by changing the display mode of the effect display device 9 to a display mode of a plurality of modes such as the daytime mode, the dusk mode, and the night mode, the possibility of the latent probability changing may be obtained. You may make it alert | report to a player. In this case, for example, when it is not a latent probability change, the day mode is easily selected and the night mode is difficult to be selected, and when the latent probability is variable, the day mode is difficult to be selected and the night mode is easily selected. The possibility of a latent probability change may be increased in the order of daytime mode, dusk mode, and night mode.

  In addition, these daytime mode, dusk mode, and night mode can be selected by, for example, lottery of “move to higher”, “do not move”, and “move to lower” every time a special game is executed. Even if it is a latent probability change, it may be changed (shifted) from the night mode to the dusk mode or the daytime mode, or may be changed (shifted) from the daytime mode to the dusk mode or the night mode.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as viewed from the back. As shown in FIG. 2, on the back side of the pachinko gaming machine 1, a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, etc. Various boards such as a game control board (main board) 31 on which is mounted, an audio output board 70, a lamp driver board 35, and a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted. ing. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, there are provided a power supply board 910 and a touch sensor board (not shown) on which power supply circuits for creating various power supply voltages such as DC30V, DC21V, DC12V and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided. ing. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. The number-of-payout counting switch 301 (see FIG. 6) for counting prize balls and rental balls is also configured as a part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back surface of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed. The terminal board 160 has, for example, an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state (starting port signal, symbol determination frequency 1 signal, jackpot 1 signal, jackpot 2 signal, jackpot 3 signal shown in FIG. An information output terminal for externally outputting a short signal, security signal, prize ball signal 1, gaming machine error state signal) is provided. Note that the gaming machine error status signal does not necessarily have to be output to the outside of the pachinko gaming machine 1, and a door indicating that the gaming frame is open from the information output terminal instead of the gaming machine error status signal. An open signal or the like may be output.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. When the ball break switch 187 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  3A is a sectional view of the first start winning opening, FIG. 3B is the second starting winning opening, FIG. 3C is the first large winning opening 23b, and FIG. It is explanatory drawing which shows a specific example. As shown in FIG. 3A, in the first start winning opening 13a, two switches (a first start opening switch 14a and a first winning confirmation switch 14b) capable of detecting a game ball won in the start winning opening. Is provided. In this embodiment, a first start opening switch 14a and a first winning confirmation switch 14b are vertically arranged in the first start winning opening 13a (in this example, the first start opening switch 14a is on the upper side). And the first winning confirmation switch 14b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the first start winning opening 13a is guided to the back of the game board 6, first detected by the first start opening switch 14a, and then by the first winning confirmation switch 14b. Detected.

  Further, as shown in FIG. 3B, in the second start winning opening 13b, there are two switches (a second start opening switch 15a and a second winning confirmation switch) capable of detecting a game ball won in the start winning opening. 15b) is provided. In this embodiment, the second start opening switch 15a and the second winning confirmation switch 15b are arranged vertically in the second start winning opening 13b (in this example, the second start opening switch 15a is on the upper side). And the second winning confirmation switch 15b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the second start winning opening 13b is guided to the back of the game board 6, first detected by the second start opening switch 15a, and then by the second winning confirmation switch 15b. Detected.

  In addition, as shown in FIG. 3C, in the first grand prize opening 23b, two switches (a first count switch 23 and a third one that can detect a game ball won in the first big prize opening 23b). A winning confirmation switch 23a) is provided. In this embodiment, the first count switch 23 and the third winning confirmation switch 23a are arranged up and down in the first big prize opening 23b (in this example, the first count switch 23 is arranged on the upper side. The third winning confirmation switch 23a is arranged on the lower side). Therefore, in this embodiment, the game ball won in the first grand prize opening 23b is guided to the back of the game board 6, first detected by the first count switch 23, and then detected by the third prize confirmation switch 23a. Is done.

  Further, as shown in FIG. 3D, in the second grand prize opening 24b, there are two switches (second count switch 24 and fourth switch that can detect the game balls won in the second big prize opening 24b. A winning confirmation switch 24a) is provided. In this embodiment, the second count switch 24 and the fourth winning confirmation switch 24a are arranged up and down in the second big prize opening 24b (in this example, the second count switch 24 is arranged on the upper side. The fourth winning confirmation switch 24a is arranged on the lower side). Therefore, in this embodiment, the game ball won in the second grand prize opening 24b is guided to the back of the game board 6, first detected by the second count switch 24, and then detected by the fourth winning confirmation switch 24a. Is done.

  Also, the first start opening switch 14a and the first winning confirmation switch 14b, the second starting opening switch 15a and the second winning confirmation switch 15b, the first count switch 23 and the third winning confirmation switch 23a, the second count switch 24 and the second Different detection method switches are used as the 4-winning confirmation switch 24a. In this embodiment, proximity switches are used as the first start port switch 14a, the second start port switch 15a, the first count switch 23, and the second count switch 24, and the first winning confirmation switch 14b and the second winning confirmation switch 15b. In this example, photosensors are used as the third winning confirmation switch 23a and the fourth winning confirmation switch 24a.

  Further, in this embodiment, as will be described later, based on the detection of the game ball by the first start port switch 14a, the first special symbol variation display is started and the prize ball payout is executed. Further, based on the fact that the game ball is detected by the second start port switch 15a, the display of the variation of the second special symbol is started, and a prize ball payout is executed. Further, based on the detection of the game ball by the first count switch 23 or the second count switch 24, a prize ball payout is executed. Further, as will be described later, it is determined whether or not an abnormal winning has occurred based on the detection result of the first winning confirmation switch 14b in addition to the detection result by the first start opening switch 14a, and the occurrence of the abnormal winning is detected. A security signal is output externally. In addition to the detection result of the second start opening switch 15a, the presence / absence of an abnormal winning is determined based on the detection result of the second winning confirmation switch 15b, and the security signal is generated based on the detection of the abnormal winning. Output externally. In addition to the detection result of the first count switch 23, whether or not an abnormal winning has occurred is determined based on the detection result of the third winning confirmation switch 23a, and the security signal is externally detected based on the detection of the abnormal winning. Is output. In addition to the detection result of the second count switch 24, whether or not an abnormal winning has occurred is determined based on the detection result of the fourth winning confirmation switch 24a, and the security signal is externally generated based on the detection of the abnormal winning. Is output. Therefore, in this embodiment, the first winning confirmation switch 14b, the second winning confirmation switch 15b, the third winning confirmation switch 23a, and the fourth winning confirmation switch 24a are used only for determination of abnormal winning.

  Thus, in this embodiment, in addition to the first start opening switch 14a, the first start winning opening 13a includes the first winning confirmation switch 14b, and the second start winning opening 13b includes the second start opening switch 15a. In addition to the second prize confirmation switch 15b, the first big prize opening 23b has a third prize confirmation switch 23a in addition to the first count switch 23, and the second big prize opening 24b has a second count switch 24. In addition, a fourth winning confirmation switch 24a is provided. The first start winning opening 13a, the second starting winning opening 13b, the first count switch 23, and the second count switch 24 are configured using proximity switches, and the first to fourth winning check switches 14b, 15b, 23a, 24a. Uses a photo sensor, but the first start opening switch 14a and the first winning confirmation switch 14b, the second starting opening switch 15a and the second winning confirmation switch 15b, the first count switch 23 and the third winning confirmation switch 23a, The detection method of the second count switch 24 and the fourth winning confirmation switch 24a is not limited to that shown in this embodiment, and for example, the first and second start port switches 14a and 15a and the first and second count switches 23, 24 and the first to fourth winning confirmation switches 14b, 15b, 23a, 24a, the first and second start points are reversed. Mouth switch 14a, 15a and the first, using a photo sensor as a second count switch 23 and 24, first to fourth winning confirmation switch 14b, 15b, 23a, may be used proximity switch as 24a. In this case, special symbol variation display and prize ball payout processing are executed based on the detection results of the first and second start port switches 14a and 15a and the first and second count switches 23 and 24, which are photosensors. The detection results of the first to fourth winning confirmation switches 14b, 15b, 23a, and 24a are abnormal in the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b. It will be used only for winning decisions. Also, for example, instead of a proximity switch or an optical photosensor that is an electromagnetic switch, the first and second start port switches 14a and 15a and the first and second count switches 23 and 24 or the first to fourth winning confirmations Mechanical switches (such as microswitches) may be used as the switches 14b, 15b, 23a, and 24a.

  Further, in this embodiment, the first and second start port switches 14a and 15a and the first and second count switches 23 and 24, which trigger the execution of the special symbol change display and the winning ball payout process, are abnormal winnings. Although provided upstream of the first to fourth winning confirmation switches 14b, 15b, 23a, 24a used for determination, they may be provided downstream of the switch used for determination of abnormal winning.

  FIG. 4 is a circuit diagram for explaining a method of detection means capable of detecting a game ball. In FIG. 4, the first start opening switch 14a and the first winning confirmation switch 14b will be described as an example. However, the second starting opening switch 15a and the second winning confirmation switch 15b, the first count switch 23, and the third winning confirmation Since the switch 23a, the second count switch 24, and the fourth winning confirmation switch 24a are the same as the first start opening switch 14a and the first winning confirmation switch 14b, detailed description thereof is omitted here.

  Further, in this embodiment, the first and second start port switches 14a and 15a, the first count switch 23, and the second count switch 24 that trigger the execution of the special symbol change display and the winning ball payout process are abnormally awarded. The first to fourth winning confirmation switches 14b, 15b, 23a, and 24a used for the determination are provided on the upstream side, but may be provided on the downstream side of the switch used for determining the abnormal winning.

  FIG. 4A shows a first start port switch 14a (second start port switch 15a) that is a proximity switch. One terminal of the first start port switch 14a (the second start port switch 15a, the first count switch 23, and the second count switch 24) is supplied with + 12V power supply voltage from the power supply board 910. A detection signal that is the voltage level of the other terminal of the first start port switch 14 a is input to the main board 31. In the main board 31, the detection signal is input from the input driver circuit to the input port of the game control microcomputer. A resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the first start port switch 14a.

  When a metal game ball passes through a hole provided in the first start port switch 14a that is a proximity switch, a counter electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Accordingly, the output of the first start port switch 14a becomes a low level close to 0V. That is, the detection signal is at a low level. When the metal game ball does not pass through the hole provided in the first starter switch 14a, the output of the first starter switch 14a is divided by + 12V by the resistance value of the coil L and the resistor R. Exceeding a threshold level that is considered high. That is, the detection signal is at a high level. Therefore, in this embodiment, the game control microcomputer can determine that the first start port switch 14a is in the OFF state if the output from the first start port switch 14a is at a high level. If the output from the start port switch 14a is at a low level, it can be determined that the first start port switch 14a is in an ON state (that is, the output of the first start port switch 14a has a negative logic). The detection signal level may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  FIG. 4B shows a first winning confirmation switch 14b (second winning confirmation switch 15b, third winning confirmation switch 23a) which is a photosensor. The photosensor illustrated in FIG. 4B includes a light-emitting diode (LED) 341 that emits light and a phototransistor 342 that receives light and outputs current. When the game ball passes in the vicinity of the light-emitting diode 341 and the phototransistor 342, the phototransistor 342 receives light from the light-emitting diode 341 reflected by the game ball and causes a current to flow to the output side. In this case, since a current flows from the collector terminal of the phototransistor 342 toward the emitter terminal, the detection signal of the photosensor is negative logic as in the proximity switch. The output side of the photosensor is connected to the main board 31, and the detection signal of the photosensor is input from the input driver circuit to the input port of the game control microcomputer. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer. As with the proximity switch, the level of the detection signal may be logically inverted by an input driver circuit and then input to the game control microcomputer 560.

  The game control microcomputer can determine that the game ball has passed through the photosensor when the detection signal from the input driver circuit is at a low level.

  In this embodiment, a reflective photosensor is used as a photosensor. As shown in the upper part of FIG. 4C, a light emitting element (LED 341) and a light receiving element (phototransistor 342) are used as winning balls. The game balls that have been installed so as to face each other and the game ball blocks light from the light emitting element and the light receiving element does not detect the light, thereby detecting the game ball that has passed between the light emitting element and the light receiving element. A transmissive photosensor may be used. When a transmissive photosensor is used, as shown in the lower part of FIG. 4C, the optical axis of the light emitting element (illustrated by a black circle in FIG. 4C) is a game ball path (winning ball). It is preferable to install the light emitting element and the light receiving element so as to deviate from the center of the game ball passing through the route. Compared to the case where the optical axis corresponds to the central portion of the game ball, a portion where the interval between two game balls passing through is relatively wide (the portion of “void” in FIG. 4C) This is because the game ball can be detected at, and the two game balls can be easily detected separately. For the same reason, when using the reflective photosensor illustrated in FIG. 4B, the light emitting element and the light receiving element are installed so that the reflection point of the light from the light emitting element is shifted from the center of the game ball. It is preferable to do.

  FIG. 5 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 5 also shows the payout control board 37, the effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads the numerical data as random R from the random number circuit 503 when a start winning to the first start port switch 14a or the second start port switch 15a occurs, and starts to change the special symbol and the effect symbol Sometimes it is determined whether or not to make a big hit display result as a specific display result based on the random R, that is, whether or not to make a big hit. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  Further, the game control microcomputer 560 inputs / outputs (transmits / receives) signals to / from the payout control board 37 (the payout control microcomputer 370) and the effect control board 80 (the effect control microcomputer) by serial communication. Serial communication circuit 505 is incorporated. The payout control microcomputer 370 and the effect control microcomputer also incorporate a serial communication circuit for inputting / outputting signals to / from the game control microcomputer 560 through serial communication (the payout control microcomputer 370 includes For the built-in serial communication circuit, see FIG. The game control microcomputer 560 includes a two-channel serial communication circuit 505, and can perform serial communication with the payout control microcomputer 370 and also performs serial communication with the effect control microcomputer 100. It is possible. However, in this embodiment, for serial communication with the production control microcomputer 100, a signal is output only from the game control microcomputer 560 to the production control microcomputer, and the production control microcomputer 100 No signal is output to the game control microcomputer 560. Note that the communication between the game control microcomputer 560 and the effect control microcomputer is not limited to the serial communication configuration, and may be configured to perform parallel communication.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as the value of the special symbol process flag and the pending storage number counter) and data indicating the number of unpaid prize balls (specifically, prize balls described later) The value of the command output counter) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). Instead of mounting the power monitoring circuit on the power supply board, it may be mounted on a board (for example, main board 31) backed up by a backup power supply. Further, a clear signal (see FIG. 5) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  In addition, the gate switch 32a, the first start opening switch 14a, the first winning confirmation switch 14b, the second starting opening switch 15a, the second winning confirmation switch 15b, the first count switch 23, the third winning confirmation switch 23a, and the second count. An input driver circuit 58 that supplies detection signals from the switch 24, the fourth winning confirmation switch 24a, and the winning opening switch 30a, 30b to the basic circuit 53 is also mounted on the main board 31, and the solenoid 16, which opens and closes the variable winning ball device 15, An output circuit 59 for driving the solenoid 21A for opening / closing the first special variable winning ball apparatus 20A and the solenoid 21B for opening / closing the second special variable winning ball apparatus 20B in accordance with a command from the basic circuit 53 is also mounted on the main board 31. A system for resetting the game control microcomputer 560 at the time of insertion. A system reset circuit (not shown) and an information output circuit 64 for outputting an information output signal such as a jackpot information indicating the occurrence of a jackpot gaming state to an external device such as a hall computer via the terminal board 160 are also main. It is mounted on the substrate 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  FIG. 6 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 6, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. The predetermined payout conditions are as follows: winning areas (ordinary winning holes 29a and 29b, first large winning holes 23b, second large winning holes 24b, first starting winning holes 13a, second starting winning holes provided in the game area) This is established when a game ball is won in 13b) or a rental ball request is made. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  The detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Further, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560. Note that specific signal exchange by serial communication between the game control microcomputer 560 and the payout control microcomputer 370 will be described in detail with reference to FIGS.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 7 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 7, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control microcomputer 101 including an effect control CPU 101a and a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). The effect control microcomputer 100 has a built-in serial communication circuit 101b that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication. In addition, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads the image data from the CGROM in response to the instruction from the effect control CPU 101a. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. In addition, the production control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decorative lamp 25a provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 8 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 8, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses a single signal line for transmission of an effect control signal to produce an effect control command (effect control signal). Is transmitted to the effect control board 80.

  As shown in FIG. 8, wiring from the first start opening switch 14a, the first winning check switch 14b, the second starting opening switch 15a, and the second winning check switch 15b is connected to the main board 31. In addition, the main board 31 has a first special variable winning ball device 20A, which is a first big winning opening 23b, a first count switch 23, a third winning confirmation switch 23a, and a second special variable, which is a second big winning opening 24b. Wiring from various switches 32a, 30a, 30b for detecting the winning of a game ball to the other winning opening, etc. is also connected to the second count switch 24, the fourth winning confirmation switch 24a of the winning ball apparatus 20B. . Further, the main board 31 is wired to the solenoid 16 for opening and closing the variable winning ball apparatus 15, the solenoid 21A for opening and closing the first special variable winning ball apparatus 20A, and the solenoid 21B for opening and closing the second special variable winning ball apparatus 20B. Is connected.

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with microcomputers provided in payout control board 37 and effect control board 80, and I / O An O port unit 57 is incorporated.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where the serial communication circuit 505 is used for communication will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  In this embodiment, as shown in FIG. 8, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, Perform serial communication. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 9 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 10 is a block diagram illustrating a configuration example of a receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 9, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 10, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. A register 711, a reception shift register 713, an interrupt control circuit 714, and a reception format / parity check circuit 716 are included.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 11 is an explanatory diagram showing an example of a data format of data transmitted / received by the serial communication circuit 505 to / from a microcomputer mounted on each control board. As shown in FIG. 11, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 11A shows an example of a data format when the data length is set to 8 bits. FIG. 11B shows an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 11, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).
Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 12 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 13A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 13A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 13B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 13B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 13B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 505) in the standby state. Is set. As shown in FIG. 13 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 13B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 13B, by setting bit 1 to “0”, the parity function is set not to be used. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 13B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 14A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 14A, the control register B 708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 14B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 14B, in the bit 7 (bit name “TIE”) of the control register B708, setting data indicating whether or not to permit a transmission interrupt request that is an interrupt request to be performed at the time of data transmission is set. Is done. As shown in FIG. 14B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 14B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request performed when data is received, is permitted. As shown in FIG. 14B, the reception interrupt request is set to be prohibited by setting bit 5 to “0”. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B708 is set with setting data indicating whether or not an idle line interrupt request that is an interrupt request to be performed when an idle line of received data is detected is permitted. As shown in FIG. 14B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 14B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 14B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used. In this embodiment, setting to use the receiving circuit is performed by setting bit 2 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 14B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 14B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 causes the microcomputer on which the control board (the payout control board 37 and the effect control board 80) is mounted with a break code (for example, a signal including “0” continuously). Send to.

  FIG. 15A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 15A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  In the present embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 15B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 15B, transmission data indicating that transmission data is not stored in transmission data register 710 (transmission data empty) in bit 7 (bit name “TDRE”) of status register A705. Stores an empty flag. As shown in FIG. 15B, when “0” is stored in the bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. In addition, when “0” is stored in bit 7, data is not written to the transmission data register. For example, in steps S5211, S52305, transmission data is set on condition that “0” is not stored in bit 7. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 15B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that. When the command storage area is in the ring buffer format, if “1” is stored in bit 6, the command read pointer is updated.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 15B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full). Whether or not the command from the payout control microcomputer 370 has been received is confirmed by whether or not “1” is stored in bit 5. For example, in steps S5221, S52401, and S52501, it is determined that the command is received on condition that “0” is not stored in bit 5. In this embodiment, bit 5 (RDRF) of status register A 705 is cleared when reception data is read from reception data register 711 by game control microcomputer 560. If the bit 5 (RDRF) of the status register A 705 is not automatically cleared when the received data is read, the game control microcomputer 560 reads the received data from the received data register 711. Every time reception data is read, it is necessary to perform processing for clearing bit 5 (RDRF) of the status register A705.

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the reception interrupt is set, the serial communication circuit 505 sets the bit 5 of the status register A 705 to “1” when reception data full is detected, and enables reception processing. As an example, an interrupt request is made to the CPU 56 (referred to as an interrupt request upon reception).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 15B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  Bit 3 (bit name “OR”) of the status register A 705 indicates that the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 15B, when “0” is stored in bit 3, it indicates that the receiving circuit is not detecting an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 15B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 15B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 15B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 16A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 16B, the status register B706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 16B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 16B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 16B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. Even when “1” is stored in bit 0, command data is not written or command data cannot be written. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 17A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 17A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if a control for writing a value to bits 4 and 5 of the control register C709 is performed, it is invalid, and all the values read from the bits 4 and 5 are “0 (= 0000b)”.

  FIG. 17B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 17B, the bit 7 (bit name “R8”) of the control register C709 stores the 9th bit data of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the 9th bit data of the transmission data when the data length is set to 9 bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 17B, by setting bit 3 to “0”, an overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 17B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 17B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 17B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 18 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 18, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when the bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where the reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of communication error is permitted, the interrupt control circuit 714 interrupts the CPU 56 with the occurrence of the communication error as a cause of interruption when detecting a parity error. Make a request.

  FIG. 19 shows a configuration example of a symbol display result determination table stored in the ROM 54. In this embodiment, as the symbol display result determination table, a first special figure display result determination table 130A shown in FIG. 19A, a second special figure display result determination table 130B shown in FIG. An ordinary map display result determination table 130C shown in FIG. 19C is prepared in advance. The first special figure display result determination table 130A has a variable display result before a fixed special symbol that becomes a variable display result is derived and displayed in the special figure game using the first special figure by the first special symbol display 8a. Whether or not to control the big hit gaming state as "big hit" and whether to control the small hit game state as "small hit" based on the random value MR1 for determining the special figure display result It is a table referred to for determination. The first special figure display result determination table 130A is a random number MR1 for determining a special figure display result depending on whether the probability variation flag provided in the game control flag setting unit provided in the ROM 54 is off or on. Are set data (determination data), etc., associated with (assigned to) big hit determination value data, small hit determination value data, and loss determination value data. The second special figure display result determination table 130B displays the variable display result before the fixed special symbol that is the variable display result is derived and displayed in the special figure game using the second special figure by the second special symbol display 8b. Is a table that is referred to in order to determine whether or not to control the big hit gaming state as “big hit” based on the random value MR1 for determining the special figure display result. The second special figure display result determination table 130B determines whether to assign the random value MR1 for determining the special figure display result to the big hit determination value data or the loss determination value data depending on whether the probability variation flag is OFF or ON. Data.

  In the ordinary figure display result determination table 130C, the comparison is made with the random number MR5 for determining the ordinary figure display result, depending on whether the time reduction flag provided in the game control flag setting unit provided in the ROM 54 is off or on. The numerical value (judgment value) to be assigned is assigned to either the common figure judgment value data or the common figure loss judgment value data. The general map display result determination table 130C is used for setting the general map change time to one of a plurality of types in accordance with the determination result of whether or not the random number MR5 matches the determination value data per universal map. When the data or the random number MR5 matches the judgment value data for each figure, the time flag for turning the second start winning opening 13b to make the game ball easy to enter (tilting control time) is off. Or setting data for setting depending on whether it is ON or ON.

  In the setting of the general map display result determination table 130C shown in FIG. 19C, the random number value MR5 for determining the general map display result is any of “1” to “15” corresponding to the case where the probability variation flag is OFF. In the meantime, the random number value MR5 for determining the normal map display result is “1” to “140” corresponding to the case where the probability variation flag is on. The determination value is allocated to the determination value data for the normal map and the determination value data for the general-purpose loss so that the determination value matches the determination value data for the normal map. With such a setting, when the probability variation flag is on corresponding to the probability variation state, the variable display result in the normal game is `` compared to when the probability variation flag is off corresponding to the normal state or the short time state ''. The probability of “per normal” is increased, and the frequency of tilt control that makes the second start winning opening 13b easy to enter the game ball can be increased. Further, the normal time fluctuation times TH3 and TH4 corresponding to when the probability variation flag is on are set shorter than the normal time fluctuation times TH1 and TH2 corresponding to when the probability variation flag is off. With this setting, when the probability variation flag is on corresponding to the probability variation state, the normal variation time in the ordinary game is shorter than when the probability variation flag is off corresponding to the normal state or the short time state. Thus, it is possible to increase the frequency at which the tilt control is performed so that the second start winning opening 13b is in a state where the game ball is likely to win. Further, the tilt control time TK2 corresponding to when the probability variation flag is on is set longer than the tilt control time TK1 corresponding to when the probability variation flag is off. With such a setting, when the probability variation flag is on, it becomes easier for a game ball to enter the second start winning opening 13b than when it is off. In the setting of the general map display result determination table 130C, when the random number MR5 for determining the general map display result is any one of “1” to “15”, corresponding to the case where the time flag is off. While it is determined that it matches the determination value data per common map, the random value MR5 for determining the general map display result is any one of “1” to “140” corresponding to the case where the time reduction flag is on. The determination value may be assigned to the normal figure determination value data and the common figure loss determination value data so that it is sometimes determined that it matches the normal figure determination value data. With this setting, even when the time reduction flag is on corresponding to the time reduction state, the variable display result in the normal game is “when the time reduction flag is off corresponding to the normal state”. The probability of “per normal” is increased, and the frequency of tilt control that makes the second start winning opening 13b easy to enter the game ball can be increased. In addition, the normal time fluctuation times TH3 and TH4 corresponding to the time reduction flag being on are set shorter than the normal time fluctuation times TH1 and TH2 corresponding to the time reduction flag being off. Even when the time reduction flag is turned on corresponding to the state, the normal time fluctuation time in the normal game is shortened compared to when the time reduction flag is turned off corresponding to the normal state, and the second start winning opening 13b. It is possible to increase the frequency with which tilt control is performed to make the game ball easy to win. Further, since the tilt control time TK2 corresponding to the time reduction flag being on is set longer than the tilt control time TK1 corresponding to the time reduction flag being off, the time reduction flag is on. In addition, it becomes easier for the game ball to enter the second start winning opening 13b than when it is off. In addition, when the time reduction flag is on corresponding to the time reduction state, the second start winning prize is obtained by increasing the number of times of tilt control compared to when the time reduction flag is off corresponding to the normal state. You may make it easier to enter the game ball into the mouth 13b.

  FIG. 19D shows a configuration example of the jackpot type determination table 131 stored in the ROM 54. When it is determined that the variable display result is “big hit” and it is determined to control to the big hit game state, the big hit type determination table 131 is based on the random number MR2 for determining the big hit type, This table is referred to in order to determine the variable display mode as one of a plurality of types of jackpot types such as “non-probability change”, “probability change A”, and “probability change B”. In the jackpot type determination table 131, whether the value of the variation special figure designation buffer (variation special figure designation buffer value) provided in the game control buffer setting unit provided in the ROM 54 is “1” or “2”. Depending on whether or not the probability variation flag is ON, the numerical value (decision value) to be compared with the random value MR2 for determining the big hit type is a big hit type of “non-probable variation”, “probability variation A”, or “probability variation B”. Assigned to. Here, the variable special symbol designation buffer value becomes “1” when the special symbol game using the first special symbol in the first special symbol display 8a is executed, and the second special symbol display 8b has the second value. It becomes “2” when the special figure game using the special figure is executed.

  In the jackpot type determination table 131, the table data indicating the determination values assigned to the plurality of types of jackpot types are the result of determining whether to control to the first jackpot state or the second jackpot state, and the end of the jackpot gaming state Later, it is data for determination corresponding to the determination result of whether to control to the probability variation state or the latent probability variation state. For example, the table data indicating the decision value assigned to the jackpot type of “non-probability change” or “probability change A” corresponds to the decision result that control is made to the first jackpot state, while the jackpot type of “probability change B”. The table data indicating the decision value assigned to the table corresponds to the decision result that the second big hit state is controlled. Further, the table data indicating the decision value assigned to the “non-probable change” jackpot type corresponds to the decision result that the control is not performed in the probability change state, while the jackpot type of “probability change A” and “probability change B”. The table data indicating the assigned decision value indicates the decision result that the control is performed in the probability variation state. The jackpot type determination table 131 sets the value of the jackpot type buffer provided in the game control buffer (the jackpot type buffer value) to a value corresponding to the determined jackpot type (for example, “0” to “2”). Table data for setting (setting data) may be included.

  In this embodiment, the assignment of the decision value to each jackpot type differs depending on whether the variable special figure designation buffer value is “1” or “2”. For example, for the jackpot type of “probability variation A”, when the fluctuation special figure designation buffer value is “1”, a decision value in the range of “21” to “60” is assigned, while the fluctuation special figure designation buffer When the value is “2”, a determined value in the range of “21” to “100” is assigned.

  For the jackpot type of “probability variation B”, when the fluctuation special figure designation buffer value is “1”, a decision value in the range of “61” to “100” is assigned, while the fluctuation special figure designation buffer value is In the case of “2”, no decision value is assigned. That is, based on the fact that the second start condition for starting the special figure game using the second special figure on the second special symbol display 8b is established, the special figure display result is controlled as the big hit gaming state as "big hit". Then, when it is determined, it is not determined that the big hit type is “probability variation B” and the second big hit state is controlled. With such a setting, when the game ball easily passes (enters) through the second start winning opening 13b in the high opening control in the probability variation state or the short time state, the big hit type becomes “probability variation B” and the prize ball Can be prevented from being controlled to the second big hit state in which the game can hardly be obtained, and a decrease in the game interest can be suppressed due to a delay in the game in the probability variation state or the short time state. In particular, when the special symbol game on the second special symbol display device 8b is executed in preference to the special graphic game on the first special symbol display device 8a, the second special symbol display device 8b is in a certain change state or a short time state. Since the frequency at which the special game is executed is increased, such a setting has a great effect of suppressing the decline of the game entertainment. Furthermore, with such a setting, the special symbol game on the second special symbol display 8b is executed in preference to the special symbol game on the first special symbol display 8a, so that the first change from the probability change state or the short time state can be made. The ratio of hitting big hits can be increased to improve the gaming fun.

  Even when the fluctuation special figure designation buffer value is “2”, for example, a smaller decision value than the case where the fluctuation special figure designation buffer value is “1” is obtained for the special figure display result of “probability variation B”. It may be assigned. Further, when the gaming state is the short-time state, if the big hit type is “probability change B” and the state shifts to the probable change state after the end of the second big hit state, the degree of advantage for the player increases. Therefore, when the gaming state is the short-time state, even if the fluctuation special figure designation buffer value is “2”, the big hit type determination table is assigned so that the determination value is assigned to the special figure display result of “probability change B”. The table data in 131 may be configured.

  FIG. 20 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 20, a payout control signal (a connection signal in this example) transmitted to the payout control board 37 is output from the output port 0. Further, a solenoid (large winning port door solenoid) 21A for opening and closing the first special variable winning ball device 20A for opening and closing the first big winning port 23b, and a second special variable winning ball device for opening and closing the second large winning port 24b. Driving signals for a solenoid (large winning opening door solenoid) 21B for opening and closing 20B and a solenoid (normal electric accessory solenoid) 16 for opening and closing the variable winning ball apparatus 15 are also output from the output port 0.

  Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 20 may be used. In particular, for the connection signal, the main board 31 and the payout control board. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  And, from the output port 1 to the external device (for example, hall computer) via the terminal board 160, the main information output signal, that is, information related to the control (for example, start port signal, symbol determination number 1 signal, jackpot 1 signal, 2 jackpots, 3 jackpots, short time signal, security signal) are output. In this embodiment, a prize ball signal 1 (a signal that is output every time one prize ball payout is detected) or a gaming machine error status signal (a gaming machine is in an error status (in this example, a ball is out of ball). An error state or a full tank error state) is also output to the external device via the terminal board 160. In this case, on the payout control board 37 side, a prize ball payout or an error state of the gaming machine is detected, and a prize ball signal 1 or a gaming machine error state signal is input to the main board 31. The prize ball signal 1 and the gaming machine error status signal input to the main board 31 are output via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. Is done. The prize ball signal 1 and the gaming machine error state signal input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the gaming control microcomputer 560.

  In addition, since the pachinko gaming machine 1 in this embodiment has two start winning ports, a first start winning port 13a and a second start winning port 13b, a game ball wins the first start winning port 13a. The start port 1 signal for notifying that the game ball has been won and the start port 2 signal for notifying that the game ball has won the second start winning port 13b are individually output to the outside via the terminal board 160. You may do it.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, a door opening signal indicating that the game frame is in an open state and prize ball information output every time ten prize balls are paid out are also output to an external device via the terminal board 160. May be. In this case, on the payout control board 37 side, it is detected that the game frame is in the open state and the payout of the winning ball is detected, and a door opening signal and winning ball information are input to the main board 31. The door opening signal and prize ball information input to the main board 31 are output to the outside via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. However, it is assumed that the door opening signal and the prize ball information are branched on the main board 31 and input to the game control microcomputer 560. In this case as well, the door opening signal and prize ball information input to the main board 31 may be output to the outside via the terminal board 160 after passing through the game control microcomputer 560 once. .

  In addition, for example, the gaming machine has two start winning ports, a first start winning port 13a and a second start winning port 13b, so that two special symbols, a first special symbol and a second special symbol, can be displayed in a variable manner. If configured, a start port 1 signal for notifying the first start winning port 13a that a game ball has won, and a second start winning port 13b for notifying that a game ball has won. The start port 2 signal is individually output to the outside through the terminal board 160, and the symbol determination number 2 signal is also added to the symbol determination number signal 1 as a symbol determination number signal for notifying the number of fluctuations of the special symbol. Alternatively, an external output may be made via the terminal board 160. In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 21 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 21, for the input ports 0 to 1 (bit 0 is not used), the gate switch 32a, the prize opening switches 30a and 30b, the magnet sensor signal 1, the magnet sensor signal 2, and the door opening signal, respectively. The prize ball information is input. In this embodiment, two magnet sensors (not shown) for detecting fraud using a magnet are provided, and detection signals from the respective magnet sensors are also input from the input port 0. . Also, the detection signal of the first start port switch 14a is input to bit 0 of the input port 1, and the detection signal of the first winning confirmation switch 14b is input to bit 1 of the input port 1, The detection signal of the second start opening switch 15a is input to bit 2, the detection signal of the second winning confirmation switch 15b is input to bit 3 of the input port 1, and the detection signal of the second winning confirmation switch 15b is input to bit 4 of the input port 1. The detection signal of the first count switch 23 is input, the detection signal of the third winning confirmation switch 23a is input to bit 5 of the input port 1, and the detection signal of the second count switch 24 is input to bit 6 of the input port 1. And the detection signal of the fourth winning confirmation switch 24a is input to bit 7 of the input port 1. In addition, a power-off signal detection signal is input to bit 0 of input port 2, and a clear switch detection signal is input to bit 1 of input port 1 (bits 2 to 7 are not used).

  FIG. 22 is a circuit diagram showing the internal configuration of the terminal board 160. In the terminal board 160 shown in FIG. 22, the upper left connector CN-1 is a connector for connecting a cable for transmitting a signal from the main board 31, and the lower left connector CN-2 is a payout control board 37. This is a connector for connecting a cable for transmitting a signal from the main board 31 via the main board 31. The right connectors CN1 to CN9 are connectors for connecting cables that transmit signals to external devices such as hall computers. The terminal board 160 is mounted with semiconductor relays (PhotoMOS relays) PC1 to PC9 as driver circuits.

  When the cable from the main board 31 is connected to the connector CN-1, various signals are input from the main board 31 (game control microcomputer 560) to the terminal board 160. Specifically, the start port signal is input to the terminal “2” of the connector CN-1, the symbol determination number 1 signal is input to the terminal “3” of the connector CN-1, and the terminal “5” of the connector CN-1 is input. 1 jackpot signal is input, 2 jackpot signals are input to terminal “6” of connector CN-1, 3 jackpot signals are input to terminal “7” of connector CN-1, and terminal “8” of connector CN-1 is input. The time reduction signal is input to “”, and the security signal is input to the terminal “9” of the connector CN-1.

  In addition, when the cable from the payout control board 37 is connected to the connector CN-2 via the main board 31, various signals from the payout control board 37 (the payout control microcomputer 370) are input to the terminal board 160. Is done. Specifically, the prize ball signal 1 is input to the terminal “2” of the connector CN-2, and the gaming machine error state signal is input to the terminal “3” of the connector CN-2.

  As shown in FIG. 22, in the terminal board 160, the signal line of the reference potential is connected to the terminal “1” of the connector CN-1 and the connector CN-2, and the signal line branches to each of the semiconductor relays PC1 to PC1. It is connected to the input terminal “1” of the PC 9. Further, the signal lines connected to the terminals “2”, “3”, “5” to “9” of the connector CN-1 and the connectors “2” and “3” of the connector CN-2 are 1 KΩ resistances, respectively. It is connected to the input terminals “2” of the semiconductor relays PC1 to PC9 via R1 to R9. The signal lines connected to the output terminals “4” of the semiconductor relays PC1 to PC9 are connected to the terminals “1” of the connectors CN1 to CN9, respectively. The signal lines connected to the output terminals “3” of the semiconductor relays PC1 to PC9 are connected to the terminals “2” of the connectors CN1 to CN9, respectively.

  In the semiconductor relays PC1 to PC9, when a signal current flows through the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is applied to the photoelectric element (solar cell) provided opposite to the LED through the transparent silicon. The photoelectric element that has received the light is exchanged for voltage according to the amount of light, and this voltage passes through the control circuit to charge the MOSFET gate of the output section. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive and turns on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the gate load of the MOSFET is rapidly discharged by the control circuit. With this control circuit, the MOSFET is turned off and the load is turned off.

  By the operation of the semiconductor relays PC1 to PC9 as described above, the signals input from the connectors CN-1 and CN-2 on the input side are transmitted to the connectors CN1 to CN9 on the output side to the external device such as a hall computer. Is output. Specifically, the start signal is output from the connector CN1, the symbol determination number 1 signal is output from the connector CN2, the jackpot signal is output from the connector CN3, the jackpot signal is output from the connector CN4, and the connector CN5 is output. Three jackpot signals are output, a time reduction signal is output from the connector CN6, a security signal is output from the connector CN7, a prize ball signal 1 is output from the connector CN8, and a gaming machine error state signal is output from the connector CN9. The assignment of connectors to each external output signal on terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the end connector (for example, connector CN9) provided on the terminal board 160. Further, the gaming machine error status signal does not necessarily have to be output to the outside of the pachinko gaming machine 1. For example, from the connector CN9, a door opening indicating that the gaming frame is in an opened state instead of the gaming machine error status signal is opened. A signal or the like may be output.

  The security signal output from the connector CN7 is a signal indicating the security state of the gaming machine. Specifically, as will be described later, the detection result of the first start opening switch 14a and the detection result of the first winning confirmation switch 14b, the detection result of the second start opening switch 15a and the detection result of the second winning confirmation switch 15b, Based on the detection result of the first count switch 23 and the detection result of the third winning confirmation switch 23a, the detection result of the second count switch 24 and the detection result of the fourth winning confirmation switch 24a, respectively, 2 When it is determined that an abnormal winning has occurred in the start winning port 13b, the first grand winning port 23b, and the second large winning port 24b, an external device such as a hall computer is used for a predetermined period (for example, 4 minutes). Is output. With such a configuration, the number of winnings to the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b using radio waves or the like is greater than the actual number of winnings. It is possible to make it possible for an external device such as a hall computer to recognize that a fraudulent act that causes recognition to increase in number is performed.

  In this embodiment, even when the gaming machine is turned on and the initialization process is executed, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds). . By configuring as such, it is recognized that the initialization process has been executed at an unnatural timing (for example, even after all the gaming machine power reset operations have been completed when the amusement store is opened). By making it possible, the external device such as a hall computer can recognize the possibility that an unauthorized act of illegally resetting the power of the gaming machine and aiming for a big hit at the power reset timing is performed. it can.

  In this embodiment, as described above, when the abnormal winning is detected and the initialization process (for example, the operation of the clear switch is performed when the power to the gaming machine is turned on) A common security signal is output from the common connector CN7 of the terminal board 160 to the outside when the process (such as clearing the stored contents) is executed. This is because the initialization process is usually performed only when the game machine power is reset when the amusement store is opened, so the terminal is used for a signal that is output only once a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, a signal for external output is configured by outputting a security signal from the common connector CN7 when an abnormal winning is detected and when an initialization process is executed. The waste of lines and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and complication of wiring work.

  The signal output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only abnormal winning to the first starting winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second big winning opening 24b, but abnormal winning to the normal winning openings 29a and 29b is detected. Thus, it may be configured such that a security signal can be externally output from the common connector CN7 of the terminal board 160. In this case, for example, with respect to the normal winning holes 29a and 29b, similarly to the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b, Two types of switches (proximity switch and photo sensor) having different detection methods are provided as switches for detection, and the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second large. The presence / absence of an abnormal prize may be determined according to the same determination method as that for the winning opening 24b.

  Further, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, a security signal is output from the common connector CN7 of the terminal board 160. You may comprise so that external output is possible. In addition, for example, when an abnormality of various switches provided in the gaming machine is detected (for example, when occurrence of a short circuit is detected by determining that the input value has exceeded the threshold value), a common terminal board 160 is used. The connector CN7 may be configured so that it can be output externally as a security signal.

  As described above, the abnormal winning, the abnormal magnetic error, and the abnormal radio wave error to the first grand prize opening 23b and the second big prize opening 24b can be externally output as security signals from the common connector CN7 of the terminal board 160. If configured, error detection can be performed by an external device such as a hall computer as long as only one signal line is connected, and the work burden related to error detection can be reduced.

  In the case of detecting an abnormal winning to the first big winning opening 23b and the second big winning opening 24b, the number detected by the first and second count switches 23, 24 and the third and fourth winning confirmation switches 23a, In addition to the case where the number of detections by 24a is determined based on a predetermined value (for example, 15) or more being determined, the value of the special symbol process flag is not a value indicating that a big hit game is being played ( For example, when the value of the special symbol process flag is not 4 or more (see FIG. 52), even when a game ball is detected by the first count switch 23 or the second count switch 24, the first big prize opening 23b or You may make it determine with the abnormal winning to the 2nd big winning opening 24b having generate | occur | produced. Further, even when it is determined that an abnormal winning to the first big winning opening 23b or the second big winning opening 24b has occurred based on the value of the special symbol process flag as described above, step S127 in the switch normal / abnormal check processing is performed. In the same manner as described above, the security signal may be externally output by setting a predetermined time (for example, 4 minutes) in the security signal information timer.

  In addition, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the security signal can be externally output from the common connector CN7 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN7 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN7 of the terminal board 160.

  In addition to the signal line and connector CN7 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  In addition to the signal line for security signal output, the detection process is detected, and the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second big winning opening 24b are detected. Separate signal lines are provided for detection of abnormal winnings, detection of abnormal magnetic errors, detection of abnormal radio wave errors, and detection of communication errors. From the terminal board 160, external outputs corresponding to the respective errors are provided along with security signals. The signal may also be output to an external device such as a hall computer. With such a configuration, it is possible to recognize that an error has occurred by checking the security signal, and further, by checking the signal output for each type of error, the type of error can be determined on the amusement store side. Can be confirmed. Therefore, when an amusement store requires a confirmation of the type of error, an external output signal for each error type is provided separately from the security signal, so that an external output that better meets the needs of the amusement store can be provided. Can be done. On the other hand, in the case of a game shop that only requests confirmation that some kind of error has occurred, only the security signal out of the externally output signals is connected to an external device such as a hall computer. Check it.

  As described above, by providing the semiconductor relays PC1 to PC9 on the terminal board 160, signal input from the outside to the inside of the gaming machine can be prevented, and as a result, illegal acts can be reliably prevented. In the above example, the semiconductor relays PC1 to PC9 are provided on the terminal board 160. However, other relay elements such as mechanical relays may be used instead of the semiconductor relays PC1 to PC9.

  Next, the structure of the first special variable winning ball device 20A constituting the first big winning opening 23b and the second special variable winning ball device 20B constituting the second big winning port 24b will be described. 23A is an internal structure diagram showing a closed state of the first special variable winning ball apparatus, FIG. 23B is an internal structure diagram showing an open state, and FIG. 23C is an enlarged cross-sectional view of a main part. is there.

  First, the first special variable winning ball device 20A will be described with reference to FIG. 23. The first special winning ball 23b of the first special variable winning ball device 20A has a horizontally long rectangular shape, and the first big winning gate door 1406 is formed. The first big winning path 1380 for guiding the game ball that has entered from the first big winning opening 23b is formed so as to face the first big winning opening 23b. The first grand prize winning passage 1380 is formed in a horizontally long shape along the first major prize winning opening 23b, and its bottom surface is inclined so as to guide the game ball that has entered the first major winning prize opening 23b to the left side when viewed from the front. It is formed in a shape.

  A first count switch 23 for detecting a game ball that has entered the first big prize opening 23b is attached to the left end side of the first big prize path 1380, and on the left side of the big prize path wall portion 1402, An outflow port 1407 through which game balls that have passed through the one count switch 23 flow out is formed. The game ball guided to the left side by the first grand prize winning passage 1380 and passing through the first count switch 23 is changed in direction toward the back side of the game board 6 and then flows out from the outlet 1407. ing.

  The solenoid 21A for driving the first grand prize opening door 1406 and the driving force of the solenoid 21A are provided at the right end in the big prize passage wall 1402, that is, on the right side of the first big prize passage 1380. An accommodating portion in which a link mechanism 1408 that transmits to 1406 is accommodated is provided.

  The first grand prize opening door 1406 is formed in a horizontally long rectangular shape that is substantially the same shape as the first big prize opening 23b. From the lower portions of the left and right side surfaces, a rotating shaft 1420 facing in the left-right direction is projected outward, and the rotating shaft 1420 can be rotated to a position near the lower portion of the first big prize opening 23b in the big prize passage wall portion 1402. The closed position (closed state, solid line in FIG. 23C) where the first big winning opening 23b is closed in the vertical direction around the rotation shaft 1420, that is, the game ball does not enter. Position) and the first large winning opening 23b by tilting outward from the closed position, that is, the open position where the ball is likely to enter (open state, the position of the two-dot chain line in FIG. 23C). It is provided so as to be rotatable between them. In the open position, the first grand prize opening door 1406 is held in an inclined posture that is inclined downward from the tip toward the rotation shaft 1420, and the ball guided on the inner surface of the first big prize opening door 1406 is It passes through the first big prize opening 23b and flows into the first big prize passage 1380.

  In addition, a linkage pin 1421 facing in the left-right direction is projected outwardly at an eccentric position that is eccentric from the rotation shaft 1420 on the right side surface of the first grand prize winning door 1406. The linkage pin 1421 is linked to a transmission member 1422 to be described later, and the first big prize opening door 1406 is opened and closed in conjunction with the rotation of the transmission member 1422.

  The solenoid 21A includes a main body portion, a plunger 21a that is detachably fitted to the main body portion, and a coil spring 21b that biases the plunger 21a to a protruding position when the solenoid 21A is in a non-excited state (off state). In the excited state (on state) of the solenoid 21A, the plunger 21a is moved to the retracted position against the urging force of the coil spring 21b.

  The link mechanism 1408 includes a transmission member 1422 and a locking member 1423. The transmission member 1422 is formed with a C-shaped linkage pin locking portion 1424 that can be locked to the linkage pin 1421 at the tip, and an elongated hole 1425 that is formed in the locking member 1423 on the inner side of the rear portion and faces in the vertical direction. A connecting pin 1426 that is slidably fitted to the connecting pin 1426 is formed. The connecting pin 1426 is provided so as to be rotatable about a rotating shaft 1427 that protrudes outward at a position eccentric to the connecting pin 1426. Yes. The rotating shaft 1427 is pivotally supported by a side wall (not shown) provided in the special winning award passage wall portion 1402.

  The locking member 1423 is attached to the distal end of the plunger 21a of the solenoid 21A, and a long hole 1425 into which the connecting pin 1426 is slidably fitted in the vertical direction is formed at the distal end. In this way, the locking member 1423 is locked to the transmission member 1422 via the connecting pin 1426 and the elongated hole 1425, so that the transmission member 1422 rotates around the rotation shaft 1427 according to the back and forth movement of the plunger 21a. By moving, the linkage pin locking portion 1424 moves up and down.

  The operating states of the solenoid 21A, the first grand prize opening door 1406, and the transmission member 1422 will be described. As shown in FIG. 23A, when the solenoid 21A is in a non-excited state (off state), the plunger 21a. Is positioned at the protruding position by the biasing force of the coil spring 21b. At this time, the transmission member 1422 has a closed posture in which the linkage pin locking portion 1424 faces downward and pushes the linkage pin 1421 toward the lower limit position, whereby the first big prize opening door 1406 is located at the closed position. Thus, the first grand prize opening 23b is closed.

  Next, when the solenoid 21A changes from the non-excited state (off state) to the excited state (on state), the plunger 21a moves backward against the biasing force of the coil spring 21b, so that it fits into the elongated hole 1425. The connected pin 1426 rotates around the rotation shaft 1427 and moves backward. As a result, the transmission member 1422 rotates around the rotation shaft 1427, so that the linkage pin locking portion 1424 at the tip is lifted from the lower limit position, and is directed to the front to push up the linkage pin 1421 to the upper limit position. As a result, the first grand prize opening door 1406 is rotated to the open position to open the first big prize opening 23b.

  Further, in the present embodiment, a link mechanism 1408 for connecting the solenoid 21A as a driving means for driving to open and close the first grand prize opening door 1406 and the first big prize opening door 1406 is as shown in FIG. In addition, the rear portion of the link mechanism 1408 does not protrude greatly toward the back side of the game board 6 because it is formed to have substantially the same thickness width dimension as the game board 6.

  The linkage pin locking portion 1424 that reciprocates up and down by rotating around the rotation shaft 1427 in accordance with the back and forth movement of the plunger 21a is positioned at the lower limit position. Since part of the opening 1428 formed in the wall 1402a is accommodated, the vertical width of the link mechanism 1408 can be shortened as much as possible to reduce the size of the apparatus.

  In addition, since the outer side of the opening 1428 is closed by the peripheral wall surface of the third opening 453 by fitting the prize-winning passage wall part 1402 in the third opening 453, an illegal member such as a wire can be used as a game. An illegal act of inserting the third opening 453 and the bottom wall 1402a from the front side of the board 6 into the big prize passage wall 1402 through the opening 1428 and forcibly opening the transmission member 1422 is prevented. can do.

  Also, the first grand prize opening door 1406 includes a first count switch 23 including a proximity switch that detects a game ball won in the first big prize opening 23b and a solenoid 21A that opens and closes the first grand prize opening door 1406. The first count switch 23 composed of an electromagnetic proximity switch due to the electromagnetic wave of the solenoid 21A, which is an electromagnetic driving means, can be prevented from being erroneously detected by being arranged apart from each other at both ends in the longitudinal direction. The solenoid 21A and the first count switch 23 can be efficiently arranged.

  Next, the second special variable winning ball apparatus 20B will be described with reference to FIGS. 24A is a longitudinal sectional view showing a closed state of the second special variable winning device, and FIG. 24B is a longitudinal sectional view showing an opened state of the second special variable winning device. FIG. 25A is a perspective view showing a closed state of the second special variable winning device, and FIG. 25B is a perspective view showing an open state of the second special variable winning device. The second special prize winning device 24B of the second special variable winning ball device 20B has a horizontally long rectangular shape, and has a lateral width dimension that allows three game balls to pass through side by side. The left-right width dimension is shorter than the left-right width dimension of the first big prize opening 23b.

  In the second special variable winning ball apparatus 20B, a movable portion 1163, which is a movable plate-like member, is provided below the second large winning path 1390 through which game balls enter. In addition, a solenoid 21B for moving the movable portion 1163 is disposed above the second special variable winning ball apparatus 20B. In addition, the movable portion 1163 and the solenoid 21B are connected by a rod-like connecting member 1164. That is, one end portion 1164a of the connecting member 1164 is connected to the movable portion 1163, and the other end portion 1164c of the connecting member 1164 is connected to the solenoid 21B. In addition, the connecting member 1164 is provided with a fixed portion 1164b which is rotatably fixed between end portions 1164a and 1164c connected to the movable portion 1163 and the solenoid 21B, respectively. Therefore, the connecting member 1164 rotates with the fixing portion 1164b as an axis in accordance with the driving of the solenoid 21B.

  When the second special variable winning ball apparatus 20B is in the closed state, as shown in FIGS. 24A and 25A, the movable portion 1163 is housed in the second large winning path 1390. It has become. The second grand prize award passage 1390 is formed such that the vertical width dimension of the second major prize winning opening 24b, which is an opening surface, can pass one game ball, but the movable portion 1163 is in the second grand prize winning passage 1390. In the housed state, the size of the opening of the second special variable winning ball apparatus 20B (the size of A shown in FIG. 24A) is equal to the thickness of the movable portion 1163, which is a plate-like member. And the opening A of the second special variable winning ball apparatus 20B is smaller than the size of one game ball. Therefore, in the closed state in which the movable portion 1163 is housed in the second grand prize winning passage 1390, the game ball cannot enter the big prize opening constituted by the second special variable prize winning ball device 20B.

  When the second special variable winning ball apparatus 20B is controlled to be in the open state, the connecting member 1164 is fixed by driving the solenoid 21B as shown in FIGS. The advancing operation is performed so that the movable portion 1163 protrudes toward the game area side by rotating around the axis 1164b. As shown in FIG. 24B, the movable portion 1163 has a second grand prize in the second big prize passage 1390 with the movable portion 1163 projecting from the back side in the second big prize passage 1390 to the game area side. An opening 1163a having a size reaching the position of the mouth 24b is provided. Therefore, when the movable portion 1163 moves forward and protrudes to the game area side, the size of the second big prize opening 24b of the second big prize passage 1390 is expanded by the opening 63a of the movable portion 1163, and the game ball is It becomes possible to pass through the second big prize opening 24b. In addition, on the front side of the opening portion 1163a of the movable portion 1163, an inclined portion 1163b that is inclined obliquely downward from the front side to the back side of the movable portion 1163 is provided, and on the right side of the opening portion 1163a. An inclined portion 1163c that is inclined obliquely downward from the front side to the left side of the movable portion 1163 is provided. The opening of the second special variable winning ball device 20B is a portion (B shown in FIG. 24 (b)) from the most front end of the inclined portion 1163b provided on the movable portion 1163 to the upper end of the opening 1163a. However, the size of the opening B of the second special variable winning ball apparatus 20B is larger than the size of the opening A in the closed state shown in FIG. 24 (a), so that one gaming ball can pass through. . Therefore, in the open state in which the movable portion 1163 moves forward and protrudes toward the game area side, the game ball can enter a big winning opening constituted by the second special variable winning ball device 20B. The game ball that has reached the opening B of the second special variable winning ball apparatus 20B is guided into the second big winning path 1390 by the inclined portions 1163b and 1163c provided in the movable portion 1163. In addition, an inclined portion 1167b that is inclined obliquely downward toward the back side is also provided above the second grand prize award passage 1390, and the game that has reached the second major prize winning opening 24b of the second major prize passage 1390 is provided. The ball is further guided into the second big prize passage 1390 by the inclined portion 1167b above the second big prize passage 1390. Then, the game ball that has entered the second grand prize-winning passage 1390 is detected by the second count switch 24.

  When the second special variable winning ball apparatus 20B is again controlled to be in the closed state, as shown in FIGS. 24A and 25A, the driving of the solenoid 21B is stopped and the connecting member 1164 is moved. It rotates in the direction opposite to the case where it is controlled to the open state with the fixed portion 1164b as an axis. Therefore, the movable portion 1163 performs a retreat operation inside the second grand prize winning passage 1390, and the movable portion 1163 is returned to the state accommodated in the second grand prize winning passage 1390.

  In this embodiment, as shown in FIG. 24 (b), when the second special variable winning ball apparatus 20B is controlled to be in the open state, an advancing operation that protrudes obliquely upward with respect to the horizontal direction is performed. A movable portion 1163 is arranged as described above. With this configuration, in this embodiment, in the second special variable winning ball apparatus 20B, a clogged ball or a game ball is sandwiched between the movable portion 1163 and the front glass (or a decorative portion 1165 described later). This makes it possible to prevent the situation from happening and allow the game to proceed smoothly.

  Specifically, when the movable portion 1163 performs an advance operation that protrudes perpendicularly to the game area, the game ball accidentally passes in front of the movable portion 1163 at the timing when the movable portion 1163 performs the protrusion operation. In this case, the game ball may be sandwiched between the movable portion 1163 and the front glass, and the movable portion 1163 may not be completely projected. Further, the impact when the game ball is caught may lead to failure of the second special variable winning ball device 20B configured using the movable portion 1163. In this embodiment, since the advancing operation is performed so that the movable portion 1163 protrudes obliquely upward with respect to the horizontal direction, the game ball accidentally passes in front of the movable portion 1163 at the timing when the movable portion 1163 performs the protrusion operation. Even if it happens, the game ball can be prevented from being sandwiched between the movable portion 1163 and the front glass.

  Further, the second special variable winning ball apparatus 20B is provided with a decoration portion 1165 which is a plate-like member having a predetermined decoration on the front side. Therefore, as shown in FIG. 24 and FIG. 25, the game ball passes to the second special variable winning ball device 20B so that the game ball enters from the upper side of the second special variable winning ball device 20B and flows downward. Routes can be restricted. Accordingly, it is possible to minimize the amount of game balls that can pass through the second special variable winning ball apparatus 20B to the minimum necessary, and more than necessary in the second large winning path 1390 of the second special variable winning ball apparatus 20B. Can be prevented from entering. Specifically, in a gaming machine, generally, a space through which one or more game balls can pass is provided between the game area of the game board 6 and the front glass, so that the movable portion 1163 is located inside the game area. Even when the player moves backward, the game ball may enter the second grand prize path 1390 from the front side with respect to the game area. By providing the decoration portion 1165 in the forward direction of the second grand prize winning passage 1390, the game balls entering from the forward direction with respect to such a game area are eliminated, and the second special winning prize passage of the second special variable prize winning ball device 20B is eliminated. It is possible to prevent the game balls from entering 1390 more than necessary.

  In this embodiment, since the front side of the second special variable winning ball apparatus 20B is covered with the decoration portion 1165, the movable portion 1163 moves forward or backward. The situation can be made difficult for the player to recognize.

  Next, winning (entry) to each winning device and each winning opening constituting the first starting winning opening 13a, the second starting winning opening 13b, the first large winning opening 23b, the second large winning opening 24b, and the winning openings 29a and 29b. ) The structure of the game ball passage through which the game balls flow down will be described with reference to FIG. 26A is a rear view showing various winning paths provided in the game board, FIG. 26B is a view showing the vicinity of the outlet of the second winning path, and FIG. 26C is the first grand prize. It is a figure which shows the discharge port vicinity of a channel | path, (d) is a figure which shows the discharge port vicinity of a 1st prize-winning channel | path, (e) is a figure which shows the discharge port vicinity of a 2nd big prize channel | path.

  As shown in FIG. 26 (a), the game board 6 is provided with a first opening 451 to which a variable display control unit including an effect display device 9 is attached and a winning device that forms a first start winning opening 13a. A second opening 452, a third opening 453 to which the variable winning ball apparatus 15 that forms the second start winning opening 13 b is attached, and a fourth special variable winning ball apparatus 20 A that forms the first large winning opening 23 b. An opening 454, a fifth opening 455 to which the second special variable winning ball apparatus 20B forming the second large winning opening 24b is attached, a sixth opening 456 to which the decorative member 25 is attached, and a seventh constituting the out opening 26. Openings 457 are respectively formed.

  From the lower part of the back of the start winning unit having the first start winning opening 13a attached to the second opening 452 from the front side, a first winning passage 1360 through which a game ball won in the first starting winning opening 13a flows downward is provided. It is extended toward. The first winning path 1360 is formed in a cylindrical shape from a transparent synthetic resin material (not shown in detail), and is suspended downward from the second opening 452.

  A first start opening switch 14a is provided on the upstream side of the first winning path 1360, and a first winning confirmation switch 14b is provided on the downstream side of the first winning opening 1360. After being detected by the 1 start port switch 14a and the first winning confirmation switch 14b arranged on the downstream side thereof, it is discharged from the discharge port 1452 and discharged into a collection basket 1500 described later.

  From the lower back of the variable winning ball apparatus 15 attached to the third opening 453 from the front side, a second winning path 1370a through which a game ball that has won a prize at the second start winning opening 13b flows downward is extended downward. Yes. The second winning path 1370a is formed in a cylindrical shape by a transparent synthetic resin material (not shown in detail), and hangs downward from the third opening 453. In addition, a second winning path 1370b provided on the back surface of the first special variable winning ball apparatus 20A, which will be described later, is connected to the lower end opening of the second winning path 1370a. The second winning path 1370b is formed in a cylindrical shape with a transparent synthetic resin material (not shown in detail), and hangs downward.

  A second start opening switch 15a is provided in the upstream second winning passage 1370a, and a second winning confirmation switch 15b is provided in the downstream second winning passage 1370b. The winning game ball is detected by the second start opening switch 15a and the second winning confirmation switch 15b arranged downstream thereof, and then discharged from the discharge opening 1453 and discharged into a collection basket 1500 described later. .

  From the back surface of the first special variable winning ball apparatus 20A attached to the fourth opening 454 from the front side, a first big winning passage 1380 in which a game ball that has won the first big winning opening 23b flows down extends downward. Has been. The first big prize passage 1380 is formed in a cylindrical shape by a transparent synthetic resin material (not shown in detail), and is suspended downward from the fourth opening 454.

  The first prize-winning passage 1380 is provided with a third prize-confirming switch 23a, and a game ball that has won a prize passage in the first special variable prize-ball device 20A from the first big prize-winning port 23b is a game board. 6 is guided to the right side when viewed from the back and then detected by the first count switch 23 and then guided to the back side of the game board 6 and flows into the first grand prize path 1380, and then the first grand prize is won. After being detected by the third winning confirmation switch 23a provided in the passage 1380, it is discharged from the discharge port 1454 and discharged into a collection basket 1500 described later.

  From the back surface of the second special variable winning ball apparatus 20B attached to the fifth opening 455 from the front side, a second large winning path 1390 through which the game balls that have won the second large winning opening 24b flow down extends downward. Has been. The second grand prize winning passage 1390 is formed in a cylindrical shape by a transparent synthetic resin material (not shown in detail), and is suspended downward from the fifth opening 455.

  The second grand prize award passage 1390 is provided with a fourth prize confirmation switch 24a. A game ball that has won a prize passage provided in the second special variable prize winning ball device 20B from the second major prize opening 24b is a game board. 6 is guided to the right side when viewed from the back and then detected by the second count switch 24 and then guided to the back side of the game board 6 and flows into the second grand prize path 1390, and then the second grand prize. After being detected by the fourth winning confirmation switch 24a provided in the passage 1390, it is discharged from the discharge port 1455 and discharged into a collection basket 1500 described later.

  From the back surfaces of the decorative members 25 and 25 attached to the left and right sixth openings 456 and 456 from the front side, the winning ball 1450 through which the winning game ball flows down to the winning port 29a and the winning game ball into the winning port 29b flow down. The winning path 1451 is extended downward. The winning passages 1450 and 1451 are formed in a cylindrical shape by a transparent synthetic resin material (not shown in detail), bent from the back of the decorative members 25 and 25 toward the center, and then suspended downward. Yes.

  The winning passages 1450 and 1451 are provided with winning opening switches 30a and 30b, respectively, and the game balls that have won the winning opening 29a are detected by the winning opening switch 30a and then discharged from the discharge opening 1457, which will be described later. Discharged inside. In addition, the game ball won in the winning opening 29b is detected by the winning opening switch 30b, and then released from the discharge opening 1458 and discharged into a collection basket 1500 described later.

  In addition, as shown in FIGS. 26 (b) (c) (d) (e), games that have dropped in the vertical direction at the lower positions of the discharge ports 1452 to 1455 of the winning paths 1360, 1370, 1380, 1390. Discharge direction changing surfaces 1460 to 1463 for changing the discharge direction of the sphere to the left diagonally downward or right diagonally downward direction are provided, respectively.

  A game ball released from each of the discharge ports 1452 to 1455 falls into a collection basket 1500 provided in a game frame (not shown) of the game machine, and is finally discharged from the game machine and is not shown. It is collected in the collection path. The recovery basket 1500 is formed in a funnel shape, and a bottom surface 1501 as a recovery path surface is formed in an inclined surface shape that is inclined downward toward the central discharge path 1502, and is discharged from each of the discharge ports 1452 to 1455. The game ball is guided toward the discharge path 1502 and discharged.

  In a state in which the game board 6 is attached to the game frame, the bottom ball 1501 is disposed in the left-right direction directly below each of the outlets 1452 to 1455, so that the game ball released from the outlets 1452 to 1455 and dropped on the bottom surface 1501. Is expected to jump, but since each of the outlets 1452 to 1455 is provided with a discharge direction changing surface 1460 to 1463, the first winning confirmation switch 14b, the second winning confirmation switch 15b, and the third winning confirmation The game balls that have passed through the switch 23a and the fourth winning confirmation switch 24a are not released in the vertical direction. In other words, it is possible to prevent the game ball falling on the bottom surface 1501 from jumping and being detected again by the first winning confirmation switch 14b, the second winning confirmation switch 15b, the third winning confirmation switch 23a, and the fourth winning confirmation switch 24a. The

  In this embodiment, the variable winning ball device 15 having the second start winning port 13b and the first special variable winning ball device 20A are arranged close to each other in the vertical direction, thereby providing an effect provided in the game area 7. It is possible to secure a wide range of arrangement space for the display unit of the display device 9 and the accessory or decoration member arranged on the right side thereof, and thereby the display unit of the effect display device 9 in the limited game area 7 It is possible to increase the size of the accessory, decoration member, etc. as much as possible.

  A second start winning opening 13b is disposed close to the first special variable winning ball apparatus 20A, and the second winning passages 1370a and 1370b through which the game balls won from the second starting winning opening 13b pass, The second start opening switch 15a and the second winning confirmation switch 15b are attached. However, if the second winning passages 1370a and 1370b are shortened, the second starting opening switch 15a and the second winning confirmation switch 15b are separated by a predetermined distance. It becomes difficult to arrange. Therefore, the second winning path 1370b on the downstream side is provided on the back surface of the first special variable winning ball apparatus 20A, and the second winning confirmation switch 15b is attached to the second winning path 1370b, thereby being limited to the second winning path 1370b. Since the variable winning ball device 15 and the first special variable winning ball device 20A that form the second start winning opening 13b can be arranged with the smallest possible interval, the effect display device 9 provided in the game area 7 It is possible to secure a wide range of arrangement space for the display unit, the accessory or the decorative member arranged on the right side thereof.

  Further, in this embodiment, the electromagnetic first start opening switch 14a and the optical second prize confirmation are detected in the first winning passage 1360 through which the game balls won from the first starting winning opening 13a pass. A switch 15b is attached, and an electromagnetic second start port switch 15a and an optical first switch having different detection methods are inserted into second winning passages 1370a and 1370b through which a game ball won from the second start winning port 13b passes. 2 Since the winning confirmation switch 15b is installed, the game ball can be detected normally without being affected by fraudulent acts caused by radio waves or light. It is possible to prevent fraudulent acts such as causing a jackpot to be executed.

  Further, in this embodiment, an electromagnetic first count switch 23 and an optical third winning confirmation switch having different detection methods in the first big winning passage 1380 through which a game ball won in the first big winning opening 23b passes. 23a and an electromagnetic second count switch 24 and an optical fourth prize confirmation switch having different detection methods in a second major prize passage 1390 through which a game ball won in the second major prize opening 24b passes. 24a is attached. That is, by providing two sensors with different detection methods in the first big prize opening 23b and the second big prize opening 24b, which are separately spaced apart on the left and right sides of the lower part of the game area 7, respectively. Unauthorized acts in both the special variable winning ball apparatus 20A and the second special variable winning ball apparatus 20B can be reliably prevented.

  If the game balls that have entered the first grand prize opening 23b and the second big prize opening 24b are detected by the pair of count switches and the prize confirmation switch, the passages extending from the respective big prize openings are merged. Therefore, it is necessary to provide a switch in the joined passage. Therefore, as in the present embodiment, if the first grand prize opening 23b and the second big prize opening 24b are arranged at a large distance from each other, the passage structure becomes complicated in order to merge, so the first major prize opening 23b and The arrangement of both the second grand prize winning ports 24b is limited in design. Therefore, by providing two sensors with different detection methods in both the first grand prize opening 23b and the second big prize opening 24b, it is possible to freely arrange the respective big prize openings 23b and 24b.

  In this embodiment, based on the fact that a game ball has won the first start winning opening 13a, the first special symbol display unit 8a starts the variable display of the first special symbol, and the second starting winning opening 13b. The second special symbol display 8b starts to display the variation of the second special symbol based on the fact that the game ball has won a prize, for example, the first start winning port 13a or the second starting winning port, for example. Based on the fact that the game ball has won 13b, the special symbol variable display may be started by one special symbol display. That is, you may provide two or more start winning openings corresponding to a single special symbol display.

  Next, the operation of the gaming machine will be described. FIG. 27 is a flowchart showing the main process executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output is impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed when the power is turned on, not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15. In addition, after setting in step S93, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  The CPU 56 sets a predetermined time (in this example, 30 seconds) in the security signal information timer (step S14a). The security signal information timer is a timer for measuring the ON time of the security signal output from the terminal board 160. In this embodiment, an initialization process is performed when the gaming machine is turned on by executing an information output process (see S31), which will be described later, based on the fact that a predetermined time is set in the security signal information timer in step S14a. Is executed, a security signal is externally output for a predetermined time (in this example, 30 seconds).

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs setting according to the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 in accordance with the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of the interrupt process by executing the process according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs an initial setting so as to preferentially execute an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 according to the interrupt process priority order table. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15 to S15b, a part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also executed in the process of step S5. For example, in step S5, an initial value is set in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  For example, in setting the internal device register, the CPU 56 sets the baud rate of the serial communication circuit 505. In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  For example, the CPU 56 sets the data format of data transmitted and received by the serial communication circuit 505. In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the presence / absence of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  Further, for example, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505. In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the game control microcomputer 560 stores in advance a designation information for designating values of each bit of the control register B 708 and the control register C 709 set by a user (for example, a manufacturer of the gaming machine) in a predetermined storage area of the ROM 54. I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  In the initialization process of the main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. Note that the process of setting the initial value to the prize ball number counter may be executed, for example, in the process of sequentially setting each initial value in the work area of steps S92 and S12, until the process proceeds to steps S15 to S17. It only has to be executed during

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the first special symbol display 8a and the second special symbol display 8b. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same process is executed in steps S26 and S27 of the interrupt process), so as to avoid conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process or reception Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the timer interrupt process will be described. FIG. 28 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) that detects whether or not a power-off signal has been output (whether the power-on signal has been turned on) (step S20). Then, the CPU 56 via the switch circuit 58, the gate switch 32a, the first start opening switch 14a, the first winning confirmation switch 14b, the second starting opening switch 15a, the second winning confirmation switch 15b, the first count switch 23, The detection signals of the switches such as the third winning confirmation switch 23a and the winning opening switches 30a and 30b are input, and the input of each switch is detected (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 performs display control to perform display control of the first special symbol display 8a, the second special symbol display 8b, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41. Processing is executed (step S22). For the first special symbol display 8a, the second special symbol display 8b, and the normal symbol display 10, a drive signal is output to each display according to the contents of the output buffer set in steps S36 and S37. Execute control.

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating a random number for determination such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of sending an effect control command by setting an effect control command related to the effect symbol synchronized with the variation of the special symbol in the transmission data register of the serial communication circuit 505 (effect symbol command control process: step S30). . It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 performs information output processing for outputting data such as a start port signal supplied to the hall management computer, a symbol determination number of times 1 signal, a jackpot 1 to 3 signal, a time reduction signal, a security signal, and the like (step S31). ).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, detection of the winning opening switches 30a, 30b, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switches 30a, 30b being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to the connection signal and the contents related to the solenoid in the RAM area of the output port 0. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in the output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs frame state output processing for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to display the error state of the gaming machine to the production control microcomputer 100. Execute (step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

  Next, the prize ball process (step S32) in the main process will be described. First, payout control signals (connection signals, prize ball information) and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described.

  FIG. 29 is an explanatory diagram showing an example of the content of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 29, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. This is a signal (connection signal for the main board 31). The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and is used for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, in step S34). Although it is output by processing, it may be output at the timing of step S4). The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time ten prize balls are paid out on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed via the input circuit 67B and the I / O port 57 of the game control microcomputer 560. To the microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 30 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined contents depending on the contents of the set 8-bit data.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with regard to “xxxx” in the second byte of the connection OK command, as shown in FIG. 31, a prize ball error (a prize ball payout operation based on winning or a ball lending operation based on a ball rental request cannot be performed normally). 92: When the main control unconnected error shown in FIG. 92, the payout switch abnormality detection error 1, the payout switch abnormality detection error 2, the payout case error, the main control communication error shown in FIG. In this case, “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified. In the example shown in FIG. 31, the connection OK command is set to a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) as a control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, when a game ball is detected by the first start port switch 14a and the second start port switch 15a, three prize balls are paid out, and the game ball is detected by one of the winning port switches 30a and 30b. Then, 10 prize balls are paid out. When a game ball is detected by the first count switch 23 and the second count switch 24, 15 prize balls are paid out. Therefore, when a game ball is detected by the first start port switch 14a and the second start port switch 15a, a prize ball number command “01010011” for notifying three prize balls is transmitted, and the prize opening switches 30a, 30a, When a game ball is detected in any of 30b, a prize ball number command “01011010” for notifying 10 prize balls is transmitted, and a game ball is detected by the first count switch 23 and the second count switch 24. If it is, a prize ball number command “0101111” for notifying 15 prize balls is transmitted. In this embodiment, the game balls are detected by the first count switch 23 and the second count switch 24 so that the number of prize balls paid out is less than 15 (for example, 3 or 5). It may be.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball quantity command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball quantity command. It is a control command transmitted as a signal. The content of the prize ball number reception command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The contents of the data of the winning ball preparation command are “4x (H)”, that is, “0100xxxx”. Here, with regard to “xxxx” in the second byte of the command for preparing a prize ball, as shown in FIG. 31, when a prize ball error occurs, “1” is set to “1” in the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. The game control microcomputer 560 can be notified that the operation has not ended, and the contents of the error can also be notified to the game control microcomputer 560. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). Note that the command for preparing a prize ball is not only in a state where an error occurs and the prize ball operation cannot be executed, but also in a state where the prize ball payout operation cannot be started immediately because the ball rental operation is in progress, This command (signal) is output even in the running state (the state in which the payout operation for the number of prize balls specified by the prize ball number command has not been completed). The example shown in FIG. 31 shows a case where a value indicating a payout error (a prize ball error, a full tank error, a ball run out error, a payout number error error) is set as a control state in the command for preparing a prize ball. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that the prize ball payout operation or the lending ball payout operation is in the control state in the award ball preparation command, and the game control microcomputer 560. You may make it transmit to.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control command, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number acceptance command, a payout end signal is realized by a prize ball end command, and a payout signal is realized by a prize ball preparation command.

  32 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 29 and the control command shown in FIG. As shown in FIG. 32, the connection signal is output by the game control microcomputer 560 via the output circuit 67A and input to the payout control microcomputer 370 via the input circuit 373A. The prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and input to the game control microcomputer 560 via the input circuit 67B. A prize ball signal 1 and a gaming machine error state signal, which will be described later, are also output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B. May be. The door opening signal may also be output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B.

  Of the control commands, the connection confirmation command and the prize ball number command are output from the serial communication circuit 505 built in the game control microcomputer 560 and input to the serial communication circuit 380 built in the payout control microcomputer 370. The Of the control commands, the connection OK command, the winning ball number acceptance command, the winning ball end command, and the winning ball preparation command are output from the serial communication circuit 380 built in the payout control microcomputer 370, and the gaming control microcomputer 560. Is input to the serial communication circuit 505 incorporated therein. In FIG. 32, two signal lines (signal lines for sending commands from the game control microcomputer 560 to the payout control microcomputer 370 side and payout control microcomputers) are used as signal lines for serial communication. 370 shows a signal line for transmitting a command from 370 to the game control microcomputer 560 side, but actually, the payout control command is transmitted and received through one signal line. A signal line for transmitting a command from the game control microcomputer 560 to the payout control microcomputer 370 side, and a signal line for transmitting a command from the payout control microcomputer 370 to the game control microcomputer 560 side. May be configured as separate signal lines.

  Next, transmission / reception of a payout control command between the game control microcomputer and the payout control microcomputer during normal operation will be described. In this embodiment, a connection confirmation command and a prize ball number command are transmitted from the game control microcomputer 560 to the payout control microcomputer 370, and the payout control microcomputer 370 is connected to the game control microcomputer 560. An OK command, a prize ball number reception command, a prize ball end command, and a prize ball preparation command are transmitted.

  FIG. 33 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 33, the game control microcomputer 560 is connected to the payout control microcomputer 370 via the serial communication circuit 505 to confirm whether or not the signal line is disconnected. A confirmation command is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives the connection confirmation command via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  34 and 35 are sequence diagrams showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during the prize ball movement. As shown in FIGS. 34 and 35, when a winning occurs and a winning ball payout operation is executed, the game control microcomputer 560 is set with data indicating the number of winning balls via the serial communication circuit 505. The prize ball number command is transmitted to the payout control microcomputer 370. In this case, the game control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the received connection OK command with respect to the connection confirmation command transmitted last time (see FIG. 31), and A winning ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received after the connection OK signal is received until 1 second elapses.

  Next, when the payout control microcomputer 370 receives the award ball number command, if the award ball operation can be executed immediately (that is, if the lending ball is not being dispensed and no error has occurred), the award A prize ball number reception command indicating that the number of balls has been received is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  Next, when the game control microcomputer 560 receives the prize ball end command, as shown in FIG. 34, if the number of prize balls to be paid out is not yet stored, the game ball control command 560 issues a prize ball end command. Transmission of a new connection confirmation command is resumed after 1 s (1 second) has elapsed from the time of reception. On the other hand, as shown in FIG. 35, when the number of prize balls to be paid out has already been stored, a prize ball number command for immediately specifying the next prize ball number is issued without waiting for 1 s (1 second). This is sent to the payout control microcomputer 370. In this case as well, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 31), and The award ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received from the reception of the ball end command until 1 second elapses. Thereafter, transmission and reception of control commands are repeated according to the same sequence.

  FIG. 36 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when the winning ball operation cannot be executed immediately. Even if the payout control microcomputer 370 receives the award ball number command, if the lending ball is being paid out or is in an error state, the award ball number specified by the received award ball number command. Unable to start the prize ball payout operation. In such a case, as shown in FIG. 36, even when the payout control microcomputer 370 receives the prize ball number command, it does not immediately send the prize ball number acceptance command, and the prize ball payout operation is completed. A command for preparing a prize ball for notifying that the game has not been sent is transmitted to the game control microcomputer 560. In this case, the payout control microcomputer 370 is in a state of preparing a prize ball at regular intervals (every 1 s) unless the payout operation of the lending ball is completed and the award ball action can be started or the error is not canceled. The command is transmitted to the game control microcomputer 560.

  Next, the payout control microcomputer 370 finishes the lending ball payout operation and becomes ready to start the next prize ball operation, or when the error is canceled, the prize indicating that the number of prize balls has been received is received. The ball number acceptance command is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  FIG. 37 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 37, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits the connection confirmation command again after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  If there is a prize when the connection confirmation communication process is not executed (between receiving the connection OK command and transmitting the next connection confirmation command), the game control microcomputer 560 The control for repeatedly transmitting the confirmation command is interrupted, data indicating the number of winning balls is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. In this case, the game control microcomputer 560 performs a process of subtracting the prize ball number storage based on the reception of the prize ball number reception command (specifically, 1 is subtracted from a prize ball command output counter described later). (See step S52404). Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command, and when the prize ball payout (prize ball payout operation) is completed, the prize ball end command is sent to the game control microcomputer. Send to computer 560. As described above, when the winning ball payout operation takes a long time, the payout control microcomputer 370 waits for 1 s (1 second) until the winning ball payout operation is completed. Is sent repeatedly. When the game control microcomputer 560 receives the prize ball end command, if the number of prize balls to be paid out is not yet stored, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. To do.

  If there is a prize during the execution of the connection confirmation communication process (between sending the connection confirmation command and receiving the connection OK command), the game control microcomputer 560 and the payout control microcomputer 370 Since the connection state is not confirmed, the award ball number command is not immediately transmitted, but the process waits until the connection OK command can be confirmed. When the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 sets data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and sets the set number of winning balls. The command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 performs the same processing, pays out the number of prize balls designated by the prize ball number command, and when the prize ball is paid out (prize ball payout operation), The ball end command is transmitted to the game control microcomputer 560.

  After receiving the winning ball end command, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 31). In addition, even when the start winning prize is received from the reception of the winning ball end command until 1 second elapses, the winning ball number command is transmitted to the payout control microcomputer 370. In other words, in this embodiment, the game control microcomputer 560 receives a prize ball end command from when a connection OK signal in which a value indicating an error is not set until one second elapses. The award ball number command can be transmitted until 1 second has elapsed.

  FIG. 38 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when an error occurs in the winning ball. As shown in FIG. 38, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. If there is a win when the communication process for confirming the connection is not executed, the game control microcomputer 560 sets the data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and the set winning prize is set. The ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command. When executing the payout operation for the number of prize balls specified by the prize ball number command, a predetermined error (for example, an abnormal payout number error, a ball lending, a full tank, or an out of ball error) occurs. When the ball payout operation cannot be performed (abnormal state, error state), the payout control microcomputer 370 issues a prize ball preparing command for notifying that an error has occurred and the prize ball payout operation has not ended. It transmits to the game control microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. When the predetermined error state is canceled (resolved) and the winning ball payout operation ends, the payout control microcomputer 370 transmits a winning ball end command to the game control microcomputer 560. The award ball preparation command is transmitted from the payout control microcomputer 370 to the game control microcomputer 560 every 1 s after the award ball number acceptance command is transmitted. Further, while the game control microcomputer 560 is receiving a command for preparing a prize ball, the game control microcomputer 560 is controlled not to transmit a connection confirmation command. Specifically, the payout control microcomputer 370 outputs a prize ball end command based on the completion of the prize ball payout operation, and the game control microcomputer 560 receives the prize ball end command. Based on this, control is performed so as to return to a state in which a connection confirmation command is output every predetermined period (1S).

  FIG. 39 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during connection confirmation. As shown in FIG. 39, the game control microcomputer 560 has transmitted the connection confirmation command to the payout control microcomputer 370, but has not received the connection OK command from the payout control microcomputer 370, that is, When a connection state abnormality (communication error) occurs, the connection confirmation command is transmitted again after 10 s (10 seconds) have elapsed since the connection confirmation command was transmitted. In other words, if the process of transmitting the connection confirmation command every 1 s (1 second) when the connection OK command cannot be received is continued, the number of connection confirmation command transmissions is increased even though the communication state is unstable. Since it increases in vain, the transmission interval of the connection confirmation command is extended to 10 s (10 seconds), and the control is switched to transmitting the connection confirmation command with the minimum necessary number of transmissions until the communication state is recovered. If a winning occurs when a communication error has occurred, the game control microcomputer 560 will receive a connection OK command from the payout controlling microcomputer 370, even if a new winning occurs. Without transmitting the award ball number command, the connection confirmation command is continuously transmitted at regular intervals (10 s). When the communication error is canceled (resolved) and a connection OK command is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a prize ball number command.

  FIG. 40 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during the prize ball number notification. As shown in FIG. 40, the game control microcomputer 560 has transmitted a prize ball number command based on the occurrence of a win, but has not received a prize ball number acceptance command from the payout control microcomputer 370. In this case, that is, when a connection state abnormality (communication error) occurs, a connection confirmation command is transmitted to the payout control microcomputer 370 after 10 seconds (10 seconds) have elapsed since the prize ball number command was transmitted. Then, the connection confirmation command is repeatedly transmitted every 10 s (10 seconds) until the communication state is recovered. After that, when the communication error is canceled (resolved) and the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 returns to the normal (normal) operation, and the prize ball number command Is retransmitted (retryed) to the payout control microcomputer 370. Specifically, the game control microcomputer 560 does not subtract the prize ball number storage if it does not receive the prize ball number acceptance command even after sending the prize ball number command (described later). If N in step S52403, the value of the prize ball command output counter in step S52404 is not subtracted by 1), and the value of the prize ball command output counter is maintained as it is when the prize ball number command is transmitted next time. The prize ball number command is retransmitted based on that (see steps S52301 to S52035 described later).

  Next, the prize ball process (step S32) will be described. FIG. 41 is a flowchart showing an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 42 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the prize ball command output counter, and the prize ball designation for designating the number of prize balls Data is set sequentially. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2, 3 (2) corresponding to the prize ball number “10”. Corresponding to the normal winning ports 29 and 30) and a prize ball command output counter 4 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15) based on the prize ball designation data for designating the number of prize balls (15). The data is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0. Based on the prize ball designation data for designating the number of prize balls (3), data indicating the number of prize balls (3) is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is issued. It transmits to the control microcomputer 370. In FIG. 42, the switch-on buffer 1 corresponds to the input port 0, and the switch-on buffer 2 corresponds to the input port 2.

  FIG. 43 is a flowchart showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded in the register and the prize ball designation data pointed to by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not on, the number of processes is reduced by 1 (step S5114), and if the number of processes is 0 The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer. (Step S111). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5112, S5113). Then, the process proceeds to step S5113.

  FIG. 44 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 45 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). . If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the processing of steps S5227 and S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and Y in step S5227. When the determination is made, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integer multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal 1 output timer.

  FIG. 46 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S5221). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S5227.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 31) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the processing of steps S52313 and S52315, which will be described later, and one second elapses without sending a prize ball number command, and Y in step S52313. If it is determined, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 47 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 4 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 4 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the processing from step S52303 is not performed. And control to suspend transmission of the prize ball number command.

  If the contents of the frame state display buffer are 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count value of the prize ball command output counters 2 and 3 is also 0, the CPU 56 checks whether the count value of the prize ball command output counter 4 is 0 or not. If the count value of the prize ball command output counter 4 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls to 3 in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs a process of outputting a prize ball number command in which the prize ball number is set to the transmission data register of the serial communication circuit 505.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in steps S52409 and S52411 described later, and 10 seconds have elapsed without receiving a prize ball number acceptance command or a prize ball preparation command. If it is timed out and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. (See steps S52403 to S52405) or by receiving the winning ball preparation command and repeating the winning ball receipt confirmation process (see steps S52406 to S52408), without returning to the winning ball transmission process 1 In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out in excess of the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. A case is also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the award ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the winning ball shortage error command transmission table is set in the pointer in step S52312, in the effect symbol command control processing in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. A prize ball shortage error command is output to the transmission data register 505, and the prize ball shortage error command is transmitted to the production control microcomputer 100. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around. Therefore, the game control microcomputer 560 may be equipped with a transmission-only serial communication circuit for communication with the effect control microcomputer 100.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command described later, the effect control microcomputer 100 performs an error notification of prize ball shortage or prize ball excess. However, the error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed from the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, on the contrary, 10 may be added to the value of the winning ball counter based on the input of winning ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. In the process of step S5312 described later, if the value of the prize ball number counter is 501 or more, a prize ball What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 48 is a flowchart showing the winning ball reception confirmation process (step S524) executed when the value of the winning ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first checks whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52402). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S52409.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 31) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. If time elapses and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 49 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S52502). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S52509.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the prize ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a winning ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorized number of prize balls, and a new prize is also generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 31) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the processing of steps S52509 and S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time is out and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 50 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the input of the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the winning ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the winning ball information input invalid timer (step S5310) and sets the value of the winning ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the prize ball information has been inputted on the condition that the prize ball information has been inputted 6 times or more out of the 8 confirmation processes, and 10 pieces of prize ball information are entered. The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the winning ball excess error command transmission table is set in the pointer in step S5315, in the effect symbol command control process in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. The award ball excessive error command is output to the transmission data register 505, and the award ball excessive error command is transmitted to the production control microcomputer 100.

  Next, the frame state output process (step S39) will be described. FIG. 51 is a flowchart showing an example of the frame state output process in step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the content of the input port 0 (step S392) and logically ANDs the input port 0 content with a predetermined door opening signal confirmation mask value (specifically 01000000). (Step S393). Further, the CPU 56 calculates the logical product of the operation result obtained by the logical product and the contents of the frame state display buffer loaded in step S391 (step S394). By executing the above processing, a calculation result is obtained in which the door opening signal input state is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the contents of the previous frame state display buffer (step S395). The previous frame state display buffer stores the calculation result of step S394 calculated when the frame state output processing is executed by the previous timer interrupt. When the calculation result is different from the content of the previous frame state display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame state display buffer and updates the previous frame state display buffer. Along with (Step S397), the calculation result calculated in Step S394 is set as it is to the frame state display command, and control is performed to transmit the frame state display command to the effect control microcomputer 100 (Step S398). Specifically, the CPU 56 performs processing for setting the address of the frame state display command transmission table in the pointer. Then, based on the fact that the address of the frame state display command transmission table is set in the pointer in step S398, in the effect symbol command control processing in step S30, the serial communication circuit 505 for the channel for transmission / reception with the effect control board 80 is performed. The frame state display command is output to the transmission data register, and the frame state display command is transmitted to the production control microcomputer 100.

By executing the above processing, error information set by the connection OK command or the winning ball preparation command from the payout control microcomputer 370 (paid-out number error error, out of ball error, full tank error, winning ball error) And the input state of the door opening signal are set in the frame state display command and transmitted to the production control microcomputer 100.

  FIG. 52 is a flowchart showing an example of processing executed in step S28 shown in FIG. 28 as the special symbol process. In this special symbol process, the CPU 56 first executes a start winning determination process (step S311). 53 and 54 are flowcharts showing an example of the start winning determination process.

  In the start winning determination process shown in FIGS. 53 and 54, the CPU 56 firstly selects the first start provided corresponding to the first start winning opening 13a among the first start opening switch 14a and the second start opening switch 15a. It is determined whether or not the detection signal from the mouth switch 14a is in an on state (step S201 in FIG. 53). At this time, if the detection signal from the first start port switch 14a is in the ON state (step S201; Yes), the first hold memory corresponding to the number of hold data stored in the first special figure hold storage unit 151A. It is determined whether or not the number is a predetermined upper limit value (eg, “4”) (step S202). At this time, the CPU 56 may identify the first reserved memory number by reading the value of the first reserved memory number counter (first reserved memory number count value) provided in the game control counter setting unit.

  If the first reserved memory number is not the upper limit value in step S202 (step S202; No), the first reserved memory number is incremented by 1, for example, by adding 1 to the first reserved memory number count value ( Step S203). From among the numerical data updated by the random number circuit 503 and the random counter, a random value MR1 for determining the special figure display result, a random value MR2 for determining the big hit type, and a random value MR3 for determining the variation pattern type are obtained. The numerical data shown is extracted (step S204). Numerical value data indicating each random number value extracted at this time is set as reserved data at the head of the empty entry in the first special figure reservation storage unit 151A, whereby each random number value is stored (step S205). Subsequently, for example, by setting the storage address (first address) of the first start opening winning designation command table in the ROM 54 in the transmission command buffer, the first starting opening winning designation command is transmitted to the effect control board 80. Is set (step S206). The first start opening winning designation command set in this way is sent from the main board 31 to the effect control board 80, for example, by executing the command control process of step S30 shown in FIG. 28 after the special symbol process process is completed. Is transmitted.

  In addition, when the detection signal from the first start port switch 14a is in the OFF state in step S201 (step S201; No), or when the first reserved storage number reaches the upper limit value in step S202 (step S202). ; Yes), it is determined whether or not the detection signal from the second start port switch 15a provided corresponding to the second start winning port 13b is on (step S221 in FIG. 54). At this time, if the detection signal from the second start port switch 15a is in an OFF state (step S221; No), the start winning determination process is terminated. On the other hand, when the detection signal from the second start port switch 15a is in the ON state (step S221; Yes), it corresponds to the number of the hold data stored in the second special figure hold storage unit 151B. It is determined whether or not the second reserved storage number is a predetermined upper limit value (for example, “4”) (step S222). At this time, the CPU 56 may specify the second reserved memory number by reading the value of the second reserved memory number counter (second reserved memory number count value) provided in the game control counter setting unit.

  If the second reserved storage number has reached the upper limit value in step S222 (step S222; Yes), the start winning determination process is terminated. On the other hand, when the second reserved memory number is not the upper limit value (step S222; No), the second reserved memory number is incremented by 1, for example, by adding 1 to the second reserved memory number count value. (Step S223). From among the numerical data updated by the random number circuit 503 and the random counter, a random value MR1 for determining the special figure display result, a random value MR2 for determining the big hit type, and a random value MR3 for determining the variation pattern type are obtained. The numerical data shown is extracted (step S224). Numerical value data indicating each random value extracted at this time is set as reserved data at the head of the empty entry in the second special figure reservation storage unit 151B, whereby each random number value is stored (step S225). Subsequently, for example, by setting the storage address of the second start opening winning designation command table in the ROM 54 in the transmission command buffer, setting for transmitting the second starting opening winning designation command to the effect control board 80 is performed. (Step S226). The second start opening winning designation command set in this way is sent from the main board 31 to the effect control board 80, for example, by executing the command control process of step S30 shown in FIG. 28 after the special symbol process process is completed. Is transmitted.

  After executing the process of step S206 and after executing the process of step S226, the total reserved memory count is incremented by 1, for example, by adding 1 to the total reserved memory count count value (step S227). Subsequently, for example, by setting the storage address of the reserved storage number notification command table in the ROM 54 in the transmission command buffer, setting for transmitting the reserved storage number notification command to the effect control board 80 is performed (step S228). . The reserved memory number notification command set in this way follows the second start winning prize designation command, for example, by executing the command control process in step S30 shown in FIG. 28 after the special symbol process process ends. The signal is transmitted from the substrate 31 to the effect control substrate 80. After the start winning determination process as described above is executed, one of the processes in steps S300 to S310 shown in FIG. 52 is selected and executed according to the value of the special figure process flag.

  The special symbol normal process of step S300 is executed when the value of the special symbol process flag is “0”. In this special symbol normal process, the first special symbol indicator 8a and the second special symbol are based on the presence / absence of reserved data stored in the first special symbol storage unit 151A and the second special diagram storage unit 151B. It is determined whether or not the special game is started by the display 8b. Also, in the special symbol normal processing, whether the variable display result of the special symbol, the decorative symbol, the color symbol, etc. is set to “big hit” or “small hit” based on the numerical data indicating the random value MR1 for determining the special symbol display result. A determination is made whether or not. Further, in the special symbol normal process, in response to the variable display result of the special symbol in the special symbol game, the final special symbol (big hit symbol, the special symbol game by the first special symbol indicator 8a and the second special symbol indicator 8b). Either a small hit symbol or a lost symbol) is set.

  The variation pattern setting process in step S301 is executed when the value of the special figure process flag is “1”. This variation pattern setting process includes a process of determining a variation pattern as one of a plurality of types according to the determination result of the variation pattern type.

  The special symbol variation process in step S302 is executed when the value of the special symbol process flag is “2”. This special symbol variation processing includes processing for setting the special symbol to be varied in the first special symbol display 8a and the second special symbol display 8b, and the elapsed time since the special symbol started to vary. It includes processing to measure Further, it is also determined whether or not the elapsed time thus measured has reached the special figure fluctuation time corresponding to the fluctuation pattern. When the special figure variation time is reached, the value of the special figure process flag is updated to “3”.

  The special symbol stop process in step S303 is executed when the value of the special symbol process flag is “3”. In the special symbol stop process, the first special symbol display unit 8a and the second special symbol display unit 8b are used to stop the variation of the special symbol and to stop and display the fixed special symbol that is the variable symbol display result. A process for setting is included. Then, a determination is made as to whether or not either the big hit flag or the small hit flag provided in the game control flag setting unit is on. Is updated to “4”, and when the small hit flag is on, the value of the special figure process flag is updated to “8”. When both the big hit flag and the small hit flag are off, the value of the special figure process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S304 is executed when the value of the special figure process flag is “4”. In the pre-opening process for the big prize opening, which of the first special variable winning ball apparatus 20A or the second special variable winning ball apparatus 20B is opened based on the fact that the variable display result is “big hit” or the like, and This includes a process for starting the execution of the round in the first jackpot gaming state or the second jackpot gaming state and setting for opening the first jackpot 23b or the second jackpot 24b.

  In this embodiment, when the big hit types are “non-probable change” and “probable change A”, in the pre-opening process of the big winning opening, the opening period (for example, 29.5) of the first big winning opening door 1406 for each round. Second) and the number of winning prizes (for example, 8) are set, and the first big winning opening 23b is controlled to be opened. Also, in the big hit state where the big hit type is “probability variation B”, the opening period (for example, 0.5 seconds) and the number of winning (for example, three) of the movable portion 1163 are set for each round in the pre-opening process for the big winning opening. Then, the second big winning opening 24b is controlled to be opened.

  Note that, in the big hit state where the big hit type is “non-probable change” and “probability change A”, in the pre-opening process of the big winning opening, the opening period of the first big winning opening door 1406 for each round in advance (for example, 29.5 seconds) May be set, and when the predetermined number of game balls (for example, 8) wins during opening, control may be performed to close the first big winning opening 23b. In the big hit state where the big hit type is “probability change B”, the opening period (for example, 0.5 seconds) of the movable portion 1163 for each round is set in advance in the pre-opening process for the big winning opening, When a predetermined number of game balls (for example, three) wins, control may be performed to close the second big winning opening 24b.

  The special winning opening opening process in step S305 is executed when the value of the special figure process flag is “5”. In the process for opening the grand prize opening, a process for measuring the elapsed time since the first big prize opening 23b or the second big prize opening 24b is opened, the measured elapsed time, and the count switch 23 are detected. A process of determining whether or not it is time to return the first grand prize winning port 23b or the second grand prize winning port 24b from the open state to the closed state based on the number of game balls and the like is included. And when returning the 1st big winning opening 23b or the 2nd big winning opening 24b to a closed state, the process etc. which stop supply of the drive signal with respect to a predetermined | prescribed solenoid should just be performed.

  The special winning opening opening post-processing in step S306 is executed when the value of the special figure process flag is “6”. In the post-opening process for the big prize opening, a process for determining whether or not the number of executions of the round in which the first big prize opening 23b or the second big prize opening 24b is in the open state has reached the maximum number of big prize opening opening times. And a process for performing a setting for transmitting a hit end designation command when the maximum number of times of winning a prize winning opening is reached. The special figure process flag value is updated to “7” when the maximum winning opening number is reached, and the special process flag value is updated to “7” when the maximum winning opening number is not reached. Update to 4 ".

  The big hit end process in step S307 is executed when the value of the special figure process flag is “7”. In this jackpot end process, a waiting time corresponding to a period in which an ending effect as an effect operation for notifying the end of the jackpot gaming state is executed by the effect electric parts such as the effect display device 9, the speaker 27, and the decoration lamp 25a. Including a process of waiting until the elapse of time, a process of performing various settings corresponding to the end of the big hit gaming state, and the like.

  The small hit release pre-processing in step S308 is executed when the value of the special figure process flag is “8”. In this small hit opening pre-processing, based on the fact that the variable display result is “small hit”, the execution of the variable winning operation is started in the small hit gaming state and the second big winning opening 24b is opened. The process to set up for is included. At this time, for example, in response to the fact that the variable display result is “small hit” and the maximum value of the number of times of opening the second big prize opening is “15”, The upper limit may be set to “0.5 seconds”.

  In this embodiment, in the small hit state, the opening period (for example, 0.5 seconds) of the movable portion 1163 for each round is set in advance in the pre-opening process for small hits, and a predetermined number of games are released during the release. When a ball (for example, three) wins, control is performed to close the second large winning opening 24b. In the pre-opening process for small hits, control is performed to set the opening period (for example, 0.5 seconds) and the number of winnings (for example, 3) of the movable portion 1163 for each round so that the second big winning opening 24b is opened. May be performed.

  The small hit releasing process in step S309 is executed when the value of the special figure process flag is “9”. In the small hit opening process, the second big prize opening 24b is closed from the open state based on the process of measuring the elapsed time since the second big prize opening 24b is opened and the measured elapsed time. A process for determining whether or not it is time to return to the state is included. When returning the second big prize opening 24b to the closed state, a process of stopping the supply of the drive signal to the predetermined solenoid may be executed.

  The small hit end processing in step S310 is executed when the value of the special figure process flag is “10”. In this small hit end process, a waiting time corresponding to a period during which the effect operation for notifying the end of the small hit gaming state is performed by the electric parts for the effect such as the effect display device 9, the speaker 27, and the decorative lamp 25a elapses. It includes processing to wait until it is done. Here, when the small hit gaming state is finished, the state of the pachinko gaming machine 1 before the small hit gaming state is continued without changing the state of the probability change flag and the short time flag.

  FIG.55 and FIG.56 is a flowchart which shows an example of the special symbol normal process performed in step S300 of FIG. In the special symbol normal process shown in FIG. 55, the CPU 56 first calculates the total value of the first reserved memory number and the second reserved memory number based on, for example, the total reserved memory number count value stored in the game control counter setting unit. It is determined whether or not the total number of pending storages is “0” (step S241). At this time, if the total reserved memory number is other than “0” (step S241; No), the total reserved memory number is updated to be subtracted by 1, for example, by subtracting 1 from the total reserved memory number count value (for example) Step S242).

  Following the processing of step S242, for example, based on the second reserved memory number count value stored in the game control counter setting unit, it is determined whether or not the second reserved memory number is “0” (step S243). ). At this time, if the second reserved storage number is “0” (step S243; Yes), as the reserved data stored in association with the reserved number “1” in the first special figure reservation storage unit 151A, Numerical data indicating the random number value MR1 for determining the display result, numerical data indicating the random value MR2 for determining the jackpot type, and numerical data indicating the random value MR3 for determining the variation pattern type are read out (step S244). . At this time, for example, the first reserved memory number count value is decremented by 1, and the first reserved memory number is updated to be decremented by 1, and the first special figure reserved memory unit 151A uses the reserved number “1”. The storage contents of the hold data stored in the lower entries (for example, entries corresponding to the hold numbers “2” to “4”) are shifted up by one entry (step S245). Then, in response to starting the special figure game using the first special figure by the first special symbol display 8a, the value of the variable special figure designation buffer provided in the game control buffer setting unit (fluctuation special figure designation) (Buffer value) is set to "1" (step S246).

  After the process of step S246 is executed, a first table shown in FIG. 19A is used as a use table for determining whether the variable display result is “lost”, “big hit”, or “small hit”. The figure display result determination table 130A is selected and set (step S247). For example, in the process of step S247, the storage address (first address) of the first special figure display result determination table 130A in the ROM 54 may be set in a determination table pointer or the like provided in a predetermined area of the RAM 102. The CPU 56 refers to the first special figure display result determination table 130A set in this manner, so that the numerical data indicating the random value MR1 for determining the special figure display result read in step S244 is the jackpot determination value data. (Step S248).

  If the numerical data indicating the random value MR1 does not match the jackpot determination value data in step S248 (step S248; No), the numerical value indicating the random number value MR1 for determining the special figure display result read in step S244. It is determined whether or not the data matches the small hit determination value data (step S249). At this time, if it matches with the small hit determination value data (step S249; Yes), the small hit flag is set to the on state (step S250).

  If the second reserved storage number is other than “0” in step S243 (step S243; No), as the hold data stored in association with the hold number “1” in the second special figure hold storage unit 151B, The numerical data indicating the random number value MR1 for determining the special figure display result, the numerical data indicating the random value MR2 for determining the jackpot type, and the random value MR3 for determining the variation pattern type are read out (step S251). At this time, for example, by subtracting 1 from the second reserved memory number count value, the second reserved memory number is updated so as to be decremented by 1, and the second special figure reserved memory unit 151B uses the reserved number “1”. The storage contents of the hold data stored in the lower entries (for example, entries corresponding to the hold numbers “2” to “4”) are shifted up by one entry (step S252). Then, in response to starting the special figure game using the second special figure by the second special symbol display 8b, the variable special figure designation buffer value is set to “2” (step S253).

  After executing the processing of step S253, the second special figure display result determination table shown in FIG. 19B is used as a use table for determining whether the variable display result is “lost” or “big hit”. 130B is selected and set (step S254). For example, in the process of step S254, the storage address of the second special figure display result determination table 130B in the ROM 54 may be set in the determination table pointer or the like. The CPU 56 refers to the second special figure display result determination table 130B set in this way, so that the numerical data indicating the random number MR1 for determining the special figure display result read in step S251 is the big hit determination value data. Is determined (step S255).

  When the numerical data indicating the random value MR1 matches the jackpot determination value data in step S248 or step S255 (step S248; Yes, or step S255; Yes), the jackpot flag provided in the game control flag setting unit Is set to the on state (step S256). At this time, the big hit type determination table 131 shown in FIG. 19D is selected and set as a use table for determining the big hit type as one of a plurality of types (step S257). Then, based on the numerical data indicating the random number MR2 for determining the big hit type read in step S244 or step S251, the big hit type is determined as “non-probable change by referring to the big hit type determination table 131 set in step S257. ”,“ Probability variation A ”, and“ Probability variation B ”are determined (step S258). When the variable special figure designation buffer value is set to “2” in the process of step S253, the random value MR2 for determining the big hit type for the big hit type of “probable change B” in the big hit type determining table 131 is set. Since it is not assigned, the jackpot type is not determined to be “probability variation B”. Corresponding to the jackpot type determined in step S258, the jackpot type buffer value is set to any one of “0” to “2” (step S259).

  After executing the process of step S259, the maximum value of the number of times of winning a prize opening is set (step S260). At this time, for example, as shown in FIG. 57, if the variable display result is determined to be “big hit”, the big hit type buffer value set in step S258 is either “0” or “1”. Then, the maximum value of the number of times of opening the first grand prize opening is set to “15” corresponding to the 15-time open game. The jackpot type buffer value is set to “0” when the jackpot type determined in step S258 is “non-probable change”, and when the jackpot type determined in step S258 is “probability change A”. , “1”. On the other hand, when the variable display result is determined to be “big hit”, if the big hit type buffer value set in step S258 is “2”, the maximum value for the number of times of opening the second big prize opening is set to 15 times. Set to “15” corresponding to the open game. Even when the variable display result is determined to be “small hit”, the maximum value of the number of times of opening the second big prize opening is set to “15” corresponding to the 15-time open game. The big hit type buffer value is set to “2” when the big hit type determined in step S258 is “probability variation B” or when the variable display result is determined as “small hit”.

  If the numerical data indicating the random value MR1 does not match the small hit determination value data in step S249 (step S249; No), or if the numerical data indicating the random value MR1 does not match the big hit determination value data in step S255 ( After executing either step S255; No) or the processing of step S250 and step S259, a fixed special symbol is set corresponding to the result of determining the variable display result or determining the jackpot type ( Step S261). As an example, if the numerical data indicating the random value MR1 does not match the small hit determination value data in step S249, or if the numerical data indicating the random value MR1 does not match the big hit determination value data in step S255, it is variable. Corresponding to the determination result that the display result is “lost”, the special symbol indicating the “−” symbol that becomes the lost symbol is set as the confirmed special symbol. If the numerical data indicating the random value MR1 matches the small hit determination value data in step S249, the small hit symbol is determined corresponding to the determination result that the variable display result is “small hit”. Set as a special symbol. Further, when the numerical data indicating the random value MR1 matches the jackpot determination value data in step S248 or step S255, one of the jackpot symbols is determined as a special special symbol according to the determination result of the jackpot type in step S258. Set to.

  After the confirmed special symbol is set in step S261, it is determined whether or not the big hit flag is on (step S262). At this time, if the big hit flag is on (step S262; Yes), the variation pattern type is set according to the table selection setting based on whether the gaming state in the pachinko gaming machine 1 is the normal state, the probability variation state, or the time reduction state. As a use table for determining one of a plurality of types, one of the big hit variation pattern type determination tables is selected and set (step S263). Here, the gaming state in the pachinko gaming machine 1 may be specified from the state of the probability change flag and the time reduction flag provided in the gaming control flag setting unit.

  When the big hit flag is off in step S262 (step S262; No), it is determined whether or not the small hit flag is on (step S264). At this time, if the small hit flag is on (step S264; Yes), based on whether the gaming state in the pachinko gaming machine 1 is the normal state, the probability variation state, or the short-time state, the variation pattern type is determined according to the table selection setting. As a use table for determining one of a plurality of types, any one of the small hit variation pattern type determination table is selected and set (step S265).

  When the small hit flag is off in step S264 (step S264; No), based on whether the gaming state in the pachinko gaming machine 1 is the normal state, the probability variation state, or the short time state, according to the table selection setting, As the use table for determining the variation pattern type as one of a plurality of types, one of the variation pattern types determination table for loss is selected and set (step S266). At this time, if the variable special figure designation buffer value is “1” (step S 267; Yes), the first hold memory number count value stored in the game control counter setting unit is read, for example. The number of memories is specified (step S268). On the other hand, if the variable special figure designation buffer value is “2” (step S267; No), for example, by reading the second reserved memory number count value stored in the game control counter setting unit, the first 2 The number of reserved storage is specified (step S269).

  After executing any of the processes of steps S263, S265, and S266, the set is performed in any of steps S263, S265, and S266 based on the random number MR3 for determining the variation pattern type read in step S244 or step S251. By referring to the used table, the variation pattern type is determined as one of a plurality of types (step S270).

  Here, in the process of step S270, the variation pattern type of the decorative symbol corresponding to the special symbol game executed using the first special symbol by the first special symbol indicator 8a based on the establishment of the first start condition is determined. Whether to determine the variation pattern type of the decorative symbol corresponding to the special symbol game executed using the second special symbol by the second special symbol display 8b based on the fact that the second start condition is satisfied Instead, the variation pattern type is determined to be one of a plurality of types by using numerical data indicating a common random value MR4 for determining the variation pattern type updated by a common random counter or the like. As an example, in the process of step S270, the variation pattern type may be determined with reference to the determination table stored in the address of the ROM 54 set in the determination table pointer.

  After the variation pattern type is determined in step S270, the special figure process flag value is updated to “1” which is a value corresponding to the variation pattern setting process (step S271), and the special symbol normal process is performed. finish. In addition, when the total number of reserved memories is “0” in step S241 shown in FIG. 55 (step S241; Yes), a predetermined demonstration display setting is performed (step S272), and then the special symbol normal process is terminated. To do.

  FIG. 58 is a flowchart showing an example of the special symbol stop process executed in step S303 of FIG. In the special symbol stop process shown in FIG. 58, the CPU 56 first determines whether or not the big hit flag is on (step S291). At this time, if the big hit flag is on (step S291; Yes), the big hit start production waiting time is set (step S292). For example, in the process of step S 292, if a timer initial value determined in advance corresponding to the big hit start production waiting time is set in the game control process timer provided in the game control timer setting unit provided in the ROM 54. Good.

  Subsequent to the process of step S292, a setting for transmitting a hit start designation command from the main board 31 to the effect control board 80 is performed (step S293). For example, in the process of step S293, the setting data indicating the storage address in the ROM 54 of the hit start designation command table prepared in advance for transmitting the hit start designation command is stored in the buffer area designated by the transmission command pointer in the transmission command buffer. Should be stored in. Thereafter, the big hit flag is cleared and turned off (step S294). Next, it is determined whether or not the probability variation flag is set (step S294 +). If so, the big hit pre-probability flag indicating that the probability variation flag has been set is set. Settings for ending the time saving state are made (step S295). For example, in step S295, a process for clearing the probability variation flag and the time-shortage flag to turn it off, a process for clearing a special-figure variation number counter for counting the number of times the special figure game is executed in the probability variation state and the time-shortage state, etc. It only has to be executed. Then, the value of the special symbol process flag is updated to “4” which is a value corresponding to the pre-opening process for the special winning opening (step S296), and then the special symbol stop process is ended.

  In this embodiment, it is determined in step S294 whether or not it is in the probability variation state, and if it is in the probability variation state, the big hit probability variation flag is set. In other words, it may be determined whether or not the time reduction flag is set, and when the base state is high, the big hit probability change flag may be set.

  If the big hit flag is off in step S291 (step S291; No), it is determined whether the small hit flag is on (step S297). At this time, if the small hit flag is ON (step S297; Yes), a small hit start start waiting time is set (step S298). For example, in the process of step S298, a timer initial value determined in advance corresponding to the small hitting start time production waiting time may be set in the game control process timer.

  Subsequent to the process of step S298, as in the process of step S293, a setting for transmitting a hit start designation command from the main board 31 to the effect control board 80 is performed (step S299). Thereafter, the small hit flag is cleared and turned off (step S300). Then, the value of the special figure process flag is updated to “8”, which is a value corresponding to the small hit release pre-processing (step S301).

  If the small hit flag is OFF in step S297 (step S297; No), the value of the special figure process flag is updated to “0” which is a value corresponding to the special symbol normal process (step S302s). . After executing one of the processes in steps S301 and S302, it is determined whether or not to end the probability change state or the time reduction state (step S303). For example, in the process of step S303, the value of the special figure fluctuation number counter (special figure fluctuation number count value) is updated by, for example, subtracting 1 or adding 1, and the updated special figure fluctuation number count value is a predetermined value. It is determined whether or not the special game state end determination value is met. At this time, if it matches the special game state end determination value, the probability variation state or the time reduction state may be terminated by clearing the probability variation flag or the time reduction flag, etc., and controlled to the normal state. On the other hand, if it does not coincide with the special game state end determination value, the state of the probability variation flag or the time reduction flag may be maintained and the process of step S303 may be ended. After executing the end determination of the probability variation state or the short time state, the special symbol stop process ends. Note that the end determination based on the special figure variation count value may be performed only in the short-time state, and the probability variation state may be continued until the next variable display result becomes “big hit”. . Alternatively, for example, by extracting numerical data indicating a random value for determining the probability change state end from a random counter provided in the game control counter setting unit, and referring to a probability change state end determination table stored in advance in the ROM 54 or the like, It may be determined whether or not to end the probability variation state.

  FIG. 59 is a flowchart showing an example of the big hit end process executed in step S307 in FIG. In the jackpot end process shown in FIG. 59, the CPU 56 first determines whether or not the jackpot end time effect waiting time has elapsed (step S341). In this case, in the process of step S341, for example, the game control process timer value is updated by subtracting 1 or the like, and depending on whether or not the updated game control process timer value matches a predetermined waiting time elapsed determination value. What is necessary is just to determine whether the production waiting time at the end of the big hit has elapsed. If the big hit end presentation waiting time has not elapsed in step S341 (step S341; No), the big hit end processing is ended as it is.

  On the other hand, when the big hit end presentation waiting time has elapsed in step S341 (step S341; Yes), the big hit type buffer value stored in the game control buffer setting unit provided in the ROM 54 is read ( Step S342). Subsequently, it is determined whether or not the jackpot type buffer value read in step S342 is “2” corresponding to the jackpot type of “probability variation B” (step S343). At this time, if the big hit type buffer value is “2” (step S343; Yes), it is determined whether or not the big hit pre-probability change flag is set, that is, whether or not the game state before the big hit is the probable change state ( If the big hit pre-probability change flag is set (step S346; Yes), the big hit pre-probability change flag is cleared (step S347), and the setting for starting control to the probable change state and the short-time state is performed (step S346). Step S348). In the process of step S348, the time reduction flag and the probability change flag are set to the on state, and the count initial value determined in advance corresponding to the upper limit value of the special figure game that can be executed in the probability change state is the special figure variation. A count initial value (for example, “100”) determined in advance corresponding to the upper limit value of the special figure game that is set in the number counter and can be executed in the short-time state may be set in the special figure fluctuation number counter. If the big hit probability change flag is not set in step S346 (step S346; No), a setting for starting control to the probability change state (latent probability change state) is performed (step S349). Further, in the process of step S349, only the probability variation flag is set to the on state, and a predetermined count initial value corresponding to the upper limit value of the special figure game that can be executed in the probability variation state is set in the special diagram variation number counter. Just do it.

  Also, if the big hit type buffer value read in step S342 is not “2” corresponding to the big hit type of “probability change B”, the big hit type buffer value is “0” corresponding to the big hit type of “non-probable change”. It is determined whether or not (step S344). At this time, if the big hit type buffer value is “0” (step S343; Yes), the setting for starting the control to the short time state is performed (step S345). In the process of step S345, the time reduction flag is set to the on state, and a count initial value (for example, “100”) determined in advance corresponding to the upper limit value of the special figure game that can be executed in the time reduction state is set. It may be set in the figure fluctuation frequency counter.

  After executing any of the processes of steps S345, S348, and S349, the special figure process flag value is updated to “0” that is a value corresponding to the special symbol normal process (step S346), and then the big hit end process Exit.

  FIG. 60 is a flowchart showing an example of the normal symbol process executed in step S29 of FIG. In this normal symbol process, the CPU 56 first checks whether or not the detection signal from the gate switch 32a provided in the passage gate 32 is in the on state, so that the game ball has passed through the passage gate 32. It is determined whether or not (step S401). When the game ball passes through the passing gate 32 and the detection signal from the gate switch 32a is turned on (step S401; Yes), the process at the time of passing the gate is executed (step S402). On the other hand, when the detection signal from the gate switch 32a is in the off state (step S401; No), the process of step S402 is skipped.

  In the process at the time of passing through the gate executed in step S402, first, the number of reserved maps stored as the number of reserved data stored in the reserved map buffer of the RAM 55 is a predetermined upper limit value (for example, “4”). It is determined whether or not. At this time, if the number of stored customary drawings is an upper limit value, the current game ball detection is invalidated and the process at the time of passing the gate is terminated as it is. On the other hand, when the number of stored customary drawings is less than the upper limit value, for example, the CPU 56 displays numerical data indicating the random number value 4 for determining the normal display result from numerical data updated by the random counter. To extract. Then, the numerical data indicating the extracted random number value random 4 is set at the head of the empty entry in the ordinary reserved storage buffer. At this time, for example, it may be updated so that 1 is added to the common figure reserved memory number count value which is the count value in the common figure reserved memory number counter provided in the game control counter setting unit. After the above-described processing at the time of passing the gate, or after it is determined in step S401 that the detection signal from the gate switch 32a is in the off state, the following processing is performed according to the value of the usual process flag. Each process of steps S410 to S414 is executed.

  The normal symbol normal process in step S410 is executed when the value of the normal symbol process flag is “0”. In this normal symbol normal process, it is determined whether or not the normal symbol display device 10 starts the normal symbol game based on the presence / absence of reserved data stored in the normal symbol storage buffer. At this time, for example, if there is pending data stored in the usual figure storage buffer, the value of the usual figure process flag is updated to “1”.

  The normal symbol determination process in step S411 is executed when the value of the normal symbol process flag is “1”. In this normal symbol determination processing, based on the numerical data indicating the random value random number 4 for determining the normal symbol display result, the normal symbol display result as the variable symbol display result of the normal symbol in the normal symbol game is set to “per normal symbol”. Or “unusual” is determined. Also, in the normal symbol determination process, the universal symbol change pattern corresponding to the universal symbol display result and the presence / absence of the advantageous state is also determined.

  The normal symbol variation process in step S412 is executed when the value of the normal symbol process flag is “2”. In this normal symbol variation process, the normal symbol display device 10 is set to vary the normal symbol. The normal symbol that changes based on these settings is displayed in the normal symbol display result, which is a variable symbol display result of the normal symbol, when the normal symbol stop process in step S413 is executed. In the normal symbol variation process, the elapsed time from the start of variation of the normal symbol is measured. At this time, a determination is made as to whether or not the measured elapsed time has reached the normal time fluctuation time determined in accordance with the normal time fluctuation pattern. Then, when the usual figure change time is reached, the value of the usual figure process flag is updated to “3”.

  The normal symbol stop process in step S413 is executed when the value of the normal symbol process flag is “3”. In this normal symbol stop process, the normal symbol display device 10 is set to stop and display the variable symbol display result of the normal symbol. Note that the setting for stopping and displaying the variable symbol display result of the normal symbol is the normal symbol process flag value when the measured elapsed time reaches the normal symbol variation time in the normal symbol variation process of step S412. It may be performed before updating to “3”. Further, in the normal symbol stop process, when the universal symbol display result is “per symbol”, a setting is made to drive the solenoid 16 provided corresponding to the second start winning opening 13b. The value of the process flag is updated to “5”. On the other hand, when the normal map display result is “out of normal map”, the value of the general map process flag is updated to “0”.

  The ordinary electric accessory actuating process of step S414 is executed when the value of the usual process flag is “4”. In this ordinary electric accessory actuating process, the movable wing piece provided in the second start winning port 13b is moved from the vertical position to the tilt position in response to the variable display result in the normal game being "per normal game". Thus, setting for changing the second start winning opening from the normal open state to the expanded open state is performed. For example, in the normal electric accessory operation process, a drive control signal for driving the solenoid 16 is generated in accordance with the setting of the normal electric operation pattern set in the normal symbol stop process in step S413. That's fine. Further, in the ordinary electric accessory actuating process, the elapsed time after the solenoid 16 is driven and the second start winning opening is set in the expanded open state is measured, and the elapsed time reaches the expanded open time corresponding to the normal operation pattern. A determination is made whether or not. When the elapsed time reaches the expansion opening period, the driving of the solenoid 16 is stopped, and the movable blade piece is returned from the tilting position to the vertical position, so that the second start winning opening is changed from the expansion opening state to the normal opening state. Set to change to. At this time, the value of the normal process flag may be updated to “0”.

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 61 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer for storing the contents of the ports 0 and 1 input this time. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. Note that the previous port buffer, port buffer, and switch-on buffer shown in FIG. 61 are prepared for each of the input ports 0 and 1. For example, in this embodiment, two switch-on buffers 1 and 2 are prepared, the switch state of the input port 0 is set to the switch-on buffer 1, and the switch state of the input port 1 is the switch-on buffer 2. Set to

  FIG. 62 is a flowchart showing an example of the switch process in step S21 in the game control process. In the switch process, the game control microcomputer 560 first inputs the data input to the input ports 0, 1, 2 (see FIG. 21) (step S101), and sets the input data in the port buffer (step S101). Step S102).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input ports 0, 1, and 2 are input again (step S106), and the logical product is performed bit by bit between the input data and the data set in the port buffer. (Step S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs a switch normal / abnormal check process (step S113).

  FIG. 63 is a flowchart showing a switch normal / abnormal check process. In the switch normal / abnormal check process shown in FIG. 63, the CPU 56 reads the contents of the switch-on buffer corresponding to the input port 1 (step S121). Then, it is confirmed whether or not the value of bit 0 corresponding to the first start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (step S122). That is, it is confirmed whether or not the first start port switch 14a (proximity switch) provided in the first winning path 1360 of the first start winning port 13a is turned on (detects a game ball).

  When the value of bit 0 corresponding to the first start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first start port switch 14a is in the ON state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S123).

  Further, the CPU 56 checks whether or not the value of bit 1 corresponding to the first winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (step S124). That is, it is confirmed whether or not the first winning confirmation switch 14b (photo sensor) provided in the first winning passage 1360 of the first start winning opening 13a is turned on (detects a game ball).

  When the value of bit 1 corresponding to the first winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first winning confirmation switch 14b is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S125).

  Further, the CPU 56 checks whether or not the value of bit 2 corresponding to the second start port switch 15a in the switch-on buffer corresponding to the input port 1 is 0 (step S126). That is, it is confirmed whether or not the second start port switch 15a (proximity switch) provided in the second winning path 1370a of the second start winning port 13b is turned on (detects a game ball).

  When the value of bit 2 corresponding to the second start port switch 15a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second start port switch 15a is in the ON state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S127).

  Further, the CPU 56 checks whether or not the value of bit 3 corresponding to the second winning confirmation switch 15b in the switch-on buffer corresponding to the input port 1 is 0 (step S128). That is, it is confirmed whether or not the second winning confirmation switch 15b (photo sensor) provided in the second winning passage 1370b of the second start winning opening 13b is turned on (detects a game ball).

  When the value of bit 3 corresponding to the second winning confirmation switch 15b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second winning confirmation switch 15b is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S129).

  Further, the CPU 56 checks whether or not the value of bit 4 corresponding to the first count switch 23 in the switch-on buffer corresponding to the input port 1 is 0 (step S130). That is, it is confirmed whether or not the first count switch 23 (proximity switch) provided in the first big winning path 1380 of the first big winning opening 23b is turned on (a game ball is detected).

  When the value of bit 4 corresponding to the first count switch 23 in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first count switch 23 is in the ON state), the bit is formed in the RAM 55. The value of the switch counter is incremented by 1 (step S131).

  Further, the CPU 56 checks whether or not the value of bit 5 corresponding to the third winning confirmation switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (step S132). That is, it is confirmed whether or not the third winning confirmation switch 23a (photo sensor) provided in the first large winning path 1380 of the first large winning opening 23b is turned on (detects a game ball).

  When the value of bit 5 corresponding to the third winning confirmation switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the third winning confirmation switch 23a is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S133).

  Further, the CPU 56 checks whether or not the value of the bit 6 corresponding to the second count switch 24 in the switch-on buffer corresponding to the input port 1 is 0 (step S134). That is, it is confirmed whether or not the second count switch 24 (proximity switch) provided in the second big winning path 1390 of the second big winning opening 24b is turned on (a game ball is detected).

  When the value of bit 6 corresponding to the second count switch 24 in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second count switch 24 is in the ON state), it is formed in the RAM 55. The value of the switch counter is incremented by 1 (step S135).

  Further, the CPU 56 confirms whether or not the value of the bit 7 corresponding to the fourth winning confirmation switch 24a in the switch-on buffer corresponding to the input port 1 is 0 (step S136). That is, it is confirmed whether or not the fourth winning confirmation switch 24a (photo sensor) provided in the second large winning path 1390 of the second large winning opening 23b is turned on (detects a game ball).

  When the value of the bit 7 corresponding to the fourth winning confirmation switch 24a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the fourth winning confirmation switch 24a is in the ON state), it is formed in the RAM 55. The value of the switch counter that has been set is decremented by 1 (step S137).

  Then, the CPU 56 checks whether or not the value of the switch counter is equal to or greater than a predetermined value (step S138). When the value of the switch counter is equal to or greater than the predetermined value, the CPU 56 selects any one of the first start winning opening 13a, the second starting winning opening 13b, the first large winning opening 23b, and the second large winning opening 24b. It is determined that an abnormal winning has occurred, and a predetermined time (in this example, 4 minutes) is set in the security signal information timer (step S139). In this embodiment, the CPU 56 sets a predetermined time (4 minutes in this example) to the security signal information timer based on the fact that the value of the switch counter has become 15 or more as a predetermined value. To do. In this embodiment, the information output process (see S31) is executed based on the predetermined time set in the security signal information timer in step S138, whereby the first start winning opening 13a and the second start winning prize are obtained. When an abnormal winning is detected at the mouth 13b, the first grand prize opening 23b, and the second big prize opening 24b, a security signal is externally output for a predetermined time (in this example, 4 minutes).

  In the process of step S138, the CPU 56, for example, based on the fact that the value of the switch counter becomes 15 or more, the first start winning port 13a, the second starting winning port 13b, the first big winning port 23b, In addition to determining that the abnormal winning at the second big winning opening 24b has occurred, conversely, the first start winning opening 13a and the second starting position are also determined based on the fact that the value of the switch counter becomes -15 or less. You may make it determine with the abnormal winning to the start winning opening 13b, the 1st big winning opening 23b, and the 2nd big winning opening 24b having generate | occur | produced. In this case, when the switch counter value is not recognized to be a negative value, for example, 15 is set as the default value of the switch counter value. Based on the counter value becoming 0 or 30 or more, abnormal winning occurs at the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b. You may make it determine with having carried out.

  In this embodiment, even if a value is already set in the security signal information timer and the security signal is being output to the outside, if a new abnormal winning is detected, the process of step S127 is executed again. The security signal information timer is overwritten with a predetermined time (in this example, 4 minutes). Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example) from the time when the new abnormal winning is detected. 4 minutes) The output of the security signal is continued.

  In this embodiment, only one switch counter is used to detect abnormal winning at the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second big winning opening 24b. The number of detections of the first start opening switch 14a and the number of detections of the first winning confirmation switch 14b or the number of detections of the second starting opening switch 15a and the number of detections of the second winning confirmation switch 15b or the first count is shown. Different switch counters may be used for the number of detections of the switch 23 and the number of detections of the third winning confirmation switch 23a or the number of detections of the second count switch 24 and the number of detections of the fourth winning confirmation switch 24a. In this case, for example, the value of the first switch counter is incremented by 1 each time the on state of the first start port switch 14a is detected, and every time the on state of the first winning confirmation switch 14b is detected. What is necessary is just to add 1 to the value of the counter for two switches. In step S138, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is equal to or greater than a predetermined value (for example, 15), the first start winning award 13a is entered. It may be determined that an abnormal winning has occurred and the process of step S139 is executed to output the security signal to the outside.

  In addition, when it is detected that an abnormal winning has occurred in the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, or the second major winning port 24b, the process of step S139 is executed. The security signal is output to the outside, and a predetermined error notification command is transmitted to the production control microcomputer 100 to display a predetermined error screen on the production display device 9 on the production control microcomputer 100 side. It is desirable that error notification can be performed.

  Further, for example, in addition to the abnormal winning at the first starting winning port 13a, the second starting winning port 13b, the first large winning port 23b, and the second large winning port 24b, the abnormal winning at the other winning ports 29a and 29b is made. When a security signal is output even when an abnormal magnetic error, abnormal radio wave error, or communication error is detected, an error notification command that differs for each error type is transmitted to the production control microcomputer 100. You may make it do. Then, on the effect control microcomputer 100 side, error notification may be performed by causing the effect display device 9 to display different error screens for each type of error.

  In the above configuration, when power supply is resumed after the power supply to the gaming machine is stopped, an error notification is being issued before the power supply is stopped. The error notification command may be transmitted again to the effect control microcomputer 100. In other words, since the storage content such as RAM is not backed up by the backup power source on the production control microcomputer 100 side, if a power failure occurs, it is not possible to execute the production such as error notification that has been executed until then. However, the error notification can be resumed when the power failure is recovered by configuring the predetermined error notification command to be transmitted again when the power failure is recovered. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM. If the security signal is being output before the power supply is stopped, it is backed up when the power failure is restored. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent an illegal act such as turning off the error notification or stopping the output of the security signal by intentionally turning off the power to the gaming machine.

  64 and 65 are explanatory diagrams for explaining the switch normal / abnormal check processing. Among these, FIG. 64 shows an example of the switch normal / abnormality check process in a normal state, and FIG. 65 shows an example of the switch normal / abnormality check process when an illegal act leading to an abnormal winning is performed. Show.

  As shown in FIGS. 64 and 65, for example, bit 0 of the switch-on buffer corresponding to the input port 1 indicates that a game ball is detected by the first start port switch 14a (proximity switch) corresponding to the bit 0. 0 ”. The bit 1 of the switch-on buffer corresponding to the input port 1 becomes “0” when a game ball is detected by the first winning confirmation switch 14 b (photo sensor) corresponding to the bit 1. If the switch is operating normally and has not received any fraudulent activity (an act of illegally turning on a detection signal from the switch or illegally turning on an on-state detection signal), the first Since the start opening switch 14a is disposed upstream of the first winning confirmation switch 14b, the first starting opening switch 14a (proximity switch) is first turned on, and then the first winning confirmation switch 14b (photo sensor). ) Should turn on. Accordingly, first, the value of the switch counter is incremented by 1 based on the fact that the first start opening switch 14a is turned on to become 1 (see step S123), and then, based on the fact that the first winning confirmation switch 14b is turned on. The counter value is decremented by 1 and returned to 0 (see step S125). Therefore, when the game ball passes through the switch, both the bit 0 and the bit 1 of the switch-on buffer corresponding to the input port 1 become “0”, and if it is in a normal operation state, the timing is shifted to the count-up timing ( As shown in FIG. 64, the value of the switch counter should be kept at 0.

  However, when a fraudulent act by radio waves is performed, as shown in FIG. 65, the off state is illegally interrupted by radio waves during the period when the first start switch 14a is turned on once, and There is a possibility that an illegal act of recognizing the starter switch 14a as if it has been turned on twice is performed. Therefore, although the first start port switch 14a is turned on only once, it is misrecognized that the first start port switch 14a is turned on twice, and the value of the switch counter is 2 in total. It is added to 2 (step S123 is executed twice). On the other hand, the first winning confirmation switch 14b arranged on the downstream side is different in detection method from the electromagnetic first start port switch 14a, and uses an optical photosensor. Unaffected by actions. Therefore, as shown in FIG. 65, when one game ball is detected by the first start opening switch 14a, when the game ball is detected by the first winning confirmation switch 14b after a short delay, the first winning game is normally completed. The ON state of the confirmation switch 14b is detected only once, and the value of the switch counter is decremented by 1 to 1 (see step S125). Therefore, when a fraudulent act by radio waves is performed, there is a difference in the number of detections between the first start opening switch 14a and the first winning confirmation switch 14b having different detection methods, and as shown in FIG. On the other hand, based on the fact that the value of the switch counter is not maintained at 0 and the value of the switch counter is equal to or greater than a predetermined value (15 in this example) (the first start port switch 14a and the first prize confirmation switch 14b). Based on the fact that the cumulative value of the detection error between the first and second winning prizes is equal to or greater than a predetermined value (15 in this example), it is possible to detect that an abnormal winning at the first start winning opening 13a has occurred.

  Here, an example is shown in which an abnormal winning to the first starting winning opening 13a is detected based on the detection result of the first starting opening switch 14a and the detection result of the first winning confirmation switch 14b. Based on the detection result of the switch 15a and the detection result of the second winning confirmation switch 15b, it is possible to detect an abnormal winning to the second start winning opening 13b. Further, based on the detection result of the first count switch 23, the detection result of the third winning confirmation switch 23a, the detection result of the second count switch 24, and the detection result of the fourth winning confirmation switch 24a, the second winning prize opening 24b is entered. An abnormal winning can be detected.

  In addition, it is also conceivable that a similar illegal act is performed by an act of illegally irradiating light. In this case, during the period when the first winning confirmation switch 14b is turned on once, an illegal act that causes the off state to be illegally interrupted by light and to recognize that the first winning confirmation switch 14b is turned on twice. May be done. However, in this case, on the contrary, since the electromagnetic first start port switch 14a side can normally detect the game ball without being affected by the illegal act of light, the value of the switch counter is kept at 0 similarly. The cumulative value of the detection error between the first start port switch 14a and the first winning confirmation switch 14b is a predetermined value based on the fact that the value of the switch counter is not less than a predetermined value (15 in this example). It is possible to detect that an abnormal winning to the first start winning opening 13a has occurred (based on (in this example, 15) or more).

  In this embodiment, the outputs of the first start opening switch 14a and the first winning confirmation switch 14b are negative logic, but the outputs of the first starting opening switch 14a and the first winning confirmation switch 14b are shown. May be configured to be positive logic. In this case, for example, the output levels of the first start port switch 14a and the first winning confirmation switch 14b are logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  Further, in this embodiment, the value of the switch counter is not kept at 0 (a detection error has occurred between the first start port switch 14a and the first winning confirmation switch 14b) and immediately. It is not determined that an abnormal winning has occurred, but it is determined that an abnormal winning has occurred based on the value of the switch counter being equal to or greater than a predetermined value (15 in this example). Such a configuration prevents, for example, a case where a game ball has become clogged in the first start winning opening 13a from being determined as an abnormal winning due to an illegal act.

  FIG. 66 (a) is an explanatory diagram showing a case where a game ball has become jammed in the first winning path 1360 through which the game ball won in the first start winning opening 13a passes. As shown in FIG. 66 (a), in the first winning path 1360, the first start port switch 14a and the first winning confirmation switch 14b are arranged at a certain distance in the vertical direction. Therefore, the game ball won in the first start winning opening 13a is first detected by the first start opening switch 14a, and then detected by the first winning check switch 14b on the downstream side after a while. Therefore, when a game ball is jammed in the first winning path 1360, there is a difference in the number of detections due to a physical distance difference between the first start port switch 14a and the first winning confirmation switch 14b. It occurs. In the first winning path 1360, a maximum of five detection errors occur between the first start port switch 14a and the first winning confirmation switch 14b.

  FIG. 66 (b) is an explanatory diagram showing a case where the game ball has become jammed in the second winning passages 1370 a, 1370 b through which the game ball won in the second start winning opening 13 b passes. As shown in FIG. 66 (b), in the second winning passages 1370a and 1370b, the second start port switch 15a and the second winning confirmation switch 15b are arranged at a certain distance in the vertical direction. Therefore, the game ball won in the second start winning opening 13b is first detected by the second start opening switch 15a, and then detected by the second winning check switch 15b on the downstream side after a while. Therefore, when the game ball is clogged in the second winning passages 1370a and 1370b, the number of detections depends on the physical distance difference between the second start opening switch 15a and the second winning confirmation switch 15b. A difference occurs. In the second winning passages 1370a and 1370b, a maximum of four detection errors occur between the second start port switch 15a and the second winning confirmation switch 15b.

  FIG. 66 (c) is an explanatory diagram showing a case where a game ball has become jammed in the first big winning path 1380 through which the game ball won in the first big winning opening 23b passes. As shown in FIG. 66 (c), in the first big prize passage 1380, the first count switch 23 and the third prize confirmation switch 23a are arranged at a certain distance from side to side and front and rear. For this reason, the game ball won in the first big winning opening 23b is first detected by the first count switch 23, and then detected by the third winning check switch 23a on the downstream side after a while. Therefore, when a game ball is jammed in the first big winning path 1380, there is a difference in the number of detections due to the physical distance difference between the first count switch 23 and the third winning confirmation switch 23a. It occurs. In the first big prize passage 1380, a maximum of four detection errors occur between the first count switch 23 and the third prize confirmation switch 23a.

  FIG. 66 (d) is an explanatory diagram showing a case where a game ball has become clogged in the second big winning path 1390 through which the game ball won in the second big winning opening 24 b passes. As shown in FIG. 66 (d), in the first big winning path 1380, the second count switch 24 and the fourth winning confirmation switch 24a are arranged at a fixed distance from side to side and front and rear. For this reason, the game ball won in the second big winning opening 24b is first detected by the second count switch 24, and then detected by the downstream fourth winning check switch 24a after a short time. Therefore, when the game ball is jammed in the second big prize passage 1390, the difference in the number of detections is caused by the physical distance difference between the second count switch 24 and the fourth prize confirmation switch 24a. It occurs. In the second big prize passage 1390, a maximum of five detection errors occur between the second count switch 24 and the fourth prize confirmation switch 24a.

  In the present embodiment, the value of the switch counter is the upstream of a plurality of winning paths (first winning path 1360, second winning paths 1370a and 1370b, first large winning path 1380, second large winning path 1390). First winning path 1360 and second winning path that have the largest physical distance difference between the proximity switch (14a, 15a, 23, 24) on the side and the photosensors (14b, 15b, 23a, 24b) on the downstream side. Sufficient margin is provided for the five detection errors of the first start port switch 14a, the first winning confirmation switch 14b, the second count switch 24, and the fourth winning confirmation switch 24a in the clogged state in the big winning passage 1390. By determining that an abnormal winning has occurred based on the given predetermined value (15 in this example) or more, the first winning path 1360, the second winning path A case where a game ball is jammed in any of the award passages 1370a and 1370b, the first grand prize passage 1380, and the second grand prize passage 1390 is prevented from being determined as an abnormal prize due to fraud. .

  In this embodiment, a sufficient margin is provided for the five detection errors of the first start opening switch 14a, the first winning confirmation switch 14b, the second count switch 24, and the fourth winning confirmation switch 24a in the ball jammed state. Although the case where it is determined that an abnormal winning has occurred based on the given predetermined value (15 in this example) or more is shown, the predetermined value used for determining the abnormal winning is shown in this embodiment. It cannot be limited to things. For example, if at least the number of detection errors of the first start opening switch 14a, the first winning confirmation switch 14b, the second count switch 24, and the fourth winning confirmation switch 24a in the ball jammed state is more than five, an error is erroneously detected. Since it can be prevented that the winning is determined, it may be determined that an abnormal winning has occurred based on the value of the switch counter being 6 or more.

  In addition, when the detection errors in the ball clogged state in the plurality of winning paths are the same number (for example, 5), the detection error has become a predetermined value (for example, 10) or more with a sufficient margin for the 5 detection errors. Based on the above, it may be determined that an abnormal winning has occurred.

  In addition, when it is configured to be able to detect abnormal winnings in a plurality of winning paths, the total number of detection errors in the blocked ball state in all these winning paths (5 + 4 + 4 + 5 = 18) If an abnormal winning determination is performed using a larger number (for example, 25) as a predetermined value, it is possible to prevent erroneous determination of an abnormal winning.

  In the present embodiment, the detection error in the ball clogged state in the plurality of winning paths can be detected by one switch counter, so that no switching counter corresponding to each winning path is provided. However, it was possible to detect abnormal winnings in each winning path, but provided a switch counter corresponding to each winning path, set a predetermined value corresponding to the detection error for each winning path, The detection error in the switch counter may be monitored to determine whether or not there is an abnormal prize. By doing in this way, it becomes possible to specify in which winning path the winning abnormality has occurred.

  FIG. 67 is a block diagram showing various signals output to the terminal board 160. As shown in FIG. 67, in this embodiment, from the game control microcomputer 560 mounted on the main board 31 to the terminal board 160, the start port signal, the symbol determination number of times 1 signal, the jackpot 1 signal, the jackpot Two signals, three jackpot signals, a time reduction signal, and a security signal are output by information output processing (see step S31) on the game control microcomputer 560 side. In this embodiment, a prize ball signal 1 and a gaming machine error status signal are sent from the payout control microcomputer 370 mounted on the payout control board 37 to the terminal board 160 via the main board 31. Is output by the information output process (see step S759) on the payout control microcomputer 370 side.

  The starting port signal is a signal for notifying the number of winnings to the first starting winning port 13a and the second starting winning port 13b. The symbol determination number 1 signal is a signal for notifying the number of changes in the special symbol. The jackpot 1 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) is in progress. The jackpot 2 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) or that the special symbol variation time reduction function is being operated (during the short-time state). The jackpot 3 signal is a signal for notifying that a 15-round jackpot game is in progress. The time reduction signal is a signal for notifying that the special symbol variation time reduction function is operating (in the time reduction state).

  The security signal is a signal indicating the security state of the gaming machine. Specifically, based on the detection result of the first start opening switch 14a and the detection result of the first winning confirmation switch 14b, it is determined that an abnormal winning to the first start winning opening 13a has occurred, or the first 2. When it is determined that an abnormal winning to the second starting winning opening 13b has occurred based on the detection result of the starting switch 15a and the detection result of the second winning confirmation switch 15b, or the detection of the first count switch 23 Based on the result and the detection result of the third winning confirmation switch 23a, when it is determined that an abnormal winning to the first big winning opening 23b has occurred, or the detection result of the second count switch 24 and the fourth winning confirmation switch On the basis of the detection result of 24a, when it is determined that an abnormal winning to the second big winning opening 24b has occurred, a security signal is displayed for a predetermined period (for example, 4 minutes). It is output to an external device such as a Le computer. Also, when the gaming machine is turned on and the initialization process is executed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  It should be noted that the signal output externally as the security signal is not limited to that shown in this embodiment. For example, not only abnormal winnings to the first starting winning port 13a, the second starting winning port 13b, the first grand winning port 23b, and the second large winning port 24b, but abnormal winnings to the normal winning ports 29 and 30 are detected. Thus, it may be configured so that it can be externally output as a security signal. In addition, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, it is configured so that it can be output externally as a security signal. Also good. In addition, for example, when an abnormality of various switches provided in a gaming machine is detected (for example, when an occurrence of a short circuit is detected by determining that an input value exceeds a threshold value), it can be externally output as a security signal. You may comprise as follows. In this way, even if there is an abnormal winning entry, abnormal magnetic error, or abnormal radio wave error at the special winning opening, if it is configured so that it can be output externally as a security signal from the common connector CN7 of the terminal board 160, even one signal line is connected. In this case, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In addition, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the security signal can be externally output from the common connector CN7 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN7 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN7 of the terminal board 160.

  In addition to the signal line and connector CN7 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  The prize ball signal 1 is a signal that is output every time one prize ball payout is detected. Further, the gaming machine error state signal is a signal indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). Instead of outputting the prize ball signal 1 to the outside every time one prize ball is detected, a certain prize ball signal is outputted every time a predetermined number (for example, 10) of prize balls is detected. Also good.

  68 to 71 are flowcharts showing the information output process of step S31. Of the processes shown in FIGS. 68 to 71, steps S1002 to S1030 are processes for outputting the start port signal, and steps S1031 to S1036 are processes for outputting the symbol determination number 1 signal. S1050 to S1068 are processes for outputting one jackpot signal, two jackpot signals, three jackpot signals and a short time signal. Steps S1069 to S1074 are processes for outputting a security signal.

  In the information output process, the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1001). Then, the address of the start port information setting table is set in the pointer (step S1002), and the number of processes pointed to by the pointer is loaded (step S1003). The number of processes (= 1) and the start port switch input bit (start port switch input bit determination value (01 (H)) are set in the start port information setting table. In step S1003, the pointer is set to the start port information setting. Since the address of the number of processes in the table is indicated, the data of the number of processes (= 1) in the start port information setting table is loaded.If the gaming machine has two start winning ports, In the start port information setting table, 2 may be set as the number of processes, and start port switch input bits for the two start winning ports may be set respectively.

  Next, the CPU 56 loads the contents of the switch-on buffer into the register (step S1004), and sets the switch-on buffer as switch input data (step S1005). The pointer is incremented by 1 (step S1006), the start port switch input bit pointed to by the pointer is loaded into the register (step S1007), and the logical product of the start port switch input bit and the switch input data is obtained (step S1008). When the content of the switch-on buffer is 01 (H), that is, when the first start port switch 14a or the second start port switch 15a is on, the logical product operation result is 01 (H). When the first start port switch 14a or the second start port switch 15a is not turned on, the operation result of the logical product is 00 (H).

  If the logical operation result is 0 (Y in step S1009), the process proceeds to step S1015. If the result of the logical product is not 0 (N in step S1009), it is determined that a winning has occurred in the first starting winning port 13a or the second starting winning port 13b, and the starting port information storage counter is loaded into the register. (Step S1010). The start port information storage counter is a counter that counts the number of remaining outputs of the start port signal (that is, the remaining number of start winnings that have not been output from the start port signal). Next, the CPU 56 adds 1 to the start port information storage counter (step S1011). Then, it is confirmed whether the calculation result (added result) is not 0 (step S1012). When the calculation result is 0 (N in step S1012), 1 is subtracted from the calculation result (step S1013). Then, the calculation result is stored in the start port information storage counter (step S1014).

  Next, the CPU 56 subtracts 1 from the number of processes (step S1015), and determines whether the number of processes is not 0 (step S1016). When the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine has only one first start winning opening 13a, 1 is set as the initial value of the processing number, and it is always determined that the processing number is 0 in step S1016. Will be.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 loads the start port information storage timer (step S1017), and reflects the state of the start port information storage timer in the flag register. (Step S1018), it is determined whether or not the start port signal is being output (step S1019). The start port information storage timer is a timer for measuring an on time and an off time (for example, an on time of 200 ms and an off time of 200 ms) of the start port signal. If the value of the start port information storage timer is not 0, it is determined that the start port signal is being output. If the value of the start port information storage timer is 0, it is determined that the start port signal is not being output.

  If the start port signal is being output (Y in step S1019), the process proceeds to step S1026. If the start port signal is not being output (N in step S1019), the CPU 56 loads the start port information storage counter (step S1020), and reflects the state of the start port information storage counter in the flag register (step S1021). Then, it is determined whether there is a remaining number of output times of the start port signal (step S1022). When the first start port switch 14a or the second start port switch 15a is turned on (N in step S1009), the start port information storage counter is incremented by 1, so there is a remaining number of output times of the start port signal. It will be determined.

  If there is no remaining number of output times of the start port signal (Y in step S1022), the process proceeds to step S1031. If there is a remaining number of output times of the start port signal (N in step S1023), the CPU 56 subtracts 1 from the start port information storage counter (step S1023), and the calculation result (result obtained by subtracting 1) is the start port information storage counter. (Step S1024). Then, the winning information operating time (100) is set in the register (step S1025). The winning information operating time (100) is a time for which a 4 ms timer interruption is executed 100 times, that is, a time of 0.400 seconds (400 ms).

  Next, if the winning information operating time is not set in step S1025, the CPU 56 subtracts 1 from the start port information storage timer, and if the winning information operating time is set in step S1025, the CPU 56 subtracts 1 from the winning information operating time. (Step S1026). Then, the calculation result (result obtained by subtracting 1) is stored in the start port information storage timer (step S1027).

  The CPU 56 compares the calculation result with the winning information on time (50) (step S1029), and determines whether the calculation result is shorter than the winning information on time (step S1030). The winning information on time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms).

  If the calculation result is not shorter than the winning information on time, that is, if the calculation result (remaining time of the start port 1 information storage timer) is longer than the winning information on time (200 ms) (N in step S1029) The CPU 56 sets the start port output bit position of the information buffer (bit 0 of the output port 1 in the example shown in FIG. 20) (step S1030). When the start port output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Will be output.

  By the processing of steps S1001 to S1030 described above, winning to the first start winning opening 13a (turning on the first start opening switch 14a) or winning to the second starting winning opening 13b (turning on the second start opening switch 15a) ) Occurs, a start port signal is output. That is, after the start port signal is turned on for 200 ms, it is turned off for 200 ms. By inputting this start port signal to the hall computer, it is possible to recognize the number of winnings to the first start winning port 13a or the second starting winning port 13b.

  Since the start port signal is turned on for 200 ms and then turned off for 200 ms, the next start port is turned off after the 200 ms off state even when a start winning is continuously generated in a short time. A signal is output. That is, the start port signals are output at intervals of at least 200 ms.

  Thus, since the start port signals are output at intervals of at least 200 ms, the hall computer can reliably grasp the total number of start winnings.

  Next, the CPU 56 loads the symbol determination number 1 information timer into the register (step S1031), reflects the state of the symbol determination number 1 information timer in the flag register (step S1032), and the symbol determination number 1 information timer times out. It is determined whether or not (step S1033). In this embodiment, in the special symbol variation process (see step S302), when the variation time times out, when the variation of the special symbol is stopped, the symbol determination number 1 information timer outputs the symbol determination number output time (in this example, 0). .500 seconds) is set, and when the symbol determination count output time has not elapsed, it is determined that the symbol determination count 1 information timer has not timed out, and when the symbol determination count output time has elapsed (symbol determination count) When the value of the 1 information timer is 0), it is determined that the symbol determination number 1 information timer has timed out.

  If the symbol determination count 1 information timer has not timed out (N in step S1033), the symbol determination count 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination count 1 information timer (step S1035). . Then, the design buffer count 1 output bit position of the information buffer (bit 1 of output port 1 in the example shown in FIG. 20) is set (step S1036). When the symbol determination number 1 output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Is output from the output port 1 (becomes ON state). If the symbol determination number 1 information timer times out (Y in step S1033), the process of step S1036 is not executed, and as a result, the symbol determination number 1 signal is turned off.

  By the processing of steps S1031 to S1036 described above, every time the change of the special symbol is stopped (stopped symbol is fixed), the symbol determination number 1 signal is turned on in the symbol determination number output time (for example, 500 ms).

  Next, the CPU 56 loads the special symbol process flag (step S1050), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1051), and then displays the special symbol process flag. It is determined whether the value of is less than 4 (step S1052). When the value of the special symbol process flag is less than 4 (Y in step S1052), the process proceeds to step S1058. When the value of the special symbol process flag is 4 or more (N in step S1052), the output bit position of the big hit of the information buffer is set (step S1053). Further, the big output 2 output bit position of the information buffer is set (step S1054). When one output bit position of jackpot and two output bit positions of jackpot of the information buffer are set, the information buffer is set to an output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. One signal and two jackpot signals are output from the output port 1 (become turned on).

  Further, the CPU 56 executes a time reduction check process for confirming whether or not it is in the time reduction state (step S1058), and determines whether or not it is in the time reduction state (step S1059). Specifically, the CPU 56 determines whether or not it is in the time reduction state by checking whether or not the time reduction flag that is set when shifting to the time reduction state is set. If the time-short state is set (Y in step S1059), the time-short output bit position of the information buffer is set (step S1060). When the time-short output bit position is set, the time buffer signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102 and outputting the output value to the output port 1 in step S1103. (Turns on) Also, the big output 2 output bit position of the information buffer is set (step S1061). When the jackpot 2 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, whereby the jackpot 2 signal is output from the output port 1. (Turns on).

  In addition, the CPU 56 loads the special symbol process flag (step S1062), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1063), and sets the special symbol process flag. It is determined whether or not the value is less than 4 (step S1064). When the value of the special symbol process flag is less than 4 (Y in step S1064), the process proceeds to step S1069. When the value of the special symbol process flag is 4 or more (N in step S1064), the contents of the big hit symbol determination buffer are loaded (step S1065), and it is confirmed whether or not it is a big hit of 15 rounds (step S1067). . Whether or not it is a big hit of 15 rounds can be determined, for example, by confirming the contents of the big hit symbol determination buffer set in the special symbol normal process. For example, the jackpot symbol determination buffer stores the contents of the jackpot type determined by the special symbol normal processing and the contents indicating the jackpot determination result. For example, “1” is a normal jackpot, “2” is a probable bonus jackpot, “3” is suddenly a big hit. If the contents of the big hit symbol determination buffer are “1” or “2”, it is determined that the number of rounds at the big hit is 15 rounds. In this case, the big output 3 output bit position of the information buffer is set (step S1068). When the jackpot 3 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, so that the jackpot 3 signal is output from the output port 1. (Turns on).

  By the processing of steps S1050 to S1068 described above, one big hit signal, two big hit signals, three big hit signals, and a short time signal are output (turned on) according to the type of big hit and the gaming state.

  Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070). S1071). In this embodiment, the detection difference between each start port switch 14a, 14b and each count switch 23, 24 and the first to fourth winning confirmation switches 14b, 15b, 23a, 24a is equal to or greater than a predetermined value (15 in this example). When it is determined that an abnormal winning to the start winning prize opening or the big winning opening has occurred, a predetermined time (4 minutes in this example) is set in the security signal information timer (switch normal / When the predetermined time has not elapsed (see steps S126 and S127 in the abnormality check process), it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (the value of the security signal information timer is 0), it is determined that the security signal information timer has timed out.

  In this embodiment, when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer (in the main process). When the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the calculation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position of the information buffer (bit 7 of output port 1 in the example shown in FIG. 20) is set (step S1074). When the security signal output bit position of the information buffer is set, the security signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102, and outputting the output value to the output port 1 in the step S1103. Is output (turns on). If the security signal information timer times out (Y in step S1071), the security signal is turned off as a result of not executing the process in step S1074.

  4 minutes after abnormal winning to the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second big winning opening 24b is detected by the processing of steps S1069 to S1074 described above. The security signal is output using the common connector CN7 of the terminal board 160 until 30 seconds elapses or until 30 seconds elapse after the initialization process is executed at the start of power supply to the gaming machine. If a new abnormal prize is detected during the output of the security signal, the output of the security signal is continued until 4 minutes have elapsed since the last abnormal prize was detected.

  Next, the security signal output timing will be described. FIG. 72 is an explanatory diagram showing the output timing of the security signal. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 to S14), a predetermined time (in this example, 30 seconds) is set in the security signal information timer. Based on the above (see step S14a), the information output process (see step S31) performs the processes of steps S1069 to S1103. As shown in FIG. 72A, from the connector CN7 of the terminal board 160, the hall computer or the like A security signal is output to the external device. In addition, after the power supply to the gaming machine is started, the number of detections of the start port switches 14a and 14b and the count switches 23 and 24 and the number of detections of the first to fourth winning confirmation switches 14b, 15b, 23a and 24a Based on the fact that the detection error of the first start winning port 13a, the second starting winning port 13b, the first large winning port 23b, and the second large winning port 24b is increased. Even when it is determined that an abnormal winning has occurred (see steps S121 to S126), based on the fact that a predetermined time (4 minutes in this example) is set in the security signal information timer (see step S127), information In the output process (see step S31), the processes of steps S1069 to S1103 are executed, and as shown in FIG. 72 (A), from the connector CN7 of the terminal board 160, Security signal is outputted to an external device such Lumpur computer. Thus, in this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, A security signal is externally output from the common connector CN7 of the terminal board 160 when an abnormal winning is detected at the two major winning openings 24b.

  Further, in this embodiment, when the security signal is being output externally, the first start winning port 13a, the second starting winning port 13b, the first big winning port 23b, and the second big winning port 24b are newly added. When an abnormal winning is detected, the output period of the security signal is substantially extended, and finally the first starting winning port 13a, the second starting winning port 13b, the first big winning port 23b, and the second big winning port 24b. The output of the security signal is continued until a predetermined time (in this example, 4 minutes) elapses from when the abnormal winning is detected. For example, in the case where the output of the security signal is started based on the fact that the initialization process is executed when the power supply to the gaming machine is started, as shown in FIG. Security signal output should continue. However, as shown in FIG. 72 (B), even before 30 seconds have elapsed, the detected numbers of the start port switches 14a and 14b and the count switches 23 and 24 and the first to fourth winning check switches 14b. , 15b, 23a, 24a and the detected number of detection errors become equal to or greater than a predetermined value (15 in this example), the first start winning opening 13a, the second starting winning opening 13b, the first large winning opening 23b, the second large There is a possibility that it is determined that an abnormal winning to the winning opening 24b has occurred. In this case, a predetermined time (in this example, 4 minutes) is overwritten and written in the security signal information timer based on the detection of the occurrence of the abnormal winning (see step S127), and the information output process (step S31). Step S1069 to S1103 are executed, and the output of the security signal is continued as shown in FIG. 72B. However, since the value of the security signal information timer was overwritten in 4 minutes, in this case, as shown in FIG. 72 (B), the first start winning opening 13a, the second starting winning opening 13b, the first large The output of the security signal is continued until 4 minutes have elapsed from the time when the abnormal winning to the winning opening 23b and the second large winning opening 24b is detected, and the output of the security signal is substantially extended. Become.

  In addition, for example, when the output of the security signal is started based on the detection of abnormal winning in the first starting winning opening 13a, the second starting winning opening 13b, the first major winning opening 23b, and the second major winning opening 24b. As shown in FIG. 72A, in principle, the output of the security signal should be continued until 4 minutes have elapsed. However, as shown in FIG. 72 (C), even before the lapse of 4 minutes, the detected numbers of the start port switches 14a and 14b and the count switches 23 and 24 and the first to fourth winning confirmation switches 14b. , 15b, 23a, and 24a, the detection error with a predetermined value (15 in this example) is greater than or equal to a predetermined value (15 in this example). There is a possibility that it is determined that an abnormal winning to the second big winning opening 24b has occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the newly detected occurrence of an abnormal winning (see step S127), and information output processing ( In step S31), the processing of steps S1069 to S1103 is executed, and the output of the security signal is continued as shown in FIG. 72C. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 72 (C), the first start winning port 13a, the second starting winning port 13b, the second The output of the security signal is continued until 4 minutes have elapsed from the time when the abnormal winning at the first grand prize opening 23b and the second big prize opening 24b is detected, and the output of the security signal is substantially extended. It will be.

  It is output when an abnormal winning is detected in the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second big winning opening 24b while the security signal is already being output. It can be considered that the output of the next security signal is started again after the output of the security signal in the middle is finished, but in this embodiment, in FIGS. 72 (B) and 72 (C). As shown, by extending the output time of the security signal being output as it is, the processing load for the security signal output processing is reduced and the program capacity for the security signal output processing is reduced. In other words, when it is configured to start the output of the next security signal after the output of the security signal being output is completed, the output of the next security signal is started after the output of the security signal is completed. For example, a process for measuring the interval time until completion is required, which increases the processing load and the program capacity. In contrast, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S14a and S127), the security signal is output. It is possible to prevent the increase in processing load and program capacity.

  In this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, a security signal is output for 30 seconds, and the first start winning opening 13a and the second starting winning opening 13b are output. In the case of detecting an abnormal winning at the first grand prize opening 23b and the second big prize opening 24b, a case where a security signal is output for 4 minutes has been shown. It is not limited to what is shown in the form. That is, it is a case where the initialization process is executed, or a case where an abnormal winning to the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, the second major winning port 24b is detected. When the initialization process is executed, an abnormal winning is detected in the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, and the second big winning opening 24b. What is necessary is just to output a security signal over different output times.

  In this embodiment, the output period of the security signal when an abnormal winning to the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b is detected. The four-minute period is as long as possible in the case of an abnormal winning to the first starting winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b. This is a substantially maximum time that can be set in order to output a security signal. That is, in this embodiment, since the game control microcomputer 560 can set a 2-byte value as the value of the security signal information timer, the maximum value is set to “FFFF (H) = 65535 in the security signal information timer. "Can be set. Therefore, in this embodiment, “60000”, which is almost the maximum value, is set in the security signal information timer, and the timer interruption period is 4 ms. Therefore, security is performed for 4 ms × 60000 = 4 minutes. A signal is output.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 73 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 73, the output port 0 outputs a signal of each phase supplied to the payout motor 289 by the stepping motor. In addition, a PRDY signal or an EXS signal is output from the output port 0 to the card unit 50, and a game indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). A machine error state signal and a prize ball signal 1 indicating that a prize ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by 7 segment LED is output. The output port 1 also outputs prize ball information indicating that ten prize ball payouts have been detected.

  FIG. 74 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 74, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 75 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 380. In this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. In the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for Further, as described above, a part of the initial setting of the serial communication circuit 380 is executed in the built-in device register setting process in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 76 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process of detecting the state of bits 0 to 7 (see FIG. 74) of the input port 0 and reflecting the detection result in a predetermined 1 byte of the RAM (referred to as a sensor input state flag). The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S754). Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. A payout control process to be executed is executed (step S755).

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing for detecting various errors (step S757). Next, the payout control CPU 371 executes a prepaid card unit error control process for performing error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes information output processing for outputting prize ball information to the main board 31 and outputting the prize ball signal 1 and the gaming machine error state signal to the outside (step S759). Further, display control processing for performing a predetermined display on the error display LED 374 according to the result of the error processing is executed (step S760).

  In the present embodiment, when various errors (for example, a payout number error error, a full tank error, a ball shortage error, a prepaid card unit unconnected error) are detected in error processing to be described later, an error corresponding to the detected error is detected. Bit is set. Then, in the display control processing in step S760, the payout control CPU 371 performs a predetermined display on the error display LED 374 that the error bit is set.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer include a payout motor control process (step S756), a prepaid card control process (step S753), a main control communication process (step S754), an information output process (step S759), and a display control process ( It is updated in step S760).

  FIG. 77 is a flowchart showing the main control communication process of step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 78 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command reception process, the payout control CPU 371 first checks whether or not a connection signal is input (step S7401). If no connection signal is input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S7402). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is abnormal. It is possible to prevent a situation in which data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S7403), and checks whether or not the value of the main control communication control code is a value “0” indicating the main control connection confirmation process. (Step S7404).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S7404, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, when the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S7404, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S7405). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. Then, the payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S7406). If it is determined in step S7404 that the value of the main control communication control code is “0” indicating the main control connection confirmation process, the process proceeds to step S7406).

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that a connection signal is not input in step S7401, if the main control connection confirmation process is not being executed in step S7404, the connection signal is not displayed after power is turned on to the gaming machine. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S7406), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this example) has elapsed since the connection OK command was transmitted, the connection confirmation command and the prize ball number command are received from the game control microcomputer 560. If not, it is determined that some communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and the connection state with the game control microcomputer 560 is confirmed again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S7407). For example, the payout control CPU 371 receives the serial communication circuit 380 if a flag indicating a parity error, framing error, noise error, overrun error, or idle line error is set in the status register of the serial communication circuit 380. It is determined that there is an error state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S7408). In this way, by initializing the receiving circuit of the serial communication circuit 380 in the case of a reception error state, it is possible to prevent a situation in which a reception command is stored in the reception data register even though some reception abnormality has occurred. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S7409).

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S7410) and checks whether or not a connection confirmation command is received (step S7411). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 30). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S7414.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 30, the contents of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is greater than or equal to the prize ball number command minimum value “51 (H)” (step S7412). Next, if the prize ball number command minimum judgment value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum judgment value “60 (H)”. It is confirmed whether or not (step S7413). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S7414.

  In step S7414, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interrupt period (1 ms in this example) in the payout control microcomputer 370 is equal to the timer interrupt period (in this example, the game control microcomputer 560). 4 ms), a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and it becomes impossible to shift to the main control communication normal process. Can be prevented.

  FIG. 79 is a flowchart showing a main control connection confirmation process (step S741) executed when the value of the main control communication control code is 0. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) to the main control communication control timer (step S7417).

  80 and 81 are flowcharts showing main control communication normal processing (step S742) executed when the value of the main control communication control code is 1. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, the fact that the main control communication control timer has timed out in step S7402 means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S7409) elapses well after 1 second from the transmission of the connection OK command. This is a case where reception was not possible. For this reason, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S7403), and returns to the main control connection confirmation process to wait for the recovery of the communication state. To do.

  If the main control communication control timer has timed out in step S74202, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If no BRDY signal is input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. That is, in this case, an error state has occurred, or during the winning ball payout operation, the ball lending payout operation, or during the ball lending preparation, the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a command for preparing a prize ball (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  FIG. 82 and FIG. 83 are flowcharts showing the main control communication in-process (step S743) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a winning ball preparing command in order to transmit the next winning ball preparing command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, the command for preparing the next prize ball is not yet ready if the prize ball payout operation cannot be started after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal has been input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, so the processing is ended as it is. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer, but this control is performed, for example, by adding the award ball number to the unpaid number counter during the lending ball payout operation. This is to prevent inconvenience in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number reception command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparing command is transmitted.

  FIG. 84 is a flowchart showing a main control communication end process (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process that is executed after receiving a prize ball number command and starting a prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74414). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74414, the command for preparing the next prize ball is transmitted if the prize ball payout operation is not yet completed after one second has passed. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 85 is a flowchart showing main control transmission command conversion processing executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets a main control communication payout number error error output bit (specifically, bit 3) in the conversion buffer (step S732).

  Next, the payout control CPU 371 checks whether or not the ball break error designation bit is set (step S733). If the ball-out error designation bit is set, the payout control CPU 371 sets the main control communication ball-out output bit (specifically bit 2) in the conversion buffer (step S734).

  Next, the payout control CPU 371 checks whether or not the full error designation bit is set (step S735). If the full error specification bit is set, the payout control CPU 371 sets the full output bit for main control communication (specifically bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 checks whether or not other prize ball error designation bits are set (step S737). Specifically, the payout control CPU 371 includes a main control communication error designation bit, a main control unconnected error designation bit, a withdrawal switch abnormality detection error 1 designation bit, a withdrawal switch abnormality detection error 2 designation bit, a withdrawal in the error flag. Check if the case error specification bit is set. If any other prize ball error designation bit is set, the payout control CPU 371 sets a main control communication ball out output bit (specifically bit 0) in the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or prize ball preparing command) set for transmission (step S739).

  FIG. 86 is a flowchart showing the payout control process in step S755. In the payout control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S7501), and checks whether the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid number counter is 0, the payout control CPU 371 adds 1 to the value of the payout number abnormality counter for counting the cumulative number of abnormal payouts (step S7503). In other words, Y in step S7502 means that the unpaid number to be paid out is not set in the unpaid-out number counter, so that the payout operation is performed even though the game ball should not be paid out. And the payout count switch 301 detects the payout of the game ball. For this reason, there is a possibility that the payout operation has been performed by some kind of fraud, so the payout control CPU 101 cumulatively adds 1 to the value of the payout number abnormality counter.

  The payout number abnormality counter indicates the number of payouts exceeding the number of unpaid game balls to be paid out and the number of payout shortages that did not meet the number of unpaid game balls to be paid out. This is a counter for cumulatively counting. As will be described later, in this embodiment, when the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), it is determined that a payout number error has occurred and the payout is stopped. Processing to control the state is performed. Note that the process of step S7503 corresponds to a process of cumulatively counting the excess payout in the payout number abnormality counter.

  In this embodiment, without distinguishing whether the ball is a winning ball or a lending ball, the payout excess number and the payout shortage number are cumulatively counted in the payout number abnormality counter. For only one of the rented balls, the excessive payout and the shortage payout may be cumulatively counted in the payout number abnormality counter. Further, for example, with respect to prize balls and lending balls, it is possible to cumulatively count the excess payout and the shortage payout using separate counters. In this case, it may be determined that a payout number error occurs when the value of one of the counters reaches a predetermined threshold value, or a payout number error error when the total value of both counters reaches a predetermined threshold value. May be determined.

  Further, in this embodiment, the case where the value of the payout number abnormality counter is incremented by 1 when an excessive payout is detected in step S7503 has been shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excessive payout number may be subtracted from the value of the payout number abnormality counter, and the insufficient payout number may be added to the value of the payout number abnormality counter. In this case, for example, the payout control CPU 371 sets “2000” as the initial value in the payout number abnormality counter in the initial setting process when the power is turned on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. In steps S75320, S75325, and S75335, which will be described later, a value corresponding to the insufficient payout number may be added to the value of the payout number abnormality counter. For example, in the processing of steps S7504, S75321, and S7725 described later, it may be determined that a payout number error has occurred based on the value of the payout number error counter being 2000 or less.

  Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7504). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payouts detected is cumulatively managed on the payout control microcomputer 370 side, and if the accumulated value is equal to or greater than a predetermined payout number abnormal error determination value (for example, 2000), It is determined that there is an extremely high possibility that a payout operation is being performed due to some sort of fraud, and it is determined that a payout number abnormality error (an error indicating that the number of game balls paid out is abnormal) has occurred. In addition, there are not a few cases where game balls are paid out excessively or insufficient due to malfunctions, etc., so when an abnormality in the number of payouts is detected, it is immediately determined as a payout number error. The frequency determined to be a payout number abnormality error becomes higher than necessary, and the game is hindered. Therefore, in this embodiment, the number of abnormal payouts detected is cumulatively managed, and the payout number abnormality error is determined on the condition that the accumulated value is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000). By determining, it is prevented that it is determined that the payout number abnormality error is more than necessary.

  In this embodiment, if it is determined that there is a payout number error and the payout number error error flag is set once, the payout number error error flag is not cleared until the power is reset, and the payout number error error is not recovered. When the payout number abnormality error flag is set, the processes in steps S7504 and S7505 and the processes in S75321, S75322, S7725, and S7726 described later may not be executed. By doing so, it is possible to prevent useless processing after it is once determined that the payout number abnormality error has occurred, and to reduce the processing burden.

  Further, in this embodiment, “2000”, which corresponds to the number of game balls that can be stored in a game ball storage box (so-called dollar box) generally used in a game store, is generally set as a predetermined payout number abnormality error determination value. Although the case where it uses is shown, other values (for example, 1000 or 3000) may be used as the predetermined payout number abnormality error determination value.

  In this embodiment, the payout control process shown in FIG. 86 is a process that is commonly executed when the prize ball payout operation is executed and when the lending ball payout operation is executed. This counter is used in common when counting the number of game balls that have not been paid out with prize balls and when counting the number of game balls that have not been paid out with lending balls. When an abnormality in the number of payouts is detected, the value of the payout number abnormality counter is incremented without distinguishing between payout with a prize ball and payout with a lending ball, and whether or not a payout number abnormality error has occurred. A determination is made.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid-out number counter (step S7506), and the payout ball detection designation bit (game ball payout) is added to the flag of the payout control state. A bit indicating detection) is set (step S7507). The payout ball detection designation bit is a bit that is set when the payout number count switch 301 is turned on, and indicates that the payout number count switch 301 has detected at least one game ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes any one of steps S7511 to S7513 according to the value of the payout control code.

  FIG. 87 is a flowchart showing the payout start waiting process (step S7511) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first checks whether or not the value of the error flag is 0 (step S75101). If an error bit (one or more of all error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, by executing the processing of step S75101, it is determined that there is a payout number abnormal error, and the payout number abnormal error designation bit of the error bit is set, so that the steps after step S75102 are set. Control is performed so as not to shift to processing, and the payout is stopped.

  If the value of the error flag is 0, the payout control CPU 371 checks whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and checks whether or not a ball lending request is being made (step S75104). Specifically, the payout control CPU 371 checks whether or not a ball lending request specifying bit (a bit indicating that a ball lending request is being made) is set in the payout control state flag. The payout control CPU 371 may determine whether or not a ball lending request is being made by confirming whether or not a BRQ signal is input. If a ball lending request is being made (that is, when a ball lending payout operation is started), the payout control CPU 371 resets the ball lending request specifying bit in the payout control state flag (step S75105) and at the same time a payout control state flag. The designated bit during the ball lending / dispensing operation is set (step S75016). Next, the payout control CPU 371 sets a predetermined ball lending number (25 in this example) in the unpaid number counter (step S75107) and a predetermined ball lending number (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, control goes to a step S75113.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  If the BRDY signal is not input, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S75109). If the value of the unpaid number counter is not 0 (that is, when the prize ball payout operation is started), the payout control CPU 371 sets the value of the unpaid number counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of prize balls designated by the received prize ball number command should be set in the unpaid quantity counter (see steps S74214 and S74319), the prize ball dispensing operation is started. Then, a process of setting the number of prize balls in the payout motor rotation frequency buffer is performed. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball paying-out operation designation bit in the payout control state flag (step S75112). Then, control goes to a step S75113.

  In step S75113, the payout control CPU 371 sets a value in the payout motor control code for selecting a process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process in step S756, a payout motor starting process for starting the payout motor 289 is executed, and a lending ball payout operation or a prize ball payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 88 is a flowchart showing a payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether or not the payout operation is completed (step S7522). Specifically, the payout control CPU 371 checks whether or not a payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake process and the payout motor ball biting release process in the payout motor control process in step S756 shown in FIG.

  In the payout motor control processing, the payout control CPU 371 performs payout motor normal processing (processing such as setting the pointer at the head address of the table stored in the ROM), payout, according to the value of the payout motor control code. Motor start-up processing (processing such as setting the initial value of the excitation pattern in bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), payout motor slow-up processing (starting the rotation of the payout motor 289 smoothly) Therefore, the output state of the output port 0 is read out by reading the contents of the payout motor excitation pattern table at intervals longer than those in the case of constant speed processing and gradually approaching the time intervals in the case of constant speed processing. , Processing of setting bits 4 to 7 in the port 0 buffer corresponding to), payout motor constant speed processing (periodic payout motor excitation pattern) The process of reading the contents of the table and setting the bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), the dispensing motor brake process (the constant speed process to smoothly stop the dispensing motor 289) Port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at intervals longer than those in the case of, and gradually away from the time interval in the case of constant speed processing Processing of setting the bits 4 to 7), the payout motor ball biting process (when the ball biting state is detected, in order to release the ball biting, the contents of the payout motor excitation pattern table are read and the output port 0 is set. Processing to set bits 4 to 7 in the port 0 buffer corresponding to the output state), and the payout motor ball biting release processing (ball biting state is released) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the payout operation has been completed, the payout control CPU 371 resets the payout operation end designation bit of the payout control state flag (step S7523) and stops the payout motor used to set a payout passage monitoring time to be described later. The waiting process setting table 2 is set (step S7524).

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S7525). The designated number of paid-out balls inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). If the payout ball number inspected designation bit is set, the process proceeds to step S7527. If the payout ball number inspected designation bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S7524 with a payout motor stop waiting process setting table. Then, control goes to a step S7527.

  In step S7527, the payout control CPU 371 sets a value “2” indicating payout passing waiting processing in the payout control code. The payout control CPU 371 sets the payout passing monitoring time in the payout control timer based on the table set in steps S7524 and S7526 (step S7527). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. In this embodiment, when the payout ball number inspected bit is set in step S7525, 1 second is set as the payout passing monitoring time based on the payout motor stop waiting process setting table 2 set in step S7524. To do. If the paid ball number inspected bit is not set in step S7525, 0.6 seconds is set as the payout passing monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  89 to 91 are flowcharts showing the payout passing waiting process (step S7513) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first checks the value of the payout control timer (step S75301). If the value is 0, the process proceeds to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). If the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the payout control CPU 371 loads the error flag, and sets the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit. It is confirmed whether or not (step S75304). If any one of the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit is set, it is determined that the dispensing operation cannot be continued any more, and step S75306 is executed. Transition. If none of the payout number error error specification bit, the payout switch error detection error 1 specification bit, and the payout switch error detection error 2 specification bit is set, the payout control CPU 371 sets the value of the unpaid number counter to 0. It is confirmed whether or not (step S75305). If the value of the unpaid-out counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads a payout control state flag (step S75306), and is requesting a ballot for the payout control state flag. Bits other than the designated bit and the payout operation end designation bit are reset (step S75307). Then, the payout control CPU 371 sets a value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 loads an error flag and confirms whether or not the ball breakage error designation bit or the full tank error designation bit is set (step S75309). . If the ball breakage error designation bit or the full tank error designation bit is set, the processing is terminated as it is. If neither the ball breakage error designation bit nor the full tank error designation bit is set, the payout control CPU 371 checks whether or not the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designation bit in the payout control status flag (step S75312). . The payout control CPU 371 also includes a 1 designation bit during re-payout operation (bit indicating execution of the first re-payout operation) and a 2 designation bit during re-payout operation (execution of the second re-payout operation). Is reset (step S75313), and the process is terminated.

  Note that the designated number of paid-out balls has been inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). Note that, when the value of the unpaid-out number counter remains two or more despite the end of the payout operation, the remaining number is added to the payout number abnormality counter. Further, the detection determination by the payout number count switch 301 at the end of the payout operation is executed only once every time the payout operation is executed, and the payout motor ball biting process or the payout motor ball bite releasing process is executed. It is not executed when the biting operation is finished (specifically, since the payout case error designation bit is set in the ball biting state, the ball biting operation is performed by setting the payout ball number checked designation bit in advance in step S75312. Even if the operation is finished, the detection by the payout number count switch 301 is not determined). It should be noted that the payout ball number inspected designation bit is also set when the payout motor constant speed process in the payout motor control process becomes full.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314) and performs processing for executing re-payout processing after step S75315.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the 2 designation bit during re-payout operation of the payout control state flag is set (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1 designation bit during re-payout operation of the payout control state flag is set (step S75316). If the 1 designation bit during re-payout operation is not set, the payout control CPU 371 sets the 1 designation bit during re-payout operation in the payout control state flag in order to execute the first re-payout operation (step S75317). .

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S75318). If the specified number of paid-out balls is inspected, the process proceeds to step S75326. If the specified number of paid-out balls has been inspected, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 2 or more (step S75319). If the value of the unpaid-out number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid number counter is 2 or more, the payout control CPU 371 adds the value of the unpaid number counter to the payout number abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S75321). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S75322).

  In this embodiment, the payout is performed on condition that the value of the unpaid-out number counter remains at a predetermined reference number (2 in this example) even though the payout operation is finished by the process of step S75319. The value of the unpaid number counter is added to the number abnormality counter. That is, since the payout operation is terminated due to a malfunction or the like, the value of the unpaid-out number counter remains in a small number (1 in this example). If even one unsettled number counter value remains, the accumulated number is immediately counted as a cumulative number in the payout number abnormality counter, and the frequency determined as a payout number abnormality error is increased more than necessary, causing problems to the game. End up. Therefore, in this embodiment, on the condition that the value of the unpaid-out number counter remains 2 or more with a little allowance, the accumulated number is counted in the payout number abnormality counter, and it is determined that there is an unnecessarily large number of payout errors. Is prevented. The process of step S75319 shows a case where the payout number abnormality counter is cumulatively counted up on condition that the payout shortage number is equal to or greater than a predetermined reference number (2 in this example). Alternatively, the payout number abnormality counter may be counted up cumulatively on condition that the number is a predetermined reference number (2 in this example) or more. In this case, for example, on the condition that the number of times determined as Y in step S7502 shown in FIG. Count up. In the processing of steps S75319 and S75320, the value of the unpaid number counter is always used as it is in the payout number abnormality counter regardless of whether or not the value of the unpaid number counter remains at a predetermined reference number (2 in this example). You may make it add.

  If the 1 designation bit during re-payout operation is set in step S75316, the payout control CPU 371 checks whether or not the dispensed ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during re-payout operation in the payout control state flag to execute the second re-payout operation (step S75324). Then, 1 is added to the value of the payout number abnormality counter (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Then, control goes to a step S75326. Note that by executing the processing of step S75325, the value of the payout number abnormality counter is incremented by 1 when the re-payout operation is not performed normally despite the execution of the first re-payout operation. The Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repaid operations in order to execute the first repaid operation. Next, the payout control CPU 371 sets the number of re-payout operations (1 in this example) in the payout motor rotation frequency buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value in the payout motor control code for selecting the process executed in the payout motor control process in accordance with the payout motor activation process (step S75330). Thereby, in the payout motor control process of step S756, the payout motor starting process for starting the payout motor 289 is executed, and the re-payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If the 2 designation bit during re-payout operation is set in step S75315, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75332). Next, the payout control CPU 371 checks whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter (step S75334). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Also, by executing the process of step S75335, even if the second re-payout operation is executed, if the re-payout operation is not performed normally, the value of the payout number abnormality counter is incremented by one. Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the re-payout waiting timer (step S75337) and ends the process. The re-payout waiting timer set in step S57337 is measured by error processing described later (see step S7710), and the payout case error designation bit in the error flag is reset based on the time-out of the re-payout timer. (See steps S7711 and S7712). By executing such processing, in this embodiment, after the payout case error is detected, the error state is automatically recovered based on the fact that two minutes have passed.

  Next, error processing will be described. FIG. 92 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 92, when no error has occurred, “−” is displayed on the error display LED 374. When the cumulative count value of the payout number abnormality counter is 2000 or more and a payout number error is detected, the payout control CPU 371 of the payout control microcomputer 370 detects an error display LED 374 as a payout number error. Control to display “A” on the screen. If a payout number abnormality error occurs, the error state is continued until the power supply of the gaming machine is reset.

  When the connection signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 performs control to display “1” on the error display LED 374 as a main board non-connection error. Do.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  When a serial communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, control is performed to display “5” on the error display LED 374 as a main control communication error. .

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S758).

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, or a main control communication error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes ON state). The payout control means returns to the state before the error occurred.

  As already described, the payout control CPU 371 specifically displays an error on the error display LED 374 according to the relationship shown in FIG. 92 in the display control process of the timer interrupt process (see step S760). For example, the payout control CPU 371 generates a prepaid card unit unconnected error in the display control process based on the setting of the prepaid card unit unconnected state designation bit in the error process described later (see step S7729). An error display “8” indicating that is displayed on the error display LED 374 is controlled. Further, for example, based on the fact that the full error specification bit is set in the error processing (see step S7714), an error display “6” indicating that a full error has occurred in the display control processing is displayed on the error display LED 374. Control the display.

  93 and 94 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the error flag payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. The other error bits are reset (step S7701). Next, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch abnormality detection error 2 designation bit, the withdrawal case error designation bit, the main control communication error designation bit, or the withdrawal number abnormality error designation bit is set) The control CPU 371 checks whether or not the operation signal is turned on from the error release switch 375 (step S7703). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S7709). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S7705). If the pre-error recovery timer value becomes 0 (step S7706), the payout switch of the error flags is set. The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the re-payout waiting timer is reset (step S7708). Then, control goes to a step S7710. If the pre-error recovery timer has not timed out, the process proceeds to step S7713.

  When the processing of step S7707 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem even if the error bit that is not set is reset. As described above, in this embodiment, when an error (see FIG. 92) that causes the setting of the payout switch abnormality detection error 2, the payout case error, and the main control communication error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  In step S7710, if set, the payout control CPU 371 subtracts 1 from the value of the re-payout waiting timer, and checks whether the re-payout wait timer after the subtraction has timed out (step S7711). If the re-payout waiting timer has timed out, the payout control CPU 371 resets the payout case error designation bit in the error flag (step S7712). Then, control goes to a step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processes of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error has been canceled (more precisely, the time before error recovery has passed) and on the condition that a predetermined time (2 minutes in this example) has passed after detection of the payout case error The error may be automatically canceled. In this embodiment, regarding the payout number abnormality error, once detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing of steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 89 to 91). Then, the game ball payout retry operation is started. That is, when the payout control process in step S755 is executed next, if the payout passing waiting process in step S7513 is executed, the repayout process is performed again. For example, if a prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is in the reset state in step S75310. Therefore, the process for starting the re-payout process after step S75314 is executed again, and the re-payout process is executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When detected (see step S75314 and subsequent steps in FIGS. 89 to 91), the control state related to payout is shifted to an error state, and an error release signal is output from the error release switch 375 in the error state, or a payout case Corrected payout that makes correction payout control again on condition that a predetermined time (2 minutes in this example) has passed since the error was detected To run the control restart processing.

  Further, even during execution of the re-payout process in the error state (specifically, during the re-payout process before setting the payout case error and during the re-payout process after pressing the error release switch 375), step S7501 shown in FIG. S7502 and S7506 are executed. That is, even when an error related to payout occurs, if the game ball passes the payout number count switch 301, the value of the unpaid-out number counter is subtracted. Accordingly, the value of the unpaid-out number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 89 to 91, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) or when a payout case error is detected for a predetermined time. (2 minutes in this example) has elapsed (steps S7707, S7712). That is, until a predetermined time (in this example, 2 minutes) has passed since the detection of the payout case error, the payout case error (insufficient payout) is automatically determined based on the fact that the game ball has passed through the payout number count switch 301. The error) state is not canceled, and the payout case error is not canceled without an artificial operation. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred. However, in this embodiment, at least a long time (2 minutes in this example) after the occurrence of the payout case error is configured to automatically cancel the payout case error so that the payout case error is generated. Prevents longer duration than necessary.

  In some cases, a gaming machine may be configured such that a hardware reset (reset for the payout control CPU 371) is performed by operating the error release switch 375. When the error release switch 375 is operated, for example, the value of the unpaid number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S7713, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit in the error flag is set (step S7714).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S7715). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 checks the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), sets the main board unconnected error designation bit. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S7720). It should be noted that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S752, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371 loads the payout control state flag when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “4”) (step S7721). In step S7722), it is confirmed whether the winning ball payout operation or the ball lending payout operation is in progress (step S7723). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit or a ball lending payout operation specifying bit is set in the payout control state flag. If the designated bit during the winning ball payout operation and the designated bit during the ball lending payout operation are both in the reset state, the payout control CPU 371 determines that the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, an error flag. Among these, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 checks whether or not the value of the payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7725). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred and sets a payout number error error flag (step S7726).

  Next, the payout control CPU 371 resets the prepaid card unit error flag for setting the error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S7728). If the VL signal is not input (if it is in the off state), the prepaid card unit error flag The prepaid card unit unconnected error designation bit is set (step S7729).

  In the display control process of step S760, the error display LED 374 performs notification by display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board unconnected error is automatically canceled when the connection signal is turned on (see steps S7701, S7717, and S7718), but the condition that the error cancel switch 375 is further operated is set. In addition, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit non-connection error and a prepaid card unit communication error) and other errors (see FIG. 92). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  In this embodiment, in error processing, first of the error flags, other than the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, and the withdrawal number abnormality error designation bit. After the bit is reset once (see step S7701), it is checked every time error processing is executed whether a full error, a ball break error, or a main control unconnected error has occurred. The payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 has been operated. However, the payout number abnormality error is not canceled once it is set. Therefore, in this embodiment, when a payout number error occurs, the payout number error is canceled as a condition that the power supply is reset.

  95 and 96 are flowcharts showing the information output processing in step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 checks whether or not the designated bit during the ball lending payout operation of the payout control state flag is set. If the ball lending / dispensing operation is in progress, the process proceeds to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 checks whether or not the payout number count switch 301 is in the on state (step S7903). If the payout number count switch 301 is in the ON state (in this case, the payout by the winning ball is detected), the payout control CPU 371 adds 1 to the value of the winning ball signal 1 output number counter (step S7904). At the same time, the value of the prize ball payout number counter is incremented by 1 (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the condition for outputting the prize ball signal 1 is satisfied. The prize ball payout number counter is a counter for counting the number of game balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the added prize ball payout counter is equal to or greater than a predetermined prize ball information output determination value (10 in this example) (step S7906). If it is equal to or greater than a predetermined prize ball information output determination value (10 in this example), the payout control CPU 371 resets the prize ball payout number counter (step S7907) and sets the value of the prize ball information output number counter. 1 is added (step S7908). The prize ball information output count counter is a counter for counting the number of times that the condition for outputting prize ball information is satisfied.

  Next, if it is set, the payout control CPU 371 decrements the prize ball information output timer by 1 (step S7909), and checks whether the prize ball information output timer after the subtraction has timed out (step S7910). The prize ball information output timer is a timer for measuring the output duration time of prize ball information. If not timed out, the process proceeds to step S7914. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball information output number counter is 0 (step S7911). If the value of the prize ball information output number counter is 0, the process proceeds to step S7915. If the value of the winning ball information output number counter is not 0 (that is, if the number of winning ball information output conditions is still satisfied), the payout control CPU 371 subtracts 1 from the value of the winning ball information output number counter. (Step S7912). Next, the payout control CPU 371 sets a prize ball information output timer in order to start outputting the next prize ball information (step S7913). Then, the payout control CPU 371 performs control to output the prize ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball information output bit (bit 7; see FIG. 73) of the output port 1.

  Next, if the payout control CPU 371 is set, the prize ball signal 1 output timer is decremented by 1 (step S7915), and it is confirmed whether or not the prize ball signal 1 output timer after the subtraction has timed out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If not timed out, the process proceeds to step S7920. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output number counter is not 0 (that is, if the number of established conditions for the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output number counter. 1 is subtracted (step S7918). Next, the payout control CPU 371 sets a prize ball signal 1 output timer to start outputting the next prize ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to output the prize ball signal 1 to the outside (step S7920). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball signal 1 output bit (bit 0; see FIG. 73) of the output port 0. In this embodiment, the winning ball signal 1 is not directly input from the payout control board 37 to the terminal board 160 and externally output, but is input to the terminal board 160 once through the main board 31. Is output externally.

  Next, the payout control CPU 371 performs processing for setting output data in the gaming machine error state signal output bit (bit 1, see FIG. 73) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the ball breakage error designation bit or the full tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of the output port 0 remains set. The process ends. In this case, the gaming machine error status signal is output to the outside based on the fact that the gaming machine error status signal output bit of the output port 0 is set in step S7921. In this embodiment, the gaming machine error state signal is not directly input from the payout control board 37 to the terminal board 160 but externally output, but is input to the terminal board 160 once through the main board 31. And output externally. On the other hand, if neither the ball breakage error designation bit nor the full tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error state signal output bit of the output port 0 (step S7925), and processing Exit.

  By executing the above processing, in this embodiment, the prize ball signal 1 is output to the outside every time one prize ball payout is detected on the payout control means side. Further, prize ball information is output to the game control means side every time ten payout balls are detected on the payout control means side. Further, when a ball break error or a full tank error is detected on the payout control means side, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 97 is a flowchart showing a main process executed by the effect control microcomputer 100 (specifically, the effect control CPU 101a) as effect control means mounted on the effect control board 80. The effect control CPU 101a starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) (step S781). . Thereafter, the effect control CPU 101a proceeds to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101a clears the flag (step S783) and executes the following effect control process.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S784).

  Next, the effect control CPU 101a performs effect control process processing (step S785). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S786). Thereafter, the process proceeds to step S782.

  FIG. 98 is a flowchart showing a specific example of command analysis processing (step S784). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101a checks the content of the command stored in the command reception buffer.

  In FIG. 98, among the effect control commands transmitted from the game control microcomputer 560, particularly, processing is shown when a command indicating an error relating to payout control is received. Various effect control commands such as a variation pattern command indicating a variation pattern and a display result specifying command indicating a display result indicating whether or not to win are transmitted from the game control microcomputer 560.

  In the command analysis process, the effect control CPU 101a first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101a sets a prize ball error bit (bit 0, see FIG. 31) among the lower 4 bits of the frame state display command. It is confirmed whether it has been done (step S615). If set, the effect control CPU 101a performs control to superimpose and display predetermined prize ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the full error bit (bit 1, see FIG. 31) of the lower 4 bits of the frame state display command is set (step S617). If set, the effect control CPU 101a performs control to superimpose and display predetermined full tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 a performs control to display a character string such as “a full tank error has occurred” on the display screen of the effect display device 9.

  In addition, the effect control CPU 101a checks whether or not the ball break error bit (bit 2, see FIG. 31) in the lower 4 bits of the frame state display command is set (step S619). If set, the effect control CPU 101a performs control to superimpose and display predetermined ball-out error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 a performs control to display a character string such as “A ball break error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the payout number error error bit (bit 3; see FIG. 31) in the lower 4 bits of the frame state display command is set (step S621). If set, the effect control CPU 101a performs control to superimpose and display predetermined payout number abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 a performs control to display a character string such as “A payout number error has occurred” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball shortage error command (step S623), the effect control CPU 101a performs control to superimpose and display predetermined prize ball shortage error notification information on the display screen of the effect display device 9 (step S623). S624). For example, the effect control CPU 101 a performs control to display a character string such as “There was a shortage of prize balls error” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball excess error command (step S625), the effect control CPU 101a performs control to superimpose and display predetermined prize ball excess error notification information on the display screen of the effect display device 9 (step S625). S626). For example, the effect control CPU 101a performs control to display a character string such as “An excessive prize ball error has occurred” on the display screen of the effect display device 9.

  In addition, each error display may not be simply displayed in a superimposed manner, but may be prioritized and notified of an error having a high priority by ranking from the viewpoint of fraud importance. For example, a payout number abnormality error may be preferentially notified with the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  If the received effect control command is another command, the effect control CPU 101a sets a flag corresponding to the received effect control command (step S627). Then, control goes to a step S611. For example, when a variation pattern command or a display result designation command is received, the effect control CPU 101a also performs processing for storing the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  FIG. 99 is a flowchart showing the effect control process (step S785) in the main process shown in FIG. In the effect control process, the effect control CPU 101a performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of the effect symbol is realized. However, control related to variable display of the effect symbol synchronized with the change of the first special symbol is also the second. Control related to the variable display of the effect symbol synchronized with the change of the special symbol is also executed in one effect control process. It should be noted that the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Production symbol variation start processing (step S801): Control is performed so that the variation of the production symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Effect symbol variation stop processing (step S803): Control is performed to stop the variation of the effect symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): When the big hit is made, after the end of the variation time, the effect display device 9 is controlled to display a screen for notifying the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805).

  Big hit game processing (step S805): Control during big hit game is performed. For example, when a special winning opening opening designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot end effect process (step S806).

  Big hit end effect processing (step S806): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  As described above, according to this embodiment, the gaming control microcomputer 560 is informed that the initialization process has been executed when the gaming machine is powered on and that a predetermined error (in this example, the first A predetermined signal output condition is satisfied, including that it is determined that the start winning port 13a, the second starting winning port 13b, the first major winning port 23b, and the second major winning port 24b are abnormal). Based on that, a security signal is output outside the gaming machine. In this case, the game control microcomputer 560 has a common output terminal (a terminal board of the terminal board) provided in the gaming machine when the initialization process is executed and when it is determined that a predetermined error has occurred. A security signal is output from the common connector CN7). Further, a predetermined signal output condition is newly established when the security signal is output (in this example, the first start winning opening 13a, the second starting winning opening 13b, the first big winning opening 23b, the second In the case of detecting an abnormal winning to the big winning opening 24b), the output time for outputting the security signal is extended. Therefore, by outputting a security signal based on the execution of the initialization process, it is possible to prevent an illegal act performed when the gaming machine is powered on. In addition, since the security signal is output to the common output terminal when the initialization process is executed and when it is determined that a predetermined error has occurred, the waste of the signal line for external output is reduced. Can do. Therefore, it is possible to reduce the waste of the signal line for external output while preventing an illegal act performed when the power to the gaming machine is turned on.

  Further, Patent Document 1 describes that an illegal act (radio wave or the like) input to the winning switch is prevented from operating a safe sensor so that an illegal act can be detected. Specifically, the use of a pass-type safe sensor is described. However, Patent Document 1 shows that the winning switch and the safe sensor are operated simultaneously by strong radio waves, so that the winning switch and the safe sensor have different detection performances. The same type of safe sensor is used. Patent Document 1 shows that all winning switches and safe sensors are operated at the same time, and that it is determined that an illegal act has been received. The winning switch and the safe sensor do not always operate simultaneously. It is assumed that all winning switches and safe sensors may or may not operate simultaneously depending on the strength of radio waves. That is, the method disclosed in Patent Document 1 is insufficient for detecting fraud.

  According to this embodiment, the game control microcomputer 560 is based on the detection signal input from the first start port switch 14a (proximity switch) and the detection signal input from the first winning confirmation switch 14b (photo sensor). Thus, the difference between the number of game balls detected by the first start opening switch 14a and the number of game balls detected by the first winning confirmation switch 14b exceeds a predetermined threshold (in this example, 15 or more). It is determined that an abnormal prize has occurred at the first start prize opening 13a as a predetermined error. In this embodiment, the first start port switch 14a and the first winning confirmation switch 14b are configured by sensors of different detection methods (in this example, a proximity switch and a photo sensor). For this reason, it is possible to more reliably detect fraudulent acts with respect to the switch that detects the game ball, and to take certain measures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 executes the special symbol variation display based on only the input of the detection signal from the first start port switch 14a and performs the winning ball payout process. Run. Further, the detection signal input from the first winning confirmation switch 14b is used only for determining whether or not an abnormal winning to the first start winning opening 13a has occurred. Further, based on only the detection signal input from the second start port switch 15a, the special symbol variation display is executed and the prize ball payout process is executed. Further, the detection signal input from the second winning confirmation switch 15b is used only for determining whether or not an abnormal winning has occurred in the second start winning opening 13b. Therefore, since the special symbol variation display and the prize ball payout process are performed based on the detection result of one of the switches, it is possible to prevent an increase in the processing burden accompanying the strengthening of countermeasures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 determines the difference between the number of game balls detected by the first start port switch 14a and the number of game balls detected by the first winning confirmation switch 14b. However, as a predetermined threshold, the number of game balls detected in the first start opening switch 14a and the game in the first prize confirmation switch 14b when the inside of the first prize passage 1360 and the second big prize passage 1390 is in a blocked state. More than the difference (for example, 15) between the detected number of balls or the detected number of gaming balls in the second count switch 24 and the detected number of gaming balls in the fourth winning confirmation switch 24a (for example, 15) It is determined whether or not. For this reason, when the first start winning opening 13a and the second large winning opening 24b are clogged, an abnormal winning to the first starting winning opening 13a and the second large winning opening 24b has occurred. Can be prevented. Accordingly, it is possible to prevent erroneous determinations associated with strengthening countermeasures against fraud.

  Further, according to this embodiment, the gaming control microcomputer 560 has a predetermined error (in this example, the first start winning award 13a, the first number) when the initialization process is executed when the gaming machine is turned on. The security signal is output over a different period of time when it is determined that the 2nd winning prize opening 13b, the first big prize opening 23b, and the second big prize opening 24b are abnormal). Specifically, in this embodiment, when the initialization process is executed when the power to the gaming machine is turned on, a security signal is output to the outside for 30 seconds, and the first start winning opening 13a, the second start When an abnormal winning is detected at the winning opening 13b, the first big winning opening 23b, or the second big winning opening 24b, a security signal is externally output for 4 minutes. Therefore, by determining the output time of the security signal, it is possible to determine whether the initialization process has been performed or a predetermined error has occurred in an external device such as a hall computer. It becomes.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. Further, the game control microcomputer 560 sends a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370 every time a predetermined period (1 second in this example) elapses. To 370. The payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using a serial communication method, it is possible to facilitate wiring between the game control microcomputer 560 and the payout control microcomputer 370. In addition, the control state signal (response signal to which the control state is added) is transmitted by placing the control state on the connection OK command that the payout control microcomputer 370 periodically outputs based on the reception of the connection confirmation command. Can do. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the cycle (interval) for transmitting the connection confirmation command is 1 second, but it may be 0.5 seconds or the like.

  Further, according to this embodiment, the game control microcomputer 560 resets a predetermined period (1 second in this example) to the prize ball process timer when the execution of the payout control is finished, and the prize ball process. Measurement control by the timer is started (see step S52505). If the number of prize balls is not stored (specifically, if no prize ball command output counter has a count value of 1 or more in step S52301), the game control microcomputer 560 resets the game. A new connection confirmation command is transmitted to the payout control microcomputer 370 based on the time-out of the prize ball process timer. For this reason, an interval period can be provided between the end of execution of payout control and the transmission of a new connection confirmation command, and processing at the end of execution of payout control is concentrated, and a new connection check command is overwritten. Can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 transmits a winning ball number command to the payout control microcomputer 370 based on the detection of a winning regardless of the transmission timing of the connection confirmation command. To do. Further, the payout control microcomputer 370 transmits a prize ball number reception command based on the reception of the prize ball number command, and receives a prize ball preparation command during execution of the payout control. The signal is transmitted to the game control microcomputer 560 every signal output period (1 second in this example). In this case, the payout control microcomputer 370 receives the prize ball in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, an out of ball error, and a payout number error error). The preparing command is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the prize ball number reception command. Therefore, it is possible to reduce the control burden of the game control microcomputer 560 by not performing connection control command transmission control unnecessarily during execution of payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the award ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, the game control microcomputer 560 receives the award ball end command and then stores the number of award balls (specifically, the prize ball command output counter in step S52301). If the count value is 1 or more), a new prize ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to speed up the execution process of the payout control.

  In addition, according to this embodiment, the game control microcomputer 560 determines whether a predetermined error (in this example, a prize ball error, a full tank error, a full ball error, based on the control state indicated by the received connection OK command. , And a payout quantity abnormality error). Then, the game control microcomputer 560 transmits a prize ball number command to the payout control microcomputer 370 on the condition that it is determined that a predetermined error has not occurred. Therefore, it is possible to prevent the inconvenience of sending a prize ball number command when the payout control cannot be normally performed due to an error state. In particular, in this embodiment, since the RAM provided in the payout control microcomputer 370 is not backed up by the backup power supply, if a prize ball number command is transmitted when there is an abnormality in the payout control, the power is reset. For example, the memorized number of prize balls may be lost, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the prize ball number command is transmitted while the memory of the prize ball number is retained on the game control microcomputer 560 side backed up by the backup power source. It is possible to prevent such a disadvantage from occurring by controlling to hold.

  Further, according to this embodiment, the game control microcomputer 560 increases the time interval for transmitting the connection confirmation command when the connection OK command cannot be received after transmitting the connection confirmation command. Whenever a specific period (10 seconds in this example) elapses, the control is switched to the connection confirmation command transmission. Therefore, in a state where the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. Can be performed less frequently, and a wasteful processing load can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 causes the game to occur when a predetermined error (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error) occurs. Information that allows the control microcomputer 560 to recognize a predetermined error is set by changing a specific bit of the connection OK command, and the connection OK command in which the setting has been made is transmitted to the game control microcomputer 560. The game control microcomputer 560 transmits a frame state display command in which information capable of recognizing a predetermined error set in the received connection OK command is set as it is to the effect control microcomputer 100. Then, based on the reception of the frame state display command, the production control microcomputer 100 controls the production device (the production display device 9 in this example) to notify that a predetermined error has occurred. Do. Therefore, it is possible to notify that a predetermined error has occurred using the effect device, and to reduce the processing load on the game control microcomputer 560.

  In addition, according to this embodiment, the payout control microcomputer 370 has a payout excess exceeding the number of unpaid game balls to be paid out and the number of unpaid games to be paid out. The number of shortage payouts that did not reach the ball is cumulatively counted using a payout number abnormality counter. When the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), the payout control is stopped and the payout stop state is controlled. Therefore, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under an abnormal condition based on the value of the payout number abnormality counter counted up cumulatively. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out the game ball.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout number abnormality counter when a payout shortage number equal to or greater than a predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary. In other words, since there are not a few small numbers (1 in this example) of insufficient payouts in the operating state of the gaming machine, the number of insufficient payouts exceeding the predetermined reference number (2 in this example) has occurred. By counting up on the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes re-payout control for driving and controlling the ball payout device 97 to pay out only one game ball when a payout shortage occurs. . If the payout of the game ball is not detected even after the re-payout control is executed, the value of the payout number abnormality counter is counted up. Therefore, even if the number of payout shortages is small, it is possible to appropriately stop the execution of payout control by reflecting it in the count value of the payout number abnormality counter, and to take illegal measures to prevent the act of illegally paying out game balls. Can be strengthened.

  Further, according to this embodiment, when the payout number abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on condition that the power supply of the gaming machine is reset. Therefore, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and the game is continued in the abnormal state. This can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can retain the stored contents for a predetermined period by the backup power supply even when the power supply to the gaming machine is stopped. In addition, when the game control microcomputer 560 is controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a winning occurs. For this reason, the number of prize balls stored in the RAM 55 (specifically, the value of the prize ball command output counter) is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that is not caused by fraud. It is possible to prevent such a situation from occurring, and it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the prize ball number to the prize ball number counter at the timing of sending the prize ball number command, and receives the prize ball information based on the received prize ball information. Subtract 10 from the value of the ball counter. Then, based on the fact that the value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (501 in this example), it is determined that there is a prize ball shortage error. Based on the fact that it is less than the determination value (0 in this example), it is determined that there is an excessive prize ball error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game ball.

  Further, according to this embodiment, the game control microcomputer 560 transmits a connection signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the payout control microcomputer 370 can confirm the communication connection state at any timing, the payout of the prize ball is performed when the communication connection state is abnormal. This can be surely prevented.

  In the above embodiment, the game control microcomputer 560 normally transmits a connection confirmation command 1 second after the connection OK command is received, and when a communication error occurs (for example, connection When the OK command cannot be received), the connection confirmation command is transmitted 10 seconds after the connection confirmation command is transmitted, and the period of 1 second or 10 seconds is measured by a timer (a counter configured by software). However, the connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the connection OK command, or the counter may be cleared if an internal interrupt is generated with a predetermined value.

  Next, a modified example of the physical configuration of the terminal board 160 mounted on the gaming machine will be described. 100 and 101 are explanatory diagrams showing modifications of the physical configuration of the terminal board 160. FIG. The gaming machine is provided with a cover member 800 for covering and protecting each board such as the main board 31, the effect control board 80, and the payout control board 37, for example, as shown in FIGS. As described above, the terminal board 160 may be embedded in the cover member 800. Also, a terminal board cover 801 for covering and protecting the terminal board 160 is attached to a portion of the cover member 800 where the terminal board 160 is attached. Here, FIG. 100 shows a state where the terminal board cover 801 is attached to the cover member 800, and FIG. 101 shows a state where the terminal board cover 801 is removed from the cover member 800. As shown in FIG. 101, two claw portions 801a for attachment are provided on the upper portion of the terminal substrate cover 801. By inserting the claw portions 801a and fastening them with screws 801b, the terminal substrate is covered. A cover 801 can be attached.

  Also, as shown in FIGS. 100 and 101, a plurality of terminals 96a, 96b, 98a, 98b,... For connecting cables with external devices such as hall computers are provided on the terminal board 160. A terminal board 900 is provided. Further, the terminal board 900 has a two-stage configuration including a terminal row including terminals 96a, 96b,... And a terminal row including terminals 98a, 98b,. One set (set of signal line and ground line). For example, in the example shown in FIGS. 100 and 101, one set of terminals 96a and 96b arranged in the horizontal direction among the terminals in the upper row of terminals is one set, and the horizontal direction of the terminals in the lower row of terminals. One set of the terminal 98a and the terminal 98b arranged in a row. Further, the terminals 96a, 96b, 98a, 98b,... Provided on the terminal board 900 are respectively provided with knobs 95a, 95b, 99a, 99b, and the knobs 95a, 95b,. The terminals 96a, 96b, 98a, 98b... Are opened by performing operations such as pressing 99a, 99b. For example, when the upper knob 95a is pressed, the cable can be connected to the terminal 96a, and when the lower knob 99a is pressed, the cable can be connected to the terminal 98a. For example, when the upper knob 95b is pressed, the cable can be connected to the terminal 96b, and when the lower knob 99b is pressed, the cable can be connected to the terminal 98b.

  Further, as shown in FIGS. 100 and 101, the knobs 95a, 95b, 99a, 99b,... Provided for each of the terminals 96a, 96b, 98a, 98b,. Has been. With such a configuration, it is possible to prevent inconveniences such as accidentally operating the knob for the adjacent terminal, and improve workability when performing the work of connecting the cable to the terminal board 900. be able to.

  FIG. 102 is an explanatory diagram showing a cross-sectional structure of a portion of the cover member 800 to which the terminal board 160 is attached. As shown in FIG. 102, the terminal board 160 is sufficiently placed so that the terminal board 900 provided on the terminal board 160 is located inside the surface of the cover member 800 (the X plane shown in FIG. 102). The cover member 800 is attached to the back side. As described above, the terminal board 900 provided on the terminal board 160 is configured to be inside the surface of the cover member 800 (the X surface shown in FIG. 102). It is possible to prevent the occurrence of inconvenience such as contact with the terminal board 900.

  Further, as shown in FIG. 102, the terminal board cover 801 is inclined so that the side wall portion 801c is gradually narrowed. Since the side wall 801c is inclined as described above, even when the terminal board cover 801 is attached, it is easy for a finger or the like to enter, and when connecting the cable to the terminal board 900, Workability can be improved.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines, arrange ball gaming machines, and sparrow ball gaming machines.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 9 Production display device 13a 1st start winning opening 13b 2nd starting winning opening 14a 1st starting opening switch 14b 1st winning confirmation switch 15 Variable winning ball apparatus 15a 2nd starting opening switch 15b 2nd winning confirmation switch 20A First special variable winning ball apparatus 23 First count switch 23a Third winning confirmation switch 23b First big winning opening 20B Second special variable winning ball apparatus 24 Second count switch 24a Fourth winning confirmation switch 24b Second big winning opening 31 Game control board (main board)
560 Microcomputer for game control

Claims (1)

A gaming machine that controls a specific gaming state advantageous to a player based on establishment of a predetermined condition,
A special variable winning device that can change to an open state in which the prize can be won in the specific gaming state;
Storage means capable of holding stored contents for a predetermined period even when power supply to the gaming machine is stopped;
Initialization operation means for outputting an operation signal in response to an operation;
Initialization processing execution means for executing initialization processing for initializing the storage contents of the storage means based on the input of the operation signal from the initialization operation means when power supply is started; ,
Error determination means for determining whether or not an abnormal winning error has occurred in the special variable winning device;
Based on the establishment of a signal output condition that includes at least that the initialization process has been executed by the initialization process execution means and that the error determination means has determined that the abnormal winning error has occurred. Security signal external output means for outputting a security signal to the outside of the gaming machine,
An abnormal winning error notification means for notifying that an abnormal winning error has occurred in the special variable winning device;
With
The security signal external output means includes:
A common output terminal provided in the gaming machine when the initialization process is executed by the initialization process execution means and when the abnormal determination error is determined by the error determination means To output the security signal to the outside of the gaming machine,
When the abnormal winning error is generated by the error determination means during the output of the security signal based on the initialization process being executed or the determination that the abnormal winning error has occurred, a new one is newly generated. When determined, extend the output period of the security signal being output,
When the initialization process is executed, the security signal is output for a predetermined time,
When it is determined that the abnormal winning error has occurred, the security signal is output for a time different from the predetermined time.

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