JP5803614B2 - 不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム - Google Patents

不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム Download PDF

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JP5803614B2
JP5803614B2 JP2011259796A JP2011259796A JP5803614B2 JP 5803614 B2 JP5803614 B2 JP 5803614B2 JP 2011259796 A JP2011259796 A JP 2011259796A JP 2011259796 A JP2011259796 A JP 2011259796A JP 5803614 B2 JP5803614 B2 JP 5803614B2
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JP2013114441A5 (enExample
JP2013114441A (ja
Inventor
肥後　豊
豊 肥後
細見　政功
政功 細見
大森　広之
広之 大森
別所　和宏
和宏 別所
徹哉 浅山
徹哉 浅山
一陽 山根
一陽 山根
裕行 内田
裕行 内田
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Sony Corp
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Sony Corp
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Priority to JP2011259796A priority Critical patent/JP5803614B2/ja
Priority to US13/681,999 priority patent/US9251057B2/en
Priority to CN201210479284.8A priority patent/CN103136119B/zh
Publication of JP2013114441A publication Critical patent/JP2013114441A/ja
Publication of JP2013114441A5 publication Critical patent/JP2013114441A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2011259796A 2011-11-29 2011-11-29 不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム Expired - Fee Related JP5803614B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011259796A JP5803614B2 (ja) 2011-11-29 2011-11-29 不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム
US13/681,999 US9251057B2 (en) 2011-11-29 2012-11-20 Nonvolatile cache memory, processing method of nonvolatile cache memory, and computer system
CN201210479284.8A CN103136119B (zh) 2011-11-29 2012-11-22 非易失性高速缓冲存储器、其处理方法以及计算机系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011259796A JP5803614B2 (ja) 2011-11-29 2011-11-29 不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム

Publications (3)

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JP2013114441A JP2013114441A (ja) 2013-06-10
JP2013114441A5 JP2013114441A5 (enExample) 2014-11-20
JP5803614B2 true JP5803614B2 (ja) 2015-11-04

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JP2011259796A Expired - Fee Related JP5803614B2 (ja) 2011-11-29 2011-11-29 不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム

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US (1) US9251057B2 (enExample)
JP (1) JP5803614B2 (enExample)
CN (1) CN103136119B (enExample)

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US9703704B2 (en) * 2012-05-01 2017-07-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6130750B2 (ja) 2013-07-16 2017-05-17 株式会社東芝 メモリ制御回路およびプロセッサ
JP6275427B2 (ja) * 2013-09-06 2018-02-07 株式会社東芝 メモリ制御回路およびキャッシュメモリ
WO2015057828A1 (en) * 2013-10-15 2015-04-23 Mill Computing, Inc. Computer processor employing cache memory storing backless cache lines
JP6030085B2 (ja) * 2014-03-20 2016-11-24 株式会社東芝 キャッシュメモリおよびプロセッサシステム
US9042160B1 (en) * 2014-07-03 2015-05-26 Sandisk Technologies Inc. Memory device with resistive random access memory (ReRAM)
US9105333B1 (en) * 2014-07-03 2015-08-11 Sandisk Technologies Inc. On-chip copying of data between NAND flash memory and ReRAM of a memory die
KR102131337B1 (ko) * 2014-10-20 2020-07-07 한국전자통신연구원 고장 제어 기능을 구비한 캐시 메모리
US9349952B1 (en) 2014-12-08 2016-05-24 Sony Corporation Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
WO2017095429A1 (en) * 2015-12-03 2017-06-08 Hitachi, Ltd. Method and apparatus for caching in software-defined storage systems
CN105677258A (zh) * 2016-02-23 2016-06-15 浪潮(北京)电子信息产业有限公司 一种日志数据管理方法及系统
US10761819B2 (en) * 2016-02-23 2020-09-01 Intel Corporation Optimizing structures to fit into a complete cache line
US10262721B2 (en) 2016-03-10 2019-04-16 Micron Technology, Inc. Apparatuses and methods for cache invalidate
CN106406767A (zh) * 2016-09-26 2017-02-15 上海新储集成电路有限公司 一种非易失性双列直插式存储器及存储方法
US10289551B2 (en) * 2017-05-11 2019-05-14 Western Digital Technologies, Inc. Preserving data upon a power shutdown
KR20200004119A (ko) * 2018-07-03 2020-01-13 에스케이하이닉스 주식회사 메모리 시스템 및 그의 동작 방법
US10447278B1 (en) 2018-07-17 2019-10-15 Northrop Grumman Systems Corporation JTL-based superconducting logic arrays and FPGAs
US10818346B2 (en) 2018-09-17 2020-10-27 Northrop Grumman Systems Corporation Quantizing loop memory cell system
US11211117B2 (en) 2019-01-24 2021-12-28 Northrop Grumman Systems Corporation Ferrimagnetic/ferromagnetic exchange bilayers for use as a fixed magnetic layer in a superconducting-based memory device
US11024791B1 (en) 2020-01-27 2021-06-01 Northrop Grumman Systems Corporation Magnetically stabilized magnetic Josephson junction memory cell
US12027196B2 (en) 2021-07-08 2024-07-02 Kioxia Corporation Memory system, control method, and power control circuit
TWI816285B (zh) * 2021-07-08 2023-09-21 日商鎧俠股份有限公司 記憶體系統、控制方法及電力控制電路

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TW576966B (en) * 2000-06-23 2004-02-21 Intel Corp Non-volatile cache integrated with mass storage device
KR100598379B1 (ko) * 2003-09-08 2006-07-06 삼성전자주식회사 컴퓨터 시스템 및 그 제어방법
US20050251617A1 (en) * 2004-05-07 2005-11-10 Sinclair Alan W Hybrid non-volatile memory system
US7299314B2 (en) * 2003-12-31 2007-11-20 Sandisk Corporation Flash storage system with write/erase abort detection mechanism
JP2007041798A (ja) * 2005-08-02 2007-02-15 Seiko Epson Corp 情報処理装置及び情報処理装置のメモリ書き換え方法
CN100456253C (zh) * 2005-12-28 2009-01-28 英业达股份有限公司 存储系统的高速缓存数据的保护方法
WO2009028298A1 (ja) 2007-08-31 2009-03-05 Tokyo Institute Of Technology スピン注入磁化反転ｍｔｊを用いた不揮発性ｓｒａｍ／ラッチ回路
JP5142685B2 (ja) * 2007-11-29 2013-02-13 株式会社東芝 メモリシステム
JP5579431B2 (ja) * 2009-12-28 2014-08-27 株式会社日立製作所 ソリッド・ステート・ドライブ装置および平準化管理情報の退避・回復方法
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Also Published As

Publication number Publication date
JP2013114441A (ja) 2013-06-10
CN103136119A (zh) 2013-06-05
US9251057B2 (en) 2016-02-02
CN103136119B (zh) 2017-09-22
US20130139007A1 (en) 2013-05-30

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