JP5785643B1 - Active cable and control method of active cable - Google Patents

Abstract

To provide a signal generation device that can cope with input from various external devices and that can be reduced in size and cost. The signal generation apparatus includes a PLL circuit and a control circuit that controls the PLL circuit, and the PLL circuit can change an operation band by changing a parameter setting. When locked, an output clock signal corresponding to the input clock signal to the PLL circuit is generated, and the control circuit sequentially changes the parameter settings until the PLL circuit is locked. [Selection] Figure 4

Description

  The present invention relates to a signal generation apparatus using a PLL circuit.

  2. Description of the Related Art A PLL (Phase Looked Loop) circuit that generates an output clock signal corresponding to an input clock signal is widely used in devices that handle image signals from external devices (for example, the transmission device of Patent Document 1).

JP 2012-60522 A (published March 22, 2012)

  The PLL circuit as described above is required to be compatible with input signals of various external devices (cameras and the like). On the other hand, a configuration is possible in which the operation band of the PLL circuit is made variable and the input (frequency, etc.) from the external device is determined to set the operation band of the PLL circuit, but the input from the external device is determined. Circuit or the like is required, which increases the size and cost.

  The present invention provides a signal generation device that can cope with inputs from various external devices and that can be reduced in size and cost.

  A signal generation device according to the present invention includes a PLL circuit and a control circuit that controls the PLL circuit. The PLL circuit can change an operation band by changing a parameter setting, and locks in each operation band. Then, an output clock signal corresponding to an input clock signal to the PLL circuit is generated, and the control circuit sequentially changes the parameter setting until the PLL circuit is locked.

  In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the parameter settings, and the PLL circuit is locked. In other words, an output clock signal corresponding to the input clock signal can be obtained in setting parameters that match the input clock signal from the outside to the PLL circuit and the operating band.

  This eliminates the need for a circuit for determining the input from the outside, and can realize a signal generation device that can cope with various external inputs and that can be reduced in size and cost.

  In this signal generation device, it is desirable that the assumed frequency band of the input clock signal be covered by a plurality of changeable operation bands.

  For example, the input clock signal of the camera link standard is 20 to 85 MHz, and this is covered by a plurality of operation bands, so that various input clock signals according to the standard can be supported.

  In this signal generation device, the output clock signal may be configured such that jitter of the input clock signal is removed.

  Since the PLL circuit has a jitter removal function by adjusting circuit characteristics (for example, a time constant), the signal generation device having the above configuration can be used as a jitter removal device that can handle various input clock signals.

  In the present signal generation device, the PLL circuit may include a plurality of frequency dividers, and the parameter may be a combination of frequency division ratios of these frequency dividers.

  Thus, the operation band of the PLL circuit can be easily changed by combining the above parameters with the division ratio.

  In this signal generation device, the control circuit may be configured to perform setting in the order of parameters having a large number of locks in the past.

  In this way, the time required for parameter setting can be shortened.

  In this signal generation device, the control circuit may be configured to determine whether it is necessary to set each parameter based on information previously added to each parameter.

  By doing this, it is possible to reduce the time required for setting while suppressing the use of the memory of the control circuit.

  The active cable includes a transmission unit, a cable, and a reception unit connected to the transmission unit via the cable, and at least one of the transmission unit and the reception unit includes the signal generation device. Features.

  Since various clock signals are input to the active cable, the signal generation device can be preferably used.

  In the present active cable, the transmission unit includes the signal generation device, the reception unit includes a PLL circuit different from the PLL circuit of the signal generation device, and the other PLL circuit included in the reception unit. The lock state is notified to the transmission unit, and the control circuit of the signal generation device included in the transmission unit determines whether to reset the parameter setting of the PLL circuit of the signal generation device based on the notified lock state It can also be set as the structure which judges.

  According to the above configuration, it is possible to set the parameters of the PLL circuit of the transmission unit even for an abnormality on the reception unit side such as the reception unit being unlocked.

  In this active cable, the transmitter includes the signal generator, and the receiver includes a PLL circuit that can change the operation band by changing the parameter settings, different from the PLL circuit of the signal generator. Then, the control circuit of the signal generation device included in the transmission unit notifies the reception unit of the parameter locked by the PLL circuit of the signal generation device, and is included in the reception unit based on the notified parameter. It is also possible to adopt a configuration in which the setting of the other PLL circuit is performed.

  According to the above configuration, setting of the PLL circuit on the receiving side is not necessary on the receiving side, so that the processing speed on the receiving side is increased.

  It is desirable that this active cable conforms to the Camera Link (registered trademark) standard (hereinafter referred to as “camera link standard”). In the camera link standard, the frequency range of the clock signal from the camera is determined, and the frequency varies depending on the camera. According to the signal generation device of this active cable, the range of the input frequency of the camera link standard can be covered by a plurality of changeable operation bands, and it can be applied to various cameras.

  In addition, the camera link standard has no jitter restriction, and the input from the camera may include a large jitter. Since the signal generation apparatus of the present active cable can be provided with a jitter removal function, appropriate signal transmission is possible even when a large jitter is included in the input from the camera.

  This signal generation method is a signal generation method using a PLL circuit that can change an operation band by changing parameter settings and generates an output clock signal corresponding to an input clock signal when locked in each operation band. The parameter setting is sequentially changed until the PLL circuit is locked.

  In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the parameter settings, and the PLL circuit is locked. That is, in the setting of parameters that match the input clock signal from the outside to the PLL circuit and the operating band of the PLL circuit, an output clock signal corresponding to the input clock signal can be obtained.

  This eliminates the need for a circuit for determining the input from the outside, and can realize a signal generation device that can cope with various external inputs and that can be reduced in size and cost.

  ADVANTAGE OF THE INVENTION According to this invention, the signal production | generation apparatus which can respond to the input of various external apparatuses and can suppress size and cost is realizable.

1 is a block diagram showing a configuration of a transmission device according to a first exemplary embodiment; It is a block diagram which shows the structure of a 1st jitter cleaner. It is a table | surface which shows the specific example of a parameter. 6 is a flowchart showing optimization processing of the first jitter cleaner according to the first exemplary embodiment. 10 is a flowchart showing optimization processing of the first jitter cleaner according to the second exemplary embodiment. 10 is a flowchart showing optimization processing of the first jitter cleaner according to the third embodiment. 10 is a flowchart illustrating another example of the optimization process of the first jitter cleaner according to the third embodiment. FIG. 6 is a block diagram illustrating a configuration of an active optical cable according to a fourth embodiment. 10 is a flowchart showing whether or not optimization processing according to a fourth embodiment is necessary. FIG. 10 is a block diagram illustrating a configuration of an active optical cable according to a fifth embodiment. 10 is a flowchart showing optimization processing according to the sixth embodiment;

  The embodiment of the present invention will be described below with reference to FIGS.

[Embodiment 1]
1 is a block diagram showing a configuration of a transmission apparatus according to Embodiment 1. FIG. As shown in FIG. 1, the transmission apparatus 1 includes a transmission unit 10 (for example, a camera-side connector) connected to a transmission source device 2 (for example, a camera or a camera board mounted on the camera), and a transmission destination device 3 ( For example, a receiving unit 20 (for example, a grabber-side connector) connected to a grabber or a grabber board mounted on the grabber and a cable 30 connecting the transmitting unit 10 and the receiving unit 20 are provided, and the transmission device 1 is an active cable. Function.

  Here, the active cable refers to a cable including an active element (an element that operates by power supplied from the outside). Examples of active elements include parallel (P) / serial (S) conversion circuit (serializer), serial (S) / parallel (P) conversion circuit (deserializer), electrical / optical (E / O) conversion circuit, optical / optical An electric (O / E) conversion circuit is exemplified. In the transmission apparatus 1, the transmission unit 10 and the reception unit 20 include active elements.

  The transmitter 10 includes a transmitter 11, a first jitter cleaner 12, and a first processor 13 (control circuit) that controls the transmitter 11 and the first jitter cleaner 12. One processor 13 constitutes a signal generation device having a jitter removal function. The receiving unit 20 includes a receiver 21, a second jitter cleaner 22, and a second processor 23 that controls the receiver 21 and the second jitter cleaner 22. The second jitter cleaner 22 and the second processor Reference numeral 23 constitutes a signal generation device having a jitter removal function.

  The transmitter 11 receives the data signal X from the transmission source device 2, and the first jitter cleaner 12 receives the clock signal ck 1 from the transmission source device 2. The first jitter cleaner 12 outputs the clock signal CK1 from which the jitter of the clock signal ck1 has been removed under the control of the first processor 13 to the transmitter 11. The transmitter 11 generates a transmission signal TS from the clock signal CK1 and the data signal X, and outputs the transmission signal TS to the transmission path in the cable 30.

  The receiver 21 generates a data signal X and a clock signal ck2 from the transmission signal TS received from the transmission path, outputs the data signal X to the transmission destination device 3, and outputs the clock signal ck2 to the second jitter cleaner 22. The second jitter cleaner 22 outputs a clock signal CK <b> 2 from which the jitter of the clock signal ck <b> 2 has been removed under the control of the second processor 23 to the transmission destination device 3.

  The configuration of the first jitter cleaner 12 of the transmitter 10 is shown in FIG. As shown in FIG. 2, the first jitter cleaner 12 includes a PLL circuit 40, a register 50, a lock detection circuit 60, and a lock detection pin 70 (abbreviated as LD as appropriate). The PLL circuit 40 includes a first divider circuit (1 / A divider circuit) 41, a second divider circuit (1 / B divider circuit) 42, a third divider circuit (1 / C divider circuit) 43, A fourth frequency dividing circuit (1 / D frequency dividing circuit) 44, a phase comparator 45, a loop filter 46, and a VCO 47 (voltage controlled oscillation circuit) are provided.

  The first frequency dividing circuit 41 is a variable frequency dividing circuit that uses the value A written in the register 50 as a frequency dividing ratio, and the second frequency dividing circuit 42 uses the value B written in the register 50. A frequency dividing circuit having a variable frequency dividing ratio, and a third frequency dividing circuit 43 is a frequency dividing circuit having a variable frequency dividing ratio having a value C written in the register 50 as a frequency dividing ratio. The divide-by-4 circuit 44 is a divide-by-variable divider circuit that uses a value D written in the register 50 as a divide ratio.

  The first frequency dividing circuit 41 outputs a clock signal having a frequency that is 1 / A times the clock signal ck <b> 1 input from the transmission source device 2 to the phase comparator 45. The second frequency divider circuit 42 outputs a clock signal having a frequency that is 1 / B times the clock signal input from the third frequency divider circuit 43 to the phase comparator 45. The phase comparator 45 is a phase difference signal having a value proportional to the phase difference between the clock signal output from the first frequency divider circuit 41 and the clock signal output from the second frequency divider circuit 42 (specifically, A voltage signal whose voltage is proportional to the phase difference). The phase difference signal generated by the phase comparator 45 is smoothed by the loop filter 46 and then input to the VCO 47. The VCO 47 outputs a clock signal having a frequency proportional to the value of the smoothed phase difference signal to the third frequency dividing circuit 43. The third frequency divider 43 outputs a clock signal having a frequency that is 1 / C times that of the clock signal input from the VCO 47 to the second frequency divider 42. The fourth frequency dividing circuit 44 outputs to the transmitter 11 a clock signal CK1 having a frequency that is 1 / D times the frequency of the clock signal input from the third frequency dividing circuit 43.

  As described above, the PLL circuit 40 includes a negative feedback circuit that sets the phase difference (frequency difference) between the clock signal output from the first frequency divider circuit 41 and the clock signal output from the second frequency divider circuit 42 to zero. It is configured. Therefore, if the frequency of the clock signal ck1 input to the first frequency dividing circuit 41 is Fck1, and the frequency of the clock signal output from the VCO 47 is Fvco, if the input clock signal ck1 is an operating band, Fck1 It operates so that / A = Fvco / (B × C). That is, if the frequency division ratios A, B, and D are set so as to satisfy B = A × D in each operation band, the frequency FCK1 = Fvco / (C × D of the clock signal CK1 output from the PLL circuit 40. ) Matches the frequency Fck1 of the clock signal ck1 input to the PLL circuit 40 (the PLL circuit 40 is locked).

  Here, if the band of the loop filter 46 is narrowed to increase the time constant, the fluctuation (jitter) of the clock signal ck1 input to the PLL circuit 40 is not included in the clock signal CK1 output from the PLL circuit 40. It becomes like this. That is, it is possible to remove jitter included in the clock signal ck1.

  The first jitter cleaner 12 is provided with a lock detection circuit 60 connected to the phase comparator 45 and a lock detection pin (LD pin) 70 connected to the lock detection circuit 60, and the lock detection circuit 60 is connected to the PLL. When the lock completion of the circuit 40 is detected, the output of the lock detection pin 70 rises from “Low (0)” to “High (1)”.

  Further, switching of the operation band of the PLL circuit 40 is realized by rewriting the frequency division ratios A, B, C, and D written in the register 50. As shown in FIG. 3, there are eleven parameters (setting numbers 1 to 11) that are combinations of the frequency division ratios A, B, C, and D, and a memory (for example, an EEPROM (registered trademark)) built in the first processor 13. )).

  For example, the parameter of setting number 1 (A = 100, B = 5000, C = 2, D = 50) corresponds to the input clock frequency 19-21 (MHz), and the parameter of setting number 2 (A = 100, B = 4200, C = 2, D = 50) corresponds to the input clock frequency 22-25 (MHz), and the parameters of setting number 11 (A = 200, B = 2400, C = 2, D = 12) are This corresponds to an input clock frequency of 78-90 (MHz). The input clock signal of 19 to 90 MHz is covered by the 11 sets of parameters shown in FIG. 3, and the camera link standard input frequency (20 to 85 MHz) can be supported.

  The process of adapting the operating band of the PLL circuit 40 of the first jitter cleaner 12 to the frequency of the clock signal ck1 from the transmission source device 2 (hereinafter referred to as optimization process) is performed as shown in FIG.

  The first processor 13 reads the parameter of the setting number i (see FIG. 3) = 1 from the memory (S1), and writes A = 100, B = 5000, C = 2, and D = 50 into the register 50 (S2). . Next, the first processor 13 reads the output of the LD pin 70 of the first jitter cleaner 12 n times (S3), determines whether it is “High” n times continuously (S4), and continues n times. If it is “High” (Yes), the optimization process is completed, and if it is “Low” even once among n times (No), the process returns to S1 and the register 50 stores A = 100, B = 4200, C = 2, and D = 42 are written (S2). Next, the first processor 13 reads the output of the LD pin 70 n times (S3), determines whether it is “High” for n times continuously (S4), and becomes “High” for n times continuously. If it is (Yes), it is determined that the PLL circuit 40 is normally locked, and the optimization process is completed. If it is “Low” even once among n times (No), the process returns to S1. The parameter of setting number i (see FIG. 3) = 3 is read from the memory (S1) and written to the register 50 (S2). This is repeated until i = 11. By this optimization processing, the clock signal CK1 obtained by removing the jitter of the clock signal ck1 can be output to the transmitter 11. Note that the output of the LD pin 70 is read n times (n is an integer equal to or greater than 2, for example, 1000). In one read, the first processor 13 erroneously detects the output of the LD pin 70, or the parameter This is because the LD pin 70 may erroneously output “High” immediately after the setting is switched. Therefore, the first processor 13 determines that the PLL circuit 40 is locked when the output of the LD pin 70 becomes “High” continuously n times in the optimization process.

  When the optimization process is completed, the first processor 13 enters a steady state and repeatedly executes the optimization process at regular intervals. That is, the output of the LD pin 70 is confirmed at regular intervals. When “L (0)”, the frequency of the input clock signal from the transmission source device 2 has been changed, or the clock signal input from the transmission source device 2 has been changed. Therefore, the optimization process is executed again.

  If the optimization process is not completed even if all parameters are set up to i = 11, the clock signal from the transmission source device 2 is not input or the clock signal from the transmission source device 2 is not input. It is determined that the frequency is out of specification, and the optimization process is repeated until a normal clock signal is input.

  The second jitter cleaner 23 of the receiving unit 20 has the same configuration as that of the first jitter cleaner 12, and a process for adjusting the operating band of the PLL circuit of the second jitter cleaner 23 to the frequency of the clock signal ck 2 from the receiver 21 (optimum). The second processor 23 performs the conversion processing) independently from the transmission unit 10. The optimization process performed by the second processor 23 is the same as that performed by the first processor 13 as shown in FIG. 4, and the clock signal CK2 obtained by removing the jitter of the clock signal ck2 is transmitted by this optimization process. It can be output to the destination device 3.

  In FIG. 1, the first jitter cleaner 12 is provided in the transmission unit 10 and the second jitter cleaner 22 is provided in the reception unit 20, but this is not a limitation. A configuration in which only the first jitter cleaner 12 is provided (the second jitter cleaner 22 is not provided) is possible, and conversely, a configuration in which only the second jitter cleaner 22 is provided (the first jitter cleaner 12 is not provided) is also possible. However, in the case where the main purpose is to remove the jitter of the clock signal ck1 from the transmission source device 2, it is conceivable that only the first jitter cleaner 12 of the transmission unit 10 is provided. This is because if the jitter of the clock signal ck1 is removed by the first jitter cleaner 12, the jitter is not included in the clock signal CK2 to the transmission destination device 3 unless the jitter is added in the transmission apparatus 1.

  According to the first embodiment, a circuit for determining the frequency of an input clock signal from a camera or the like, for example, an FPGA (Field Programmable Gate Array) or the like is not required, that is, the size and cost are increased. Therefore, it is possible to realize a transmission apparatus having a jitter removal function that can cope with various input clock signals.

  A conventional active cable having no jitter removal function is also provided with a processor for controlling the signal conversion circuit and transmitting / receiving the internal link signal. Therefore, an active cable (transmission apparatus 1) having a jitter removal function can be realized by providing a jitter cleaner in a conventional active cable and providing the processor with the optimization processing function shown in FIG. As described above, in the first embodiment, it is not necessary to add any parts other than the jitter cleaner, so that a significant increase in the size and cost of the active cable (particularly the connector portion) can be avoided.

  In the camera link standard, the frequency (input frequency) of the clock signal from the camera is defined in a range (20 to 85 MHz), and the frequency of the clock signal from the camera can take any value within this range. Also, there is no restriction on the jitter of the clock signal from the camera (a camera with a large jitter of about ± 1.6% may not be able to properly transmit signals with a conventional active cable having no jitter removal function). In this regard, the transmission apparatus 1 has a jitter removal function (for example, reduces jitter to within ± 1.0%) that covers the range of the input frequency of the camera link standard by 11 operation bands that can be changed. As described above, since the size of the connector portion is also suppressed, it can be said that it is suitable as an active cable of the camera link standard.

[Embodiment 2]
The optimization process in Embodiment 1 can also be performed as shown in FIG. That is, the first processor 13 reads the parameter setting history from the built-in memory (S11), rearranges the parameters in the order of the highest number of settings, sets the parameter with the highest number of settings to the setting number i = 1, and the parameter with the lowest number of settings. Is set number i = 11 (S12).

  Then, the parameter with the setting number i (see FIG. 3) = 1 is read (S13) and written to the register 50 (S14). Next, the first processor 13 reads the output of the LD pin 70 of the first jitter cleaner 12 n times (S15), determines whether it is “High” n times continuously (S16), and continues n times. If it is “High” (Yes), the parameter set this time is stored in the memory as a history (S17), and the optimization process is completed. If at least one of n times is “Low” in step S16 (No), the process returns to S13 to read the parameter of the setting number i = 2 from the memory and write it to the register 50 (S14). This is repeated until i = 11.

  According to the second embodiment, when the cameras to be connected are the same, the time required for optimization can be shortened.

[Embodiment 3]
The optimization processing in Embodiment 1 can also be performed as shown in FIG. Here, a valid or invalid flag is added in advance to each of the 11 sets of parameters. The addition of the flag may be performed before passing to the user (manufacturing stage) or may be performed by the user. Further, it may be performed based on information from the transmission source device 2. The first processor 13 reads the parameter of the setting number i from the memory (S21), and determines whether the flag is valid or invalid (S22). If invalid, the process returns to S21, the parameter of the setting number (i + 1) is read, and the validity / invalidity of the flag is determined (S22). If it is valid in step S22, the first processor 13 writes the parameter into the register 50 (S23), then reads the output of the LD pin 70 of the first jitter cleaner 12 n times (S24), continuously n times. It is determined whether or not it is “High” (S25). The first processor 13 completes the optimization process if it is “High” n times continuously in step S25 (Yes), and if it is “Low” even once in n times, the first processor 13 performs step S21. Return to. This is repeated until i = 11.

  The optimization processing in Embodiment 1 can also be performed as shown in FIG. Here, a valid or invalid flag is added in advance to each of the 11 sets of parameters. The validity / invalidity determination is determined based on information from the transmission source device 2, for example. The first processor 13 reads the parameter setting history from the built-in memory (S31), rearranges the parameters in the order of the highest number of settings, sets the parameter with the highest number of settings, setting number i = 1, and sets the parameter with the lowest number of settings. The number i is set to 11 (S32).

  Then, the parameter with the setting number i (see FIG. 3) = 1 is read (S33), and the validity / invalidity of the flag is determined (S34). If invalid, the process returns to S33, the parameter of the setting number (i + 1) is read, and the validity / invalidity of the flag is determined (S34). If valid in step S34, the first processor 13 writes the parameter in the register 50 (S35). Next, the first processor 13 reads the output of the LD pin 70 of the first jitter cleaner 12 n times (S36), determines whether it is “High” n times continuously (S37), and continues n times. If it is “High” (Yes), the parameter set this time is stored in the memory as a history (S38), and the optimization process is completed. If at least one of the n times is “Low” in step S37 (No), the process returns to step S33. This is repeated until i = 11.

  According to the third embodiment, it is possible to reduce the time required for optimization while suppressing the use of the memory of the first processor 13.

[Embodiment 4]
FIG. 8 shows a configuration example when this transmission apparatus is applied to an optical camera link cable (an active optical cable conforming to the camera link standard). As shown in FIG. 8, the optical camera link cable 101 connects the camera side connector 110 connected to the camera, the grabber side connector 120 connected to the frame grabber board 103, and the camera side connector 110 and the grabber side connector 120. Cable 130 to be provided.

  The cable 130 includes an optical signal transmission path (optical fiber) 131, an internal link signal transmission path 132, a control signal (CC1 to CC4) transmission path 133, and an upstream and downstream serial signal transmission path 134. The internal link signal is a signal representing internal control information other than the control signals (CC1 to CC4) defined by the camera link standard.

  The camera-side connector 110 includes a serializer 111, a first jitter cleaner 12, and a first processor 13 (control circuit) that controls the serializer 111 and the first jitter cleaner 12. The processor 13 constitutes a signal generation device having a jitter removal function. The grabber-side connector 120 includes a deserializer 121 and a second processor 24 that controls the deserializer 121.

  Data signals x0 to x3 (parallel signals) are input from the camera 102 to the serializer 111, and a clock signal ck1 is input from the camera 102 to the first jitter cleaner 12. Here, the first jitter cleaner 12 outputs the clock signal CK1 from which the jitter of the clock signal ck1 has been removed under the control of the first processor 13 to the serializer 111. This process is realized by the optimization process described in the first to third embodiments.

  The serializer 111 generates an optical signal (serial signal) from the clock signal CK1 and the data signals x0 to x3 (parallel signal), and outputs the optical signal to the optical signal transmission path (optical fiber) 131 in the cable 130.

  The deserializer 121 generates data signals x0 to x3 and a clock signal CK2 from the optical signal received from the optical signal transmission path 131 in the cable 130, and outputs them to the frame grabber board 103.

  The deserializer 121 is provided with a PLL circuit (not shown) that generates the clock signal CK2, and a lock detection pin (LD) that outputs a lock state of the PLL circuit. The second processor 24 reads the output of the lock detection pin (LD) of the deserializer 121 and notifies the lock state of the PLL circuit to the first processor 13 via the internal link signal transmission path 132. A configuration in which the first processor 13 reads the output of the lock detection pin (LD) of the deserializer 121 via the internal link signal transmission path 132 and the second processor 24 is also possible.

  In the steady state after the optimization process, the first processor 13 determines whether the optimization process is necessary in consideration of the lock state of the PLL circuit of the deserializer 121. That is, as shown in FIG. 9, the output of the LD pin 70 of the first jitter cleaner 12 is confirmed (S41). If it is “H” (Yes), the process proceeds to step S42, and if it is “L” (No) ), It is determined that the optimization process of the first jitter cleaner 12 is necessary, and the optimization process is performed (S43). In step S42, it is determined whether the PLL circuit of the deserializer 121 is locked. If the PLL circuit is locked (Yes), it is determined that the optimization processing of the first jitter cleaner 12 is unnecessary, and if it is not locked (No), It is determined that the first jitter cleaner 12 needs to be optimized (S43).

  According to the fourth embodiment, it is possible to perform the optimization process of the first jitter cleaner 12 of the camera-side connector 110 even for an abnormality of the grabber-side connector 120 such as the PLL circuit of the deserializer 121 being unlocked. .

[Embodiment 5]
FIG. 10 shows another configuration example when this transmission apparatus is applied to an optical camera link cable. As shown in FIG. 10, the optical camera link cable 101 connects a camera side connector 110 connected to the camera, a grabber side connector 120 connected to the frame grabber board 103, and the camera side connector 110 and the grabber side connector 120. Cable 130 to be provided.

  The cable 130 includes an optical signal transmission path (optical fiber) 131, an internal link signal transmission path 132, a control signal (CC1 to CC4) transmission path 133, and an upstream and downstream serial signal transmission path 134.

  The camera-side connector 110 includes a serializer 111, a first jitter cleaner 12, and a first processor 13 (control circuit) that controls the serializer 111 and the first jitter cleaner 12. The processor 13 constitutes a signal generation device having a jitter removal function.

  The grabber connector 120 includes a deserializer 121, a second jitter cleaner 22, and a second processor 23 (control circuit) that controls the deserializer 121 and the second jitter cleaner 22. The processor 23 constitutes a signal generation apparatus having a jitter removal function.

  Data signals x0 to x3 (parallel signals) are input from the camera 102 to the serializer 111, and a clock signal ck1 is input from the camera 102 to the first jitter cleaner 12. Here, the first jitter cleaner 12 outputs the clock signal CK1 from which the jitter of the clock signal ck1 has been removed under the control of the first processor 13 to the serializer 111. This process is realized by the optimization process described in the first to third embodiments.

  The serializer 111 generates an optical signal (serial signal) from the clock signal CK1 and the data signals x0 to x3 (parallel signal), and outputs the optical signal to the optical signal transmission path (optical fiber) 131 in the cable 130.

  The deserializer 121 generates the data signals x0 to x3 and the clock signal ck2 from the optical signal received from the optical signal transmission path 131 in the cable 130, outputs the data signals x0 to x3 to the frame grabber board 103, and outputs the clock signal ck2 Output to the second jitter cleaner 22. The second jitter cleaner 22 outputs a clock signal CK <b> 2 from which the jitter of the clock signal ck <b> 2 has been removed under the control of the second processor 23 to the frame grabber board 103.

  Here, the first processor 13 notifies the second processor 23 of the parameters set in the optimization processing of the first jitter cleaner 12 via the internal link signal transmission path 132. The second processor 23 By setting the notified parameter in the second jitter cleaner 22, the clock signal CK2 from which the jitter of the clock signal ck2 has been removed is generated.

  The grabber connector 120 is provided with a jitter cleaner that generates a clock signal having a frequency different from that of the first jitter cleaner 12 provided in the camera connector 110 (the operation band can be changed by changing parameter settings). In some cases, the operating band of the jitter cleaner is changed. Here, the different frequencies are, for example, (N / M) times (N and M are integers) times CK1 generated by the first jitter cleaner 12 (N and M are grabber side connectors 120 or camera side connectors). 110 is determined by a frequency dividing circuit, a frequency multiplying circuit, etc., and is finally multiplied by (M / N) and output to the grabber as CK2 having the same frequency as CK1). In this case, the second processor 23 sets a parameter determined based on the parameter notified from the first processor 13 (a parameter different from the parameter set in the first jitter cleaner 12) in this jitter cleaner. Thus, a clock signal from which jitter has been removed is also generated from this jitter cleaner.

  According to the fourth embodiment, optimization processing on the grabber side is unnecessary on the grabber side, so that the processing speed on the grabber side is increased.

[Embodiment 6]
In each of the above embodiments, the optimization process is performed for the purpose of removing jitter, but the present invention is not limited to this. For example, when the serializer 111 in FIGS. 8 and 10 is provided with a PLL circuit whose operation band can be changed by setting a parameter in the register and an LD pin that outputs the presence or absence of the lock, the PLL circuit of the serializer 111 For the purpose of adapting the operating band to the clock signal ck1 input from the camera, the optimization process of FIG. 11 can be performed.

  That is, the first processor 13 reads the parameter of the setting number i (see FIG. 3) = 1 from the memory (S1), and writes A = 100, B = 5000, C = 2, and D = 50 in the register 50 ( S2). Next, the first processor 13 reads the output of the LD pin of the serializer 111 n times (S3), determines whether it is “High” n times continuously (S4), and “High” n times continuously. If it is (Yes), the optimization process is completed, and if it is “Low” even once in n times (No), the process returns to S1, and A = 100, B = 4200 in the register. , C = 2, and D = 42 are written (S2). Next, the first processor 13 reads the output of the LD pin of the serializer 111 n times (S3), determines whether it is “High” n times continuously (S4), and “High” n times continuously. If it is (Yes), the optimization process is completed, and if it is “Low” even once in n times (No), the process returns to S1 and the setting number i (see FIG. 3) = 3 parameter is read (S1) and written to the register (S2). This is repeated until i = 11. By this optimization processing, the operation band of the PLL circuit of the serializer 111 can be adapted to the clock signal ck1 input from the camera.

  The present invention can be applied to a transmission system (for example, camera link) using a clock signal.

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 2 Transmission source device 3 Transmission destination device 10 Transmission part 11 Transmitter 12 1st jitter cleaner 13 1st processor (control circuit)
DESCRIPTION OF SYMBOLS 20 Receiver 21 Receiver 22 2nd jitter cleaner 23 2nd processor 40 PLL circuit

Claims (10)

An active cable comprising a transmitter, a cable, and a receiver connected to the transmitter via the cable,
The transmission unit is provided with a signal generation device,
The signal generation device includes a first PLL circuit and a control circuit that controls the first PLL circuit,
The first PLL circuit can change an operation band by changing a parameter setting, and generates an output clock signal corresponding to an input clock signal to the first PLL circuit when locked in each operation band. The control circuit sequentially changes the setting of the parameter until the first PLL circuit is locked ,
The receiver includes a second PLL circuit different from the first PLL circuit,
The lock state of the second PLL circuit is notified to the transmission unit, and the control circuit determines whether to reset the parameter setting of the first PLL circuit based on the notified lock state . Active cable . The active cable according to claim 1, wherein an assumed frequency band of the input clock signal is covered by a plurality of changeable operation bands. The active cable according to claim 1, wherein jitter of the input clock signal is removed from the output clock signal. 4. The active cable according to claim 1, wherein the first PLL circuit includes a plurality of frequency dividers, and the parameter is a combination of frequency division ratios of the frequency dividers. . The active cable according to any one of claims 1 to 4, wherein the control circuit performs setting in the order of parameters having a large number of locks in the past. The active cable according to claim 1, wherein the control circuit determines whether or not each parameter needs to be set based on information added in advance to each parameter. An active cable comprising a transmitter, a cable, and a receiver connected to the transmitter via the cable,
The transmission unit is provided with a signal generation device,
The signal generation device includes a first PLL circuit and a control circuit that controls the first PLL circuit,
The first PLL circuit can change an operation band by changing a parameter setting. When locked in each operation band, the first PLL circuit generates an output clock signal corresponding to an input clock signal to the first PLL circuit. The control circuit sequentially changes the setting of the parameter until the first PLL circuit is locked,
In the receiving unit, separate from the upper Symbol first 1 PLL circuit, includes first 2 PLL circuit capable of changing the operating band by the configuration change of parameters,
The control circuit, a parameter which the first 1 PLL circuit is locked and notifies the receiving unit, wherein the to luer active cable that setting of the upper Symbol first 2 PLL circuit is performed based on the transmitted parameter. The active cable according to claim 1 , wherein the active cable conforms to a camera link standard. An operation band can be changed by changing parameter settings, and a transmitter including a first PLL circuit that generates an output clock signal corresponding to an input clock signal when locked in each operation band, a cable, and a second PLL circuit And an active cable control method comprising a receiver connected to the transmitter via the cable,
The parameter setting is sequentially changed until the first PLL circuit is locked,
An active cable control method comprising: notifying the transmitter of the lock status of the second PLL circuit, and determining whether to reset the parameter setting of the first PLL circuit based on the notified lock status . Operation band can be changed by changing parameter settings, and a transmitter including a first PLL circuit that generates an output clock signal corresponding to an input clock signal when locked in each operation band, a cable, and parameter settings A control method of an active cable including a second PLL circuit capable of changing an operation band by change and including a receiving unit connected to the transmitting unit via the cable,
The parameter setting is sequentially changed until the first PLL circuit is locked,
An active cable control method comprising: notifying a parameter locked by the first PLL circuit to the receiving unit; and setting the second PLL circuit based on the notified parameter.

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