KR101619506B1 - Signal generating device, active cable, and method for signal generating - Google Patents

Signal generating device, active cable, and method for signal generating Download PDF

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Publication number
KR101619506B1
KR101619506B1 KR1020150099052A KR20150099052A KR101619506B1 KR 101619506 B1 KR101619506 B1 KR 101619506B1 KR 1020150099052 A KR1020150099052 A KR 1020150099052A KR 20150099052 A KR20150099052 A KR 20150099052A KR 101619506 B1 KR101619506 B1 KR 101619506B1
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pll circuit
clock signal
parameter
circuit
cable
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KR1020150099052A
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Korean (ko)
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KR20160008973A (en
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마모루 오타케
카즈요시 타케시타
요시노리 아라이
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가부시키가이샤후지쿠라
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/077—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal

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  • Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Studio Devices (AREA)

Abstract

The present signal generating apparatus includes a PLL circuit and a control circuit for controlling the PLL circuit. The PLL circuit is capable of changing the operation band in accordance with the setting change of the parameter. When locked in each operation band, Generates an output clock signal in accordance with the input clock signal, and the control circuit sequentially changes the setting of the parameter until the PLL circuit is locked.

Description

Technical Field [0001] The present invention relates to a signal generating device, an active cable, and a signal generating method,

The present invention relates to a signal generating apparatus using a PLL circuit.

2. Description of the Related Art A PLL (Phase Looked Loop) circuit for generating an output clock signal in accordance with an input clock signal is widely used in an apparatus (for example, a transmission apparatus of Patent Document 1) that handles an image signal from an external device.

Japanese Patent Laid-Open Publication No. 2012-60522 (published on March 22, 2012)

The PLL circuit as described above is required to be capable of responding to input signals of various external apparatuses (cameras, etc.). On the other hand, it is possible to consider a configuration in which the operating band of the PLL circuit is varied to determine the input (frequency and the like) from the external device to set the operating band of the PLL circuit, but a circuit for determining input from the external device Resulting in an increase in size and cost.

The present invention provides a signal generating apparatus capable of coping with input of various external apparatuses and capable of suppressing size and cost.

The signal generating apparatus according to the present invention includes a PLL circuit and a control circuit for controlling the PLL circuit. The PLL circuit is capable of changing an operation band according to a parameter setting change, The control circuit generates an output clock signal corresponding to an input clock signal to the PLL circuit, and the control circuit sequentially changes the setting of the parameter until the PLL circuit is locked.

In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the setting of the parameters, and the PLL circuit is locked. That is, an output clock signal according to this input clock signal can be obtained in the setting of a parameter suitable for the input clock signal and the operating band from the outside to the PLL circuit. This makes it unnecessary to provide a circuit for judging an input from the outside, and it is possible to realize a signal generating apparatus capable of coping with various inputs from outside, and capable of suppressing size and cost.

1 is a block diagram showing a configuration of a transmission apparatus according to the first embodiment.
2 is a block diagram showing a configuration of a first jitter cleaner.
3 is a table showing a specific example of the parameter.
4 is a flowchart showing optimization processing of the first jitter cleaner according to the first embodiment.
5 is a flowchart showing an optimization process of the first jitter cleaner according to the second embodiment.
6 is a flowchart showing optimization processing of the first jitter cleaner according to the third embodiment.
7 is a flowchart showing another example of the optimization processing of the first jitter cleaner according to the third embodiment.
8 is a block diagram showing a configuration of an active optical cable according to the fourth embodiment.
9 is a flowchart showing the determination as to whether or not the optimization processing according to the fourth embodiment is necessary.
10 is a block diagram showing the configuration of the active optical cable according to the fifth embodiment.
11 is a flowchart showing an optimization process according to the sixth embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to Figs. 1 to 11. Fig.

[Embodiment 1]

1 is a block diagram showing a configuration of a transmission apparatus according to the first embodiment. 1, the transmission apparatus 1 includes a transmission section 10 (for example, a camera-side connector) connected to a transmission source device 2 (for example, a camera or a camera board mounted on the camera) A receiving portion 20 (for example, a grabber side connector) connected to the transfer destination device 3 (for example, a grabber mounted on a grabber or a grabber), and a cable connecting the transmitting portion 10 and the receiving portion 20 (30), and the transmission apparatus (1) functions as an active cable.

Here, the active cable refers to a cable having an active element (an element that operates by power supplied from the outside). Examples of the active element include a parallel / serial (S) conversion circuit (serializer), a serial / parallel conversion circuit (deserializer), an electric / (O / E) conversion circuit. In the transmission apparatus 1, the transmission section 10 and the reception section 20 are provided with active elements.

The transmission section 10 includes a first processor 13 (control circuit) for controlling the transmitter 11, the first jitter cleaner 12, the transmitter 11 and the first jitter cleaner 12, The one-jitter cleaner 12 and the first processor 13 constitute a signal generating apparatus having a jitter canceling function. The receiving unit 20 includes a second processor 23 for controlling the receiver 21, the second jitter cleaner 22, the receiver 21 and the second jitter cleaner 22, The second processor 22 and the second processor 23 constitute a signal generating apparatus having a jitter canceling function.

The data signal X is input from the transmission source device 2 to the transmitter 11 and the clock signal ck1 is input from the transmission source device 2 to the first jitter cleaner 12. [ The first jitter cleaner 12 outputs the clock signal CK1 to the transmitter 11 by removing the jitter of the clock signal ck1 under the control of the first processor 13. [ The transmitter 11 generates a transmission signal TS from the clock signal CK1 and the data signal X and outputs the transmission signal TS to the transmission path in the cable 30. [

The receiver 21 generates the data signal X and the clock signal ck2 from the transmission signal TS received from the transmission path and outputs the data signal X to the transfer destination device 3 and outputs the clock signal ck2 ck2 to the second jitter cleaner 22. [ The second jitter cleaner 22 outputs the clock signal CK2 obtained by removing the jitter of the clock signal ck2 to the transfer destination device 3 under the control of the second processor 23. [

The configuration of the first jitter cleaner 12 of the transmission unit 10 is shown in Fig. 2, the first jitter cleaner 12 includes a PLL circuit 40, a register 50, a lock detection circuit 60, and a lock detection pin 70 (appropriately abbreviated as LD). The PLL circuit 40 includes a first dividing circuit 41, a 1 / A dividing circuit 42, a second dividing circuit 42, a 1 / B dividing circuit, a third dividing circuit 43 A phase comparator 45, a loop filter 46, and a VCO 47 (voltage controlled oscillation circuit).

The first dividing circuit 41 is a frequency dividing circuit for dividing the value A written in the register 50 into a dividing ratio. The second dividing circuit 42 divides the value B written in the register 50, Variable dividing circuit for dividing the value C written in the register 50 into a dividing ratio and a fourth dividing circuit 44 for dividing the value C written in the register 50 into a dividing ratio variable dividing circuit, Variable dividing circuit that divides the value D written in the register 50 into division ratios.

The first frequency divider circuit 41 outputs to the phase comparator 45 a clock signal having a frequency that is one-half the frequency of the clock signal ck1 input from the transfer source device 2. [ The second frequency divider circuit 42 outputs to the phase comparator 45 a clock signal having a frequency that is one-half the frequency of the clock signal input from the third frequency divider circuit 43. The phase comparator 45 outputs a phase difference signal having a value proportional to the phase difference between the clock signal output from the first frequency divider circuit 41 and the clock signal output from the second frequency divider circuit 42 A voltage signal proportional to the phase difference). The phase difference signal generated in the phase comparator 45 is smoothed by the loop filter 46 and then input to the VCO 47. The VCO 47 outputs a clock signal having a frequency proportional to the value of the smoothed phase difference signal to the third frequency divider circuit 43. The third frequency divider circuit 43 outputs to the second frequency divider circuit 42 a clock signal having a frequency that is one Cth of the clock signal input from the VCO 47. [ The fourth frequency divider circuit 44 outputs the clock signal CK1 having the frequency one time D times the frequency of the clock signal input from the third frequency divider circuit 43 to the transmitter 11.

As described above, the PLL circuit 40 is constituted by a feedback circuit that sets the phase difference (frequency difference) between the clock signal output from the first frequency divider circuit 41 and the clock signal output from the second frequency divider circuit 42 to zero . Therefore, when the frequency of the clock signal ck1 input to the first frequency divider circuit 41 is Fck1 and the frequency of the clock signal output from the VCO 47 is Fvco, the input clock signal ck1 operates Band, it operates so that Fck1 / A = Fvco / (B x C). The frequency FCK1 = Fvco / (CxD) of the clock signal CK1 output from the PLL circuit 40 is set to be the frequency dividing ratio A, B, and D, (The PLL circuit 40 is locked) with the frequency Fck1 of the clock signal ck1 input to the PLL circuit 40. [

If the band of the loop filter 46 is narrowed and the relaxation time is increased, the jitter (jitter) of the clock signal ck1 input to the PLL circuit 40 is reduced by the clock signal CK1 output from the PLL circuit 40, . That is, it becomes possible to eliminate the jitter included in the clock signal ck1.

On the other hand, the first jitter cleaner 12 is provided with a lock detection circuit 60 connected to the phase comparator 45 and a lock detection pin 70 (LD pin) connected to the lock detection circuit 60, When the circuit 60 detects the completion of the lock of the PLL circuit 40, the output of the lock detection pin 70 is raised from "Low (0)" to "High (1)".

The switching of the operation band of the PLL circuit 40 is realized by interchanging the division ratios A, B, C, and D written in the register 50. As shown in FIG. 3, the parameter which is a combination of the division ratios A, B, C and D is 11 sets (setting numbers 1 to 11) and is a memory built in the first processor 13 (for example, EEPROM Trademark)).

For example, the parameter of the setting number 1 (A = 100, B = 5000, C = 2, D = 50) corresponds to the input clock frequency 19-21 (A = 200, B = 2400, C = 2, D = 12) corresponding to the input clock frequency 22-25 Corresponds to input clock frequency 78-90 (MHz). The input clock signal of 19 to 90 MHz is covered by the parameter of the 11th column in Fig. 3, so that it is possible to cope with the input frequency (20 to 85 MHz) of the camera link standard.

The processing of optimizing the operation band of the PLL circuit 40 of the first jitter cleaner 12 to the frequency of the clock signal ck1 from the transfer source device 2 (hereinafter, optimization processing) is performed as shown in Fig.

The first processor 13 reads a parameter of the setting number i (see FIG. 3) = 1 from the memory (S1) and writes A = 100, B = 5000, C = 2 and D = 50 in the register 50 (S2). Subsequently, the first processor 13 reads the output of the LD pin 70 of the first jitter cleaner 12 n times (S3) and determines whether or not it is "high" for n consecutive times (S4) (No), it returns to S1 and sets A = 100 and B = 4200 in the register 50. If the result of the comparison is " High " , C = 2, and D = 42 are written (S2). Next, the first processor 13 reads out the output of the LD pin 70 n times (S3) and judges whether or not it is "High" for n consecutive times (S4) (Yes), it is determined that the PLL circuit 40 is normally locked, and the optimization process is completed. If it is "Low" even once in n cycles (No), the process returns to S1 and the setting number i ) = 3 is read out (S1) and written into the register 50 (S2). Repeat this until i = 11. With this optimization processing, it is possible to output the clock signal CK1 obtained by removing the jitter of the clock signal ck1 to the transmitter 11. Fig. On the other hand, the output of the LD pin 70 is read out n times (where n is an integer equal to or more than 2, for example, 1000). The first processor 13 reads the LD pin 70, The output of the LD pin 70 may be erroneously detected or the LD pin 70 may output "High" immediately after the setting of the parameter is switched. For this reason, in the optimization processing, the first processor 13 determines that the PLL circuit 40 is locked when the output of the LD pin 70 becomes "High" for n consecutive times.

When the optimization processing is completed, the first processor 13 enters the steady state and repeatedly executes the optimization processing at regular intervals. That is, the output of the LD pin 70 is checked at regular intervals, and when the value is "L (0)", the frequency of the input clock signal from the transfer source device 2 is changed or the clock from the transfer source device 2 It is determined that the input of the signal has been cut off, and the optimization processing is executed again.

When the optimization processing is not completed even if all the parameters up to i = 11 are set, if the clock signal from the source device 2 is in the non-input state or the frequency of the clock signal from the source device 2 is outside the specification And the optimization process is repeated until a normal clock signal is input.

The second jitter cleaner 23 of the receiving section 20 has the same configuration as the first jitter cleaner 12 and the operating band of the PLL circuit of the second jitter cleaner 23 is connected to the clock signal ck2 from the receiver 21. [ (Optimization processing) in which the second processor 23 is adapted to the frequency of the second processor 23 independently from the transmission section 10. The optimization process performed by the second processor 23 is the same as that performed by the first processor 13 as shown in Fig. 4. The jitter of the clock signal ck2 is removed by this optimization processing, and the clock signal CK2 And output it to the transfer destination device 3.

1, the first jitter cleaner 12 is provided in the transmitter 10 and the second jitter cleaner 22 is provided in the receiver 20. However, the present invention is not limited to this. The first jitter cleaner 12 may be provided with only the first jitter cleaner 12 (not provided with the second jitter cleaner 22) Configuration) is also possible. However, when the main purpose is to remove the jitter of the clock signal ck1 from the transmission source device 2, it can be considered that only the first jitter cleaner 12 of the transmission section 10 is provided. When the jitter of the clock signal ck1 is removed by the first jitter cleaner 12, the jitter is not included in the clock signal CK2 to the transfer destination device 3 unless jitter is added in the transfer device 1 Because.

According to the embodiment (1), a circuit for determining the frequency or the like of an input clock signal from a camera or the like, for example, an FPGA (Field Programmable Gate Array) or the like is not required, It is possible to realize a transmission apparatus having a jitter removing function capable of coping with various input clock signals.

On the other hand, a conventional active cable not having a jitter removing function is also provided with a processor that controls the signal conversion circuit and transmits and receives an internal link signal. Therefore, it is possible to realize an active cable (transfer apparatus 1) having a jitter removing function by merely providing a jitter cleaner in a conventional active cable and having the processor have the optimization processing function shown in Fig. As described above, in the embodiment (1), since it is unnecessary to add a component other than the jitter cleaner, it is possible to avoid a significant increase in the size and cost of the active cable (particularly, the connector portion).

In the camera link standard, the frequency (input frequency) of the clock signal from the camera is specified in the range (20 to 85 MHz), and the frequency of the clock signal from the camera can take any value within this range. In addition, there is no restriction on the jitter of the clock signal from the camera. (For a camera with a large jitter of about 1.6%, proper signal transmission may not be possible with a conventional active cable having no jitter removal function.) In this respect, the transmission apparatus 1 has a jitter canceling function (for example, reducing the jitter to within ± 1.0%) covering a range of the input frequency of the camera link standard by 11 changeable operating bands, The size of the connector portion is limited as shown in Fig.

[Embodiment 2]

The optimization processing in the first embodiment may be performed as shown in Fig. That is, the first processor 13 reads the setting history of the parameters from the internal memory (S11), arranges the parameters in the order of increasing the number of times, sets the parameter having the largest setting number as the setting number i = 1, Is set to a setting number i = 11 (S12).

Then, the parameter of the setting number i (see FIG. 3) = 1 is read out (S13), and written to the register 50 (S14). Subsequently, the first processor 13 reads out the output of the LD pin 70 of the first jitter cleaner 12 n times (S15) and judges whether or not it is "High" for n consecutive times (S16 quot; High " for n consecutive times (Yes), the parameter set this time is stored as history in the memory (S17) and the optimization process is completed. (No), the process returns to S13 to read the parameter of the setting number i = 2 from the memory and write it to the register 50 (S14). Repeat this until i = 11.

According to the second embodiment, when the cameras to be connected are the same, the time required for optimization can be shortened.

[Embodiment 3]

The optimization processing in Embodiment 1 may be performed as shown in Fig. Here, valid or invalid flags are added to each of the 11 sets of parameters in advance. The addition of the flags may be performed before the transfer to the user (manufacturing step), or may be performed by the user. Further, it may be performed based on the information from the transfer source device 2. [ The first processor 13 reads the parameter of the setting number i from the memory (S21) and determines whether the flag is valid or invalid (S22). If it is invalid, the process returns to S21 to read the parameter of the setting number (i + 1) and determine whether the flag is valid or invalid (S22). If it is valid in step S22, the first processor 13 writes the parameter to the register 50 (S23), then reads the output of the LD pin 70 of the first jitter cleaner 12 n times (S24) , it is determined whether or not it is "High" for n consecutive times (S25). The first processor 13 completes the optimization processing if it is " High " for n consecutive times (Yes) in step S25, and returns to step S21 if it is " Low " Repeat this until i = 11.

The optimization processing in Embodiment 1 may be performed as shown in Fig. Here, valid or invalid flags are added to each of the 11 sets of parameters in advance. The validity / invalidity determination is determined based on information from the transfer source device 2, for example. The first processor 13 reads the setting history of the parameters from the internal memory (S31), arranges the parameters in the order of increasing the number of the settings, sets the parameter having the largest setting number as the setting number i = 1, The parameter is set to the setting number i = 11 (S32).

Then, a parameter of the setting number i (see FIG. 3) = 1 is read out (S33) and it is judged whether the flag is valid or invalid (S34). If it is invalid, the process returns to S33 to read the parameter of the setting number (i + 1) and determine whether the flag is valid or invalid (S34). If it is valid in step S34, the first processor 13 writes the parameter in the register 50 (S35). Then, the first processor 13 reads out the output of the LD pin 70 of the first jitter cleaner 12 n times (S36), judges whether or not it is " High " , and if it is " High " for n consecutive times (Yes), the parameter set this time is stored as history (S38) and the optimization process is completed. If it is "Low" even once in n times in step S37 (No), the process returns to step S33. Repeat this until i = 11.

According to the third embodiment, it is possible to shorten the time required for optimization while suppressing the use of the memory of the first processor 13. [

[Embodiment 4]

Fig. 8 shows a configuration example in a case where this transmission apparatus is applied to an optical camera link cable (active optical cable conforming to the camera link standard). 8, the optical camera link cable 101 includes a camera side connector 110 connected to the camera, a grabber side connector 120 connected to the frame grabber board 103, and a camera side connector 110, And a cable 130 connecting the grabber side connector 120. [

An optical signal transmission path 131 (optical fiber), an internal link signal transmission path 132, control signals CC1 to CC4 transmission path 133 and a rising and falling serial signal transmission path 134 are connected to the cable 130 . The internal link signal is a signal indicating internal control information other than the control signals CC1 to CC4 defined by the camera link standard.

The camera side connector 110 is provided with a first processor 13 (control circuit) for controlling the serializer 111, the first jitter cleaner 12, the serializer 111 and the first jitter cleaner 12 And the first jitter cleaner 12 and the first processor 13 constitute a signal generating apparatus having a jitter removing function. The grabber side connector 120 is provided with a deserializer 121 and a second processor 24 for controlling the deserializer 121. [

Data signals x0 to x3 (parallel signals) are input from the camera 102 to the serializer 111 and a clock signal ck1 is input from the camera 102 to the first jitter cleaner 12. [ The first jitter cleaner 12 receives the clock signal CK1 after removing the jitter of the clock signal ck1 under the control of the first processor 13 and outputs the clock signal CK1 to the serializer 111. [ This process is realized by the optimization process described in the first to third embodiments.

The serializer 111 generates an optical signal (serial signal) from the clock signal CK1 and the data signals x0 to x3 (parallel signal) and outputs it to the optical signal transmission path 131 (optical fiber) in the cable 130 .

The deserializer 121 generates data signals x0 to x3 and a clock signal CK2 from the optical signal received from the optical signal transmission path 131 in the cable 130 and outputs the data signals to the frame grabber board 103. [

The deserializer 121 is provided with a PLL circuit (not shown) for generating a clock signal CK2 and a lock detection pin LD for outputting a lock state of the PLL circuit. The second processor 24 reads the output of the lock detection pin LD of the deserializer 121 and notifies the first processor 13 of the locked state of the PLL circuit through the internal link signal transmission path 132. It is also possible that the first processor 13 reads the output of the lock detection pin LD of the deserializer 121 through the internal link signal transmission path 132 and the second processor 24.

The first processor 13 determines whether or not the optimization processing is necessary in consideration of the lock state of the PLL circuit of the deserializer 121 in the steady state after the optimization processing. 9, the output of the LD pin 70 of the first jitter cleaner 12 is checked (S41). If the result is " H " (Yes), the process proceeds to step S42, It is determined that the optimization processing of the first jitter cleaner 12 is necessary and the optimization processing is performed (S43). In step S42, it is determined whether or not the PLL circuit of the deserializer 121 is locked. If it is locked (Yes), it is determined that the optimization processing of the first jitter cleaner 12 is unnecessary. It is determined that the optimization processing of the cleaner 12 is necessary and the optimization processing is performed (S43).

According to the fourth embodiment, it is possible to optimize the first jitter cleaner 12 of the camera-side connector 110 against the abnormality of the grabber side connector 120 such as the lock of the PLL circuit of the deserializer 121 being released .

[Embodiment 5]

Fig. 10 shows another configuration example in the case where this transmission apparatus is applied to an optical camera link cable. 10, the optical camera link cable 101 includes a camera side connector 110 connected to the camera, a grabber side connector 120 connected to the frame grabber board 103, a camera side connector 110, And a cable 130 for connecting the grabber side connector 120.

An optical signal transmission line (optical fiber) 131, an internal link signal transmission path 132, control signals CC1 to CC4 transmission path 133, and a rising and falling serial signal transmission path 134 are connected to the cable 130, .

The camera side connector 110 includes a first processor 13 (control circuit) for controlling the serializer 111, the first jitter cleaner 12, the serializer 111 and the first jitter cleaner 12 And the first jitter cleaner 12 and the first processor 13 constitute a signal generating apparatus having a jitter canceling function.

The grabber side connector 120 is provided with a second processor 23 (control circuit) for controlling the deserializer 121, the second jitter cleaner 22, the deserializer 121 and the second jitter cleaner 22 The second jitter cleaner 22 and the second processor 23 constitute a signal generating apparatus having a jitter removing function.

Data signals x0 to x3 (parallel signals) are input from the camera 102 to the serializer 111 and a clock signal ck1 is input from the camera 102 to the first jitter cleaner 12. [ The first jitter cleaner 12 outputs the clock signal CK1 obtained by removing the jitter of the clock signal ck1 to the serializer 111 under the control of the first processor 13. [ This process is realized by the optimization process described in the first to third embodiments.

The serializer 111 generates an optical signal (serial signal) from the clock signal CK1 and the data signals x0 to x3 (parallel signal) and outputs the optical signal to the optical signal transmission path 131 (optical fiber) in the cable 130 .

The deserializer 121 generates the data signals x0 to x3 and the clock signal ck2 from the optical signal received from the optical signal transmission path 131 in the cable 130 and outputs the data signals x0 to x3 to the frame grabber board (Ck2) to the second jitter cleaner (22). The second jitter cleaner 22 outputs the clock signal CK2 obtained by removing the jitter of the clock signal ck2 to the frame grabber board 103 under the control of the second processor 23. [

Here, the first processor 13 notifies the second processor 23 of the parameter set in the optimization process of the first jitter cleaner 12 via the internal link signal transmission path 132, and the second processor 23 Sets the notified parameter to the second jitter cleaner 22, thereby generating the clock signal CK2 from which the jitter of the clock signal ck2 is removed.

On the other hand, in the grabber side connector 120, a jitter cleaner for generating a clock signal of a frequency different from that of the first jitter cleaner 12 provided in the camera-side connector 110 ) May be provided to change the operation band of the jitter cleaner. Here, the other frequency is, for example, a frequency of N / M times (N, M is an integer) of CK1 generated by the first jitter cleaner 12 (N and M are frequencies of the grabber side connector 120 or the camera side connector Multiplied by M / N and finally outputted as a grabber as CK2 which is the same frequency as CK1). In this case, the second processor 23 sets the parameter (which is different from the parameter set in the first jitter cleaner 12) determined on the basis of the parameter notified from the first processor 13, to the jitter cleaner , A jitter-free clock signal is generated in this jitter cleaner.

According to the fourth embodiment, since the same optimizing process as that on the camera side is not required on the grabber side, the processing speed on the grabber side can be increased.

[Embodiment 6]

In each of the above embodiments, the optimization process is performed for the purpose of jitter removal, but the present invention is not limited to this. For example, when the serializer 111 shown in FIG. 8 or 10 is provided with a PLL circuit whose operation band can be changed by setting a parameter to a register and an LD pin outputting the presence or absence of the lock, the serializer 111 11 may be performed for the purpose of matching the operating band of the PLL circuit of FIG. 11 with the clock signal ck1 input from the camera.

3) = 1 from the memory (S1), the first processor 13 reads the parameter A = 100, B = 5000, C = 2, D = 50 is written (S2). Then, the first processor 13 reads out the output of the LD pin of the serializer 111 n times (S3) and judges whether or not it is "High" for n consecutive times (S4) (No), it returns to S1 and sets A = 100, B = 4200, C = 2, and D = 42 in the register to "0" (S2). Next, the first processor 13 reads out the output of the LD pin of the serializer 111 n times (S3) and judges whether or not it is "High" for n consecutive times (S4) (Yes), the optimization process is completed. If it is "Low" even once in n cycles (No), the process returns to S1 to read the parameter of the setting number i (see FIG. 3) = 3 from the memory (S1), and writes it into a register (S2). Repeat this until i = 11. With this optimization processing, the operating band of the PLL circuit of the serializer 111 can be adapted to the clock signal ck1 input from the camera.

[theorem]

A signal generating apparatus according to the present invention includes a PLL circuit and a control circuit for controlling the PLL circuit. The PLL circuit is capable of changing an operation band according to a setting change of a parameter, and when locked in each operation band, And generates an output clock signal corresponding to an input clock signal to the PLL circuit, and the control circuit sequentially changes the setting of the parameter until the PLL circuit is locked.

In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the setting of the parameters, and the PLL circuit is locked. That is, an output clock signal according to this input clock signal can be obtained in the setting of a parameter suitable for the input clock signal and the operation band from the outside to the PLL circuit.

This makes it possible to realize a signal generating apparatus which can cope with various inputs from the outside, and which can suppress the size and the cost, without a circuit or the like for judging an input from the outside.

In this signal generating apparatus, it is preferable that a frequency band in which the input clock signal is assumed is covered by a plurality of changeable operation bands.

For example, the input clock signal of the camera link standard is 20 to 85 MHz, and this is covered by a plurality of operating bands, so that it is possible to cope with various input clock signals according to the standard.

In this signal generating apparatus, the jitter of the input clock signal may be eliminated from the output clock signal.

Since the PLL circuit has a jitter canceling function by adjusting the circuit characteristics (for example, the relaxation time), the signal generating apparatus having the above-described configuration can be used as a jitter canceling device capable of coping with various input clock signals.

In the present signal generating apparatus, the PLL circuit may include a plurality of frequency dividers, and the parameter may be a combination of division ratios of these frequency divisions.

Thus, by changing the parameter to a combination of division ratios, it is easy to change the operating band of the PLL circuit.

In the present signal generating apparatus, the control circuit may be configured to set in the order of a parameter having a large number of locks in the past.

In this case, the time required for parameter setting can be shortened.

In the present signal generating apparatus, the control circuit may be configured to determine whether or not the setting of each parameter is necessary based on information previously added to each parameter.

By doing so, it is possible to shorten the time required for setting while suppressing the memory use of the control circuit.

The active cable includes a transmitter, a cable, and a receiver connected to the transmitter via the cable, wherein the signal generator is included in at least one of the transmitter and the receiver.

Since various clock signals are input to the active cable, the signal generating apparatus can be suitably used.

In this active cable, the signal generator is included in the transmitter, the receiver includes a PLL circuit different from the PLL circuit of the signal generator, and the lock state of the other PLL circuit included in the receiver is detected by the transmitter And the control circuit of the signal generating apparatus included in the transmitting section may be configured to determine whether or not to set the parameter of the PLL circuit of the signal generating apparatus again based on the notified lock situation.

According to the above configuration, it is possible to set the parameters of the PLL circuit of the transmitting unit to the abnormality of the receiving unit such as the unlocking of the receiving unit.

In this active cable, the transmitter includes the signal generating device, and the receiver includes a PLL circuit which is different from the PLL circuit of the signal generating device and is capable of changing the operation band in accordance with the parameter setting change, The control circuit of the signal generation apparatus notifies the reception section of the parameter locked by the PLL circuit of the signal generation apparatus and sets the other PLL circuit included in the reception section on the basis of the notified parameter It is possible.

According to the above configuration, since setting of the same PLL circuit as that of the transmitting side is not required on the receiving side, the processing speed on the receiving side can be increased.

It is preferable that this active cable conforms to the standard of the camera link (registered trademark) (hereinafter referred to as "camera link standard"). In the camera link specification, the frequency range of the clock signal from the camera is fixed, and the frequency varies depending on the camera. According to the signal generating device of the present active cable, it is possible to cover a range of the input frequency of the camera link standard by a plurality of changeable operation bands, and thus it is possible to cope with various cameras.

In addition, there is no jitter restriction in the camera link specification, and there may be a case where a large jitter is included in the input from the camera. Since the signal generating apparatus of this active cable can have a jitter canceling function, appropriate signal transmission is possible even when a large jitter is contained in the input from the camera.

A signal generating method using a PLL circuit for generating an output clock signal according to an input clock signal when an operation band can be changed according to a parameter setting change and locked in each operation band, And the setting is sequentially changed until the PLL circuit is locked.

In the above configuration, the operation band of the PLL circuit is sequentially changed by sequentially changing the setting of the parameters, and the PLL circuit is locked. In other words, an output clock signal according to the input clock signal can be obtained by setting a parameter suitable for the input clock signal from the outside to the PLL circuit and the operation band of the PLL circuit.

This makes it possible to realize a signal generating apparatus which can cope with various inputs from the outside, and which can suppress the size and the cost, without a circuit or the like for judging an input from the outside.

The present invention can be applied to a transmission system using a clock signal (for example, a camera link).

1: Transmission device 2: Transfer source device
3: transfer destination device 10:
11: Transmitter 12: First jitter cleaner
13: first processor (control circuit) 20:
21: receiver 22: second jitter cleaner
23: second processor 40: PLL circuit

Claims (11)

1. An active cable having a transmitter, a cable, and a receiver connected to the transmitter via the cable,
A signal generator is provided in the transmitter,
The signal generating apparatus includes a first PLL circuit and a control circuit for controlling the first PLL circuit,
The first PLL circuit generates an output clock signal corresponding to an input clock signal to the first PLL circuit when the operation band is locked in each operation band,
Wherein the control circuit sequentially changes the setting of the parameter until the first PLL circuit is locked,
A second PLL circuit different from the first PLL circuit is included in the receiving unit,
The lock status of the second PLL circuit is notified to the transmission unit, and the control circuit determines whether or not to set the parameter of the first PLL circuit again based on the notified lock situation. The method according to claim 1,
Wherein a frequency band in which the input clock signal is assumed is covered by a plurality of changeable operation bands. 3. The method according to claim 1 or 2,
Wherein the jitter of the input clock signal is eliminated in the output clock signal. 3. The method according to claim 1 or 2,
Wherein the first PLL circuit includes a plurality of frequency dividers, and the parameter is a combination of division ratios of these frequency divisions. 3. The method according to claim 1 or 2,
Wherein the control circuit sets the control circuit in the order of the number of past lock cycles. 3. The method according to claim 1 or 2,
Wherein said control circuit judges whether or not setting of each parameter is necessary based on information added in advance to each parameter. 1. An active cable having a transmitter, a cable, and a receiver connected to the transmitter via the cable,
A signal generator is provided in the transmitter,
The signal generating apparatus includes a first PLL circuit and a control circuit for controlling the first PLL circuit,
The first PLL circuit generates an output clock signal corresponding to an input clock signal to the first PLL circuit when the operation band is locked in each operation band,
Wherein the control circuit sequentially changes the setting of the parameter until the first PLL circuit is locked,
A second PLL circuit capable of changing an operation band according to a setting change of a parameter different from the first PLL circuit is included in the receiving unit,
Wherein the control circuit notifies the receiver of the parameter locked by the first PLL circuit, and sets the second PLL circuit based on the notified parameter. 8. The method of claim 1, 2 or 7,
An active cable used for a camera link standard. A first PLL circuit for generating an output clock signal corresponding to an input clock signal when the operation band can be changed in accordance with the setting change of the parameter and locked in each operating band, a cable and a second PLL circuit And a receiving unit connected to the transmitting unit via the cable, the control method comprising:
Sequentially changing the setting of the parameter until the first PLL circuit is locked,
Notifies the transmitter of the lock state of the second PLL circuit and determines whether to set the parameter of the first PLL circuit again based on the notified lock situation. And a first PLL circuit for generating an output clock signal corresponding to an input clock signal when the operation band is changed in accordance with the setting change of the parameter and locked in each operating band, A control method for an active cable including a second PLL circuit capable of changing an operation band and connected to the transmission unit via the cable,
Sequentially changing the setting of the parameter until the first PLL circuit is locked,
Notifies the receiver of the locked parameter of the first PLL circuit, and sets the second PLL circuit based on the notified parameter. delete
KR1020150099052A 2014-07-15 2015-07-13 Signal generating device, active cable, and method for signal generating KR101619506B1 (en)

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