KR101454296B1 - Field-programmable gate array phase detecting apparatus being used for the phase-locked loop circuit - Google Patents

Abstract

An FPGA phase comparison device used in a PLL circuit is disclosed. A 1/2 divider that receives the feedback signal and divides it by two; A 1/8 divider that receives 8,192 MHz local clock signal and divides it by 8; A multiplexer for selectively outputting one of a burst clock signal selected from a recovery clock signal 1 to a recovered clock signal 4 of 1,024 MHz and a signal divided by eight in the 1/8 frequency divider; A 1/4 frequency divider that receives the signal selected by the multiplexer and divides the divided signal into 4 frequency bands; A 1/1 frequency divider for receiving a 256 kHz signal divided into four in the 1/4 frequency divider as a reference clock REFCLK and a divider for dividing the 16,384 MHz divider signal in the divide- A reference clock signal divided by 1 in the 1/1 frequency divider and a phase difference of 64 divided signals in the 1/64 frequency divider are compared with each other to output the same phase Thereby constituting a phase comparator. According to the FPGA phase comparator used in the PLL circuit, by configuring the FPGA phase comparator composed of the divider and the multiplexer using only the counter and the NAND gate, the phase comparator can be easily and conveniently provided. There is an effect that can be manufactured.

Description

FIELD PROGRAMMABLE GATE ARRAY PHASE DETECTING APPARATUS BEING USED FOR THE PHASE-LOCKED LOOP CIRCUIT USED IN PLL CIRCUIT

The present invention relates to a phase comparison device, and more particularly, to an FPGA phase comparison device used in a PLL circuit.

In the digital transmission system, the clock is restored to synchronize the data to transmit the data. As a method for synchronizing synchronization, a method using a phase-locked loop (PLL) circuit is generally used.

The PLL circuit detects the phase difference between the input signal and the output signal and controls the phase of the output with a voltage proportional to the phase difference. Here, a circuit for keeping the phase of the output signal and the phase of the input signal the same, a phase detector, a low-pass filter, and a voltage-controlled oscillator are required.

Such an automatic phase control loop is manufactured and used as a dedicated chip. However, there is a problem in that there is no way to solve this problem when there is a problem in the supply and demand of the conventional automatic phase control loop chip.

In order to meet demand, supply, or breakdown of such an automatic phase control loop chip, it is necessary to prepare for an emergency in case of exhibition or emergency.

An object of the present invention is to provide an FPGA phase comparison device used in a PLL circuit.

The FPGA phase comparison device used in the PLL circuit according to the object of the present invention includes a 1/2 divider that receives a feedback signal and divides it by two; A 1/8 divider that receives 8,192 MHz local clock signal and divides it by 8; A multiplexer for selectively outputting one of a burst clock signal selected from a recovery clock signal 1 to a recovered clock signal 4 of 1,024 MHz and a signal divided by eight in the 1/8 frequency divider; A 1/4 frequency divider that receives the signal selected by the multiplexer and divides the divided signal into 4 frequency bands; A 1/1 frequency divider for receiving a 256 kHz signal divided into four in the 1/4 frequency divider as a reference clock REFCLK and a divider for dividing the 16,384 MHz divider signal in the divide- A reference clock signal divided by 1 in the 1/1 frequency divider and a phase difference of 64 divided signals in the 1/64 frequency divider are compared with each other to output the same phase Phase comparator.

At this time, in the 1/2 frequency divider, a signal output from the phase comparison is subjected to low-pass filtering by a loop filter to remove a high-frequency component, and a signal from which a high-frequency component is removed is input to a 32,768 MHz voltage- To receive the feedback signal.

The phase comparator may compare the reference clock signal and the 64 divided signals using a counter and a NAND gate to output the same phase.

According to the FPGA phase comparator used in the PLL circuit as described above, by configuring the FPGA phase comparator composed of the divider and the multiplexer using only the counter and the NAND gate, There is an effect that a device can be manufactured. Even if it is not a chip for phase comparison, it can easily implement clock synchronization by implementing phase comparison device using FPGA, so it can cope with supply and demand anxiety or breakdown.

1 is a block diagram of an FPGA phase comparison device used in a PLL circuit according to an embodiment of the present invention.
2 is a detailed circuit diagram of an FPGA phase comparison device used in a PLL circuit according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail to the concrete inventive concept. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an FPGA phase comparison device used in a PLL circuit according to an embodiment of the present invention.

Referring to FIG. 1, an FPGA phase comparison apparatus 100 (hereinafter referred to as FPGA phase comparison apparatus) used in a PLL circuit according to an embodiment of the present invention includes a 1/2 divider, A 1/8 divider 120, a multiplexer 130, a 1/4 frequency divider 140, and a phase comparator 150. The phase comparator 150 may include a phase comparator 110, a 1/8 divider 120,

The FPGA phase comparison apparatus 100 is implemented with a divider and a multiplexer 130 using only a counter and a NAND gate. Therefore, clock synchronization can be easily implemented using an FPGA, and it is possible to cope with an unstable supply / demand failure of a chip for phase comparison only. Hereinafter, the detailed configuration will be described.

The 1/2 frequency divider 110 receives the feedback signal from the voltage controlled oscillator 300 and divides the frequency divider into two. Here, a 32,768 MHz local oscillation frequency of the voltage-controlled oscillator 300 is output. Thus, the signals are divided into two by a signal of 16,384 MHz by a 1/2 frequency divider 110. [ The two divided signals are input to the 1/64 frequency divider 152 of the multiplexer 130 and used as the system clock signal.

The 1/8 frequency divider 120 is configured to receive a local clock signal of 8,192 MHz and divide it by 8. The 8-divided 1,024 MHz signal is input to the multiplexer 130. [

The multiplexer 130 is configured to selectively output one of the burst clock signal selected from the recovery clock signal 1 of 1, 024 MHz, or the recovery clock signal 4 and the signal divided by 8 in the 1/8 frequency divider 120.

The 1/4 frequency divider 140 is configured to receive the signal selected by the multiplexer 130 and to divide it into four signals. The divided signal of 256 kHz is input to the 1/1 frequency divider 151.

The phase comparator 150 is composed of a 1/1 frequency divider 151 and a 1/64 frequency divider 152.

The 1/1 frequency divider 151 is configured to receive a signal of 256 kHz divided by four in the 1/4 frequency divider 140 as a reference clock REFCLK and to divide the divided frequency by one.

The 1/64 frequency divider 152 is configured to receive a signal of 16,384 MHz divided by 1/2 in the frequency divider 110 as an input signal and divide the frequency by 64.

The phase comparator 150 compares the phase difference of the reference clock signal divided by 1 in the 1-minute cycle 151 and the 64-divided signal in the 1/64 frequency divider 152 to output the same phase.

The loop filter 200 low-pass filters the signal output from the phase comparator 150 to remove high frequency components.

The voltage-controlled power generator 300 provides a signal obtained by removing the high-frequency component from the loop filter 200 and a feedback signal of 32,768 MHz as a 1/2 frequency divider 110.

2 is a detailed circuit diagram of an FPGA phase comparison device used in a PLL circuit according to an embodiment of the present invention.

FIG. 2 illustrates a detailed circuit of the FPGA phase comparison device 100, which is composed of only a counter and a NAND gate. Thus, there is an advantage that the configuration of the phase comparison can be configured only by FGPA, and a dedicated chip can be used more conveniently.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims There will be.

110: 1/2 cycle
120: 1/8 minute cycle
130: multiplexer
140: 1/4 minute cycle
150: phase comparator
151: 1/1 cycle
152: 1/64 minute cycle
200: Loop filter
300: Voltage Controlled Oscillator

Claims (3)

A 1/2 divider that receives the feedback signal and divides it by two;
A 1/8 divider that receives 8,192 MHz local clock signal and divides it by 8;
A multiplexer for selectively outputting one of a burst clock signal selected from a recovery clock signal 1 to a recovered clock signal 4 of 1,024 MHz and a signal divided by eight in the 1/8 frequency divider;
A 1/4 frequency divider that receives the signal selected by the multiplexer and divides the divided signal into 4 frequency bands;
A 1/1 frequency divider for receiving a 256 kHz signal divided into four in the 1/4 frequency divider as a reference clock REFCLK and a divider for dividing the 16,384 MHz divider signal in the divide- A reference clock signal divided by 1 in the 1/1 frequency divider and a phase difference of 64 divided signals in the 1/64 frequency divider are compared with each other to output the same phase An FPGA phase comparison device used in a PLL circuit including a phase comparator. The method of claim 1,
A signal output from the phase comparison is subjected to low-pass filtering by a loop filter to remove a high-frequency component, and a signal from which a high-frequency component is removed receives the feedback signal through a voltage control generator VCXO of 32,768 MHz An FPGA phase comparator used in a PLL circuit characterized by. The phase comparator of claim 1,
Wherein the reference clock signal and the 64-divided signal are compared with each other using a counter and a NAND gate to output the same phase, and the FPGA phase used in the PLL circuit; Comparison device.

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