JP2005303582A - Pll synthesizer and pll synthesizer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL synthesizer which can bring the frequency of a frequency dividing signal in which the frequency of an oscillation signal is divided into coincidence with the frequency dividing frequency of a reference signal rapidly, even if a difference between an operating frequency and a setting frequency is large. <P>SOLUTION: The PLL synthesizer includes a VCO 5, a reference signal oscillator 1 for generating the reference signal, a first frequency converter 31 for converting the frequency of the oscillation signal of the VCO to output a first frequency conversion signal, a reference counter 35 for converting the frequency of the reference signal to output a second frequency conversion signal, a phase comparator 3 for comparing the phase difference between the first frequency conversion signal and the second frequency conversion signal to output a phase difference signal, an LPF 4 for integrating the phase difference signal, a VCO capacitor switching controller 6 for switching a main tuning capacitor which influences the frequency of the oscillation signal, and a BBIC 2 for controlling the frequency conversion in the first and second frequency converters by transmitting the frequency set data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL synthesizer for outputting an oscillation signal whose phase matches a reference signal, and a control method for the PLL synthesizer.

  An example of a conventional PLL synthesizer is described in (Patent Document 1). FIG. 14 is a block diagram showing a PLL synthesizer described in (Patent Document 1).

  In FIG. 14, reference numeral 1 is a reference signal oscillator that generates a reference signal, which is a reference signal, and 3 a is a frequency divider obtained by dividing the oscillation signal output from a VCO (voltage controlled oscillator) 5 described later by a frequency divider 10. A phase comparator that compares the phase of the signal (frequency conversion signal) with the reference signal from the reference signal oscillator 1 and outputs a phase difference signal, and 4 is an LPF that integrates the phase difference signal from the phase comparator 3a (Patent Literature). 1 is described as a loop filter, but is substantially the same) 5 is a VCO in which the frequency of the output oscillation signal is controlled by the input voltage value. As described above, the PLL synthesizer of FIG. 14 includes the phase comparator 3a that performs phase comparison between the oscillation signal of the VCO 5 and the reference (reference signal), the LPF 4 that integrates the phase difference signal from the phase comparator 3a, and the control voltage. It comprises a VCO 5 that can vary the frequency of the oscillation signal output by (input voltage), and a frequency divider 10 that divides the frequency of the oscillation signal of the VCO 5.

  The operation of the PLL synthesizer configured as described above will be described.

The frequency of the oscillation signal output from the VCO 5 is divided by the frequency divider 10 (that is, frequency-converted). The frequency of the divided oscillation signal (frequency-divided signal) is compared with the reference (reference signal) by the phase comparator 3a, and the difference from the desired frequency (frequency of the reference signal) is output from the phase comparator 3a as a phase difference signal. Is output. Although the phase difference signal output from the phase comparator 3a is a pulse voltage, the pulse voltage is integrated by the LPF 4, and the integrated voltage becomes the control voltage of the VCO 5, and the oscillation of the VCO 5 is the difference from the frequency of the reference signal. Change the frequency. By repeating the above operation (loop back operation), the frequency of the oscillation signal of the VCO 5 is set to a desired frequency.
Japanese Patent Laid-Open No. 9-294070

  As described above, the conventional PLL synthesizer is set to the desired frequency by repeating the loopback operation, but the difference between the current operating frequency (hereinafter also simply referred to as “operating frequency”) and the set frequency is large. (For example, when the difference between the set frequency set in the next slot and the frequency set in the operation slot that is the current slot (operation frequency) is large), the frequency pull-in operation cannot be performed at high speed, and the desired frequency is obtained. It has a problem that it takes time to complete.

  In this PLL synthesizer and PLL synthesizer control method, by changing the capacity of the main tuning capacitor of the VCO according to the set frequency, the operating frequency that is the frequency set in the current slot (the previous slot for the next slot) The frequency of the frequency-divided signal obtained by frequency-dividing the frequency of the oscillation signal from the VCO is made to coincide with the frequency of the reference signal at a high speed even if the difference from the set frequency that is the frequency set in the next slot is large. Is required.

  In order to satisfy this requirement, the present invention matches the frequency of the divided signal obtained by dividing the frequency of the oscillation signal with the divided frequency of the reference signal at high speed even if the difference between the operating frequency and the set frequency is large. PLL synthesizer that can be used to quickly match the frequency of the divided signal obtained by dividing the frequency of the oscillation signal to the divided frequency of the reference signal even if the difference between the operating frequency and the set frequency is large An object of the present invention is to provide a PLL synthesizer control method.

  In order to solve the above problems, a PLL synthesizer of the present invention includes a VCO in which the frequency of an oscillation signal to be output is controlled by an input voltage value, a reference signal oscillator that generates a reference signal that is a reference signal, A first frequency converter that converts a frequency and outputs a first frequency converted signal; a second frequency converter that converts a frequency of a reference signal and outputs a second frequency converted signal; A phase comparator that compares the phase difference between the frequency conversion signal and the second frequency conversion signal and outputs the phase difference signal, an LPF that integrates the phase difference signal, and a main tuning capacitor that affects the frequency of the oscillation signal are switched. A configuration having a VCO capacitor switching control unit and a BBIC that controls frequency conversion in the first and second frequency conversion units by transmitting frequency setting data. That.

  As a result, even if the difference between the operating frequency and the set frequency is large, a PLL synthesizer that can quickly match the frequency of the divided signal obtained by dividing the frequency of the oscillation signal with the divided frequency of the frequency of the reference signal is obtained. It is done.

  In order to solve the above-described problem, a PLL synthesizer control method according to the present invention is a PLL synthesizer control method for setting a frequency by transmitting a slot to the PLL synthesizer. The frequency setting data is set, and the transmission / reception process of the previous slot is performed after the frequency setting data is set.

  As a result, even if the difference between the operating frequency and the set frequency is large, a PLL synthesizer control method for making the frequency of the frequency-divided signal obtained by frequency-dividing the frequency of the oscillation signal coincide with the frequency-divided frequency of the reference signal at high speed. can get.

  The PLL synthesizer of the present invention includes a VCO in which the frequency of an oscillation signal to be output is controlled by an input voltage value, a reference signal oscillator that generates a reference signal that is a reference signal, and a first signal by converting the frequency of the oscillation signal. A first frequency conversion unit that outputs a frequency conversion signal of the second, a second frequency conversion unit that converts the frequency of the reference signal and outputs a second frequency conversion signal, a first frequency conversion signal, and a second frequency conversion signal A phase comparator that compares the phase difference with the frequency conversion signal and outputs a phase difference signal; an LPF that integrates the phase difference signal; a VCO capacitor switching control unit that switches a main tuning capacitor that affects the frequency of the oscillation signal; By having the BBIC that controls the frequency conversion in the first and second frequency converting units by transmitting the frequency setting data, Since the frequency conversion in the conversion unit can be controlled, an oscillation signal having an arbitrary frequency can be output from the VCO, and the first frequency conversion signal can be generated at high speed by switching the main tuning capacitor of the VCO capacitor switching control unit. The second frequency conversion signal can be brought close to the second frequency conversion signal. Therefore, an advantageous effect that the first frequency conversion signal can be set to the second frequency conversion signal at high speed is obtained.

  Further, since the BBIC controls the main tuning capacitor capacity in the VCO capacitor switching control unit by transmitting the frequency setting data, the BBIC sets the VCO main tuning capacitor after setting the frequency setting data, so the frequency is set in advance. By setting the frequency when there is time, an advantageous effect is obtained that the lock-up time of the PLL synthesizer can be shortened.

  Further, a VCO control voltage monitor unit for monitoring the input voltage value of the VCO is provided, and the VCO control voltage monitor unit controls the capacitance of the main tuning capacitor while monitoring the input voltage value of the VCO, thereby setting the frequency set from the BBIC. Can control the capacitance of the main tuning capacitor and can correct the input voltage value of the VCO with respect to a temperature change or the like. As a result, an advantageous effect that high-speed operation with excellent C / N can be obtained.

  In addition, a thermistor section that monitors the ambient temperature is provided, and the thermistor section controls the capacitance of the main tuning capacitor based on the detected ambient temperature, thereby correcting the capacitance of the main tuning capacitor based on the ambient temperature. Therefore, an advantageous effect that the influence of the ambient temperature on the capacitance of the main tuning capacitor can be reduced can be obtained.

  Furthermore, the power supply monitoring circuit for monitoring the supplied power supply voltage value is provided, and the power supply monitoring circuit controls the capacity of the main tuning capacitor based on the power supply voltage value. Since the correction based on the voltage value can be performed, an advantageous effect that the influence of the power supply voltage value on the capacity of the main tuning capacitor can be reduced is obtained.

  Further, the VCO capacitor switching control unit may reduce the change in the input voltage value in the control of the frequency of the oscillation signal of the VCO by performing control so that the change in the input voltage value is minimized in the frequency setting in the VCO. Therefore, an advantageous effect is obtained that the frequency of the first frequency conversion signal can be set to the frequency of the second frequency conversion signal at high speed.

  A PLL synthesizer control method according to the present invention, a PLL synthesizer control method for realizing speedup by transmitting frequency setting data of the next slot to the previous slot by the PLL synthesizer according to any of the first to sixth inventions, Set the frequency setting data before the slot transmission / reception process by setting the frequency setting data for the next slot before performing the slot transmission / reception process, and performing the transmission / reception process for the previous slot after setting the frequency setting data. Therefore, the advantageous effect that the lock-up time (time required for phase synchronization) of the PLL synthesizer can be increased can be obtained.

  Furthermore, in the PLL synthesizer control method of realizing speedup by transmitting the frequency setting data of the next slot to the previous slot by the PLL synthesizer of any of the first to sixth inventions, the frequency setting data of the next slot is obtained. By transmitting with the preamble of the previous slot and setting the frequency in the next slot immediately after the reception process is completed, the frequency setting data can be set before the reception process of the previous slot, so the lock-up time of the PLL synthesizer The advantageous effect that it can be lengthened is obtained.

  Furthermore, in the PLL synthesizer control method of realizing speedup by transmitting the frequency setting data of the next slot to the previous slot by the PLL synthesizer of any of the first to sixth inventions, the frequency setting data of the next slot is obtained. By performing transmission in the X and Z fields of the previous slot and performing reception processing after transmission, the frequency setting data can be set before the reception processing of the previous slot, so that the lock-up time of the PLL synthesizer can be increased. The advantageous effect that it can be obtained.

  Furthermore, since the length of the preamble is variable, it is possible to obtain an advantageous effect that if necessary, the length of the preamble can be increased to increase the lock-up time of the PLL synthesizer.

  Furthermore, a PLL synthesizer control method for realizing speed-up by transmitting the frequency setting data of the next slot to the previous slot by the PLL synthesizer of any one of the first to sixth inventions, comprising a delay state of a slot and an adjacent slot By making the slot length variable depending on the state of the slot, it is possible to increase the lockup time of the PLL synthesizer by increasing the length of the preamble depending on the delay state of the slot and the state of the adjacent slot. can get.

  Further, the BBIC has two memories, and by performing parallel operation using the two memories, one of the memories can be used for the lock-up operation of the PLL synthesizer, resulting in the lock-up of the PLL synthesizer. An advantageous effect that the time can be lengthened is obtained.

  Further, the BBIC has a memory, has two access pointers for accessing the memory, and performs parallel operation using the two access pointers, so that the access pointer of one memory is used for the lock-up operation of the PLL synthesizer. As a result, the advantageous effect that the lock-up time of the PLL synthesizer can be extended is obtained.

  According to the present invention, even if the difference between the operating frequency and the set frequency is large, the frequency of the frequency-divided signal (first frequency conversion signal) obtained by frequency-dividing the frequency of the oscillation signal is divided into the frequency of the frequency of the reference signal (second frequency). The purpose of matching the frequency of the main tuning capacitor of the VCO according to the set frequency is realized.

  In order to solve the above problems, a first invention is a VCO in which the frequency of an oscillation signal to be output is controlled by an input voltage value, a reference signal oscillator that generates a reference signal that is a reference signal, and an oscillation signal A first frequency conversion unit that converts the frequency of the reference signal and outputs a first frequency conversion signal; a second frequency conversion unit that converts the frequency of the reference signal and outputs a second frequency conversion signal; A phase comparator that outputs a phase difference signal by comparing the phase difference between the frequency conversion signal and the second frequency conversion signal, an LPF that integrates the phase difference signal, and a main tuning capacitor that affects the frequency of the oscillation signal. A VCO capacitor switching control unit for switching, and a BBIC for controlling frequency conversion in the first and second frequency conversion units by transmitting frequency setting data. Since the frequency conversion in the two frequency conversion units can be controlled by the BBIC, an oscillation signal of an arbitrary frequency can be output from the VCO, and the main tuning capacitor of the VCO capacitor switching control unit is switched to the first frequency. The conversion signal can be brought close to the second frequency conversion signal at high speed, and therefore, the first frequency conversion signal can be set as the second frequency conversion signal at high speed.

  The second invention made to solve the above problem is that the BBIC controls the main tuning capacitor capacity in the VCO capacitor switching control unit by transmitting the frequency setting data, and sets the frequency setting data. Since the VCO main tuning capacitor is set later, if there is time to set the frequency in advance, setting the frequency can shorten the lock-up time of the PLL synthesizer.

A third invention made to solve the above problems includes a VCO control voltage monitor unit that monitors an input voltage value of the VCO, and the VCO control voltage monitor unit monitors the input voltage value of the VCO while monitoring the input voltage value of the VCO. The capacitance of the main tuning capacitor can be controlled by the set frequency from the BBIC, and the input voltage value of the VCO can be corrected with respect to a temperature change or the like. In addition to being able to perform correction control for temperature changes and the like, it has the effect of being able to perform high-speed operation with excellent C / N with the optimum input voltage value.

  A fourth invention made to solve the above-described problem is provided with a thermistor section that monitors the ambient temperature, and the thermistor section controls the capacitance of the main tuning capacitor based on the detected ambient temperature. In addition, since the correction based on the ambient temperature can be performed in the control of the capacitance of the main tuning capacitor, the effect of the ambient temperature on the capacitance of the main tuning capacitor can be reduced.

  A fifth invention made to solve the above-described problem includes a power supply monitoring circuit for monitoring a supplied power supply voltage value, and the power supply monitoring circuit controls the capacity of the main tuning capacitor based on the power supply voltage value. Since the correction based on the power supply voltage value can be performed in the control of the capacity of the main tuning capacitor, the effect of the power supply voltage value on the capacity of the main tuning capacitor can be reduced. Have

  A sixth invention made to solve the above-described problem is that the VCO capacitor switching control unit performs control so that the change of the input voltage value is minimized in the frequency setting in the VCO. Since the change of the input voltage value can be reduced in the control of the frequency of the oscillation signal, it is possible to set the frequency of the first frequency conversion signal to the frequency of the second frequency conversion signal at high speed. Have.

  A seventh invention made to solve the above problems is a PLL synthesizer which realizes a high speed by transmitting the frequency setting data of the next slot to the previous slot in the PLL synthesizer of any one of the first to sixth inventions. This is a control method in which the frequency setting data of the next slot is set before the transmission / reception processing of the previous slot is performed, and the transmission / reception processing of the previous slot is performed after the frequency setting data is set. Since the frequency setting data can be set before processing, the PLL synthesizer has an operation and effect that the lock-up time (time required for phase synchronization) can be increased.

  An eighth invention made to solve the above-described problems is a PLL synthesizer that achieves higher speed by transmitting the frequency setting data of the next slot to the previous slot in the PLL synthesizer of any one of the first to sixth inventions. In this control method, the frequency setting data of the next slot is transmitted in the preamble of the previous slot, and the frequency setting in the next slot is performed immediately upon completion of the reception process. The frequency is set before the reception process of the previous slot. Since the setting data can be set, there is an effect that the lock-up time of the PLL synthesizer can be extended.

  A ninth invention made to solve the above problems is a PLL synthesizer which realizes a high speed by transmitting the frequency setting data of the next slot to the previous slot in the PLL synthesizer of any one of the first to sixth inventions. This is a control method in which the frequency setting data of the next slot is transmitted in the X and Z fields of the previous slot, and reception processing is performed after transmission. The frequency setting data is set before the reception processing of the previous slot. Therefore, the lock-up time of the PLL synthesizer can be lengthened.

  In a tenth aspect of the invention for solving the above-mentioned problem, the length of the preamble is variable. If necessary, the length of the preamble is increased to lock up the PLL synthesizer. It has the action and effect that the time can be lengthened.

An eleventh invention made to solve the above-described problems is a PLL synthesizer that achieves higher speed by transmitting the frequency setting data of the next slot to the previous slot in the PLL synthesizer of any of the first to sixth inventions. In this control method, the slot length is made variable according to the delay state of the slot and the state of the adjacent slot, and depending on the delay state of the slot and the state of the adjacent slot, the length of the preamble is increased, This has the effect that the lock-up time of the PLL synthesizer can be extended.

  In a twelfth aspect of the present invention, the BBIC has two memories and performs parallel operation using the two memories, and locks up one of the memories to the PLL synthesizer. Since it can be used for operation, it has the effect that the lock-up time of the PLL synthesizer can be increased as a result.

  In a thirteenth invention made to solve the above-described problem, the BBIC has a memory, has two access pointers for accessing the memory, and performs parallel operation using the two access pointers. Since the access pointer of one memory can be used for the lock-up operation of the PLL synthesizer, the lock-up time of the PLL synthesizer can be increased as a result.

(Embodiment 1)
1A is a block diagram showing a PLL synthesizer according to Embodiment 1 of the present invention, and FIG. 1B is a block diagram showing a PLLIC that constitutes the PLL synthesizer of FIG. 1A. .

  In FIG. 1A, reference numeral 1 is a reference signal oscillator that generates a reference signal that is a reference signal, and 2 is a frequency in first and second frequency converters 31 and 35 to be described later by transmitting frequency setting data. BBIC for controlling the conversion, 3 is a PLLIC for comparing the phase of the divided signal of the oscillation signal output from a VCO (voltage controlled oscillator) 5 described later and the divided signal of the reference signal from the reference signal oscillator 1 4 is an LPF that integrates the phase difference signal from the phase comparator 3, 5 is a VCO in which the frequency of the output oscillation signal is controlled by the input voltage value, and 6 is a VCO that switches the main tuning capacitor that affects the frequency of the oscillation signal. This is a capacitor switching control unit.

In FIG. 1B, reference numeral 31 denotes a first frequency conversion unit that converts the frequency of the oscillation signal and outputs a first frequency conversion signal (frequency-divided signal), and 35 denotes a first frequency conversion unit that converts the frequency of the reference signal. A reference counter serving as a second frequency conversion unit for outputting the second frequency conversion signal, and a phase comparison for outputting a phase difference signal by comparing the phase difference between the first frequency conversion signal and the second frequency conversion signal. T1, T2, and T3 are input terminals, and T4 is an output terminal. As shown in the figure, the first frequency converter 31 includes a prescaler, a swallow counter, and a programmable counter whose values are determined by the frequency setting data from the BBIC 2 and divides the frequency of the oscillation signal from the VCO 5. Generate a divided signal. Further, the reference counter 35 outputs a second frequency conversion signal having a divided frequency obtained by dividing the frequency of the reference signal from the reference signal oscillator 1. Here, when the oscillation frequency of the VCO is FVCO, the frequency of the reference signal is REF, the counter value of the reference counter is RC, the counter values of the prescaler, swallow counter and programmable counter are PS, SC and PC, respectively.
A relationship of FVCO / (PS × PC + SC) = REF / RC is established.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 2 is an explanatory diagram for the switching control of the main tuning capacitor (VCO main tuning capacitor) of the VCO 5 at the optimum operating voltage of the VCO 5.

The oscillation frequency of the VCO 5 can be changed depending on the capacity of the main tuning capacitor even when the control voltage of the VCO 5 is the same as shown by the characteristic line SC in FIG. As shown in FIG. 2, by changing the capacitance of the VCO main tuning capacitor, setting the rough frequency at high speed, and shortening the frequency acquisition time of the PLL synthesizer, the lock-up (phase synchronization acquisition) is fast. To do. In the following, the operation for drawing from the set frequency of the current slot (previous slot, operation slot) to the set frequency of the next slot will be described.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. The controller 6 determines the value of the main tuning capacitor of the VCO 5 so that the frequency closest to the given frequency data is obtained. Next, the PLLIC 3 starts control of the VCO 5 so as to become the frequency according to the set frequency data. The reference signal of the reference signal oscillator 1 is compared with the oscillation signal of the VCO 5 (assuming that the reference signal and the oscillation signal are divided before the comparison, as shown in FIG. 1B), The result is output to the LPF 4 as a phase difference signal. The LPF 4 integrates the phase difference signal, and the VCO 5 changes so that the frequency becomes the target frequency (the frequency of the reference signal, the desired frequency) according to the resulting control voltage (input voltage) value. Go.

  The frequency pull-in time until the PLL synthesizer reaches the target frequency is determined by the time constant of the LPF when the reference frequency is the same. If the time constant is reduced, the frequency can be drawn at a high speed, but the leak of the reference to the local area increases, and the time constant cannot be reduced significantly. Therefore, the PLL frequency pull-in cannot be significantly increased, and when the set frequency is far from the previously set frequency, it has been impossible to significantly reduce the lock-up time. Therefore, as in this method, the lock-up time is greatly shortened by first changing the main tuning capacitor of the VCO 5 and bringing the frequency of the oscillation signal output from the VCO 5 close to the set frequency. Is possible.

(Embodiment 2)
The configuration of a PLL synthesizer according to the second embodiment of the present invention is the configuration shown in FIG. The second embodiment is different from the first embodiment in the control procedure of the PLL synthesizer.

  The operation will be described. The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. The PLLIC 3 starts control of the VCO 5 so as to become the frequency according to the set frequency data (frequency setting data). Next, the control unit 6 determines the value of the main tuning capacitor of the VCO 5 so that the frequency closest to the given frequency data is obtained. The reference signal of the reference signal oscillator 1 is compared with the oscillation signal of the VCO 5 and the resulting phase difference signal is output to the LPF 4. The LPF 4 integrates the phase difference signal, and the VCO 5 changes so that the oscillation frequency becomes the target frequency by the control voltage resulting from the integration.

  The difference from the first embodiment is that the frequency setting data is set and then the varicap (main tuning capacitor) is set. If there is time to set the frequency in advance, doing so can reduce the lock-up time of the PLL synthesizer.

(Embodiment 3)
FIG. 3 is a block diagram showing a PLL synthesizer according to Embodiment 3 of the present invention.

  In FIG. 3, the reference signal oscillator 1, BBIC2, PLLIC3, LPF4, VCO5, and VCO capacitor switching control unit 6 are the same as those in FIG. Reference numeral 7 denotes a VCO control voltage monitor for monitoring the control voltage of the VCO 5.

  Next, the operation will be described. The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. The controller 6 determines the value of the main tuning capacitor of the VCO 5 so that the frequency closest to the given frequency data is obtained. Next, the PLLIC 3 starts control of the VCO 5 so as to become the frequency according to the set frequency data. The reference signal of the reference signal oscillator 1 is compared with the oscillation signal of the VCO 5 and the resulting phase difference signal is output to the LPF 4. The LPF 4 integrates the phase difference signal, and the VCO 5 changes so that the oscillation frequency becomes the target frequency by the control voltage resulting from the integration.

  The VCO control voltage monitor unit 7 monitors the control voltage to the VCO 5 and outputs the result to the VCO capacitor switching control unit 6. The relationship between the VCO main tuning capacitor and the oscillation frequency of the VCO 5 at the optimum operating voltage of the VCO 5 may be shifted due to, for example, a change in temperature, and may need to be corrected. Therefore, in order to operate the PLL synthesizer at high speed, the control voltage to the VCO 5 is monitored, and control is performed to change the value of the main tuning capacitor of the VCO 5 when not operating at the optimum operating voltage of the VCO 5. . This control not only enables correction control for temperature and the like, but also enables high-speed operation with excellent C / N.

(Embodiment 4)
FIG. 4 is a block diagram showing a PLL synthesizer according to Embodiment 4 of the present invention.

  In FIG. 4, the reference signal oscillator 1, BBIC2, PLLIC3, LPF4, VCO5, and VCO capacitor switching controller 6 are the same as those in FIG. Reference numeral 8 denotes a thermistor section for monitoring the ambient temperature.

  Next, the operation will be described. The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. The controller 6 determines the value of the main tuning capacitor of the VCO 5 so that the frequency closest to the given frequency data is obtained. Next, the PLLIC 3 starts control of the VCO 5 so as to become the frequency according to the set frequency data. The reference signal of the reference signal oscillator 1 is compared with the oscillation signal of the VCO 5 and the resulting phase difference signal is output to the LPF 4. The LPF 4 integrates the phase difference signal, and the VCO 5 changes so that the oscillation frequency becomes the target frequency by the control voltage resulting from the integration.

  As the temperature changes, the relationship between the VCO main tuning capacitor and the oscillation frequency of the VCO 5 at the optimum operating voltage of the VCO 5 changes, so that correction is required. Therefore, according to the temperature information output from the thermistor unit 8, the VCO capacitor switching control unit 6 switches the main tuning capacitor of the VCO 5 in consideration of not only the set frequency but also the temperature. Since the present embodiment requires a smaller system than the third embodiment using the VCO control voltage monitor unit 7, it is possible to realize a PLL synthesizer that can perform temperature correction at low cost.

(Embodiment 5)
FIG. 5 is a block diagram showing a PLL synthesizer according to the fifth embodiment of the present invention.

  Fifth, the reference signal oscillator 1, BBIC2, PLLIC3, LPF4, VCO5, and VCO capacitor switching control unit 6 are the same as those in FIG. Reference numeral 9 denotes a power supply monitoring circuit for monitoring the battery voltage.

Next, the operation will be described. By BBIC2 that sets the frequency of the next slot,
The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6. The controller 6 determines the value of the main tuning capacitor of the VCO 5 so that the frequency closest to the given frequency data is obtained. Next, the PLLIC 3 starts control of the VCO 5 so as to become the frequency according to the set frequency data. The reference signal of the reference signal oscillator 1 is compared with the oscillation signal of the VCO 5 and the resulting phase difference signal is output to the LPF 4. The LPF 4 integrates the phase difference signal, and the VCO 5 changes so that the oscillation frequency becomes the target frequency by the control voltage resulting from the integration.

  When the PLL synthesizer according to the present embodiment is battery-driven, it is necessary to perform parameter correction for setting the VCO main tuning capacitor due to battery voltage fluctuations. Therefore, according to the power supply voltage information output from the power supply monitoring circuit 9, the VCO capacitor switching control unit 6 switches the main tuning capacitor of the VCO 5 in consideration of not only the set frequency but also the battery voltage. As a result, a PLL synthesizer capable of correcting the battery voltage can be realized as compared with the first embodiment.

(Embodiment 6)
The configuration of a PLL synthesizer according to the sixth embodiment of the present invention is the configuration shown in FIG.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 6 is a graph for explaining a control method of the PLL synthesizer according to the sixth embodiment.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. The controller 6 determines the value of the main tuning capacitor of the VCO 5 so that the frequency closest to the given frequency data is obtained. Next, the PLLIC 3 starts control of the VCO 5 so as to become the frequency according to the set frequency data. The reference signal of the reference signal oscillator 1 is compared with the oscillation signal of the VCO 5 and the resulting phase difference signal is output to the LPF 4. The LPF 4 integrates the phase difference signal, and the VCO 5 changes so that the oscillation frequency becomes the target frequency by the control voltage resulting from the integration.

  FIG. 6 shows the relationship between the optimum operating voltage of the VCO 5 and the oscillation frequency of the VCO 5 with the capacitance of the VCO main tuning capacitor as a parameter. SV is a characteristic line showing the relationship between the optimum operating voltage of the VCO 5 and the oscillation frequency of the VCO 5 for a certain capacity of the VCO main tuning capacitor. When it is desired to move the VCO 5 at high speed, the PLL synthesizer is set at higher speed and the C / N is improved as the operating voltage of the VCO 5 by frequency setting is smaller. Therefore, based on the measurement result of the graph shown in FIG. 6, control is performed so that the fluctuation of the operating voltage of the VCO 5 due to the frequency setting is minimized according to the characteristic SV of the VCO 5. By this control, not only can correction control for temperature and the like be performed, but also C / N can be improved, and high-speed operation can be performed more stably.

(Embodiment 7)
The configuration of a PLL synthesizer according to the seventh embodiment of the present invention is the configuration shown in FIG.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 7 is a slot data diagram for explaining a control method of the PLL synthesizer according to the seventh embodiment.

Conventionally, the frequency setting data of the next slot is transmitted after the transmission processing or reception processing of the previous slot is performed at the guard time (Guard Time). As a result, the lock-up time allowed for the PLL synthesizer is shortened, and the requirements for hardware or control become severe. Therefore, before the transmission or reception process of the previous slot is performed, the frequency setting data of the next slot is set and the capacity of the main tuning capacitor of the VCO 5 is switched, and then the transmission process or reception process of the previous slot is performed. As a result, the lock-up time of the PLL synthesizer can be lengthened, and an inexpensive system can be constructed more easily because the demand for hardware or control becomes easier.

(Embodiment 8)
The configuration of a PLL synthesizer according to the eighth embodiment of the present invention is the configuration shown in FIG.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 8 is a slot data diagram for explaining a control method of the PLL synthesizer according to the eighth embodiment.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. In this case, the frequency setting data is transmitted at the Guard Time of each slot. However, the synthesizer lock-up time allowed is shortened by the time from the transmission of the frequency setting data to the latch, and the requirement for hardware or control becomes severe. Therefore, the frequency setting data of the PLL synthesizer is transmitted at the time of the preamble of the previous slot, and the frequency setting data is latched immediately after the end of transmission or after the end of reception. As a result, the lock-up time of the PLL synthesizer can be extended.

(Embodiment 9)
The configuration of the PLL synthesizer according to the ninth embodiment of the present invention is the configuration shown in FIG.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 9 is a slot data diagram for explaining a control method of the PLL synthesizer according to the ninth embodiment.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. In this case, the frequency setting data is transmitted at the Guard Time of each slot. However, the allowable lock-up time of the PLL synthesizer is shortened by the time from the transmission of the frequency setting data to the latch, and the requirement for hardware or control becomes severe. Therefore, the frequency setting data of the PLL synthesizer is transmitted at the X, Z-Field (X, Z field) of the previous slot. As a result, the lock-up time of the PLL synthesizer can be extended.

(Embodiment 10)
The configuration of the PLL synthesizer according to Embodiment 10 of the present invention is the configuration shown in FIG.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 10 is a slot data diagram for explaining a control method of the PLL synthesizer according to the tenth embodiment.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. In this case, the frequency setting data is transmitted at the Guard Time of each slot. However, the allowable lock-up time of the PLL synthesizer is shortened by the time from the transmission of the frequency setting data to the latch, and the requirement for hardware or control becomes severe. However, for example, in the DECT standard, the Sync preamble is 16 bits (bits), but the detection is performed only with about 8 bits. Therefore, the number of bits taken for the preamble can be reduced as necessary. As a result, the lock-up time of the PLL synthesizer can be extended. In addition, in this case, there is no influence on the processing of the preamble.

(Embodiment 11)
The configuration of the PLL synthesizer according to the eleventh embodiment of the present invention is the configuration shown in FIG.

  The operation of the PLL synthesizer configured as described above will be described with reference to FIG. FIG. 11 is a slot data diagram for explaining the control method of the PLL synthesizer according to the present embodiment.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. In this case, the frequency setting data is transmitted at the Guard Time of each slot. However, the allowable lock-up time of the PLL synthesizer is shortened by the time from the transmission of the frequency setting data to the latch, and the requirement for hardware or control becomes severe. In the case of multi-slot communication, depending on the operation status of adjacent slots, for example, if the previous slot is a control channel or an empty channel, the allowed lock-up time becomes long. Therefore, it is possible to select a combination of slots that can be lengthened as necessary, and as a result, it is possible to lengthen the lock-up time of the PLL synthesizer.

(Embodiment 12)
The configuration of the PLL synthesizer according to the twelfth embodiment of the present invention is the configuration shown in FIG. FIG. 12 is an explanatory diagram showing a case where the BBIC 2 has two memories. In FIG. 12, reference numerals 11 and 12 denote memories.

  The operation of the PLL synthesizer configured as described above will be described.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. In this case, the frequency setting data is transmitted at the Guard Time of each slot. However, the allowable lock-up time of the PLL synthesizer is shortened by the time from the transmission of the frequency setting data to the latch, and the requirement for hardware or control becomes severe. Therefore, two memories are used in the BBIC 2 and different memories are used for data transmission / reception and PLL synthesizer frequency setting data. As a result, the BBIC 2 can operate in parallel, transmit frequency setting data at the time of data transmission / reception, and latch the next frequency data immediately after transmission / reception. As a result, the lock-up time of the PLL synthesizer can be extended. In addition, in this case, transmission / reception processing is not delayed.

(Embodiment 13)
The configuration of the PLL synthesizer according to the thirteenth embodiment of the present invention is the configuration shown in FIG. FIG. 13 is an explanatory diagram showing a case where the BBIC 2 has a memory having two access pointers. In FIG. 13, 13 is a memory, and 14 and 15 are access pointers.

  The operation of the PLL synthesizer configured as described above will be described.

  The frequency setting data is sent to the PLLIC 3 and the VCO capacitor switching control unit 6 by the BBIC 2 that sets the frequency of the next slot. In this case, the frequency setting data is transmitted at the Guard Time of each slot. However, the allowable lock-up time of the PLL synthesizer is shortened by the time from the transmission of the frequency setting data to the latch, and the requirement for hardware or control becomes severe. Therefore, two pointers that can access the memory 13 in the BBIC 2 are provided. As a result, the BBIC 2 can operate in parallel, transmit frequency setting data at the time of data transmission / reception, and latch the next frequency setting data immediately after the transmission / reception is completed. As a result, the lock-up time of the PLL synthesizer can be extended. In addition, in this case, transmission / reception processing is not delayed.

  The present invention relates to a PLL synthesizer for outputting an oscillation signal whose phase matches a reference signal. Even if the difference between the operating frequency and the set frequency is large, the frequency of the divided signal obtained by dividing the oscillation signal The frequency can be matched with the divided frequency at high speed.

(A) A block diagram showing a PLL synthesizer according to the first, second, seventh, eighth, ninth, tenth, eleventh, twelfth and thirteenth embodiments of the present invention, and (b) a PLLIC constituting the PLL synthesizer of (a). Block Diagram Explanatory diagram for switching control of VCO main tuning capacitor at optimum operating voltage of VCO Block diagram showing a PLL synthesizer according to Embodiment 3 of the present invention Block diagram showing a PLL synthesizer according to Embodiment 4 of the present invention Block diagram showing a PLL synthesizer according to Embodiment 5 of the present invention Graph for explaining the control method of the PLL synthesizer according to the sixth embodiment of the present invention Slot data diagram for explaining the control method of the PLL synthesizer according to the seventh embodiment of the present invention Slot data diagram for explaining the control method of the PLL synthesizer according to the eighth embodiment of the present invention Slot data diagram for explaining the control method of the PLL synthesizer according to the ninth embodiment of the present invention Slot data diagram for explaining the control method of the PLL synthesizer according to the tenth embodiment of the present invention Slot data diagram for explaining the control method of the PLL synthesizer according to the eleventh embodiment of the present invention Explanatory diagram showing the case where the BBIC has two memories Explanatory drawing showing a case where the BBIC has a memory having two access pointers Block diagram showing a PLL synthesizer described in Patent Document 1

Explanation of symbols

1 Reference signal oscillator 2 BBIC
3 PLLIC
4 LPF
5 VCO
6 VCO capacitor switching control unit 7 VCO control voltage monitoring unit 8 thermistor unit 9 power supply monitoring circuit 11, 12, 13 memory 14, 15 access pointer

Claims (13)

A VCO in which the frequency of an oscillation signal to be output is controlled by an input voltage value, a reference signal oscillator that generates a reference signal that is a reference signal, and a first frequency conversion signal that outputs the first frequency conversion signal by converting the frequency of the oscillation signal A first frequency converter, a second frequency converter that converts the frequency of the reference signal and outputs a second frequency converted signal, the first frequency converted signal, and the second frequency converted signal A phase comparator that compares the phase difference and outputs a phase difference signal, an LPF that integrates the phase difference signal, a VCO capacitor switching unit that switches a main tuning capacitor that affects the frequency of the oscillation signal, and a frequency setting A PLL synthesizer comprising: a BBIC that controls frequency conversion in the first and second frequency conversion units by transmitting data. The PLL synthesizer according to claim 1, wherein the BBIC controls the main tuning capacitor capacity in the VCO capacitor switching unit by transmitting frequency setting data. A VCO control voltage monitor unit for monitoring an input voltage value of the VCO, wherein the VCO control voltage monitor unit controls the capacitance of the main tuning capacitor while monitoring the input voltage value of the VCO. Item 3. A PLL synthesizer according to Item 1 or 2. The PLL synthesizer according to claim 1, further comprising a thermistor that monitors an ambient temperature, wherein the thermistor controls a capacitance of the main tuning capacitor based on the detected ambient temperature. The power supply monitoring circuit for monitoring a supplied power supply voltage value, wherein the power supply monitoring circuit controls the capacitance of the main tuning capacitor based on the power supply voltage value. PLL synthesizer. 4. The method of controlling a PLL synthesizer according to claim 3, wherein the VCO capacitor switching unit performs control such that a change in the input voltage value is minimized in frequency setting in the VCO. A PLL synthesizer control method for realizing high speed by transmitting the frequency setting data of the next slot during the previous slot in the PLL synthesizer according to any one of claims 1 to 6,
A PLL synthesizer control method comprising: setting the frequency setting data of the next slot before performing transmission / reception processing of the previous slot, and performing transmission / reception processing of the previous slot after setting the frequency setting data. A PLL synthesizer control method for realizing high speed by transmitting the frequency setting data of the next slot during the previous slot in the PLL synthesizer according to any one of claims 1 to 6,
A PLL synthesizer control method characterized in that the frequency setting data of the next slot is transmitted in the preamble of the previous slot, and the frequency setting in the next slot is performed immediately upon completion of reception processing. A PLL synthesizer control method for realizing high speed by transmitting the frequency setting data of the next slot during the previous slot in the PLL synthesizer according to any one of claims 1 to 6,
A PLL synthesizer control method characterized by transmitting the frequency setting data of the next slot in the X and Z fields of the previous slot and performing reception processing after transmission. 9. The PLL synthesizer control method according to claim 8, wherein the preamble has a variable length. A PLL synthesizer control method for realizing high speed by transmitting the frequency setting data of the next slot during the previous slot in the PLL synthesizer according to any one of claims 1 to 6,
A PLL synthesizer control method, wherein a slot length is variable according to a delay state of a slot and a state of an adjacent slot. The PLL synthesizer control method according to claim 7, wherein the BBIC includes two memories and performs parallel operation using the two memories. 12. The BBIC includes a memory, has two access pointers for accessing the memory, and performs a parallel operation using the two access pointers. PLL synthesizer control method.

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