JP5772170B2 - Capacitive load drive circuit and fluid ejection device - Google Patents

Description

  The present invention relates to a technique for driving an electrical load by outputting a drive signal.

So-called class D amplifiers push two MOSFETs between the power supply and ground.
A technique is used in which a pull connection is made, a voltage between two MOSFETs is extracted and input to a smoothing filter, and then output to the outside as a drive signal. Power supply side MOSFET is O
If the ground side MOSFET is turned off (disconnected state) as N (conducting state), the power supply voltage is input to the smoothing filter. Conversely, the power supply side MOSFET is turned off and the ground side MOSFET is turned on. Then, the ground voltage is input to the smoothing filter. Therefore, if a drive waveform signal serving as a reference of a drive signal to be output is pulse-modulated and two MOSFETs are driven based on the obtained modulation signal, a power amplification modulation signal obtained by power amplification of the modulation signal is generated. be able to. Then, by smoothing the power amplification modulation signal with a smoothing filter, a drive signal corresponding to the drive waveform signal can be output. In addition, a technique for driving an electric load having a capacitive component (capacitive load) using this technique has been proposed (Patent Document 1).

Here, although PchMOSFET and NchMOSFET exist in MOSFET, NchMOSFET is used for a class D amplifier. This is because NchM has low resistance (ON resistance) in the conductive state from the viewpoint of taking advantage of the class D amplifier that power loss is small.
This is because OSFET is more suitable than PchMOSFET having a large on-resistance.

JP 2007-96364 A

However, when a class D amplifier is configured using an Nch MOSFET, the MOSFE on the power supply side
If the state where T is rarely turned off continues, the MOSFET cannot be turned on, and as a result, the class D amplifier does not operate normally and cannot output a drive signal. was there.

The present invention has been made to solve at least a part of the above-described problems of the prior art, and even if the state where the MOSFET on the power supply side is turned off rarely continues,
An object of the present invention is to provide a technique capable of operating a class D amplifier normally and outputting a drive signal.

In order to solve at least a part of the problems described above, the capacitive load driving circuit of the present invention employs the following configuration. That is,
A drive waveform signal generating circuit for generating a drive waveform signal;
A modulation circuit that generates a modulation signal by pulse-modulating the drive waveform signal;
A digital power amplifier that amplifies the modulated signal to generate a power amplified modulated signal;
A smoothing filter that generates a drive signal by smoothing the power amplification modulation signal,
The digital power amplifier is:
A first voltage source;
A first switch connected in series with the first voltage source;
A second switch connected in series with the first switch;
A second voltage generation source connected in series with the second switch and generating a voltage lower than a voltage generated by the first voltage generation source;
A switch driving circuit for driving the first and second switches based on the modulation signal,
The switch driving circuit includes a bootstrap capacitor that stores current while the second switch is ON. When the first switch is turned ON, the current stored in the bootstrap capacitor is Supplying the first switch with the first switch ON;
A summary of the first switch is that a switch using an N-channel MOSFET and a switch using a P-channel MOSFET are connected in parallel.

In the capacitive load drive circuit of the present invention having such a configuration, the drive waveform signal generated by the drive waveform signal generation circuit is converted into a modulation signal by the modulation circuit, and then the power is amplified by the digital power amplifier to obtain the power amplification modulation signal. Is generated. Then, the drive signal is generated by smoothing the power amplification modulation signal with a smoothing filter. The digital power amplifier includes a first voltage generation source, a first switch connected in series with the first voltage generation source, a second switch connected in series with the first switch, and a second switch. And a switch driving circuit for driving the first and second switches based on the modulation signal, the second voltage generating source generating a voltage lower than the voltage generated by the first voltage generating source. Is provided. In addition, the switch driving circuit is equipped with a bootstrap capacitor that stores current while the second switch is ON. When the first switch is turned on, the first switch is turned on by supplying the current stored in the bootstrap capacitor to the first switch.
To be. The first switch is connected in parallel with a switch with a P-channel MOSFET in addition to a switch with an N-channel MOSFET.

For this reason, a sufficient current is not stored in the bootstrap capacitor.
Even when the switch by the N channel MOSFET constituting the switch of the N channel cannot be turned ON, the switch of the N channel MOSFET includes the P channel MOSFE.
The switch by T is connected in parallel, and the switch by this P channel MOSFET can be turned ON. As a result, it is possible to amplify the power of the modulation signal with the digital power amplifier, and it is possible to output a drive signal corresponding to the drive waveform signal. Also,
Since the switch by the N-channel MOSFET and the switch by the P-channel MOSFET are connected in parallel, the combined resistance becomes small, and there is a problem that the on-resistance of the P-channel MOSFET is larger than that of the N-channel MOSFET. Absent.

In the capacitive load driving circuit of the present invention described above, the voltage stored in the bootstrap capacitor is detected, and the switch by the N-channel MOSFET or the switch by the P-channel MOSFET is driven according to the detected voltage. You may do it.

Driving both the N-channel MOSFET switch and the P-channel MOSFET switch consumes more power than driving either one. there,
When the voltage stored in the bootstrap capacitor is detected and the voltage is a voltage that can drive the switch by the N-channel MOSFET, the N-channel MO
The switch by SFET is driven, and the switch by P channel MOSFET is driven in other cases. In this way, the switch by the N-channel MOSFET is driven according to the voltage stored in the bootstrap capacitor, and the P-channel M
Since it is possible to switch between the case where the OSFET switch is driven, it is possible to suppress power loss for driving the switch.

In the capacitive load driving circuit of the present invention described above, which of the switch by the N channel MOSFET or the switch by the P channel MOSFET is driven,
Switching may be performed based on the drive waveform signal.

Whether or not the voltage stored in the bootstrap capacitor is insufficient can be determined in advance based on the drive waveform signal. Therefore, when driving a switch by an N-channel MOSFET and when driving a switch by a P-channel MOSFET,
If switching is performed based on the drive waveform signal, it is not necessary to drive the two switches together, so that it is possible to suppress power loss for driving the switches. Further, since it is not necessary to detect the voltage stored in the bootstrap capacitor, it can be realized with a simple circuit configuration.

Further, in the capacitive load driving circuit of the present invention described above, even when the on-duty ratio of the modulation signal continues to be close to the upper limit, the modulation signal is normally amplified to output a drive signal. Can do. Therefore, the capacitive load driving circuit of the present invention described above can be suitably applied to the following fluid ejecting apparatus. That is, a fluid supply means (such as a supply pump) that supplies fluid, a fluid chamber into which the fluid supplied from the fluid supply means flows, an actuator that is a capacitive load, and an injection that ejects the fluid that has flowed into the fluid chamber As a capacitive load driving circuit that generates a driving signal in a fluid ejecting apparatus that ejects fluid in a fluid chamber in a pulsed manner from an ejecting nozzle by applying a driving signal to an actuator. It can be suitably applied.

It is explanatory drawing which showed the structure of the fluid injection apparatus carrying the capacitive load drive circuit of 1st Example. It is explanatory drawing which showed the circuit structure of the capacitive load drive circuit of 1st Example. It is the circuit diagram which showed the detailed structure of the digital power amplifier of 1st Example. FIG. 2 is a circuit diagram illustrating a detailed configuration of a switch drive circuit according to a first embodiment. It is explanatory drawing which showed the operation | movement which a switch drive circuit drives N channel MOSFET connected to the power supply side. It is explanatory drawing which illustrated the conditions from which N channel MOSFET connected to the power supply side cannot operate | move normally. It is the circuit diagram which showed the detailed structure of the switch drive circuit of 2nd Example. It is the circuit diagram which showed the structure of the capacitive load drive circuit of 3rd Example. It is the flowchart which showed the process in which the switch selection circuit mounted in the capacitive load drive circuit of 3rd Example outputs a selection signal.

Hereinafter, in order to clarify the contents of the present invention described above, examples will be described in the following order.
A. First embodiment:
A-1. overall structure:
A-2. Capacitive load drive circuit configuration:
A-3. Digital power amplifier of the first embodiment:
A-4. Operation of the digital power amplifier of the first embodiment:
B. Second embodiment:
C. Third embodiment:

A. First Example:
A-1. overall structure :
FIG. 1 is an explanatory diagram showing a configuration of a fluid ejecting apparatus 100 equipped with a capacitive load driving circuit 200 of the first embodiment. As shown in the drawing, the fluid ejection device 100 is roughly divided into:
A pulsation generating unit 110 for ejecting liquid, a fluid supply unit 120 (supply pump) for supplying fluid toward the pulsation generating unit 110, and a control unit 130 for controlling operations of the pulsation generating unit 110 and the fluid supply unit 120. Etc. The fluid ejecting apparatus 100 is an example of a water jet knife as a surgical tool used for excising or incising a living tissue by ejecting a pulsed liquid from a pulsation generating unit 110.

The pulsation generating unit 110 is provided on the second case 113 made of metal and the first case 114 made of metal.
A circular pipe-shaped fluid ejection pipe 112 is erected on the front surface of the second case 113, and a nozzle 111 is inserted at the tip of the fluid ejection pipe 112. Second case 11
3 and the first case 114 are formed with a thin disk-shaped fluid chamber 115, and the fluid chamber 115 is connected to the nozzle 111 via the fluid ejection pipe 112. A laminated piezoelectric element 116 is provided inside the first case 114. Pulsation generator 11
0 and the control unit 130 are connected by a wiring cable 150, and a drive signal is transmitted from the capacitive load driving circuit 200 in the control unit 130 via the wiring cable 150 to the piezoelectric element 116.
To be supplied. Further, the wiring cable 150 is attached to the pulsation generator 110 by a connector.

The fluid supply means 120 sucks up the fluid from the fluid container 123 in which the fluid to be ejected (water, physiological saline, chemical solution, etc.) is stored through the first connection tube 121, and then moves the second connection tube 122. And supplied to the fluid chamber 115 of the pulsation generator 110. For this reason, the fluid chamber 115 is in a state filled with fluid. Then, when a drive signal is applied from the control unit 130 to the piezoelectric element 116, the piezoelectric element 116 expands and the fluid chamber 115 is compressed,
As a result, the fluid filled in the fluid chamber 115 is ejected from the nozzle 111 in a pulse shape. The expansion amount of the piezoelectric element 116 depends on the voltage applied as the drive signal. The drive signal is generated by the capacitive load drive circuit 200 mounted in the control unit 130.

A-2. Overview of capacitive load drive circuit configuration:
FIG. 2 is an explanatory diagram showing a circuit configuration of the capacitive load driving circuit 200 mounted on the control unit 130. As shown in the figure, the capacitive load drive circuit 200 includes a drive waveform signal generation circuit 210 that outputs a drive waveform signal (hereinafter referred to as WCOM) serving as a reference for the drive signal, and a pulse-modulated WCOM to generate a modulation signal (hereinafter referred to as a drive signal) Modulation circuit 230 for conversion into MCOM), and modulation circuit 230
The digital power amplifier 240 that digitally amplifies the MCOM from the power to generate a power amplified modulated signal (hereinafter referred to as ACOM), receives the ACOM from the digital power amplifier 240, removes the modulation component, and drives the signal (hereinafter referred to as COM). ) As the piezoelectric element 1 of the pulsation generator 110.
16 is provided with a smoothing filter 250 to be supplied to 16.

Of these, the drive waveform signal generation circuit 210 includes a waveform memory storing WCOM data and a D / A converter, and converts data read from the waveform memory into an analog signal by the D / A converter. To generate a WCOM (drive waveform signal). Modulation circuit 2
30 is equipped with a triangular wave generator for generating a triangular wave having a constant period (modulation period), and by comparing the WCOM received from the drive waveform signal generation circuit 210 with a triangular wave, a pulse wave-like MCOM (modulated signal) is provided. (Pulse modulation). For example, the MCOM outputs a high voltage state (output is “H”) when WCOM is larger than the triangular wave, and outputs a MCOM such that the low voltage state (output is “L”) when WCOM is smaller than the triangular wave. Is done. The time ratio at which MCOM is “H” is called “duty ratio (or on-duty ratio)”.

The MCOM obtained by the modulation circuit 230 is amplified by the digital power amplifier 240. Although the detailed configuration will be described later, the digital power amplifier 240 is equipped with a power source. When the input of the MCOM is “H”, the power source and the output of the digital power amplifier 240 are connected inside the digital power amplifier 240, and the voltage of the power source is output as the output of the digital power amplifier 240. When the input of MCOM is “L”,
The ground and the output of the digital power amplifier 240 are connected inside the digital power amplifier 240, and the ground voltage is output as the output of the digital power amplifier 240. As a result, the power of MCOM is amplified to a pulsed signal that becomes a power supply voltage when MCOM is “H” and a ground voltage when MCOM is “L”. AC thus amplified
OM (power amplification modulation signal) is converted into COM (driving signal) by passing through a smoothing filter 250 constituted by an LC circuit, and is applied to the piezoelectric element 116.

A-3. Digital power amplifier of the first embodiment:
FIG. 3 is a circuit diagram showing the internal configuration of the digital power amplifier 240 of the first embodiment. As shown, the digital power amplifier 240 of the first embodiment includes a power source Vdd and two N
A channel MOSFET (shown as FET1 and FET3 in FIG. 3), one P-channel MOSFET (shown as FET2 in FIG. 3), and a switch drive circuit 242 for driving these MOSFETs are mounted. Of the three MOSFETs, FET1 and FET
3 is push-pull connected between the power supply Vdd and the ground. That is, the power supply V
The drain electrode of FET1 (shown as D in the figure) is connected to dd, and the drain electrode of FET3 is connected to the source electrode of FET1 (shown as S in the figure). And FE
The source electrode of T3 is connected to the ground. And the source electrode of FET1, FE
The voltage at the portion where the drain electrode of T3 is connected is output as ACOM.

The FET 2 which is a P-channel MOSFET has a source electrode connected to the power supply Vdd and a drain electrode connected to the output line of the ACOM. Therefore, the FET 2 is connected to the FET 1 in parallel. Furthermore, the gate electrodes of FET1, FET2, and FET3 are connected to the switch drive circuit 242. In this embodiment, the FET 1 corresponds to the “first switch” of the present invention, and the FET 3 corresponds to the “second switch” of the present invention. Since FET1 is an N-channel MOSFET and FET2 is a P-channel MOSFET, FET1 corresponds to the “switch by N-channel MOSDET” of the present invention, and FET2 also corresponds to “switch by P-channel MOSDET” of the present invention. It corresponds. Further, the power supply Vdd corresponds to the “first voltage generation source” of the present invention, and the ground corresponds to the “second voltage generation source” of the present invention.

FIG. 4 is a circuit diagram showing the configuration of the switch drive circuit 242 of the first embodiment. The first
The digital power amplifier 240 according to the embodiment includes a power source Vdd of a general digital power amplifier 240.
The FET 2 is connected in parallel to the side FET 1. Corresponding to this, the switch drive circuit 242 of the first embodiment has a circuit portion (indicated as 242b in FIG. 4) for driving the FET 2 with respect to the switch drive circuit of the general digital power amplifier 240. It has been added. The circuit portion for driving the FET 1 (shown as 242a in FIG. 4) is the same as that used in the switch drive circuit of a general digital power amplifier 240. Further, the circuit portion for driving the FET 3 in the switch driving circuit 242 is not shown because it is not related to the present invention. The digital power amplifier 240 of this embodiment having such a configuration operates as follows.

A-4. Operation of the digital power amplifier of the first embodiment:
First, an operation in which the switch drive circuit 242 of the digital power amplifier 240 drives the FET 1 (accordingly, an operation of a portion indicated by 242a in FIG. 4) will be described. FIG. 5A shows a case where the output of MCOM is “L”. When MCOM is “L”, FET 1 (and FET 2) connected to the power supply Vdd side is turned OFF, and FET 3 connected to the ground side is turned ON. As a result, the digital power amplifier 240 outputs the ground voltage as ACOM.

Here, as shown in FIG. 5A, a capacitor BSC is mounted on the circuit portion 242a for driving the FET1. One terminal of this capacitor BSC is AC
The other terminal is connected to the driving power source of the switch driving circuit 242. Therefore, as shown in FIG. 5A, when the output of the MCOM becomes “L” and the output of the ACOM becomes the ground voltage, the voltage of the driving power supply is applied between both terminals of the capacitor BSC. Thus, the capacitor BSC is charged. After that, FIG.
), When the output of the MCOM becomes “H”, the voltage stored in the capacitor BSC is applied to the gate electrode of the FET 1, and accordingly, the gate electrode is more potential than the source electrode of the FET 1. As a result, FET1 is turned on. Such a capacitor BSC is called a bootstrap capacitor. If the bootstrap capacitor is used, the FET 1 can be turned on without using the power source for the gate electrode of the FET 1 in addition to the driving power source.

However, when the FET 1 is driven using the capacitor BSC, the charge stored in the capacitor BSC leaks if the FET 1 continues to be ON, and the capacitor BSC
The voltage between both terminals of SC (therefore, the potential difference between the source electrode and the gate electrode of FET1) gradually decreases. As a result, finally, the FET 1 cannot be maintained in the ON state.

For example, when the drive waveform signal generation circuit 210 outputs WCOM in the vicinity of the upper limit, the MCOM output from the modulation circuit 230 is an MCOM having a very high on-duty ratio (the time frequency at which H becomes 95% or more, for example). Become. When such MCOM is received, as illustrated in FIG. 6, the FET 1 on the power supply Vdd side of the digital power amplifier 240 is almost always in an ON state and is switched to an OFF state only rarely. On the contrary, the FET 3 on the ground side of the digital power amplifier 240 is almost always in the OFF state, and is ON
This state can only be switched very rarely.

As described above, since the capacitor BSC is charged when the FET 1 is OFF and the FET 3 is ON, if the digital power amplifier 240 is operated in the state shown in FIG. 6, the capacitor BSC is stored in the capacitor BSC. As a result, the voltage gradually decreases and the FET 1 cannot be turned on. As a result, the digital power amplifier 240 cannot amplify the MCOM power, and the piezoelectric element 116 cannot be driven. Of course, if the FET 1 is driven using a power supply prepared separately instead of the capacitor BSC, such problems can be avoided. However, if a power source for driving the FET 1 is separately prepared in addition to the driving power source, the circuit size of the switch driving circuit 242 increases, and the manufacturing cost of the circuit increases.

On the other hand, in the digital power amplifier 240 of the first embodiment, the FET 2 is connected in parallel to the FET 1 as described above with reference to FIG. The FET 1 uses an N-channel MOSFET, while the FET 2 uses a P-channel MOSFET. As is well known, the P-channel MOSFET is turned on when the potential of the gate electrode is lower than a certain voltage compared to the source electrode. Therefore, it can be turned on without using a bootstrap capacitor such as the capacitor BSC. Therefore, as illustrated in FIG. 6, even when the MCOM is a signal in which the on-duty ratio is very high (for example, 95% or more) continues for a long time, and the FET 1 is not turned ON,
FET2 is turned on. As a result, the digital power amplifier 240 can amplify the power of MCOM and drive the piezoelectric element 116.

Of course, the FET 2 is a P-channel MOSFET having a larger on-resistance than the N-channel MOSFET. However, as shown in FIG. 3, the FET 2 is connected in parallel with the FET 1, and the FET 2 alone is in the ON state only in a special situation as described above with reference to FIG. For this reason, in most cases, both FET1 and FET2 are in the ON state. Therefore, the digital power amplifier 240 is caused by the large on-resistance of FET2.
There is no increase in power loss.

B. Second embodiment:
In the first embodiment described above, it has been described that FET1 and FET2 are driven in parallel. However, in order to drive FET1 and FET2 in parallel, more power is required than when FET1 is driven alone. Therefore, the FET 2 may not be driven while the FET 1 can be normally driven, and the FET 2 may be driven only when it is difficult to normally drive the FET 1. Hereinafter, such a second embodiment will be described. In the second embodiment, the components not particularly mentioned are the same as those in the first embodiment described above. And about the structure similar to 1st Example mentioned above, detailed description is abbreviate | omitted by attaching | subjecting the same number.

FIG. 7 shows a switch drive circuit 342 mounted on the digital power amplifier 240 of the second embodiment.
FIG. In the switch drive circuit 342 of the second embodiment, the voltage between both terminals of the capacitor BSC is divided by a resistor and then input to the operational amplifier OP1, and the operational amplifier OP1 calculates the voltage difference between the input voltages as the operational amplifier OP2. Output to. Operational amplifier OP
2 compares the voltage difference input from the operational amplifier OP1 with the threshold voltage Vref, and outputs a signal “H” if the voltage difference is larger than the voltage Vref, and outputs “H” signal if the voltage difference is smaller than the voltage Vref. L "signal is output. The output of the operational amplifier OP2 is connected to the switch SW1 and the switch SW2. Of these, the switch SW1 has an operational amplifier OP.
2 is connected as it is, and is connected to the switch SW2 after being inverted by an inverter.

In such a switch drive circuit 342 of the second embodiment, the switch SW1 is turned on and the switch SW2 is turned off while the voltage difference output from the operational amplifier OP1 is larger than the threshold voltage Vref. The voltage difference from the operational amplifier OP1 is the threshold voltage Vre.
When smaller than f, the switch SW1 is turned OFF and the switch SW2 is turned ON.
Therefore, when the voltage between the terminals of the capacitor BSC becomes lower than a voltage having a slight margin with respect to the voltage for turning on the FET 1, the output of the operational amplifier OP2 is set to a voltage that becomes “L”. The threshold voltage Vref is set in advance. In this way, the capacitor BSC
Since the switch SW1 is turned ON while the sufficient voltage is stored in the FET 1, the FET 1 is driven, and when the voltage of the capacitor BSC decreases, the switch SW2 is turned ON, so the FE.
T2 is driven. As a result, it is possible to switch between the case where the FET 1 is driven and the case where the FET 2 is driven according to the voltage stored in the capacitor BSC, so that the power for driving the switch drive circuit 342 can be suppressed. It becomes possible.

C. Third embodiment:
In the switch drive circuit 342 of the second embodiment described above, two operational amplifiers are required. However, if it is as follows, it becomes possible to switch between the case of driving FET1 and the case of driving FET2 without using an operational amplifier. Hereinafter, the third embodiment will be described. In the third embodiment as well, configurations not particularly mentioned are the same as those in the first embodiment or the second embodiment described above. And about the structure similar to 1st Example or 2nd Example mentioned above, detailed description is abbreviate | omitted by attaching | subjecting the same number.

FIG. 8 is an explanatory diagram showing a part of the capacitive load driving circuit 200 of the third embodiment. As shown in the figure, in the capacitive load driving circuit 200 of the third embodiment, the MCOM output from the modulation circuit 230 is a signal for driving the FET 1 (FET M1 driving MCOM), and the FET 2.
Signal for driving FET2 (MCOM for driving FET2) and signal for driving FET3 (
And is supplied to the digital power amplifier 240 separately. Among these, the MCOM for driving the FET1 is connected to the digital power amplifier 240 via the switch SW1, and the MCOM for driving the FET2 is connected to the digital power amplifier 240 via the switch SW2.

Furthermore, a switch selection circuit 235 is mounted on the capacitive load driving circuit 200 of the third embodiment. As will be described in detail later, the switch selection circuit 235 is a drive waveform signal generation circuit 210.
When WCOM is received, the FET1 selection signal or the FET2 selection signal is output.
When the FET1 selection signal is output, the switch SW1 is turned ON and the FE
The MCOM for driving T1 and the MCOM for driving FET3 are supplied to the digital power amplifier 240. As a result, in the digital power amplifier 240, power amplification is performed using the FET1 and the FET3. When the FET2 selection signal is output from the switch selection circuit 235, the switch SW2 is turned on, and the MCOM for driving the FET2 and the MCOM for driving the FET3.
COM is supplied to the digital power amplifier 240. As a result, the digital power amplifier 24
At 0, power amplification is performed using FET2 and FET3. The switch selection circuit 235 of the third embodiment corresponds to “determination means” in the present invention.

FIG. 9 is a flowchart of a selection signal output process performed for the switch selection circuit 235 of the third embodiment to output a selection signal. In the selection signal output processing, first, WCOM (drive waveform signal) output from the drive waveform signal generation circuit 210 is read (step S).
100). Subsequently, the on-duty ratio of MCOM is calculated from the read WCOM (step S102). The on-duty ratio of MCOM can be calculated by dividing the voltage value of MCOM by Vdd, where Vdd is the voltage of power supply Vdd of digital power amplifier 240. When the on-duty ratio is displayed as a percentage, the divided value may be further multiplied by 100.

Next, it is determined whether or not the calculated on-duty ratio is equal to or greater than a predetermined threshold (for example, 95%) (step S104). As a result, when the calculated on-duty ratio is smaller than the threshold (step S104: no), the FET1 selection signal is output (step S106).
). On the other hand, if the calculated on-duty ratio is greater than or equal to the threshold value (step S
104: yes), the FET2 selection signal is output (step S108). Thus, FE
When either the T1 selection signal or the FET2 selection signal is output, the process returns to the top, reads WCOM again (step S100), and then performs the above-described series of processes.

As described above with reference to FIG. 5, the capacitor BS mounted on the switch drive circuit 242.
C is not charged unless FET1 is OFF and FET2 is ON. Conversely, discharging is performed little by little while FET1 is ON and FET2 is OFF. Therefore, when the on-duty ratio of MCOM becomes too high, the capacitor BSC is discharged with respect to the time when the capacitor BSC is discharged (that is, the time when the FET1 is ON and the FET2 is OFF).
The time to charge the SC (that is, the time when the FET1 is OFF and the FET2 is ON) becomes too short, and the voltage stored in the capacitor BSC decreases, and the FET1 is turned ON.
Can not be. However, in the third embodiment described above, when the on-duty ratio of MCOM becomes larger than the threshold value (for example, 95%), the FET2 selection signal is output, so that FET2 is driven from the state where FET1 is driven. Switch to state. As described above, the FET 2 is configured by using a P-channel MOSFET, and can be driven without using a bootstrap capacitor such as the capacitor BSC. For this reason, even when the on-duty ratio of MCOM is close to the upper limit, the digital power amplifier 240 can perform power amplification and drive the piezoelectric element 116 appropriately.

In the third embodiment described above, the MCOM on-duty ratio is calculated based on the WCOM output from the drive waveform signal generation circuit 210, and the FET 1 is driven based on the calculated value (outputs the FET 1 selection signal). Case) and the case of driving the FET 2 (when outputting the FET 2 selection signal). For this reason, it is not necessary to detect the voltage between the terminals of the capacitor BSC as in the second embodiment, and it is not necessary to mount an operational amplifier.

In the third embodiment described above, WCOM is once converted into the MCOM on-duty ratio, and the obtained on-duty ratio is compared with a threshold value. However, as described above, there is a one-to-one correspondence between WCOM and the on-duty ratio of MCOM, and the value of WCOM at which the on-duty ratio exceeds the threshold value can be obtained in advance.
Therefore, this value may be stored as a threshold value, and this threshold value may be compared with WCOM. If WCOM is smaller than this threshold, an FET1 selection signal is output, and conversely, WC
When OM is larger than this threshold, an FET2 selection signal may be output.

In the second and third embodiments described above, the example in which the switch 1 and the switch 2 are switched exclusively is shown. However, when the voltage between the terminals of the BSC is sufficiently high, both the switch 1 and the switch 2 are driven. You may do it. When both switch 1 and switch 2 are ON, switch 1
Therefore, the combined resistance when both the switch 1 and the switch 2 are turned on is lower than the on resistance of the switch 1 and the switch 2. For this reason, when a large current flows through the load, the power loss in the digital power amplifier 240 is reduced, which is more preferable.

Although the capacitive load drive circuit 200 of various embodiments has been described above, the present invention is not limited to all the embodiments described above, and can be implemented in various modes without departing from the scope of the invention. . For example, when a pulse voltage is applied to the capacitive load, the capacitive load driving circuit 200 of the present invention can be suitably used without making the smoothing filter 250 an essential component. Further, by using the circuit wiring pattern or the parasitic inductance or parasitic capacitance of the circuit element as the L component or C component of the smoothing filter 250, the smoothing filter may not be an essential component.

Further, as an example that can be suitably applied, since the ejection nozzle that ejects ink with an inkjet printer uses a piezoelectric element as an actuator, the capacitive load drive circuit 200 that drives the piezoelectric element of the ejection nozzle can also be used. It can be suitably applied. Alternatively, the capacitive load driving circuit of the present invention is also applied to a capacitive load driving circuit for driving various electronic devices including medical devices such as a fluid ejection device used for forming a microcapsule containing a medicine or a nutrient. The load driving circuit 200 can be suitably applied.

DESCRIPTION OF SYMBOLS 100 ... Fluid injection apparatus, 110 ... Pulsation generation | occurrence | production part, 111 ... Nozzle,
112 ... Fluid ejection pipe, 113 ... Second case, 114 ... First case,
115 ... Fluid chamber, 116 ... Piezoelectric element, 120 ... Fluid supply means,
121 ... 1st connection tube, 122 ... 2nd connection tube, 123 ... Fluid container,
130 ... Control unit, 150 ... Wiring cable,
200: Capacitive load drive circuit, 210 ... Drive waveform signal generation circuit,
230 ... Modulation circuit, 235 ... Switch selection circuit, 240 ... Digital power amplifier,
242 ... Switch drive circuit, 250 ... Smooth filter, 342 ... Switch drive circuit

Claims (6)

A drive waveform signal generating circuit for generating a drive waveform signal;
A modulation circuit that generates a modulation signal by pulse-modulating the drive waveform signal;
A digital power amplifier that amplifies the modulated signal to generate a power amplified modulated signal;
A smoothing filter that generates a drive signal by smoothing the power amplification modulation signal;
With
The digital power amplifier is:
A first voltage source;
A first switch connected in series with the first voltage source;
A second switch connected in series with the first switch;
A second voltage generation source connected in series with the second switch and generating a voltage lower than a voltage generated by the first voltage generation source;
A switch driving circuit for driving the first and second switches based on the modulation signal,
The first switch includes a switch based on an N-channel MOSFET and a switch based on a P-channel MOSFET connected in parallel with the switch based on the N-channel MOSFET.
The switch driving circuit has a bootstrap capacitor that stores electric charge during a period in which the second switch is ON,
When turning on the first switch, the switch by the N-channel MOSFET is turned on by the electric charge stored in the bootstrap capacitor, and the switch by the N-channel MOSFET is turned on by the electric charge stored in the bootstrap capacitor. A capacitive load drive circuit that turns on the switch by the P-channel MOSFET. In the capacitive load driving circuit according to claim 1,
The switch driving circuit detects a voltage of the bootstrap capacitor and turns on one of the switch by the N-channel MOSFET and the switch by the P-channel MOSFET according to the detected voltage. Driving circuit. In the capacitive load driving circuit according to claim 1,
Based on the drive waveform signal, a determination means for determining which of the switch by the N-channel MOSFET or the switch by the P-channel MOSFET is to be turned ON,
The switch drive circuit is a capacitive load drive circuit in which one of a switch by the N-channel MOSFET and a switch by the P-channel MOSFET is turned on based on a result determined by the determination means. In the capacitive load driving circuit according to claim 1,
Capacitive load driving in which the first switch is turned on , and when the switch by the N-channel MOSFET is turned on by the charge stored in the bootstrap capacitor, the switch by the P-channel MOSFET is also turned on. circuit. In the capacitive load driving circuit according to claim 1,
Capacitive load drive in which the first switch is turned on, and when the N-channel MOSFET switch is turned on by the charge stored in the bootstrap capacitor, the P-channel MOSFET switch is turned off. circuit. A capacitive load driving circuit according to any one of claims 1 to 5,
Fluid supply means for supplying a fluid;
A fluid chamber into which the fluid supplied from the fluid supply means flows;
An actuator that is a capacitive load;
An injection nozzle for injecting the fluid that has flowed into the fluid chamber,
A fluid ejecting apparatus in which a drive signal output from the capacitive load driving circuit is applied to the actuator, whereby fluid flowing into the fluid chamber is ejected in a pulse form from the ejecting nozzle.

Images