JPH11204850A - Piezo-driving circuit - Google Patents
Piezo-driving circuitInfo
- Publication number
- JPH11204850A JPH11204850A JP10014786A JP1478698A JPH11204850A JP H11204850 A JPH11204850 A JP H11204850A JP 10014786 A JP10014786 A JP 10014786A JP 1478698 A JP1478698 A JP 1478698A JP H11204850 A JPH11204850 A JP H11204850A
- Authority
- JP
- Japan
- Prior art keywords
- switching element
- power supply
- piezo
- low
- piezo drive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 2
- 230000000153 supplemental effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 16
- 230000007704 transition Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/802—Circuitry or processes for operating piezoelectric or electrostrictive devices not otherwise provided for, e.g. drive circuits
Landscapes
- Generation Of Surge Voltage And Current (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ピエゾ圧電素子の
駆動回路に関し、特にピエゾ圧電素子を用いたインクジ
ェットプリンタ等のヘッド駆動装置に用いて好適とされ
る低消費電力化を図るピエゾ駆動回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a piezo element, and more particularly to a piezo driving circuit suitable for use in a head driving apparatus such as an ink jet printer using the piezo element for reducing power consumption. .
【０００２】[0002]
【従来の技術】この種のピエゾ圧電素子の駆動回路の従
来技術として例えば特開平４−１１３８５０号公報、特
開平５−２１８５６号公報等が参照される。図９に、従
来のピエゾ圧電素子の駆動波形発生回路の一例をブロッ
ク図にて示す。図９を参照すると、基準波形発生回路、
電流増幅回路を備え、電流増幅回路の出力をピエゾ圧電
素子駆動波形としている。2. Description of the Related Art Japanese Patent Application Laid-Open Nos. 4-113850 and 5-21856 are referred to as prior art of a driving circuit for a piezoelectric element of this kind. FIG. 9 is a block diagram showing an example of a conventional driving waveform generating circuit for a piezoelectric element. Referring to FIG. 9, a reference waveform generation circuit,
A current amplifying circuit is provided, and the output of the current amplifying circuit is a piezo piezoelectric element driving waveform.
【０００３】基準波形発生回路で生成したピエゾ駆動波
形を電流増幅回路で必要な分だけピエゾに電流を供給す
る。図１０は、図９に示した回路構成をトランジスタレ
ベルで示した図である（特開平５−７７４５６号公報等
参照）。The piezo drive waveform generated by the reference waveform generation circuit is supplied to the piezo by a current amplifier circuit as needed. FIG. 10 is a diagram showing the circuit configuration shown in FIG. 9 at the transistor level (see Japanese Patent Application Laid-Open No. 5-77456, etc.).
【０００４】図１１の（ａ）はピエゾ駆動波形を、
（ｂ）は図１０の電流増幅回路のバイポーラトランジス
タＴｒ１のコレクタ電流ｉ１、（ｃ）は図１０のバイポ
ーラトランジスタＴｒ２のコレクタ電流ｉ２である。バ
イポーラトランジスタＴｒ１、２で発生するエネルギー
はそれぞれ、Ｐ１＝（Ｖｈ−Ｖｐｚｔ）×ｉ１、 Ｐ２
＝Ｖｐｚｔ×ｉ２となり、図１１の（ｄ）、（ｅ）のよ
うになる。FIG. 11A shows a piezo drive waveform,
(B) is the collector current i1 of the bipolar transistor Tr1 of the current amplifier circuit of FIG. 10, and (c) is the collector current i2 of the bipolar transistor Tr2 of FIG. The energy generated by the bipolar transistors Tr1 and Tr2 is P1 = (Vh−Vpzt) × i1 and P2, respectively.
= Vpzt × i2, as shown in (d) and (e) of FIG.
【０００５】[0005]
【発明が解決しようとする課題】これらの発生エネルギ
ーは全てトランジスタからの発熱となるので、定格の大
きなトランジスタを採用したり、ヒートシンクを付けた
りして対策していた。Since all of the generated energy is generated by the transistor, measures have been taken by using a transistor with a high rating or attaching a heat sink.
【０００６】したがって、本発明は、上記問題点に鑑み
てなされたものであって、その目的は、低消費電力を低
減し、トランジスタからの発熱を低減可能とし、小型化
を達成するピエゾ駆動回路を提供することにある。SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to reduce the power consumption, reduce the heat generated from the transistors, and achieve the miniaturization of a piezo drive circuit. Is to provide.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
に、本発明は、高電位電源と低電位電源間に第１、及び
第２のスイッチング素子を直列形態に接続し、前記第
１、及び第２のスイッチング素子の制御端子にＰＷＭ変
調した信号を相補的に供給して交互にオン・オフさせ、
前記第１、第２のスイッチング素子の接続点から低域通
過フィルタを介してピエゾ駆動波形を出力する。In order to achieve the above object, the present invention comprises connecting a first and a second switching element in series between a high potential power supply and a low potential power supply, And supplying a PWM-modulated signal complementarily to the control terminal of the second switching element to alternately turn on and off.
A piezo drive waveform is output from a connection point of the first and second switching elements via a low-pass filter.
【０００８】[0008]
【発明の実施の形態】本発明のピエゾ駆動回路は、その
好ましい実施の形態において、高電位電源と低電位電源
の間に直列に接続された二つのスイッチング素子１、２
を設け、それらをＰＷＭ変調した信号で交互にオン、オ
フして、得られたパルス波形の高周波成分をフィルタ４
で除去してピエゾ駆動波形を生成するものであり、ピエ
ゾ駆動回路部での電力損失を低減するようにしたもので
ある。以下実施例に即して詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment, a piezo drive circuit according to the present invention comprises two switching elements 1, 2 connected in series between a high potential power supply and a low potential power supply.
Are turned on and off alternately by a PWM-modulated signal, and the high-frequency component of the obtained pulse waveform is filtered by a filter 4.
To generate a piezo drive waveform, thereby reducing power loss in the piezo drive circuit. Hereinafter, the present invention will be described in detail with reference to examples.
【０００９】[0009]
【実施例】本発明の実施例について図面を参照して以下
に説明する。図１は、本発明の一実施例の構成を示す図
である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.
【００１０】図１を参照すると、スイッチング素子１は
高電位側電源（高圧側電源）とスイッチング素子２のと
の間に接続され、スイッチング素子２との接続点（Ａ
点）と高圧側電源の接続、切断を行う。スイッチング素
子２のは低電位側電源（低圧側電源）とスイッチング素
子１との間に接続され、Ａ点と低圧側電源の接続、切断
を行う。Referring to FIG. 1, a switching element 1 is connected between a high potential side power supply (high voltage side power supply) and a switching element 2 and has a connection point (A
Point) and the high-side power supply. The switching element 2 is connected between the low-potential power supply (low-voltage power supply) and the switching element 1, and connects and disconnects the point A with the low-voltage power supply.
【００１１】スイッチング素子１、２の制御端子にはＰ
ＷＭ（パルス幅変調）コントローラ３の出力が接続さ
れ、オン・オフ制御が行われる。The control terminals of the switching elements 1 and 2 have P
The output of the WM (pulse width modulation) controller 3 is connected, and on / off control is performed.
【００１２】フィルタ４はスイッチング素子１とスイッ
チング素子２の接続点（Ａ点）に接続され、Ａ点に発生
するパルス出力の高周波成分を除去し、低周波成分のみ
を出力端子に伝達する。The filter 4 is connected to a connection point (point A) between the switching element 1 and the switching element 2 and removes a high-frequency component of a pulse output generated at the point A, and transmits only a low-frequency component to an output terminal.
【００１３】図２は、図１におけるスイッチング素子の
詳細な構成を示した図であり、スイッチング素子１とス
イッチング素子２にＮチャネルＭＯＳ−ＦＥＴを用いた
ものである。スイッチング素子１、スイッチング素子２
には電力損失を低減するために、オン抵抗が小さくスイ
ッチング速度の速いＭＯＳ−ＦＥＴを使用するのが望ま
しい。FIG. 2 is a diagram showing a detailed configuration of the switching element in FIG. 1, in which N-channel MOS-FETs are used for the switching elements 1 and 2. Switching element 1, switching element 2
In order to reduce the power loss, it is desirable to use a MOS-FET having a small ON resistance and a high switching speed.
【００１４】スイッチング素子１は、そのゲート端子が
ＰＷＭコントローラ３の出力に、ドレイン端子が高圧側
電源に、ソース端子がスイッチング素子２のドレイン端
子にそれぞれ接続されている。スイッチング素子２は、
そのゲート端子がＰＷＭコントローラ３の出力に、ドレ
イン端子がスイッチング素子１のソース端子に、ソース
端子が低圧側電源にそれぞれ接続されている。The switching element 1 has a gate terminal connected to the output of the PWM controller 3, a drain terminal connected to the high-voltage power supply, and a source terminal connected to the drain terminal of the switching element 2. The switching element 2 is
The gate terminal is connected to the output of the PWM controller 3, the drain terminal is connected to the source terminal of the switching element 1, and the source terminal is connected to the low voltage side power supply.
【００１５】ＰＷＭコントローラ３は、スイッチング素
子１およびスイッチング素子２のオン・オフをＰＷＭ制
御で行う。The PWM controller 3 turns on and off the switching elements 1 and 2 by PWM control.
【００１６】ここで、ＰＷＭの方式について説明する。
ＰＷＭ（Ｐｕｌｓｅ Ｗｉｄｅ Ｍｏｄｕｌａｔｉｏ
ｎ）制御はスイッチング素子のオン／オフを制御信号の
パルスの幅で変調する。図２を参照すると、制御信号が
Highレベルのときにスイッチング素子１、スイッチング
素子２がオンとなり、制御信号がLowレベルのときにス
イッチング素子１、スイッチング素子２がオフとなる。
時間平均のオン時間を短くしたいときは短時間の制御信
号パルスを、長くしたいときは長時間の制御信号パルス
を出力する。Here, the PWM method will be described.
PWM (Pulse Wide Modulatio)
n) The control modulates on / off of the switching element by a pulse width of the control signal. Referring to FIG. 2, the control signal is
When the control signal is at the low level, the switching elements 1 and 2 are turned off.
To shorten the time averaged ON time, a short-time control signal pulse is output, and to lengthen it, a long-time control signal pulse is output.
【００１７】フィルタ４はインダクタンスＬとキャパシ
タンスＣで構成され、Ａ点のパルス出力の高周波成分を
取り除き低周波成分のみを出力端子に伝達する。The filter 4 is composed of an inductance L and a capacitance C, and removes the high-frequency component of the pulse output at point A and transmits only the low-frequency component to the output terminal.
【００１８】本発明の一実施例の動作について説明す
る。以下では、図３に示す電圧波形が、目的のピエゾ駆
動波形であるものとして説明する。図４は、本発明の一
実施例を説明するためのタイミングチャートであり、Ｐ
ＷＭコントローラの出力、Ａ点の電圧波形を示す図であ
る。The operation of one embodiment of the present invention will be described. Hereinafter, the description will be made assuming that the voltage waveform shown in FIG. 3 is a target piezo drive waveform. FIG. 4 is a timing chart for explaining one embodiment of the present invention.
FIG. 5 is a diagram illustrating an output of a WM controller and a voltage waveform at a point A.
【００１９】高圧側電源には駆動波形の最大電圧Ｖhigh
を入力し、低圧側電源はＧＮＤ（グランド）に接続す
る。回路の初期状態ではスイッチング素子２がオンにな
っているので、Ａ点の電位はＧＮＤレベルとなる。The high voltage side power supply has the maximum voltage Vhigh of the drive waveform.
And the low-voltage side power supply is connected to GND (ground). Since the switching element 2 is turned on in the initial state of the circuit, the potential at the point A becomes the GND level.
【００２０】図３の駆動波形を得るために、スイッチン
グ素子１、スイッチング素子２のＰＷＭ制御を行う。Ｐ
ＷＭコントローラー３の出力として図４（ａ）に示すよ
うな制御信号をスイッチング素子１のゲート端子に加
え、図４（ｂ）に示すような制御記号をスイッチング素
子２のゲート端子に加える。In order to obtain the driving waveform shown in FIG. 3, PWM control of the switching elements 1 and 2 is performed. P
As an output of the WM controller 3, a control signal as shown in FIG. 4A is applied to the gate terminal of the switching element 1, and a control symbol as shown in FIG.
【００２１】図４の制御信号（ａ）、（ｂ）はスイッチ
ング素子１とスイッチング素子２が排他的にオンするよ
うになるような相補信号となっているので、スイッチン
グ素子１がオンのときはスイッチング素子２がオフ、ス
イッチング素子１がオフのときはスイッチング素子２が
オンとなる。Since the control signals (a) and (b) in FIG. 4 are complementary signals such that the switching element 1 and the switching element 2 are exclusively turned on, when the switching element 1 is turned on, When the switching element 2 is off and the switching element 1 is off, the switching element 2 is on.
【００２２】スイッチング素子１がオンの時はＡ点の電
圧は高圧側電源（Ｖｈｉｇｈ）まで上昇し、次に時間ｔ
経過後にスイッチング素子１がオフになると同時にスイ
ッチング素子２がオンになると、Ａ点の電圧は低圧側電
源（ＧＮＤ）まで下降する。When the switching element 1 is on, the voltage at the point A rises to the high voltage side power supply (Vhigh), and then the time t
When the switching element 2 is turned on at the same time as the switching element 1 is turned off after the lapse of time, the voltage at the point A falls to the low voltage side power supply (GND).
【００２３】このようにして、Ａ点には図４（ｃ）に示
すようなパルス波形が発生する。In this way, a pulse waveform as shown in FIG. 4C is generated at the point A.
【００２４】スイッチング素子１、スイッチング素子２
にオン抵抗の小さいＭＯＳ−ＦＥＴを用いると、スイッ
チング素子１、スイッチング素子２に電流が流れたとき
にここで発生する損失を小さく押えることができる。Switching element 1, switching element 2
When a MOS-FET having a small on-resistance is used, the loss that occurs when a current flows through the switching elements 1 and 2 can be reduced.
【００２５】図５に、図２のスイッチング素子１（ＣＮ
チャネルＭＯＳ−ＦＥＴ）を示す。スイッチング素子１
に流れる電流をｉＤ、スイッチング素子１のドレインと
ソース間に加わる電圧をＶｄｓとする。FIG. 5 shows the switching element 1 (CN
Channel MOS-FET). Switching element 1
Is iD, and the voltage applied between the drain and the source of the switching element 1 is Vds.
【００２６】図６に、図５に示したスイッチング素子１
がオフからオンになりさらにオフになる状態を、ｉＤ、
Ｖｄｓ及びこれらの積で表わされるエネルギーをＰで示
す。図６を参照して、スイッチング素子１部のｉＤ、Ｖ
ｄｓ、Ｐについて説明する。FIG. 6 shows the switching element 1 shown in FIG.
The state in which i is turned on from off and then turned off is iD,
The energy represented by Vds and their product is denoted by P. With reference to FIG. 6, iD, V
ds and P will be described.
【００２７】スイッチング素子１がオフのときｉＤは０
であり、Ｖｄｓ＝高圧側電源電圧となっている。When switching element 1 is off, iD is 0
And Vds = high-side power supply voltage.
【００２８】Ｐ＝ｉＤ×Ｖｄｓで表せるので、この時の
Ｐは０となる。Since P = iD × Vds, P becomes 0 at this time.
【００２９】スイッチング素子１がオフからオンへの遷
移状態にある時は、Ｖｄｓが減少しつつｉＤが増加する
ので、このときにＰのピークが現れる。When the switching element 1 is in a transition state from off to on, iD increases while Vds decreases. At this time, a peak of P appears.
【００３０】スイッチング速度の速いＭＯＳ−ＦＥＴを
用いると、Ｖｄｓ、ｉＤの立上りと立ち下がりの時間が
速くなるので、スイッチング時の損失を低減することが
できる。When a MOS-FET having a high switching speed is used, the rise and fall times of Vds and iD are shortened, so that the loss at the time of switching can be reduced.
【００３１】スイッチング素子１がオンのときは、スイ
ッチング素子１のオン抵抗Ｒｏｎと流れる電流ｉＤによ
り、ドレイン・ソース間電圧Ｖｄｓ＝ｉＤ×Ｒｏｎが発
生する。When the switching element 1 is on, a drain-source voltage Vds = iD × Ron is generated by the ON resistance Ron of the switching element 1 and the current iD flowing.
【００３２】Ｐ＝Ｖｄｓ×ｉＤであるが、オン抵抗Ｒｏ
ｎが十分に小さいＦＥＴを選択すればＰを小さくするこ
とができる。P = Vds × iD, but the ON resistance Ro
If an FET with sufficiently small n is selected, P can be reduced.
【００３３】次にスイッチング素子１がオンからオフへ
の遷移状態にある時は、Ｖｄｓが増加しつつｉＤが減少
するので、このときにもＰのピークが現れる。Next, when the switching element 1 is in a transition state from on to off, iD decreases while Vds increases, so that a peak of P also appears at this time.
【００３４】最後にスイッチング素子１がオフになると
ｉＤ＝０となり、再度Ｐが０となる。Finally, when the switching element 1 is turned off, iD = 0, and P becomes 0 again.
【００３５】次にＡ点に発生した図４（ｃ）のパルス出
力電圧をフィルタ４により高周波成分を除去する。フィ
ルタ４はインダクタンスＬとキャパシタンスＣで構成さ
れる。Next, high frequency components are removed by the filter 4 from the pulse output voltage of FIG. The filter 4 includes an inductance L and a capacitance C.
【００３６】インダクタンスＬのインピーダンスは２π
ｆＬ、キャパシタンスＣのインピーダンスは１／（２π
ｆＣ）で表されるので、周波数ｆの大きい成分はインダ
クタンスＬを通りにくく、キャパシタンスＣを通りやす
いので、フィルター４の後段には高周波成分が伝達しな
い。The impedance of the inductance L is 2π
fL, the impedance of the capacitance C is 1 / (2π
Since the frequency f is represented by fC), a component having a large frequency f does not easily pass through the inductance L and easily passes through the capacitance C. Therefore, no high-frequency component is transmitted to the subsequent stage of the filter 4.
【００３７】ＬとＣの定数を適切に選ぶことで、Ａ点の
パルス出力の高周波成分を除去することができ、図３の
ピエゾ駆動波形を得ることが出来る。By appropriately selecting the constants of L and C, the high frequency component of the pulse output at point A can be removed, and the piezo drive waveform shown in FIG. 3 can be obtained.
【００３８】スイッチング素子１、スイッチング素子２
のオン，オフの間隔を制御することにより、任意の単位
時間当たりの傾斜をもったピエゾ駆動波形を生成でき
る。Switching element 1, switching element 2
By controlling the on / off interval of the piezo, a piezo drive waveform having an arbitrary slope per unit time can be generated.
【００３９】本発明の他の実施例について説明する。高
周波を遮断するフィルタ４は、図７に示すように、キャ
パシタンスＣやインダクタンスＬを単体で用いたり、あ
るいはＬとＣを組み合わせて使用することができる。ま
たフィルタ４を取った場合でも配線等の浮遊容量や分布
インダクタンスにより必要なピエゾ駆動波形が得られれ
ば、あえて付ける必要がなくなる。Another embodiment of the present invention will be described. As shown in FIG. 7, the filter 4 that blocks high frequencies can use the capacitance C or the inductance L alone or can use a combination of L and C. Even if the filter 4 is removed, if a necessary piezo drive waveform can be obtained by the stray capacitance or distributed inductance of the wiring or the like, it is not necessary to attach the filter.
【００４０】前記第一の実施例の説明ではスイッチング
素子にＭＯＳ−ＦＥＴを用いて説明したが、高速スイッ
チング用バイポーラトランジスタでも特性が必要な仕様
を満足する物であれば十分に使用可能である。In the above description of the first embodiment, the MOS-FET is used as the switching element. However, a bipolar transistor for high-speed switching can be used as long as it satisfies the required specifications.
【００４１】また前記実施例では、スイッチング素子
１、スイッチング素子２のオン、オフをＰＷＭコントロ
ーラ３を用いたＰＷＭ制御を例にして説明したが、図８
に示すようなＰＤＭ（Ｐｕｌｓｅ Ｄｅｎｓｉｔｙ Ｍ
ｏｄｕｌａｔｉｏｎ；パルス密度変調）制御でもかまわ
ない。ＰＤＭ制御では制御信号が短い時間のパルスの集
まりとなる。また、低圧側電源をＧＮＤとして説明した
が、ここには高圧側電源以下の任意の電圧を加えること
ができる。In the above-described embodiment, the on / off of the switching element 1 and the switching element 2 has been described by way of the PWM control using the PWM controller 3 as an example.
PDM (Pulse Density M)
modulation (pulse density modulation) control. In the PDM control, the control signal is a collection of short-time pulses. Although the low-voltage power supply is described as GND, any voltage lower than the high-voltage power supply can be applied here.
【００４２】[0042]
【発明の効果】以上説明したように、本発明によれば、
スイッチング素子部の電力損失、すなわちスイッチング
素子の発熱を低減することができる。As described above, according to the present invention,
Power loss of the switching element, that is, heat generation of the switching element can be reduced.
【００４３】その理由は、スイッチング素子をオンのと
きは飽和状態、オフのときは遮断領域で使用するためで
ある。すなわち、飽和領域ではスイッチング素子の両端
の電圧Ｖｄｓはほぼ０に等しく、遮断領域ではスイッチ
ング素子に流れる電流ｉＤ＝０であるので、スイッチン
グ素子部での発生エネルギーＰ＝Ｖｇｓ×ｉＤはほぼ図
６で示したスイッチング時の損失だけとなり、従って、
スイッチング素子部での熱の発生を低減することができ
る。The reason is that the switching element is used in a saturation state when it is turned on, and is used in a cutoff area when it is turned off. That is, in the saturation region, the voltage Vds across the switching element is substantially equal to 0, and in the cutoff region, the current iD flowing through the switching element is 0. Therefore, the energy P = Vgs × iD generated in the switching element portion is substantially equal to that in FIG. The only switching losses shown are:
Generation of heat in the switching element portion can be reduced.
【図１】本発明の一実施例の構成を示すブロック図であ
る。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
【図２】本発明の一実施例の回路構成を示す図である。FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.
【図３】ピエゾ駆動波形を示す図である。FIG. 3 is a diagram showing a piezo drive waveform.
【図４】本発明の一実施例におけるタイミング波形を示
す図である。FIG. 4 is a diagram showing a timing waveform in one embodiment of the present invention.
【図５】本発明の一実施例におけるスイッチング素子を
説明するための図である。FIG. 5 is a diagram for explaining a switching element in one embodiment of the present invention.
【図６】本発明の一実施例における電力の推移を示す図
である。FIG. 6 is a diagram showing transition of power in one embodiment of the present invention.
【図７】本発明の一実施例におけるフィルタを説明する
ための図である。FIG. 7 is a diagram illustrating a filter according to an embodiment of the present invention.
【図８】本発明の第二の実施例におけるにおけるタイミ
ング波形を示す図である。FIG. 8 is a diagram showing a timing waveform in a second embodiment of the present invention.
【図９】従来のピエゾ駆動回路の構成を示すブロック図
である。FIG. 9 is a block diagram showing a configuration of a conventional piezo drive circuit.
【図１０】従来のピエゾ駆動回路の回路構成を示す図で
ある。FIG. 10 is a diagram showing a circuit configuration of a conventional piezo drive circuit.
【図１１】従来のピエゾ駆動回路のタイミング波形を示
す図である。FIG. 11 is a diagram showing a timing waveform of a conventional piezo drive circuit.
１、２ スイッチング素子 ３ ＰＷＭコントローラ ４ フィルタ（低域通過フィルタ） 1, 2 switching element 3 PWM controller 4 filter (low-pass filter)
Claims (5)
２のスイッチング素子を直列形態に接続し、 前記第１、及び第２のスイッチング素子の制御端子にＰ
ＷＭ（Pulse WidthModulation；パルス幅変調）方式で
変調した信号を相補的に供給して交互にスイッチングさ
せ、 前記第１、第２のスイッチング素子の接続点から低域通
過フィルタを介してピエゾ駆動波形を出力することを特
徴とするピエゾ駆動回路。A first switching element connected in series between a high-potential power supply and a low-potential power supply; and a control terminal connected to the control terminal of the first and second switching elements.
A signal modulated by a WM (Pulse Width Modulation) method is supplied complementarily and alternately switched, and a piezo driving waveform is connected from a connection point of the first and second switching elements via a low-pass filter. A piezo drive circuit characterized by outputting.
接続された第１、及び第２のＭＯＳトランジスタと、 前記第１、及び第２のＭＯＳトランジスタの接続点に接
続された低域通過フィルタと、 互いに相補のＰＷＭ（Pulse Width Modulation；パル
ス幅変調）変調信号を出力するＰＷＭコントローラと、 を備え、 前記第１、及び第２のＭＯＳトランジスタのゲート端子
に前記ＰＷＭコントローラの出力を供給して交互にスイ
ッチングさせ、前記低域通過フィルタを介してピエゾ駆
動波形を出力することを特徴とするピエゾ駆動回路。2. A first and a second MOS transistor, which are push-pull connected between a high potential power supply and a low potential power supply, and a low pass connected to a connection point between the first and second MOS transistors. And a PWM controller that outputs complementary PWM (Pulse Width Modulation) signals. The PWM controller supplies an output of the PWM controller to gate terminals of the first and second MOS transistors. A piezo drive circuit that alternately switches the piezo drive waveform through the low-pass filter.
２のスイッチング素子を直列形態に接続し、 前記第１、及び第２のスイッチング素子の制御端子にＰ
ＤＭ（Pulse DensityModulation；パルス密度変調）方
式で変調した信号を交互に供給してスイッチングさせ、 前記第１、及び第２のスイッチング素子の接続点から低
域通過フィルタを介してピエゾ駆動波形を出力すること
を特徴とするピエゾ駆動回路。3. A first and a second switching element are connected in series between a high-potential power supply and a low-potential power supply, and a control terminal of the first and second switching elements is connected to a P terminal.
A signal modulated by a DM (Pulse Density Modulation) method is alternately supplied and switched, and a piezo driving waveform is output from a connection point of the first and second switching elements via a low-pass filter. A piezo drive circuit, characterized in that:
オン抵抗の小さなＭＯＳトランジスタであることを特徴
とする請求項１又は３記載のピエゾ駆動回路。4. The first and second switching elements are:
4. The piezo drive circuit according to claim 1, wherein the piezo drive circuit is a MOS transistor having a small on-resistance.
ＯＳトランジスタ又はバイポーラトランジスタで構成し
たことを特徴とする請求項１又は３記載のピエゾ駆動回
路。5. The method according to claim 1, wherein the first and second switching elements are M
4. The piezo drive circuit according to claim 1, wherein the piezo drive circuit is constituted by an OS transistor or a bipolar transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10014786A JPH11204850A (en) | 1998-01-09 | 1998-01-09 | Piezo-driving circuit |
| DE19900474A DE19900474A1 (en) | 1998-01-09 | 1999-01-08 | Piezo drive circuit for inkjet printer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10014786A JPH11204850A (en) | 1998-01-09 | 1998-01-09 | Piezo-driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11204850A true JPH11204850A (en) | 1999-07-30 |
Family
ID=11870749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10014786A Pending JPH11204850A (en) | 1998-01-09 | 1998-01-09 | Piezo-driving circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11204850A (en) |
| DE (1) | DE19900474A1 (en) |
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1999
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| Publication number | Publication date |
|---|---|
| DE19900474A1 (en) | 1999-07-22 |
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