JP5763465B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine provided with fraud prevention means for preventing an illegal jackpot.

  Conventionally, pachinko machines, which are a type of gaming machine, have been provided with a fraudulent board (also referred to as a hanging board) in the machine, and fraudulent acts are sometimes performed. Specifically, after the power is turned on, the time from the rise of the INT signal of the power-on initial command output from the main control board until the big hit determination random number becomes the big hit determination value is constant. For this reason, there is a possibility that a fraudulent board that illegally generates a big hit is attached by specifying the time (big hit occurrence timing) until the big hit determination value is triggered by the illegal board reading the rising edge of the INT signal. It was. As a result, at the game store, a big hit is given to a player who has performed an illegal act, and there is a possibility that a disadvantage may be obtained.

  In view of this, a pachinko machine has been proposed that can prevent fraud due to an illegal board that causes an illegal jackpot based on a control signal output from a main control board to a peripheral board (for example, Patent Document 1). In the pachinko machine described in Patent Document 1, the time from the rise of the INT signal of the power-on initial command output from the main control board after turning on the power is not constant until the big hit judging random number becomes the big hit judging value. I am doing so. Accordingly, it is possible to identify the time (big hit occurrence timing) until the big hit determination value is triggered by the illegal board reading the rising edge of the INT signal, thereby preventing illegal big hits from occurring.

  By the way, in Patent Document 1, the INT signal is output every time the control signal starts to be output regardless of the power-on initial command. On the other hand, the fraud prevention circuit on the main control board did not delay the output timing except when the first INT signal was output after the power was turned on. This is because if all the INT signals and the output of the subsequent control signal are delayed, a bug may occur due to the delay of the control signal depending on the program.

  For this reason, there is a possibility that a fraudulent board that stops the power supply from the backup power supply to the RAM (storage means) in which the random number for determining the big hit is stored is attached and the fraud may be performed. Specifically, when the unauthorized board stops the power supply from the backup power supply to the RAM, the stored contents of the RAM (random number for jackpot determination) can be forcibly initialized. When the stored contents are initialized, the CPU of the main control board outputs an INT signal to the effect control board indicating that a game is possible. At this time, since the power supply voltage from the operating power supply that supplies the power supply voltage other than the RAM is not cut off, the fraud prevention circuit determines that it is not the first INT signal after the power is turned on, and the output timing of the INT signal Is not delayed. For this reason, there is a possibility that the time until the big hit determination value (big hit occurrence timing) can be specified when the illegal substrate reads the rising edge of the INT signal.

  Therefore, in recent years, it has been considered that the power supply voltage is supplied to the RAM from other than the backup power supply. According to this, even when the supply of the power supply voltage from the backup power supply is stopped, the RAM can supply the power supply voltage from other than the backup power supply. As a result, with the stop of the supply of the power supply voltage to the RAM, the big hit determination random number is not initialized, and the INT signal and the game start signal subsequent thereto are not output. In other words, it is impossible to measure the time from when the power supply voltage from the backup power supply is shut off until the output of the INT signal (timing that is a big hit), and it is not possible to specify the timing for generating an illegal big hit. To prevent fraud.

JP 2009-183539 A

  Incidentally, when the main control board inputs a power-off signal notifying that the power supply voltage has become a predetermined value or less, the main control board prohibits access to the RAM and backs up the control information of the RAM. Thereafter, the main control board stands by until a reset signal output when the power supply voltage becomes a predetermined value or less is input, and the operation is restricted by the input of the reset signal. As a result, the main control board can perform backup when the power is shut off.

  However, when the unauthorized board outputs only the power-off signal to the main control board without outputting the reset signal, the main control board remains in the standby state after performing the backup. If the main control board remains in the standby state, the main control board resets itself after a predetermined time by the function of the watchdog timer. Aiming at the time when the reset is performed, when the illegal board outputs a RAM clear signal, the stored contents of the RAM are initialized. After that, the CPU of the main control board starts to update the random number for jackpot determination from the state in which the stored contents of the RAM are initialized, and outputs the INT signal to control the control signal indicating that the game is possible It will output to the substrate. At this time, since the power supply voltage from the operating power supply that supplies the power supply voltage other than the RAM is not cut off, the fraud prevention circuit determines that it is not the first INT signal after the power is turned on, and the output timing of the INT signal Is not delayed. For this reason, there is a possibility that the time until the big hit determination value (big hit occurrence timing) can be specified when the illegal substrate reads the rising edge of the INT signal.

  The present invention has been made paying attention to such problems existing in the prior art, and its purpose is to prevent fraud that generates a big hit based on a control signal output from the main control board. An object of the present invention is to provide a gaming machine provided with prevention means.

In order to achieve the above object, the invention described in claim 1 includes a main control board for controlling the entire gaming machine, and an effect control means for controlling the effect execution means based on a control signal from the main control board. In the gaming machine, the main control board updates the value of the jackpot determination random number every predetermined cycle after starting, stores the updated value of the jackpot determination random number in the storage means, and can play the game. In some cases, when the game start state signal for informing that the game is possible by starting the update of the jackpot determination random number is output, while the game start signal instructing the start of the control related to the game effect is input, The control signal output to the effect control means is started, and control related to the game effect is started, and the value of the random number for jackpot determination obtained from the storage means when the game ball wins the start winning means is used. A control device that gives a big hit gaming state when the determination result of the big hit determination is affirmative, and an input for inputting an activation instruction signal that instructs activation of the control device And when the activation instruction signal is inputted to the input means and the game ready state signal is inputted, the game start signal is transmitted to the control device after a randomized delay time has elapsed. The control device is in a standby state after inputting a standby instruction signal to enter a standby state until an activation instruction signal is input to the input means, and the input means When the control device is activated based on the activated instruction signal, and when the control device enters a standby state after a predetermined time, a device equivalent to the activation instruction signal is obtained. The being adapted to enter the re-activation instruction signal having said activation instruction signal is a binary signal indicating a first state and a second state as the signal level, the controller inputs the start instruction signal When the signal level is in the first state, the operation is restricted, and when the signal level transitions from the first state to the second state, the control device is configured to be activated. When the standby state is entered until a predetermined time elapses after the standby instruction signal is input, a restart instruction signal in the first state having the same function as the start instruction signal in the first state is input to the input means. And when the input means inputs the restart instruction signal in the first state, the start instruction signal in the first state is output to the control device for a predetermined time, and the operation is restricted. The start instruction signal in the second state is The gist is to start by outputting to the control device .

  According to the present invention, it is possible to prevent fraud that generates a big hit based on a control signal output from the main control board.

The front view which shows the machine surface side of a pachinko machine. The block diagram which shows the structure of a pachinko gaming machine. The flowchart which shows the flow of a main process. The flowchart which shows the flow of a timer interruption process. The flowchart which shows the flow of a standby process. The block diagram which shows the structure of a game start signal generation circuit. The block diagram which shows the structure of an instruction | indication circuit. The timing chart which shows the delay timing of a reset signal and a game start signal. The timing chart which shows the delay timing of a reset signal and a game start signal.

Hereinafter, a first embodiment in which the present invention is embodied in a pachinko gaming machine (hereinafter referred to as a “pachinko machine”) that is a kind of the present invention will be described with reference to FIGS.
In FIG. 1, the front side of the pachinko machine 10 is schematically shown, and a vertical rectangular middle frame 12 for setting various game components is opened and closed on the front side of the opening of the outer frame 11 that forms the outline of the machine body. And is detachably assembled. Further, on the front side of the middle frame 12, a front frame 14 and a top ball tray 15 each having a glass frame for protecting the game board 13 disposed inside the machine in a see-through manner are assembled so as to be openable and closable in a laterally open state. ing. In addition, the front side of the front frame 14 and the game area 13a of the game board 13 are provided with a decoration lamp 40 as an effect execution means that turns on (flashes) or turns off and performs a light emission effect based on the light emission decoration. In addition, a speaker 41 is provided on the front side of the upper ball tray 15 as an effect executing means for outputting various sounds (sound effects) and performing sound effects based on the sound output. A lower ball tray 16 and a launcher 17 are attached to the lower part of the middle frame 12.

  In the approximate center of the game area 13 a of the game board 13, a display device 18 is provided as an effect execution means having a liquid crystal display type variable display H. On the variable display H of the display device 18, a game effect (display effect) based on a varying image (or image display) is performed. Then, on the variable display H of the display device 18, a symbol combination game (symbol variation game) is displayed in which a plurality of types of symbols are varied and displayed in a plurality of columns. In the present embodiment, combinations of three columns of symbols are derived in the symbol combination game, and the types of symbols of each column forming the combination are eight types of 1-8.

  Then, the player can recognize a big hit or loss from the symbol combination finally displayed in the symbol combination game. When the symbols of all the columns displayed on the variable display H are of the same type, the big hit can be recognized from the symbol combination ([222] [777], etc.). The symbol combination that can recognize the jackpot is a jackpot symbol combination. When the jackpot symbol combination is displayed, the player is given a jackpot gaming state. On the other hand, when the symbols of all the columns displayed on the variable display H of the display device 18 are not of the same type, the deviation from the symbol combination ([123] [122] [767] etc.) can be recognized. A symbol combination that can recognize this deviation is a symbol combination that is out of sync.

  Also, below the display device 18, a start winning port 19 is provided as a start winning means including an opening / closing blade that opens and closes by an operation of an actuator (solenoid, motor, etc.) (not shown). A winning detection sensor SE (shown in FIG. 2) for detecting a winning game ball is provided in the back of the start winning opening 19. The start winning opening 19 can give a start condition for the symbol combination game in response to detection of a winning game ball. Also, below the start winning port 19, a large winning port 20 having a large winning port door that is opened and closed by the operation of an actuator (solenoid, motor, etc.) (not shown) is disposed. When the big hit gaming state is given, the big winning opening 20 is opened by the opening operation of the big winning opening door and the game ball can be won, so that the player has a chance to acquire a large number of prize balls. be able to.

Next, the control configuration of the pachinko machine 10 will be described with reference to FIG.
On the back side of the pachinko machine 10, a power supply board 21 that supplies a power source (for example, AC 24 V) of the game hall to various components constituting the pachinko machine 10 is mounted. A main control board 22 for controlling the entire pachinko machine 10 is mounted on the back side of the pachinko machine 10. The main control board 22 executes various processes for controlling the entire pachinko machine 10, performs arithmetic processing on various control signals (control commands) for controlling the game according to the processing results, and outputs the control signals ( Control command). In addition, a sub-control board 23 as an effect control means is mounted on the back side of the machine. The sub-control board 23 is based on the control signal (control command) output from the main control board 22 and the display mode of the variable display H of the display device 18 (display image of symbols, backgrounds, characters, etc.) and the light emission of the decoration lamp 40. The mode (lighting (flashing) / lighting off timing, etc.) and the sound output mode (sound output timing, etc.) of the speaker 41 are controlled. The main control board 22 is accommodated in the case cover and mounted on the back side of the machine so that the unauthorized control board cannot be mounted on the main control board 22 itself.

Hereinafter, specific configurations of the power supply board 21, the main control board 22, and the sub control board 23 will be described.
The power supply board 21 is provided with a power supply circuit 24 as an operation power supply for converting the power supply of the game hall into a power supply voltage V1 (for example, DC 30 V) as a supply voltage to the pachinko machine 10. The power supply circuit 24 is connected to a main control board 22 and a sub control board 23 as an effect control means. Then, the power supply circuit 24 further converts the power supply voltage V1 after the conversion processing into predetermined power supply voltages V2 (5V) and V3 (5V) to be supplied corresponding to the main control board 22 and the sub control board 23. The converted power supply voltages V2 and V3 are supplied to the main control board 22 and the sub control board 23, respectively.

  Further, the power supply substrate 21 is provided with a power supply interruption monitoring circuit 25, and the power supply interruption monitoring circuit 25 is connected to the power supply circuit 24. The power cut-off monitoring circuit 25 monitors the voltage value of the power supply voltage V1 supplied from the power supply circuit 24. That is, the power-off monitoring circuit 25 determines whether or not the power supply voltage V1 has dropped to a predetermined voltage V (for example, DC 20V). The voltage V is a minimum voltage necessary for operating the pachinko machine 10 without causing any trouble in the game. Here, the voltage value of the power supply voltage V1 drops below the voltage V, for example, when the power is turned off (power is turned off) or during a power failure. In this case, since no power is supplied to the pachinko machine 10, the voltage value of the power supply voltage V1 drops below the voltage V. On the contrary, when power is turned on (power is turned on) or when power is restored (restored power), the power is supplied to the pachinko machine 10, so that the voltage rises and the voltage value of the power supply voltage V1 becomes the voltage V. That's it.

  Further, the power supply substrate 21 is provided with a reset signal circuit 26, and the reset signal circuit 26 is connected to the power cut-off monitoring circuit 25. When the determination result is affirmative (that is, the power supply voltage V1 ≦ voltage V), the power-off monitoring circuit 25 sets the power supply voltage V1 to a voltage V or less with respect to the main control board 22 and the reset signal circuit 26. A power-off signal S indicating that it has been lowered is output. The reset signal circuit 26 outputs a reset signal Re to the main control board 22 and the sub control board 23 at the start of power supply (at power-on or power recovery) or at the time of input of the power-off signal S. The operations of the main control board 22 and the sub control board 23 are regulated. The reset signal Re is a binary signal indicating a high level state and a low level state as its signal level. In this embodiment, when the reset signal Re is input (output), the signal level of the reset signal Re is set to a high level state, and when the input (output) of the reset signal Re is stopped, the reset signal Re The signal level is set to a low level state. The reset signal circuit 26 continues the high level state of the reset signal Re for a certain time T1 (for example, about 400 ms to 1800 ms), and then changes the output state of the reset signal Re from the high level state to the low level state. It is supposed to let you.

  The power supply board 21 includes a backup power supply (dedicated power supply) 27 made of, for example, an electric double layer capacitor. The backup power supply 27 is connected to the power supply circuit 24, and a power supply voltage is supplied from the power supply circuit 24 to the backup power supply 27. Further, the power supply board 21 includes a RAM clear switch 36 that is stored and held in the main control board 22 (RAM 22c) and is operated when it is desired to erase various control information (stored contents) that are appropriately rewritten during the operation of the pachinko machine 10. ing. The RAM clear switch 36 receives an operation of the RAM clear switch 36 and outputs to the main control board 22 an initialization instruction signal for instructing erasure (initialization processing) of the stored contents. The RAM clear switch circuit 37 is connected. In the present embodiment, the RAM clear switch 36 is provided on the back side of the machine so that only operations of a game shop clerk are allowed. When the RAM clear switch 36 is operated, an initialization instruction is issued from the RAM clear switch circuit 37. A signal is output. When the power is turned on while operating the RAM clear switch 36 (at the same time as the operation), an initialization instruction signal is output from the RAM clear switch circuit 37 and the initialization process is executed. Accordingly, the RAM clear switch 36 and the RAM clear switch circuit 37 of this embodiment serve as an initialization instruction means for instructing execution of initialization processing when the gaming machine is turned on.

Next, the configuration of the main control board 22 will be described.
The main control board 22 is provided with a main CPU 22a as a control device, a ROM 22b, and a RAM 22c as storage means. A ROM 22b, a RAM 22c, and a winning detection sensor SE are connected to the main CPU 22a. After startup, the main CPU 22a sequentially updates various random number values such as jackpot determination random numbers used for jackpot determination at predetermined intervals (for example, 4 ms), and sets the updated values in the setting area of the RAM 22c. The value before update is rewritten. The ROM 22b stores various control programs (main control program, interrupt processing program, power-off processing program, etc.) for controlling the pachinko machine 10, a plurality of types of variation patterns, and the like. The RAM 22c stores (sets) various information (such as the value of a big hit determination random number) that is appropriately rewritten during the operation of the pachinko machine 10. The main CPU 22a of the present embodiment is connected to an external oscillation circuit 70 that generates and outputs an external clock signal, and updates various random numbers based on the period of the external clock signal output by the external oscillation circuit 70. It is supposed to be.

  The variation pattern is a game effect (display effect, light emission effect, sound effect) from when the symbol starts to change (start of the symbol combination game) to when all the symbols are displayed (the symbol combination game ends). ) Is a base pattern. Further, the plurality of types of variation patterns are classified into variation patterns for a big hit effect and variation patterns for a loss effect. The jackpot effect is an effect that the symbol combination game is developed so as to finally display the symbol combination of the jackpot. The outlier effect is an effect in which the symbol combination game is finally developed so as to display a symbol pattern combination that is out of place.

  In addition, the main CPU 22a takes the predetermined number (4 ms) so that the big hit determination random number can take a numerical value within a predetermined numerical range (for example, all 631 kinds of integers from “0” to “630”). Each time) is incremented by one and updated. Then, the main CPU 22a stores the updated value in the RAM 22c as the value of the jackpot determination random number, and sequentially updates the value of the jackpot determination random number by rewriting the stored value of the jackpot determination random number. It has become. More specifically, the main CPU 22a sets the value (initial value) at the start of updating to “0” which is the minimum value, and in order from the initial value “0” → “1” →... → “629” → “ "630" is incremented by one and updated. When the main CPU 22a reaches “630 (maximum value)” that is the last updated numerical value (final value), the value updated as the value of the jackpot determination random number again ranges from “0” to “630”. The number is updated by adding 1. That is, in the pachinko machine 10 of the present embodiment, the value of the big hit determination random number is sequentially updated by setting the value of the big hit determination random number to “0” to “630” as one cycle of the big hit determination random number. One cycle of update processing is repeatedly executed during operation of the pachinko machine 10.

  The RAM 22c is connected to the backup power supply 27 of the power supply substrate 21. When the power supply voltage V1 (power supply) is cut off (when the voltage drops below the voltage V), the power supply voltage VB (for example, supplied from the backup power supply 27) , DC5V), various control information can be stored and held. This makes it possible to back up the gaming state (game content) when the power is shut off. The RAM 22c is also connected to the power supply circuit 24 separately from the backup power supply 27 so that the power supply voltage V2 is supplied. The RAM 22c is connected to the power supply circuit 24 via a diode (rectifier element) so that the power supply voltage does not flow backward from the backup power supply 27 when the power supply voltage V2 is no longer supplied from the power supply circuit 24. Note that the RAM 22c has inconveniences such as the stored contents cannot be read or the stored contents cannot be maintained normally when the supplied power supply voltage becomes a predetermined voltage V10 (for example, 2V) or less. On the other hand, the RAM 22c can maintain the stored contents normally when a voltage higher than the predetermined voltage V10 is supplied.

  The main control board 22 is provided with a reset input circuit (input means) 22d. The reset input circuit 22d is connected to the reset signal circuit 26 of the power supply substrate 21, and receives the reset signal Re output from the reset signal circuit 26. The reset input circuit 22d is connected to the main CPU 22a, and is configured to be able to input a re-reset signal Re1 that is output when a predetermined time elapses while the main CPU 22a is in a standby state.

  When the reset signal Re is input from the reset signal circuit 26 or when the reset signal Re1 is input from the main CPU 22a, the reset input circuit 22d sends the reset signal Re to the main CPU 22a side (instruction circuit I described later in more detail). ) Is output. The reset input circuit 22d has a time T1 + T2 obtained by adding a predetermined delay time T2 to the time T1 in which the input state of the reset signal Re from the reset signal circuit 26 continues to be in the high level state (with respect to the main CPU 22a). ) The output state of the reset signal Re is set to a high level state. Similarly, the reset input circuit 22d has a time T1 + T2 in which a predetermined delay time T2 is added to a time T1 in which the input state of the re-reset signal Re1 from the main CPU 22a continues the high level state (with respect to the main CPU 22a). ) The output state of the reset signal Re is set to a high level state. The reset input circuit 22d shifts the output state of the reset signal Re from the high level state to the low level state after the time T1 + T2 has elapsed. Note that the operation (control processing) of the main CPU 22a is restricted when the input state of the reset signal Re input via the reset signal circuit 26 becomes a high level state. Therefore, in the present embodiment, the reset signal Re becomes the activation instruction signal. Further, the reset signal Re1 becomes a restart instruction signal.

  The reset input circuit 22d is connected to the main CPU 22a via an instruction circuit I described later, and outputs a reset signal Re to the main CPU 22a via the instruction circuit I. When the input state of the reset signal Re input from the reset input circuit 22d transitions from the low level state to the high level state, the instruction circuit I outputs the reset signal Re output to the main CPU 22a during a random delay time. Is maintained at a low level. Then, the instruction circuit I changes the output state of the reset signal Re output to the main CPU 22a from the low level state to the high level state after the delay time has elapsed. Similarly, when the input state of the reset signal Re input from the reset input circuit 22d transitions from the high level state to the low level state, the instruction circuit I receives the reset signal Re output to the main CPU 22a during a random delay time. The output state is maintained at a high level. Then, the instruction circuit I shifts the output state of the reset signal Re output to the main CPU 22a from the high level state to the low level state after the delay time has elapsed.

  The main control board 22 is provided with a game start signal generation circuit 22e. The game start signal generation circuit 22e is connected to be able to input a game available state signal K1 output from the main CPU 22a via a D-flip flop (D-FF) (not shown). The game start signal generation circuit 22e is connected to the main CPU 22a so as to be able to output a game start signal K2. The game start signal generation circuit 22e outputs the game start signal K2 for a random delay time when the input state of the game ready state signal K1 input first from the start of the transition is changed from the low level state to the high level state. The state is maintained at a low level. Then, the game start signal generation circuit 22e changes the output state of the game start signal K2 from the low level state to the high level state after the delay time has elapsed. The game start signal generation circuit 22e outputs the game start signal K2 for a random delay time when the input state of the game ready state signal K1 input first from the start of the transition is changed from the high level state to the low level state. Maintain state at high level. Then, the game start signal generation circuit 22e changes the output state of the game start signal K2 from the high level state to the low level state after the delay time has elapsed.

  The game start signal generation circuit 22e is connected to the reset input circuit 22d so that the reset signal Re output from the reset input circuit 22d can be input. Note that the reset input circuit 22d receives a reset signal Re from the outside of the main control board 22 (a similar signal (hereinafter referred to as “this signal”) that performs the same function (role) as the reset signal Re output by the unauthorized board. The reset signal Re is output to the game start signal generation circuit 22e when the re-reset signal Re1 is input. The game start signal generation circuit 22e receives a reset signal Re from the reset input circuit 22d (after entering the high level state) and inputs a control signal other than the game enable state signal K1 that was input first. Outputs a control signal without delay. That is, the game start signal generation circuit 22e delays when the input state of the control signals other than the game enable state signal K1 that is input first after the reset signal Re is input transitions from the low level state to the high level state. Instead, the output state of the control signal output to the main CPU 22a is changed from the low level state to the high level state. Similarly, the game start signal generation circuit 22e delays when the input state of the control signal other than the game enable state signal K1 that is input first after the reset signal Re is input transitions from the high level state to the low level state. Without changing the output state of the control signal output to the main CPU 22a from the high level state to the low level state.

  When the main CPU 22a finishes the initialization process and starts updating at least the jackpot determination random number and becomes ready for gaming, the main CPU 22a changes the output state of the game possible state signal K1 from the low level state. Transition to the high level state. Further, when the game start signal K2 transitions from the low level state to the high level state, the main CPU 22a starts outputting a control signal to the sub control board 23.

Next, various processes executed by the main CPU 22a of the main control board 22 will be described.
First, processing based on the power-off processing program will be described. When the main control board 22 (main CPU 22a) inputs the power-off signal S, the main control board 22 (main CPU 22a) executes a backup process based on the power-off process program. That is, the main CPU 22a executes the power-off process program when the power-off signal S is input, and does not execute the power-off process program when the power-off signal S is not input (does not execute the backup process). In the backup process, the main CPU 22a stores and holds control information such as a register and a stack pointer in the RAM 22c in addition to various control information such as the value of the big hit determination random number stored and held in the RAM 22c. The main CPU 22a calculates and stores the checksum of the RAM 22c. Further, the main CPU 22a sets a backup flag (a flag for determining whether or not the control information stored and held in the RAM 22c is correct when the power is turned on) in the RAM 22c. Thereafter, the main CPU 22a prohibits access to the RAM 22c, and waits until the reset signal Re output from the reset input circuit 22d (reset signal circuit 26) is input (becomes a high level state). When the reset signal Re is input, the operation of the main CPU 22a is restricted. After the power is turned off, power is supplied from the backup power supply (capacitor) 27 of the power supply substrate 21 to the RAM 22c, and the storage contents of the RAM 22c at the time of the power cut are held as backup data.

  When the main CPU 22a enters a standby state, the main CPU 22a measures the time from the standby state by the watch dog timer. The main CPU 22a resets itself when a predetermined time elapses after entering the standby state. That is, the main CPU 22a is activated and executes main processing (see FIG. 3) based on the main control program. This is because when the main CPU 22a remains in the standby state, it is determined that the power-off signal S is erroneously input, and the standby state is canceled. For this reason, even if the unauthorized board outputs the power-off signal S and puts the main CPU 22a into a standby state, if the reset signal Re is not input, the main CPU 22a cancels the standby state and releases the main CPU 22a. Processing will be executed.

  The main CPU 22a is configured to output a re-reset signal Re1 to the reset input circuit 22d when resetting itself because a predetermined time has elapsed during the standby state. More specifically, when the main CPU 22a resets itself due to the elapse of a predetermined time during the standby state, the output state of the reset signal Re1 remains high until the time T1 elapses. Keep it in a state. Since the main process is executed after resetting again due to the output of the re-reset signal Re1, in the present embodiment, when a predetermined time has elapsed during the standby state, the main process is performed by resetting itself. It is not necessary to execute processing.

Next, main processing at power-on based on the main control program will be described.
When the reset input circuit 22d of the main control board 22 receives the reset signal Re output from the reset signal circuit 26 in response to the start of power supply (becomes a high level state), the reset input circuit 22d is connected to the main CPU 22a via the instruction circuit I. The reset signal Re is continuously output (maintained in a high level state) for a predetermined regulation time. The reset input circuit 22d receives a re-reset signal Re1 output from the main CPU 22a having a function equivalent to the reset signal Re output from the reset signal circuit 26 or an illegal reset signal Re2 output from the unauthorized board. Similarly, the reset signal Re is output to the main CPU 22a. When the main CPU 22a receives the reset signal Re via the instruction circuit I (becomes a high level state), the operation is restricted. When the output of the reset signal Re from the reset input circuit 22d is stopped (transitioned to the low level state) and the input of the reset signal Re to the main CPU 22a is stopped (transitioned to the low level state), the main CPU 22a is activated. Then, main processing (see FIG. 3) based on the main control program is executed.

  Based on the main control program, the main CPU 22a first prohibits interruption of timer interrupt processing (step MA1), permits access to the CPU's built-in RAM (step MA2), and further initializes the CPU peripheral devices and the watchdog timer. Settings are made (steps MA3 and MA4), and various settings required when the power is turned on. Next, the main CPU 22a checks whether or not the RAM clear switch 36 is turned on (step MA5). That is, the main CPU 22a determines whether or not an initialization instruction signal for instructing deletion of various control information stored in the RAM 22c (a value of a random number for jackpot determination, a backup flag, etc.) is input.

  If the determination result in step MA5 is negative, the main CPU 22a checks the backup flag set in the RAM 22c when the pachinko machine 10 is powered off, and determines whether the backup flag is normal (step MA6). That is, it is determined whether backup processing is normally performed. Then, the main CPU 22a proceeds to step MA7 when the determination result of step MA6 is affirmative, and proceeds to step MA16 when the determination result of step MA6 is negative.

  The main CPU 22a that has shifted to step MA7 calculates the checksum of the RAM 22c, and then determines whether or not the checksum calculated in step MA7 matches the checksum value calculated when the power is turned off (step MA8). As described above, by the processing of step MA6 and step MA8, the main CPU 22a stores and holds whether or not there is control information (stored content) stored and held in the RAM 22c, and if there is stored and held control information. It is determined whether the control information is abnormal. If these determination results are affirmative, that is, if the control information stored and held in the RAM 22c is abnormal, the main CPU 22a proceeds to step MA16 and initializes the RAM 22c.

  Note that if the determination result in step MA6 or step MA8 is affirmative, the stored content may be stored when the power-off process program is executed at the time of power-off but the backup process is not performed normally or due to noise after the backup process. An abnormality may have occurred. In such a case, the backup flag or checksum indicates an abnormality (abnormal value). When the main CPU 22a inputs the reset signal Re and executes the main control program from the beginning when the power is not shut off (without inputting the power shut-off signal S) (that is, when the main CPU 22a is restarted). ) In this case, the backup flag is not set because the backup process is not executed. The cause of the restart of the main CPU 22a is that the reset signal circuit 26 of the power supply board 21 malfunctions or a similar signal (illegal reset signal Re2) that performs the same function (role) as the reset signal Re is improperly attached. It may have been output from an unauthorized substrate. Therefore, in this embodiment, the unauthorized reset signal Re2 is a start instruction signal.

  Further, the main CPU 22a may be restarted because the main CPU 22a outputs a reset signal Re1 after a predetermined time has elapsed after the power-off signal S is input. It should be noted that the power supply voltage V2 becomes equal to or lower than the predetermined voltage V10 even though the power-off signal S is not input is considered that the power supply to the main control board 22 is intentionally cut off by an unauthorized board.

  Returning to the description of the main control program, the main CPU 22a proceeds to step MA9 if the determination result in step MA8 is positive, and proceeds to step MA16 if the determination result in step MA8 is negative. When the determination result of step MA5 is affirmative, the determination result of step MA6 is negative, or the determination result of step MA8 is negative, the main CPU 22a deletes the backup data stored in the RAM 22c and based on the initial value, the pachinko machine 10 is started (processing after step MA16). On the other hand, when the determination result at step MA8 is affirmative, the main CPU 22a activates the pachinko machine 10 based on the set value of the backup data (processing after step MA9).

  If the determination result in step MA8 is affirmative, the main CPU 22a performs processing at the time of power recovery after step MA9 because the RAM clear switch 36 is not turned on and backup is performed normally. In step MA9, the main CPU 22a restores the stack pointer before the power is turned off. Next, the main CPU 22a transmits a return command for returning to the gaming state (including the probability variation state and the variation time reduction state) when the power is turned off to the sub-control board 23 (step MA10). By this return command, the sub-control board 23 notifies the gaming state when the power is cut off. Next, the main CPU 22a sets an interrupt interval timer (for example, 4 ms) (step MA11), and restores the register before power-off (step MA12). Next, the main CPU 22a determines whether or not an interrupt is permitted before the power is turned off (step MA13). When the determination result at step MA13 is affirmative, the main CPU 22a sets an interrupt permission (step MA14), and when the determination result is negative, the main CPU 22a proceeds to step MA15 without permitting an interrupt and permits the interrupt. / Return non-permission (prohibition) to the state before power off. Then, the main CPU 22a sets an address before power-off at step MA15, and returns to the set address.

  On the other hand, the main CPU 22a that has shifted to step MA16 performs initialization processing of the RAM 22c. This processing is performed when the power is first turned on from the shipping state, when the RAM clear switch 36 is turned on (when an initialization instruction signal is input), and when the backup is abnormal. Also, in the initialization process, after the power-off signal S is input, when the standby state continues for a predetermined time and the main CPU 22a resets (restarts) itself and executes the main process, the initialization instruction signal is illegally input If so, it may be executed. In step MA16, the main CPU 22a clears all the RAM 22c. That is, the entire storage area of the RAM 22c is cleared to 0 (zero). As a result of the processing in step MA16, “0 (zero)” is set as the initial value for the value of the big hit determination random number. Next, the main CPU 22a sets 8000H in the stack pointer (initializes the stack pointer) (step MA17) and sets an initial value in the RAM 22c (step MA18). The processes in steps MA16 to MA18 are initialization processes.

  Next, the main CPU 22a sets an interrupt interval timer (for example, 4 ms) (step MA19). Then, the main CPU 22a sets the interrupt to be prohibited at step MA20, executes the waiting time random number update process at step MA21, and sets the interrupt to be enabled at step MA22 after the interval timer elapses. The waiting time random number update process executed in step MA21 is a process for updating the random number value during the waiting time until the next interruption time elapses. In this waiting time random number update process, random numbers such as a random number for fluctuation pattern distribution used for determining the fluctuation pattern and a random number for the big hit symbol initial value used for determining the initial value of the random number for the big hit symbol are updated. It has become.

  After step MA22 ends, the main CPU 22a outputs a game ready state signal K1 to the game start signal generation circuit 22e (step MA23), ends the main processing, and subsequently executes timer interrupt processing at predetermined intervals. To do. In this timer interrupt process, the main CPU 22a updates the jackpot determination random number and executes a process related to the game. That is, at the same time as the main CPU 22a outputs the game available state signal K1, the big hit determination random number is updated on the main control board so that the game can be played.

Next, timer interrupt processing will be described with reference to FIG.
The timer interrupt process is a process that is repeatedly executed every predetermined control period (for example, 4 ms) after the pachinko gaming machine 10 is started, and processes related to various games are executed by the timer interrupt process.

  When executing the timer interrupt process, the main CPU 22a first clears the watchdog timer (step MB1). Next, the main CPU 22a determines whether or not the game start signal K2 has already been input from the game start signal generation circuit 22e (the input state of the game start signal K2 has already become a high level state) (step MB2). If this determination result is negative, the main CPU 22a determines whether or not the current input state of the game start signal K2 is a high level state (step MB3). That is, in the current timer interrupt process, the main CPU 22a determines whether or not the input state of the game start signal K2 has transitioned from the low level state to the high level state. If this determination result is affirmative, the main CPU 22a outputs various control signals based on the initialization of the RAM 22c to the sub-control board 23 (step MB4). The main CPU 22a outputs, for example, a control command (output start signal) for displaying an initial symbol on the sub-control board 23 in the process of step MB4.

  When the determination result of step MB2 is affirmative or when the process of step MB4 is completed, the main CPU 22a reads the input states of signals from various sensors (step MB5). Then, the main CPU 22a stores the read input state for each sensor (step MB6). Next, the main CPU 22a determines whether or not a winning detection signal is input from a winning detection sensor of a winning opening among various sensors (step MB7). If the determination result is affirmative, the main CPU 22a outputs a prize ball payout instruction command to a payout control board (not shown) (step MB8). When the payout control board inputs the prize ball payout instruction command, the payout control board controls the ball payout device so as to pay out the prize ball based on the prize ball payout instruction command.

  When the determination result of step MB7 is negative and when the process of step MB8 ends, the main CPU 22a executes various game-related processes such as a special symbol game process related to the symbol variation game (step MB9). In the process of step MB9, the main CPU 22a executes various game-related processes such as jackpot determination, determination of a final stop symbol to be finally displayed, determination of a variation pattern, and provision of a jackpot game state.

  For example, when the main CPU 22a has input a winning detection signal indicating that a winning of the game ball from the winning detection sensor SE of the start winning opening 19 has been detected, the big hit determination random number stored in the RAM 22c at that timing. Get the value of. Then, when starting the symbol combination game, the main CPU 22a stores a predetermined jackpot determination value (for example, “7” and “511”) in which the value of the jackpot determination random number acquired when the winning of the game ball is detected is stored in the ROM 22b. ) Is determined by determining whether or not it matches. The main CPU 22a gives a jackpot gaming state when the determination result of the jackpot determination is affirmative (match). Further, since the numbers of the big hit determination random numbers are “0” to “630” (631 kinds in total), when the big hit values are set to “7” and “511”, the big hit probability of the pachinko machine 10 is 315 1/5 (= 2/631).

  If the determination result of the jackpot determination is affirmative (in the case of a jackpot), the main CPU 22a determines the final stop symbol based on the jackpot symbol random number so that all the columns are of the same type, and changes for the jackpot effect. A variation pattern is determined from the patterns. On the other hand, when the determination result of the big hit determination is negative (in the case of a loss), the main CPU 22a determines the final stop symbol so that the symbols in all the rows are not of the same type, and changes from the variation pattern for the offending effect. Determine the pattern.

  The main CPU 22a, which has determined the variation pattern and the final stop symbol, outputs a predetermined control command to the sub control board 23 (sub CPU 23a) at a predetermined timing. Specifically, the main CPU 22a first outputs a variation pattern designation command that designates a variation pattern and instructs the start of symbol variation. Next, the main CPU 22a outputs a symbol designation command for designating a final stop symbol for each column. After that, the main CPU 22a instructs the change stop based on the change time set in the specified change pattern, and outputs the all symbol stop command for ending the symbol combination game. Thus, the main CPU 22a executes various processes relating to the game at step MB9.

  Then, the main CPU 22a executes a random number update process when the determination result of step MB3 is negative or when the process of step MB9 is completed (step MB10). In this random number update process, the main CPU 22a updates at least the jackpot determination random number. In this embodiment, the big hit determination random number and the big hit symbol random number for determining the big hit symbol combination are updated. When the process of step MB10 ends, the main CPU 22a executes the standby process shown in FIG. 5 (step MB11), and ends the timer interrupt process.

  In this way, in the timer interrupt process, the main CPU 22a starts updating the jackpot determination random number before inputting the game start signal K2, and does not input the winning detection signal before inputting the game start signal K2. It has become. In other words, execution of processing related to the game is restricted while the game is possible. Accordingly, in the timer interrupt process, the main CPU 22a starts updating the jackpot determination random number before entering the game start signal K2 to make it possible to play the game, but restricts the start of the game.

  Then, when executing the standby process shown in FIG. 5, the main CPU 22a first sets the interruption to be prohibited (step MC1) and executes a standby time random number update process (step MC2). The standby time random number update process executed during the standby process is a process for updating the random number value during the standby time until the next interrupt time elapses after execution of step MB10 of the timer interrupt process. The time related to is a variable time that varies depending on the end point of the process related to the game effect of the symbol variation game (the process up to step MB10). That is, for example, when the process related to the game effect (the process up to step MB10) ends early, such as when no game is being performed, the processing time of the waiting time random number update process becomes long, and the process such as the time of starting the symbol variation game When the amount of processing is large and time is required for the processing related to the game effect (processing up to step MB10), the processing time of the waiting time random number update processing is shortened. In this waiting time random number update process, random numbers such as a random number for fluctuation pattern distribution used for determining the fluctuation pattern and a random number for the big hit symbol initial value used for determining the initial value of the random number for the big hit symbol are updated. It has become. Thereafter, the main CPU 22a sets the interruption to be permitted (step MC3). Then, the main CPU 22a determines whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the watchdog timer was cleared (step MC4). If this determination result is negative, the main CPU 22a returns to step MC1 again and repeatedly executes steps MC1 to MC4. On the other hand, if the determination result of step MC4 is affirmative, the main CPU 22a ends the standby process and ends the timer interrupt process.

  Further, when the supply of the power supply voltage to the RAM 22c is stopped while the timer interrupt process is being executed and the value of the watchdog timer has passed a predetermined value (for example, 4 ms), the main CPU 22a supplies the RAM 22c to the RAM 22c. The storage contents of the RAM 22c are initialized after the supply of the power supply voltage is resumed. More specifically, when the main CPU 22a stops supplying the power supply voltage to the RAM 22c and cannot read control information such as a random number from the RAM 22c, the main CPU 22a cannot proceed with the process. In this state, the value of the watchdog timer passes a predetermined value. When the watchdog timer value exceeds a predetermined value, the main CPU 22a executes main processing to initialize the RAM 22c when the power supply voltage supplied to the RAM 22c becomes larger than the predetermined voltage V10. Execute the process. That is, the main CPU 22a executes steps MA1 to MA6 and MA16 to MA23 of the main process. When the supply of the power supply voltage to the RAM 22c is stopped and then the power supply voltage is restored, the main CPU 22a executes the main process and outputs the game ready state signal K1 to the game start signal generation circuit 22e. . In the present embodiment, the main CPU 22a is configured to output a re-reset signal Re1 to the reset input circuit 22d when resetting and executing main processing after a predetermined time has elapsed from the standby state. For this reason, the game start signal generation circuit 22e outputs the game start signal K2 without delay unless the first game ready state signal K1 is input after the reset signal Re is input. Since the reset signal Re1 is input, the game start signal K2 is delayed. The main CPU 22a is reset again based on the re-reset signal Re1, and executes the main process.

Next, the configuration of the sub control board 23 will be described.
The sub control board 23 is provided with a sub CPU 23a, a ROM 23b, and a RAM 23c. A ROM 23b and a RAM 23c are connected to the sub CPU 23a. The ROM 23b stores a game effect control program for controlling game effects (display effects, light emission effects, audio effects), and the like. The RAM 23c stores (sets) various information (various control flags, various timer values, etc.) that can be appropriately rewritten during operation of the pachinko machine 10.

  The sub control board 23 is provided with a reset input circuit 23d. The reset input circuit 23d is connected to the reset signal circuit 26 of the power supply substrate 21, and receives the reset signal Re output from the reset signal circuit 26. The reset input circuit 23d is connected to the sub CPU 23a. When the reset signal Re is input, the reset input circuit 23d continuously outputs the reset signal Re to the sub CPU 23a for a predetermined time T1. The execution of the operation (control processing) is restricted while the signal level of the reset signal Re is in the high level state, and the sub CPU 23a starts to be activated when the signal level is in the low level state. In the present embodiment, the output time T1 of the reset signal Re in the reset input circuit 23d is set to be shorter than the output time (output time T1 + delay time T2) of the reset signal Re in the reset input circuit 22d of the main control board 22. Has been. For this reason, the sub CPU 23a starts to be activated earlier than the main CPU 22a. Then, the sub CPU 23a of the sub control board 23 performs initialization when starting. In this initial setting, the sub CPU 23a performs processing such as initialization of the contents stored in the RAM 23c.

  Then, after the initial setting is completed, the sub CPU 23a shifts to normal processing. In this normal processing, when the sub CPU 23a inputs a control command from the main control board 22 (main CPU 22a), the sub CPU 23a performs control according to the input control command based on the game effect control program. For example, when the sub CPU 23a inputs the variation pattern designation command, the sub CPU 23a controls the display device 18, the decoration lamp 40, and the speaker 41 so as to start the symbol combination game based on the variation pattern designated by the variation pattern designation command. When the sub CPU 23a inputs the all symbol stop command, the display contents of the variable display H of the display device 18 are displayed on the variable display H of the display device 18 so that the symbol combination designated by the input symbol designation command is displayed. To control. Since the sub CPU 23a starts up earlier than the main CPU 22a starts and shifts to normal processing, even if a control command is input immediately after the main CPU 22a is started, the processing according to the control command is reliably executed. be able to.

Next, the game start signal generation circuit 22e will be described. Hereinafter, the game start signal generation circuit 22e will be described in detail with reference to FIG.
The game start signal generation circuit 22 e is provided on the main control board 22 and is connected to the main CPU 22 a of the main control board 22. The game start signal generation circuit 22e receives a game available state signal K1 from the main CPU 22a via a D-FF (not shown). The game start signal generation circuit 22e is provided with a timing generator 51 and a delay circuit 52 so that the game ready state signal K1 from the main CPU 22a is input to the timing generator 51 and the delay circuit 52. It has become.

  The delay circuit 52 is connected to the timing generator 51. The delay circuit 52 receives a command (signal) from the timing generator 51 and then outputs a game start signal to the main CPU 22a side when the signal level of the game available state signal K1 input from the main CPU 22a changes to a different state. The signal level of K2 is changed to a different state. That is, the delay circuit 52 is delayed from the time when the game ready state signal K1 is input and is output to the main CPU 22a side as the game start signal K2. Note that transition to a state in which the signal levels of the game ready state signal K1 and the game start signal K2 are different means transition from a high level state to a low level state or transition from a low level state to a high level state.

  The timing generator 51 is connected to an oscillation circuit 53 (oscillator) provided in the game start signal generation circuit 22e. The oscillation circuit 53 generates an internal clock signal and outputs the internal clock signal every predetermined cycle. The timing generator 51 receives the internal clock signal and synchronizes in the game start signal generation circuit 22e based on the internal clock signal. The oscillation circuit 53 is connected to a first counter 54 (10-bit binary counter 1) provided in the game start signal generation circuit 22e, and the first counter 54 inputs an internal clock signal from the oscillation circuit 53. Then, each time the internal clock signal is input (every period of the internal clock signal), the first counter 54 is within a predetermined numerical range (for example, all 1024 integers from “0” to “1023”). The counter value is incremented by 1 and updated. That is, the first counter 54 sets the value (initial value) at the start of updating to “0” which is the minimum value, and in order from the initial value “0” → “1” →... → “1022” → “1023 The counter value is incremented by 1 and updated. Then, when the first counter 54 reaches “1023 (maximum value)” that is a numerical value (final value) that is updated last, the first counter 54 adds 1 to “0” to “1023” again. Update. That is, in the present embodiment, the counter value is sequentially updated with “0” to “1023” as one cycle, and this one-cycle update process is repeatedly executed during operation of the pachinko machine 10. The counter value update cycle (that is, the cycle of the internal clock signal) is different from the big hit determination random number update cycle (4 ms in this embodiment). Specifically, the counter value update cycle is much earlier.

  The timing generator 51 is connected to a register 55 (10 bit register) provided in the game start signal generation circuit 22e. The register 55 is connected to the first counter 54 so that a counter value can be input. Then, the timing generator 51 instructs the register 55 to store the counter value of the first counter 54 when the signal level of the game ready state signal K1 input to the game start signal generation circuit 22e changes to a different state. ). The register 55 stores the counter value of the first counter 54 when receiving the instruction from the timing generator 51. That is, the register 55 stores a counter value of the first counter 54 when the signal level of the game available state signal K1 input to the game start signal generation circuit 22e is changed to a different state.

  The timing generator 51 is connected to a second counter 56 (10-bit binary counter 2) provided in the game start signal generation circuit 22e. The second counter 56 receives an update clock signal having a predetermined period from a frequency dividing circuit 60 provided in the game start signal generating circuit 22e. Then, each time the update clock signal is input (every cycle of the update clock signal), the second counter 56 is within a predetermined numerical range (for example, all 1024 patterns from “0” to “1023”). The determination value is incremented by 1 and updated. That is, the second counter 56 sets the value (initial value) at the start of updating to “0” which is the minimum value, and in order from the initial value “0” → “1” →... → “1022” → “1023 The decision value is incremented by one and updated. In this embodiment, the determination value update cycle (cycle of the update clock signal) is set to be different from the big hit determination random number update cycle (4 ms in this embodiment). Specifically, the determination value update cycle (1 ms in this embodiment) is earlier.

  Then, the timing generator 51 updates the determination value from the initial value “0” to the second counter 56 when the signal level of the game possible state signal K1 input to the game start signal generation circuit 22e is changed to a different state. An instruction (signal) is sent to do so. That is, the second counter 56 starts updating the determination value after the counter value is stored in the register 55. Each time the second counter 56 updates the determination value, the second counter 56 determines whether or not the determination value matches the counter value. When the second counter 56 determines that the determination value matches the counter value, the second counter 56 notifies the timing generator 51 ( Signal).

  When the timing generator 51 receives notification from the second counter 56 that the determination value and the counter value match, the timing generator 51 sets the signal level of the game start signal K2 output to the main CPU 22a to the delay circuit 52 in a different state. Instruct to transition. Thereby, the delay circuit 52 changes the signal level of the game start signal K2 output to the main CPU 22a side to a different state.

  From the above, the game start signal generation circuit 22e according to the present embodiment serves as fraud prevention means. In addition, the first counter 54 of the game start signal generation circuit 22e serves as a first updating unit (update unit for fraud prevention unit) that updates the counter value. Further, the register 55 of the game start signal generation circuit 22e serves as an acquisition unit (acquisition unit for fraud prevention unit) that acquires a counter value. Further, the second counter 56 of the game start signal generation circuit 22e serves as second update means (second update means for fraud prevention means) for updating the determination value. Further, the delay circuit 52 of the game start signal generation circuit 22e serves as a transition unit (transition unit for fraud prevention unit) that outputs the game start signal K2. Further, the oscillation circuit 53 of the game start signal generation circuit 22e serves as first signal generation means (first signal generation means for fraud prevention means) that outputs an internal clock signal to the first counter 54, and the game start signal generation circuit 22e The connected external oscillation circuit 70 serves as second signal generation means (second signal generation means for fraud prevention means) that outputs an external clock signal to the second counter 56. Timing instruction means (timing prevention means timing instruction means) that instructs the timing generator 51 of the game start signal generation circuit 22e to change the signal level of the game start signal K2 to a different state to the delay circuit 52; Become.

  As described above, when the signal level of the game possible state signal K1 is changed to a different state, the counter 55 stores the counter value of the first counter 54 and the second counter 56 updates the determination value. When the determination value matches the counter value, the timing generator 51 instructs the delay circuit 52 to shift the signal level of the game start signal K2 to a different state. For this reason, the delay time of the game start signal K2 depends on the counter value when the signal level of the game ready state signal K1 changes to a different state.

  The first counter 54 continues to update the counter value after power is supplied to the game start signal generation circuit 22e, that is, the main control board 22. Therefore, the counter value when the signal level of the game enable state signal K1 changes to a different state is not constant when the signal level of the game enable state signal K1 changes to a different state. The delay time of the start signal K2 is not constant. That is, the signal level of the game start signal K2 that the game start signal generation circuit 22e outputs to the main CPU 22a side after the signal level of the game ready state signal K1 input to the game start signal generation circuit 22e changes to a different state. The delay time until the timing of transition to a different state is not constant.

  For this reason, the time from when the main CPU 22a outputs the game possible state signal K1 to when the game start signal K2 is input is not constant, and the output start timing of the start signal output to the sub control board 23 is not constant. On the other hand, the main CPU 22a outputs the start signal to the sub-control board 23 in order to start updating the big hit determination random number even after inputting the game start state signal K1 and before inputting the game start signal K2. The time until the big hit determination value is acquired from the time is not constant, and the timing of the big hit cannot be grasped. Therefore, even if the illegal board illegally reads the output timing of the start signal (for example, the INT signal of the power-on initial command) and measures the time from the output timing, it is not possible to grasp the timing that is a big hit. Can prevent fraud.

  In addition, the oscillation circuit 53 of the present embodiment is composed of a capacitor, a capacitor, a resistor, and the like, and these performances usually vary, and also when the power is not supplied, the residual charge of the capacitor, etc. Usually varies. For this reason, the cycle of the internal clock signal generated by the oscillation circuit 53 is often not constant immediately after the power is turned on. In addition, the counter value of the first counter 54 is updated at least a plurality of times from when the power is turned on until the game ready signal K1 is input to the game start signal generation circuit 22e. In other words, the oscillation circuit 53 has an internal clock signal having a cycle that is fast enough to input the internal clock signal a plurality of times from when the power is turned on until the game start signal generation circuit 22e is input with the game ready state signal K1. Is supposed to generate. From the above, there is a high possibility that the counter value acquired when the signal level of the game-ready state signal K1 is changed to a different state after the power is turned on first will vary. For this reason, the delay time is also different, and it becomes difficult to grasp the timing of the first big hit after the power is turned on.

  In the present embodiment, the counter value is updated inside the game start signal generation circuit 22e, and the counter value update cycle may change due to environmental changes or individual differences in ICs. It is difficult to grasp. Also, since the cycle of the internal clock signal output from the oscillation circuit 53, that is, the update cycle of the counter value and the update cycle of the big hit determination random number are not synchronized, the counter value can be determined while determining the big hit determination random number. It becomes extremely difficult to do. Similarly, since the counter value update cycle and the determination value update cycle are also different (asynchronous), it is extremely difficult to grasp the counter value while grasping the judgment value.

  In the present embodiment, although not shown, the delay circuit 52 of the game start signal generation circuit 22e is configured to be able to input the reset signal Re from the reset input circuit 22d. The delay circuit 52 delays only the input of the first game available state signal K1 after inputting the reset signal Re. That is, the delay circuit 52 is configured to delay only when the game ready state signal K1 first changes from the low level state to the high level state after inputting the reset signal Re.

  The frequency dividing circuit 60 provided in the game start signal generation circuit 22e is outside the game start signal generation circuit 22e and has a frequency of an external clock signal input from the external oscillation circuit 70 provided in the main control board 22. Is high, the frequency of the external clock signal can be divided to reduce the frequency to be an update clock signal. Specifically, the frequency dividing circuit 60 is provided with data lines S1 and S2, and the frequency of the external clock signal is reduced to 1/160000 or 20000 depending on the input state of signals to the data lines S1 and S2. A signal divided by 1 is output as an update clock signal, or output as an update clock signal.

  More specifically, the frequency divider circuit 60 includes a third counter 61 (15-bit binary counter 3), a data selector 63 (SEL), a divider 62 (Divide 20000 / Divide 16000), and a selection switch 64 (MUX: Multiplexer). ing. Then, the data selector 63 outputs the frequency of the external clock signal input from the outside to the divider 62 as it is based on the signals input from the data lines S1 and S2, or outputs 1/60000 or Set whether to divide by 20,000 and output. When it is set to output as an update clock signal in the same cycle, the data selector 63 outputs the external clock signal input from the outside as it is to the second counter 56 as an update clock signal to the selection switch 64. To instruct. Accordingly, the external clock signal input from the outside is output to the second counter 56 as it is as an update clock signal. For example, when an external clock signal of 1 KHz (kilohertz) is input, the frequency dividing circuit 60 outputs the clock signal to the second counter 56 as a 1 KHz update clock signal without frequency division.

  On the other hand, if it is set to divide by 16000, the data selector 63 instructs the divider 62 to that effect. Receiving this instruction, the divider 62 causes the selection switch 64 to output the update clock signal once every time the third counter 61 measures that the external clock signal is input 16000 times. That is, every time an external clock signal input from the outside is input 16000 times, an update clock signal is output to the selection switch 64 once. The selection switch 64 outputs the update clock signal to the second counter 56. Note that the same processing is performed when the frequency is divided by 1/20000, and thus detailed description thereof is omitted. For example, when an external clock signal of 16 MHz (megahertz) is input, the frequency dividing circuit 60 divides the frequency by 1/16 and outputs it as a 1 KHz update clock signal. Similarly, when an external clock signal of 20 MHz (megahertz) is input, the frequency dividing circuit 60 divides the frequency by 1/2000 and outputs it as a 1 KHz update clock signal.

  In this way, by dividing the external clock signal input from the outside, even if an external clock signal having various frequencies is input, it has an appropriate period for updating the determination value (for example, 1 KHz). It can be converted into an update clock signal. In addition, when the external clock signal is divided, the update period for the big hit determination random number and the determination value are different, making it difficult to grasp the update period for the decision value, making it even more difficult to grasp the timing of the big hit. Can do.

  Next, the instruction circuit I will be described with reference to FIG. In this embodiment, since the instruction circuit I and the game start signal generation circuit 22e have the same circuit configuration, the same configuration as the game start signal generation circuit 22e is denoted by the same reference numeral as the game start signal generation circuit 22e. The detailed description thereof is omitted or simplified.

  The instruction circuit I is provided on the main control board 22 and is connected to the reset input circuit 22 d of the main control board 22. The reset signal Re from the reset input circuit 22d is input to the timing generator 51 and the delay circuit 52 of the instruction circuit I. The delay circuit 52 receives the instruction (signal) from the timing generator 51 and then outputs the reset signal Re to the main CPU 22a side when the signal level of the reset signal Re input from the reset input circuit 22d changes to a different state. The signal level of is shifted to a different state. That is, the delay circuit 52 delays the input reset signal Re and outputs it to the main CPU 22a side.

  The timing generator 51 is connected to an oscillation circuit 53 provided in the instruction circuit I. The oscillation circuit 53 generates an internal clock signal and outputs the internal clock signal every predetermined cycle. The timing generator 51 receives the internal clock signal and synchronizes in the instruction circuit I based on the internal clock signal. The oscillation circuit 53 is connected to a first counter 54 provided in the instruction circuit I, and the first counter 54 inputs an internal clock signal from the oscillation circuit 53. Then, each time the internal clock signal is input (every period of the internal clock signal), the first counter 54 is within a predetermined numerical range (for example, all 1024 integers from “0” to “1023”). The counter value is incremented by 1 and updated.

  The timing generator 51 is connected to a register 55 provided in the instruction circuit I. The register 55 is connected to the first counter 54 so that a counter value can be input. Then, the timing generator 51 sends an instruction (signal) to store the counter value of the first counter 54 in the register 55 when the signal level of the reset signal Re input to the instruction circuit I changes to a different state. It has become. The register 55 stores the counter value of the first counter 54 when receiving the instruction from the timing generator 51. In other words, the register 55 stores the counter value of the first counter 54 when the signal level of the reset signal Re input to the instruction circuit I changes to a different state.

  The timing generator 51 is connected to a second counter 56 provided in the instruction circuit I. The second counter 56 receives an update clock signal having a predetermined period from a frequency dividing circuit 60 provided in the instruction circuit I. Then, each time the update clock signal is input (every cycle of the update clock signal), the second counter 56 is within a predetermined numerical range (for example, all 1024 patterns from “0” to “1023”). The determination value is incremented by 1 and updated.

  The timing generator 51 instructs the second counter 56 to update the determination value from the initial value “0” when the signal level of the reset signal Re input to the instruction circuit I changes to a different state ( Signal). That is, the second counter 56 starts updating the determination value after the counter value is stored in the register 55. Each time the second counter 56 updates the determination value, the second counter 56 determines whether or not the determination value matches the counter value. When the second counter 56 determines that the determination value matches the counter value, the second counter 56 notifies the timing generator 51 ( Signal).

  When the timing generator 51 receives a notification from the second counter 56 that the determination value matches the counter value, the signal level of the reset signal Re output to the main CPU 22a side with respect to the delay circuit 52 changes to a different state. To instruct. Thereby, the delay circuit 52 changes the signal level of the reset signal Re output to the main CPU 22a side to a different state.

  From the above, the first counter 54 of the instruction circuit I according to the present embodiment serves as first instruction circuit update means for updating the counter value. The register 55 of the instruction circuit I serves as an instruction circuit acquisition unit that acquires a counter value. Further, the second counter 56 of the instruction circuit I serves as second instruction circuit updating means for updating the determination value. Further, the delay circuit 52 of the instruction circuit I serves as an instruction circuit transition means for outputting the reset signal Re. The oscillation circuit 53 of the instruction circuit I serves as first signal generation means for instruction circuit that outputs an internal clock signal to the first counter 54, and the external oscillation circuit 70 connected to the instruction circuit I is connected to the second counter 56. The second signal generating means for the instruction circuit for outputting the external clock signal to Further, the timing generator 51 of the instruction circuit I serves as instruction circuit timing instruction means for instructing the delay circuit 52 to shift the signal level of the reset signal Re to a different state.

  In this way, since the same circuit as the game start signal generation circuit 22e is used as the instruction circuit I, the signal level of the input reset signal Re is different for the same reason as when the game start signal generation circuit 22e is used. The delay time of the reset signal Re that is output depends on the counter value when transitioning to. That is, the delay from the time when the signal level of the reset signal Re input to the instruction circuit I changes to a different state to the timing when the instruction circuit I changes the signal level of the reset signal Re output to the main CPU 22a to a different state. Time will not be constant.

  For this reason, the time from when the reset signal Re is input to the main control board 22 until the main CPU 22a starts to start and the update of the big hit determination random number is not constant, and the reset signal Re is sent to the main control board 22 Even if the time is measured after the input, it is not possible to grasp the timing of the big hit. Therefore, even if the time since the input of the unauthorized reset signal Re2 to the main control board 22 is measured, it becomes difficult to grasp the timing of the big hit, and the unauthorized operation can be prevented.

  In many cases, the period of the internal clock signal generated by the oscillation circuit 53 of the present embodiment is not constant. Further, even when the reset signal circuit 26 outputs the reset signal Re at the same timing every time the power is turned on, it is highly likely that the time from when the power is turned on until the reset signal Re is input to the instruction circuit I is not constant. . In addition, the counter value of the first counter 54 is updated at least a plurality of times from when the power is turned on until the reset signal Re is input to the instruction circuit I. From the above, there is a high possibility that the counter value acquired when the signal level of the reset signal Re transitions to a different state for the first time after power-on will vary. For this reason, the delay time is also different, and it becomes difficult to grasp the timing of the first big hit after the power is turned on.

  Further, the instruction circuit I delays the transition timing each time the signal level of the reset signal Re transits to a different state. For this reason, when the input time of the reset signal Re is too short, the reset signal Re may not be normally output from the instruction circuit I. Specifically, the time from when the reset signal Re input to the instruction circuit I transitions to the high level state to when the reset signal Re transitions to the low level state indicates that the reset signal Re input to the instruction circuit I is at the high level state. If the reset signal Re output from the delay circuit 52 after the transition is shorter than the time from the transition to the high level state, it may not be output normally. Similarly, the time from when the reset signal Re input to the instruction circuit I transitions to the low level state to when it transitions to the high level state indicates that the reset signal Re input to the instruction circuit I is at the low level state. Even if the reset signal Re output from the delay circuit 52 after the transition is shorter than the time from the transition to the low level state, the reset signal Re may not be output normally. Therefore, an accurate input time of the reset signal Re cannot be set unless the maximum delay time of the reset signal Re is grasped in advance. Therefore, it is possible to prevent the illegal reset signal Re2 from being input with a short input time. Similarly, it is possible to remove noise that transitions to a low level state after instantaneously transitioning to a high level state.

  Further, in the present embodiment, the counter value is updated inside the instruction circuit I, and the counter value update cycle may change due to environmental changes or individual differences of ICs, so that the counter value is grasped. It is difficult. Also, since the cycle of the internal clock signal output from the oscillation circuit 53, that is, the update cycle of the counter value and the update cycle of the big hit determination random number are not synchronized, the counter value can be determined while determining the big hit determination random number. It becomes extremely difficult to do. Similarly, since the counter value update cycle and the determination value update cycle are also different (asynchronous), it is extremely difficult to grasp the counter value while grasping the judgment value.

Note that the frequency dividing circuit 60 provided in the instruction circuit I has the same configuration as the frequency dividing circuit 60 of the game start signal generating circuit 22e, and thus the same reference numerals are given and detailed description thereof is omitted.
Next, the delay timing of the reset signal Re by the instruction circuit I and the delay timing of the game start signal K2 by the game start signal generation circuit 22e will be described with reference to FIG.

  When the pachinko machine 10 is powered on (time point A1), the signal level of the reset signal Re input to the instruction circuit I transitions from the low level state to the high level state. As a result, the timing generator 51 of the instruction circuit I instructs the register 55 to store the counter value of the first counter 54. In response to this instruction, the register 55 of the instruction circuit I stores the counter value of the first counter 54. At the same time, the timing generator 51 of the instruction circuit I instructs the second counter 56 to update the determination value from the initial value. In response to this instruction, the second counter 56 of the instruction circuit I updates the determination value from the initial value for each cycle of the update clock signal input from the frequency divider circuit 60. When the determination value matches the counter value stored in the register 55, the second counter 56 of the instruction circuit I instructs the timing generator 51 that the determination value matches the counter value. Upon receiving this instruction, the timing generator 51 of the instruction circuit I instructs the transition of the signal level of the reset signal Re output to the delay circuit 52 to a different state.

  Upon receiving this instruction, the delay circuit 52 of the instruction circuit I shifts the signal level of the reset signal Re output to the main CPU 22a from the low level state to the high level state (time point A2). That is, the delay circuit 52 of the instruction circuit I sets the signal level of the reset signal Re to be output to the main CPU 22a for the time α1 obtained by multiplying the counter value at the time of transition to the high level state by the period of the update clock signal to the high level state Delay the transition timing to. When the signal level of the reset signal Re input to the main CPU 22a becomes a high level state, the activation of the main CPU 22a is restricted.

  Then, after the time T1 + T2 elapses after the power is turned on, the signal level of the reset signal Re input to the instruction circuit I changes from the high level state to the low level state (time point A3). As a result, the timing generator 51 of the instruction circuit I instructs the register 55 to store the counter value of the first counter 54. In response to this instruction, the register 55 of the instruction circuit I stores the counter value of the first counter 54. At the same time, the timing generator 51 of the instruction circuit I instructs the second counter 56 to update the determination value from the initial value. In response to this instruction, the second counter 56 of the instruction circuit I updates the determination value from the initial value every cycle of the update clock signal. When the determination value matches the counter value stored in the register 55, the second counter 56 of the instruction circuit I instructs the timing generator 51 that the determination value matches the counter value. Upon receiving this instruction, the timing generator 51 of the instruction circuit I instructs the transition of the signal level of the reset signal Re output to the delay circuit 52 to a different state.

  Upon receiving this instruction, the delay circuit 52 of the instruction circuit I shifts the signal level of the reset signal Re output to the main CPU 22a from the high level state to the low level state (time point A4). That is, the delay circuit 52 of the instruction circuit I sets the signal level of the reset signal Re that is output to the main CPU 22a side for the time α2 obtained by multiplying the counter value at the time of transition to the low level state by the cycle of the update clock signal to the low level state. Delay the transition timing to.

  When the signal level of the reset signal Re input to the main CPU 22a transitions to a low level state, the restriction of the main CPU 22a is released and activation is started. At this time, the main CPU 22a performs an initialization process when an initialization instruction signal is input or when the storage content of the RAM 22c is abnormal. Thereby, when the main CPU 22a executes the timer interrupt process, the main CPU 22a updates the jackpot determination random number from the initial value “0”. In the following description, it is assumed that initialization processing is performed. For this reason, the output time T1 + T2 of the reset input circuit 22d, the delay time α2 of the instruction circuit I, the time required for the initialization process, and the value of the jackpot determination random number are changed from the initial value “0” to the jackpot determination value (“7”). Alternatively, if a big hit determination random number is acquired when the time obtained by adding the time until reaching “511” elapses after the power is turned on, a big hit is obtained. However, since the delay time α2 is not constant, the timing of the big hit from the power-on is not constant, and even when the time is measured from the power-on, the timing of the big hit cannot be grasped and fraud can be prevented.

  If the initialization instruction signal is not input and the stored contents of the RAM 22c are normal, the main CPU 22a restores the backed-up stored contents and shifts to normal processing. As a result, the main CPU 22a continues to update the jackpot determination random number from the backed up value. In this case, since it is not possible to grasp the timing of the big hit without further knowing the backup contents, it becomes even more difficult to cheat.

  Then, the main CPU 22a outputs a game ready state signal K1 in the main process (time A5), executes a timer interrupt process, and waits until the game start signal K2 is input while updating the jackpot determination random number. . That is, the main CPU 22a updates the jackpot determination random number until the game start signal K2 is input, but does not execute various processes related to the game.

  When the game ready state signal K1 is input to the game start signal generation circuit 22e via the D-FF, the signal level of the game ready state signal K1 input to the game start signal generation circuit 22e is changed from the low level state to the high level state. Transition to. Thereby, the timing generator 51 of the game start signal generation circuit 22e instructs the register 55 to store the counter value of the first counter 54. In response to this instruction, the register 55 of the game start signal generation circuit 22e stores the counter value of the first counter 54. At the same time, the timing generator 51 of the game start signal generation circuit 22e instructs the second counter 56 to update the determination value from the initial value. In response to this instruction, the second counter 56 of the game start signal generation circuit 22e updates the determination value from the initial value for each cycle of the update clock signal input from the frequency divider circuit 60. Then, when the determination value matches the counter value stored in the register 55, the second counter 56 of the game start signal generation circuit 22e instructs the timing generator 51 that the determination value matches the counter value. Upon receiving this instruction, the timing generator 51 of the game start signal generation circuit 22e instructs the delay circuit 52 to shift the signal level of the game start signal K2 to a different state.

  Upon receiving this instruction, the delay circuit 52 of the game start signal generation circuit 22e shifts the signal level of the game start signal K2 output to the main CPU 22a side from the low level state to the high level state (time point A6). That is, the delay circuit 52 for the game start signal K2 increases the signal level of the game start signal K2 to be output to the main CPU 22a only for the time α3 obtained by multiplying the counter value at the time of transition to the high level state by the cycle of the update clock signal. Delay the transition to the level state. When the signal level of the game start signal K2 input to the main CPU 22a becomes a high level state, in the timer interrupt process, an output start signal is output to the sub-control board 23 (time point A7), and thereafter various processes relating to the game are executed. . That is, the player can play a game.

  For this reason, the time from when the main CPU 22a outputs the game ready state signal K1 to when the value of the random number for jackpot determination reaches the jackpot determination value (“7” or “511”) from the initial value “0” is measured. For example, it is possible to specify the timing for the big hit. However, the game available state signal K1 is not output to the outside of the main control board 22, and the external sub-control board 23 is merely provided with an output start signal after the delay time α3 has elapsed from the output of the game available state signal K1. is there. Since the delay time α3 is not constant, the timing of the big hit after the sub control board 23 inputs the output start signal is not constant. Therefore, even if the time is measured from the time when the output start signal is input from the main CPU 22a to the sub control board 23, it is not possible to grasp the timing of the big hit, and the illegal board that reads the control signal output from the main control board 22 Can prevent fraud.

Next, a case where an illegal reset signal Re2 is input from the unauthorized board to the main control board 22 during the operation of the pachinko machine 10 will be described.
When the signal level of the illegal reset signal Re2 input from the illegal board changes from the low level state to the high level state (time point A7), the timing generator 51 of the instruction circuit I stores the counter value of the first counter 54 in the register 55. Instruct to memorize. In response to this instruction, the register 55 of the instruction circuit I stores the counter value of the first counter 54. At the same time, the timing generator 51 of the instruction circuit I instructs the second counter 56 to update the determination value from the initial value. In response to this instruction, the second counter 56 of the instruction circuit I updates the determination value from the initial value for each cycle of the update clock signal input from the frequency divider circuit 60. When the determination value matches the counter value stored in the register 55, the second counter 56 of the instruction circuit I instructs the timing generator 51 that the determination value matches the counter value. Upon receiving this instruction, the timing generator 51 of the instruction circuit I instructs the delay circuit 52 to shift the signal level of the reset signal Re (signal based on the illegal reset signal Re2) output to the main CPU 22a to a different state.

  Upon receiving this instruction, the delay circuit 52 of the instruction circuit I shifts the signal level of the reset signal Re (a signal based on the illegal reset signal Re2) output to the main CPU 22a from the low level state to the high level state (time point A8). . In other words, the delay circuit 52 of the instruction circuit I outputs a reset signal Re (based on the illegal reset signal Re2) that is output to the main CPU 22a only for a time α4 obtained by multiplying the counter value at the time of transition to the high level state by the cycle of the update clock signal. The timing at which the signal level of the signal) transitions to the high level state is delayed. When the signal level of the reset signal Re input to the main CPU 22a becomes a high level state, the activation of the main CPU 22a is restricted.

  Then, when the signal level of the illegal reset signal Re2 input from the illegal board changes from the high level state to the low level state (time point A9), the timing generator 51 of the instruction circuit I stores the counter of the first counter 54 in the register 55. Instructs to store the value. In response to this instruction, the register 55 of the instruction circuit I stores the counter value of the first counter 54. At the same time, the timing generator 51 of the instruction circuit I instructs the second counter 56 to update the determination value from the initial value. In response to this instruction, the second counter 56 of the instruction circuit I updates the determination value from the initial value every cycle of the update clock signal. Then, when the determination value matches the counter value stored in the register 55, the second counter 56 of the instruction circuit I instructs the timing generator 51 of the instruction circuit I that the determination value matches the counter value. Upon receiving this instruction, the timing generator 51 of the instruction circuit I instructs the delay circuit 52 to shift the signal level of the reset signal Re (signal based on the illegal reset signal Re2) output to the main CPU 22a to a different state.

  Upon receiving this instruction, the delay circuit 52 of the instruction circuit I shifts the signal level of the reset signal Re (a signal based on the illegal reset signal Re2) output to the main CPU 22a from the high level state to the low level state (time point A10). . That is, the delay circuit 52 of the instruction circuit I outputs a reset signal Re (based on the illegal reset signal Re2) that is output to the main CPU 22a only for a time α5 that is obtained by multiplying the counter value at the time of transition to the low level state by the period of the update clock signal. The timing at which the signal level of the signal is shifted to the low level state is delayed.

  When the signal level of the reset signal Re (a signal based on the illegal reset signal Re2) input to the main CPU 22a transitions to the low level state, the restriction of the main CPU 22a is released, and activation is started. At this time, since the reset signal Re (a signal based on the illegal reset signal Re2) is input during the operation, the main CPU 22a does not input the initialization instruction signal, and the storage content of the RAM 22c is abnormal. Is being processed. As a result, the main CPU 22a continues to update the jackpot determination random number from the initial value “0”. For this reason, after inputting the illegal reset signal Re2 to the main control board 22, the output time T1 + T2 of the reset input circuit 22d, the delay time α5 of the instruction circuit I, the time required for the initialization process, and the jackpot determination random number When a time obtained by adding the time until the value reaches the big hit determination value (“7” or “511”) from the initial value “0” has elapsed, if the big hit determination random number is acquired, the big hit is obtained. However, since the delay time α5 is unknown, the timing of the big hit from the input of the illegal reset signal Re2 is unknown, and even if the time is measured after the power is turned on, the timing of the big hit cannot be grasped to prevent fraud. it can.

  Even when the illegal reset signal Re2 is input, the game available state signal K1 is not output to the outside of the main control board 22, and the external sub-control board 23 receives the game from the output of the game available state signal K1. An output start signal is only output after a random delay time has elapsed by the start signal generation circuit 22e. And since the said delay time is not constant by operation | movement of the game start signal generation circuit 22e, the timing which becomes a big hit after the sub control board 23 inputs an output start signal is not constant. Therefore, even if the time is measured from the time when the output start signal is input from the main CPU 22a to the sub control board 23, it is not possible to grasp the timing of the big hit, and the illegal board that reads the control signal output from the main control board 22 Can prevent fraud.

Next, a description will be given of a countermeasure when an unauthorized board that cuts off the power supply voltage from the backup power supply 27 to the RAM 22c is attached.
Even when the unauthorized board cuts off the power supply voltage from the backup power supply 27 to the RAM 22 c, the power supply voltage is supplied from the power supply circuit 24 instead of the backup power supply 27. For this reason, the unauthorized substrate cannot forcibly initialize the RAM 22c even if the power supply voltage VB from the backup power supply 27 to the RAM 22c is cut off. Accordingly, by forcibly initializing the RAM 22c and reading out the first INT signal (output start signal) to the sub-control board 23, it is possible to identify the start time of updating the big hit determination random number and estimate the big hit timing. become unable. As described above, fraud can be prevented when a fraudulent board that cuts off the power supply voltage from the backup power supply 27 to the RAM 22c is attached.

Next, a description will be given of what to do when an illegal board that cuts off the power supply voltage from the backup power supply 27 and the power supply circuit 24 to the RAM 22c is attached.
When the unauthorized board cuts off the power supply voltage from the power supply circuit 24 and the backup power supply 27 to the RAM 22c, the main CPU 22a cannot proceed with the process unless it can read control information such as a random number from the RAM 22c. In this state, the value of the watchdog timer passes a predetermined value. When the value of the watchdog timer exceeds a predetermined value, the main CPU 22a automatically restarts and executes main processing when the power supply voltage supplied to the RAM 22c becomes higher than the predetermined voltage V10. Then, initialization processing of the RAM 22c is executed.

  Note that the main CPU 22a outputs a re-reset signal Re1 to the reset input circuit 22d in order to restart after the predetermined time has passed. Then, the reset input circuit 22d outputs a reset signal to the game start signal generation circuit 22e based on the input of the re-reset signal Re1. Thus, when the game start signal generation circuit 22e receives the game enable state signal K1 after the reset signal Re is input, the game start state signal K1 is input first after the reset signal Re is input. The signal K1 is output, and the game start signal K2 is output with a delay. Then, as described above, the main CPU 22a restarts and starts updating the jackpot determination random number after the random time has elapsed from the time of power-off by the function of the instruction circuit I. Further, as described above, the main CPU 22a sends an INT signal (output start signal) to the sub control board 23 after a random time has elapsed since the update of the big hit determination random number is started by the action of the game start signal generation circuit 22e. Is output. As a result, the big hit timing cannot be determined. That is, fraud can be prevented.

Next, a countermeasure when an unauthorized power-off signal S is output by the unauthorized substrate will be described with reference to FIG.
When an unauthorized power-off signal S is output to the main control board 22 by the unauthorized board, the main CPU 22a executes a process based on the power-off process program (see time point B1 in FIG. 9). As a result, the main CPU 22a executes the backup process and enters a standby state. If the reset signal Re is not input to the main control board 22 as it is, a standby state is entered and a predetermined time elapses. When a predetermined time elapses, the main CPU 22a resets itself and executes main processing (see time point B2). At this time, the main CPU 22a resets itself, and therefore outputs a re-reset signal Re1 to the reset input circuit 22d (see time point B2). That is, the signal level of the reset signal Re1 is set to the high level state for the time T1.

  When the reset input circuit 22d receives the reset signal Re1, the reset input circuit 22d outputs the reset signal Re to the instruction circuit I (time point B2). That is, after the signal level of the reset signal Re output to the instruction circuit I is set to the high level state (time point B2), it is set to the low level state after time T1 + T2 (time point B4).

  When the signal level of the input reset signal Re transitions from the low level state to the high level state (time point B2), the instruction circuit I delays at random, and then sets the signal level of the reset signal Re output to the main CPU 22a to low level. The level state is changed to the high level state (time point B3). Thereby, the operation of the main CPU 22a is restricted. Then, when the signal level of the input reset signal Re transitions from the high level state to the low level state (time point B4), the instruction circuit I delays at random and then outputs the signal level of the reset signal Re output to the main CPU 22a. Is changed from the high level state to the low level state (time point B5). As a result, the main CPU 22a starts up and executes main processing (time point B5).

  Further, when the reset input circuit 22d receives the reset signal Re1, the reset input circuit 22d outputs the reset signal Re to the game start signal generation circuit 22e (time point B2). For this reason, the game start signal generation circuit 22e, when the main CPU 22a finishes the main processing and starts updating the jackpot determination random number and outputs the game available state signal K1 (time point B6), randomly delays After that, the game start signal K2 is output (time point B7). Based on the input of the game start signal K2, the main CPU 22a outputs an output start signal to the sub control board 23 (time point B7). For this reason, since the output start signal is output after a random time has elapsed since the start of updating the big hit determination random number, the value of the big hit determination random number cannot be known from the time when the output start signal is output.

  The time from the input of the power-off signal S to the end of the initialization process and the start of updating the jackpot determination random number is the time from the input of the power-off signal S to the output of the game enable state signal K1. Time is reached (time points B1 to B6). However, since the reset signal Re based on the re-reset signal Re1 is randomly delayed and output to the main CPU 22a by the instruction circuit I, until the big hit determination random number starts to be updated after the power-off signal S is output. The time is changed randomly. More specifically, the time from when the power-off signal S is output until the main CPU 22a is activated (time point B5) is random. For this reason, even if the time after the power-off signal S is output is measured, the value of the jackpot determination random number cannot be known, and an illegal jackpot can be prevented.

As described above in detail, the present embodiment has the following effects.
(1) The main CPU 22a enters the standby state after inputting the power-off signal S that is in a standby state until the reset signal Re is input to the reset input circuit 22d. The reset input circuit 22d inputs a re-reset signal Re1 having the same function as the reset signal Re when the main CPU 22a enters a standby state after a predetermined time. As a result, even if the unauthorized board causes the main CPU 22a to output the power-off signal S to the standby state without causing the reset input circuit 22d to input the unauthorized reset signal Re2, the reset input circuit 22d The re-reset signal Re1 having the same function as the reset signal Re is input. For this reason, the reset input circuit 22d newly activates the main CPU 22a, and the game start signal generation circuit 22e inputs the game available state signal K1 when the reset signal Re is input to the reset input circuit 22d. Can do. That is, the game start signal generation circuit 22e can output the game start signal K2 to the main CPU 22a after a randomized delay time has elapsed since the game ready state signal K1 was input. Accordingly, the main CPU 22a starts outputting a control signal (output start signal) to the sub-control board 23 after the randomized delay time has elapsed from the start of updating the value of the random number for determining the big hit, and controls the game effects. Can start. That is, the time from when the power-off signal S (standby instruction signal) is input to the main CPU 22a until the main CPU 22a outputs the first control signal (output start signal) to the sub-control board 23 is not constant. Even if it is measured, it becomes impossible to specify the value of the random number for determining the big hit, and the illegal big hit can be prevented.

  (2) Since the main CPU 22a outputs the re-reset signal Re1, it is not necessary to provide a device for monitoring the input / output states of the power-off signal S and the reset signal Re and means for outputting the re-reset signal Re1. For this reason, the circuit configuration can be simplified.

  (3) When the reset input circuit 22d receives the high-level re-reset signal Re1, the reset input circuit 22d outputs the high-level reset signal Re to the main CPU 22a for a predetermined time (time T1 + T2) and regulates its operation. After that, a low level reset signal Re is output to the main CPU 22a to be activated. For this reason, the main CPU 22a can be automatically activated without shutting down the power supply by an operation of an administrator or the like, and the labor of the operation can be reduced.

  (4) The game start signal generation circuit 22e outputs the game start signal K2 without delay when the game ready state signal K1 is input when the reset signal Re is not input to the reset input circuit 22d. Output to the CPU 22a. As a result, the output of all control signals is not delayed, and bugs due to control signal delays can be prevented without changing the program.

  (5) In addition to the backup power supply 27 (dedicated power supply), the RAM 22c is supplied with a power supply voltage from the power supply circuit 24 (operating power supply). For this reason, even when the supply of the power supply voltage from the backup power supply 27 is stopped, the RAM 22 c can supply the power supply voltage from the power supply circuit 24. Accordingly, the main CPU 22a does not initialize the jackpot determination random number and stop outputting the INT signal (output start signal) and the game start signal following the stop of supply of the power supply voltage to the RAM 22c. That is, it becomes impossible to measure the time (timing for big hit) from when the power supply voltage from the backup power supply 27 is cut off until the INT signal is output. For this reason, by cutting off the power supply voltage from the backup power supply 27, it becomes impossible to specify the timing for generating an illegal jackpot, thereby preventing the illegality.

  (6) The main CPU 22a starts updating the jackpot determination random number, outputs the game available state signal K1, and then updates the jackpot determination random number and inputs the game start signal K2 and the sub control board 23. The first control signal (output start signal) was not output in a standby state. When the game start signal generation circuit 22e receives the game ready state signal K1, the game start signal generation circuit 22e outputs the game start signal K2 to the main CPU 22a after a random delay time has elapsed from the time of input (when transitioned to the high level state) (high). Transition to the level state). For this reason, when a control signal (output start signal) that is first output from the main CPU 22a to the sub control board 23 is input, it can be input only after a random delay time has elapsed since the start of updating the big hit determination random number. Therefore, it becomes impossible to grasp the timing of the big hit from when the start signal is input. Accordingly, it is possible to prevent fraud due to an illegal board that causes an illegal big hit based on a control signal (output start signal) that is first output from the main CPU 22a to the sub-control board 23.

  (7) Since the timing of inputting the reset signal Re to the main CPU 22a becomes random by the operation of the instruction circuit I, the reset signal Re is illegally input to initialize the value of the big hit determination random number, and the reset signal Re It is also difficult to specify the timing that is a big hit from the time of output.

  (8) When the supply of the power supply voltage from the power supply circuit 24 and the backup power supply 27 is stopped and a standby state is entered until a predetermined time elapses, the main CPU 22a supplies the power supply voltage supplied to the RAM 22c. When the voltage becomes larger than the predetermined voltage V10, the reset signal Re1 is output to the reset input circuit 22d. At the same time, the main CPU 22a automatically restarts to execute main processing, and executes initialization processing of the RAM 22c. Thereby, the reset input circuit 22d outputs a reset signal to the game start signal generation circuit 22e based on the input of the re-reset signal Re1. For this reason, when the game start signal generation circuit 22e receives the game enable state signal K1 after the reset signal Re is input, the game start state signal K1 is first input after the reset signal Re is input. The signal K1 is output, and the game start signal K2 is output with a delay. For this reason, the main CPU 22a outputs an output start signal to the sub-control board 23 after a lapse of a random time from the start of updating the big hit determination random number. Thereby, even if time is measured from the time of outputting the output start signal, the big hit timing can be determined. For this reason, even if the initial value is set as the value of the jackpot determination random number, the timing at which the jackpot is determined cannot be specified from the timing when the power is turned off because the input timing of the reset signal Re is random. As described above, fraud caused by shutting off the power supply circuit 24 and the backup power supply 27 can be prevented.

  (9) The game start signal generation circuit 22e is provided separately from the main CPU 22a in the main control board 22. For this reason, it is not necessary to change the control program of the main CPU 22a. Further, since the game start signal generation circuit 22e and the instruction circuit I have the same circuit configuration, it is not necessary to design the circuits separately, and the design effort can be reduced.

  (10) The game start signal generation circuit 22e includes the counter value acquired by the register 55 when the input of the game ready state signal K1 starts (or ends), and the second counter 56 after the register 55 acquires the counter value. When the determination value to be updated matches, the signal level of the game start signal K2 output to the main CPU 22a is changed to a different state. In other words, the input of the game start signal K2 to the main CPU 22a is started (or ended) after a time delay based on the counter value from the start (or end) of the input of the game possible state signal K1 from the main CPU 22a. The delay time is not constant because it is based on the counter value. From the above, the time from when the game ready state signal K1 is input to when the game start signal K2 is output is not constant, and is a big hit that is measured based on the control signal output from the main CPU 22a to the sub-control board 23. Timing is also not constant. Therefore, it is possible to make it difficult to grasp the timing of occurrence of the big hit, and to prevent fraud.

  (11) In the instruction circuit I, the counter value acquired by the register 55 when the input state of the reset signal Re (or the illegal reset signal Re2) is changed, and the second counter 56 after the register 55 acquires the counter value When the determination value to be updated matches, the signal level of the reset signal Re output to the main CPU 22a is changed to a different state. That is, the output state of the reset signal Re output to the main CPU 22a transitions after a time delay based on the counter value from when the input state of the reset signal Re (or the illegal reset signal Re2) transitions from the reset signal circuit 26 or the unauthorized substrate. To do. The delay time is not constant because it is based on the counter value. From the above, the timing at which the main CPU 22a is activated after the input state of the reset signal Re (or the illegal reset signal Re2) to the main control board 22 transitions is not constant, and the timing of the big hit is also not constant. Therefore, it is possible to make it difficult to grasp the timing of occurrence of the big hit, and to prevent fraud.

  (12) Since the counter value of the instruction circuit I is updated at a predetermined update cycle different from the update cycle of the big hit determination random number, the reset signal circuit 26 (or illegal substrate) is reset by the reset signal Re (or illegal reset). Even if it is attempted to measure the timing of a big hit at a constant update cycle after the signal Re2) is output, it is difficult to grasp the timing of the big hit. Therefore, it is possible to make it difficult to grasp the timing of occurrence of the big hit, and to prevent fraud.

  (13) The instruction circuit I delays the timing and outputs the reset signal Re to the main CPU 22a each time the signal level of the reset signal Re (or the illegal reset signal Re2) changes to a different state. For this reason, if the input time of the reset signal Re (or the illegal reset signal Re2) is too short, the reset signal Re input to the instruction circuit I is low before the reset signal Re output to the main CPU 22a enters the high level state. There may be a level state. Similarly, the reset signal Re input to the instruction circuit I may be in a high level state before the reset signal Re output to the main CPU 22a side is in a low level state. In these cases, the instruction circuit I cannot normally output the reset signal Re to the main CPU 22a side, and the main CPU 22a cannot be normally regulated or activated. Accordingly, it is possible to prevent the illegal reset signal Re2 having a short input time from being input.

  (14) The instruction circuit I delays the timing each time the signal level of the reset signal Re (or illegal reset signal Re2) changes to a different state, and sends the reset signal Re (or illegal reset signal Re2) to the main CPU 22a side. Output to. For this reason, even if the main CPU 22a is activated when the signal level of the reset signal Re (or the illegal reset signal Re2) transitions from the low level state to the high level state, it transitions from the high level state to the low level state. In this case, even if the main CPU 22a is activated, the main CPU 22a can be handled.

  (15) Capacitors and resistors used in the oscillating circuit 53 of the instruction circuit I and the game start signal generating circuit 22e usually vary in performance, and the residual charge stored in the capacitors when the power is turned on Since there are usually variations, the cycle of the clock signal output from the oscillation circuit 53 varies after the power is turned on. For this reason, every time the power is turned on, there is a high possibility that the delay time of the first reset signal Re and the game start signal K2 after the power is turned on is different. That is, every time the power is turned on, there is a high possibility that the timing of the first big hit after the power is turned on will be different. Further, the counter value is updated a plurality of times during the time from when the power is turned on until the reset signal Re or the game ready state signal K1 is input. The counter value is likely to be different. For this reason, there is a high possibility that the delay time is different every time the power is turned on, and the timing of the big hit is different. Therefore, it is difficult to measure the time from the point of turning on the power and grasp the jackpot timing.

  (16) The main control board 22 is housed in a case cover, and the case cover is provided with anti-tampering measures so that an unauthorized circuit or the like cannot be directly attached to the main control board 22 from the outside. For this reason, by attaching the instruction circuit I and the game start signal generation circuit 22e to the main control board 22, an illegal board is provided between the main CPU 22a and the instruction circuit I or between the main CPU 22a and the game start signal generation circuit 22e. Can be prevented from being attached. Therefore, it is possible to reliably input the reset signal Re through the instruction circuit I. That is, the reset signal Re (or the illegal reset signal Re2) can be reliably delayed and input to the main CPU 22a. Further, it is possible to reliably input a game start signal from the game start signal generation circuit 22e. That is, the game start signal K2 can be reliably delayed and input to the main CPU 22a.

  (17) Each of the instruction circuit I and the game start signal generation circuit 22e is provided with a frequency dividing circuit 60, and the delayed external clock signal input from the external oscillation circuit 70 provided outside is output as an update clock signal. I tried to do it. Therefore, the reset signal Re can be sufficiently delayed even when a high-frequency external clock signal is input.

  (18) The second counter 56 updates the determination value every cycle of the update clock signal. For this reason, if the cycle of the update clock signal is different from the update cycle of the big hit determination random number, the timing of the big hit may be shifted when the timing is measured at a constant cycle after the reset signal Re transitions to a different state. Become. In addition, it is difficult to switch the measurement cycle in the middle because it is necessary to know the counter value stored in the register 55 of the instruction circuit I. Therefore, it is possible to make it difficult to grasp the timing of the big hit, and it is possible to prevent fraud due to the input of the illegal reset signal Re2.

  (19) An oscillation circuit 53 that generates and outputs an internal clock signal that determines the update cycle of the counter value is provided in the instruction circuit I and the game start signal generation circuit 22e. For this reason, it is difficult to recognize the cycle of the internal clock signal from the outside of the instruction circuit I. Therefore, it is difficult to grasp the timing of the big hit, and fraud can be prevented.

  (20) The frequency of the external clock signal input from the external oscillation circuit 70 provided outside the instruction circuit I and the game start signal generation circuit 22e is divided by 16000 or 1/20000 by the frequency dividing circuit 60. I was able to. For this reason, it is difficult to recognize from the outside of the instruction circuit I and the game start signal generation circuit 22e how much the external clock signal input from the external oscillation circuit 70 is divided, and it is possible to recognize the update period of the determination value. It becomes difficult. Therefore, it is difficult to grasp the timing of the big hit, and fraud can be prevented.

In addition, you may change the said embodiment as follows.
In the above embodiment, the main CPU 22a is configured to output the re-reset signal Re1 for the time T1, but the output time may be arbitrarily changed. In this case, the reset input circuit 22d that inputs the re-reset signal Re1 needs to output the reset signal Re to the instruction circuit I for the time T1 + T2 when the re-reset signal Re1 is input.

  In the above embodiment, the main CPU 22a inputs the reset signal Re1 to the reset input circuit 22d. However, the main control board 22 may be provided with a circuit that monitors the state of the main CPU 22a and outputs the reset signal Re1. good.

In the above embodiment, the power supply circuit 24 also supplies the power supply voltage to the RAM 22c, but it may not be supplied.
In the above embodiment, the instruction circuit I is provided, but it may not be provided.

  In the above embodiment, the game start signal generation circuit 22e and the instruction circuit I have the same circuit configuration. The timing at which the reset signal Re is input to the instruction circuit I is the timing at which the game ready signal K1 is input to the game start signal generation circuit 22e and the timing at which the game start signal generation circuit 22e outputs the game start signal K2. Completely different. The timing at which the reset signal Re is output from the instruction circuit I is completely the same as the timing at which the game ready state signal K1 is input to the game start signal generation circuit 22e and the timing at which the game start signal generation circuit 22e outputs the game start signal K2. Different. Therefore, the game start signal generation circuit 22e and the instruction circuit I may be a single circuit. In this way, the number of components can be reduced, and the fraud prevention circuit can be installed even if the circuit installation space in the main control board 22 is small.

In the above embodiment, the instruction circuit I is provided, but it may not be provided. That is, the reset input circuit 22d and the main CPU 22a may be directly connected.
In the above embodiment, the game start signal generation circuit 22e and the instruction circuit I have the same circuit configuration, but may have different circuit configurations.

  In the above embodiment, if the game start signal generation circuit 22e can output the game start signal K2 after a random delay time has elapsed since the input of the game ready state signal K1, the circuit configuration is arbitrarily changed. You may do it. Similarly, if the instruction circuit I can output the reset signal Re to the main CPU 22a after a random delay time has elapsed since the input of the reset signal Re, the circuit configuration may be arbitrarily changed.

  In the above embodiment, if the update period of the determination value is an appropriate period for providing a delay time, the frequency dividing circuit 60 that divides the external clock signal output from the external oscillation circuit 70 may not be provided. . That is, the second counter 56 may update the determination value for each cycle of the external clock signal output from the external oscillation circuit 70.

  In the above embodiment, the main CPU 22a starts when the reset signal Re transitions from the high level state to the low level state, but starts when the reset signal Re transitions from the low level state to the high level state. Anyway. In this case, it is necessary to invert the reset signal Re output from the instruction circuit I.

  In the above embodiment, the instruction circuit I delays the transition timing every time the reset signal Re (or the illegal reset signal Re2) transitions to a different state. As another example, if the start of the main CPU 22a is performed at the timing of transition from the high level state to the low level state, the reset signal Re is delayed only when transitioning from the high level state to the low level state. Also good. Further, if the start of the main CPU 22a is started at a timing when the low level state is changed to the high level state, the reset signal Re may be delayed only when the reset signal Re changes from the low level state to the high level state.

  In the above embodiment, when the big hit determination random number is updated to the maximum value, it is continuously updated from the minimum value, but it is not always necessary to continuously update from the minimum value. For example, “0” → “1” →... “630” → “100” → “101” →... May be continuously updated from a non-minimum value next to the maximum value. In this way, it is possible to make it difficult to grasp the timing of a big hit and to prevent fraud.

  In the above embodiment, the determination value is incremented by 1 to determine the timing for transitioning the signal level of the reset signal Re output from the instruction circuit I, and it is determined whether or not the counter value is reached. Alternatively, the counter value may be subtracted by 1 to determine whether or not the counter value has become 0.

  In the above embodiment, the external oscillation circuit 70 that outputs the external clock signal is provided outside the instruction circuit I, but may be provided in the instruction circuit I and the game start signal generation circuit 22e. In this way, it becomes more difficult to discriminate the update period of the determination value, and fraud can be prevented.

  In the above embodiment, the oscillation circuit 53 that generates and outputs the internal clock signal is provided in the instruction circuit I and the game start signal generation circuit 22e. However, the oscillation circuit 53 is provided outside the instruction circuit I and the game start signal generation circuit 22e. It may be provided.

  In the above embodiment, the backup process is configured to be executable, but the backup process may not be performed. In this case, initialization processing is always performed when the power is shut off.

In the above embodiment, the RAM clear switch 36 and the RAM clear switch circuit 37 are provided, but they may not be provided.
In the above embodiment, the main CPU 22a, the instruction circuit I, and the game start signal generation circuit 22e receive the external clock signal having the same cycle from the external oscillation circuit 70, but the main CPU 22a, the instruction circuit I, The game start signal generation circuit 22e may input signals having different periods. In this way, the update period of the jackpot determination random number and the update period of the determination value are asynchronous. And since it is difficult to grasp these three different periods from the outside of the main control board 22, fraud can be effectively prevented.

  In the above embodiment, when the signal level of the reset signal Re is in the high level state, it is assumed that the reset signal Re (signal based on the illegal reset signal Re2) is input (output), and in the low level state, the reset signal Re ( It is assumed that the input (output) of the signal based on the illegal reset signal Re2 is completed. As another example, when the signal level of the reset signal Re is in the low level state, it is assumed that the reset signal Re (signal based on the illegal reset signal Re2) is input (output), and in the high level state, the reset signal Re (incorrect The input (output) of the signal based on the reset signal Re2 may be completed. Similarly, when the signal level of the game ready state signal is in the low level state, it is assumed that the game ready state signal is input (output), and when in the high level state, the input (output) of the game ready state signal is completed. Good. Similarly, a game start signal may be input (output) when the game start signal level is in the low level state, and a game start signal input (output) may be completed when the game start signal level is in the high level state.

  In the timer interrupt process of the above embodiment, the main CPU 22a may update a random number directly related to the player's profit. For example, to determine whether or not a probability variation state that gives a high probability of winning the jackpot determination is given (for example, a jackpot symbol) or whether to open or close the opening / closing blade Or a random number for deciding whether or not to give a small hit game for opening the big winning opening may be updated.

  In the standby time random number update process of the above embodiment, the main CPU 22a may update a random number such as a reach determination random number for determining whether or not to execute the reach effect.

  In the above-described embodiment, it is adopted in a pachinko machine, but may be embodied in a pachinko slot machine (rotating game machine, hereinafter referred to as “pachislot”) which is a kind of gaming machine. In addition, after the player sets the number of bets (the number of bets), the pachislot starts the game (fluctuating game) by operating the start lever and stops the symbol by operating the stop button. Has a game characteristic in which a medal, which is a game medium, is awarded to a player when an award mode that satisfies a game medium payout condition is formed. In addition, the pachislot is played (variable game) with one game unit from the start of the game (variable game) to the completion of payout of the game medium to be awarded as a prize.

  More specifically, the pachi-slot includes a main control board that controls the entire gaming machine and an effect control means that controls the effect execution means based on a control signal from the main control board. The pachi-slot is provided with a symbol display means (effect execution means) for displaying a plurality of symbols. In addition, the pachislot allows the player to set the number of bets (the number of bets) of coins as a game medium within the range of the minimum bet number to the maximum bet number set in advance by the selection means, and then change the symbols on the symbol display means. When starting one game, a start lever is provided as a start signal output means that is operated by the player and outputs a start signal instructing the start of one game.

  Further, the main control board of the pachislot obtains the value of the winning combination determination random number based on the input of the start signal, and by lottery from a plurality of predetermined winning combinations based on the value of the winning combination determination random number A control device for determining the winning combination is provided. In addition, the control device has a function as a symbol variation means for starting the variation of the symbol based on the input of the start signal. Further, the control device includes a stop signal output means for outputting a stop signal for instructing to stop the change of the symbol changing in the symbol display means based on the stop operation by the player, and the stop signal Is provided as a stop control means for stopping a symbol that is changing based on the input of.

  The pachislot control device gives a prize when the combination of symbols stopped and displayed on the winning line of the predetermined symbol display means is a combination of symbols corresponding to the winning combination determined by the winning combination determining means. It is supposed to be. Further, the control device of the pachislot determines the winning combination by lottery from a plurality of predetermined winning combinations based on the winning combination determining random number acquired with the input of the start signal. Then, when the determined winning combination is a predetermined winning combination (bonus combination), the control device determines the winning combination in which the combination of symbols stopped and displayed on the winning line of the predetermined symbol display means is determined. In the case of a combination of symbols corresponding to the combination, a big hit game (bonus game) advantageous to the player is given.

Next, a technical idea that can be grasped from the above embodiment and another example will be added below.
(A) After the control device has entered the standby instruction signal to enter a standby state until a start instruction signal is input to the input means, and enters a standby state until a predetermined time has elapsed, the control device performs a reset, and When an initialization instruction signal is input at the reset, the storage contents of the storage means for storing at least the value of the random number for jackpot determination are initialized, and the output start indicating that the control for the effect control means is started starts the output of the signal, we start the control related to game effects.

(B) The control device determines the jackpot when the game is possible by erasing the stored contents of the storage means storing the jackpot determining random number and then starting to update the jackpot determining random number. and start updating use random numbers that have been a game state signal indicating that it is possible to gaming to output to the proof means.

(C) The fraud prevention means sends the game start signal to the control device without delay when the game ready state signal is inputted when the activation instruction signal is not inputted to the input means. you output for.

(D) The fraud prevention means receives the first update means for updating the counter value within a predetermined range for each cycle of the internal clock signal output by the first signal generation means, and the game available state signal. Acquisition means for acquiring the counter value in this case, second signal generation means for generating and outputting an update clock signal for each predetermined period different from the update period of the big hit determination random number, and the acquisition means includes the counter A second updating unit that updates the determination value for each period of the update clock signal output by the second signal generating unit after acquiring the value; a counter value acquired by the acquiring unit; and the second updating unit. Transition means for outputting the game start signal to the control device when the updated determination values match .

(E) a power supply board that supplies power to the main control board and the effect control board when the power is turned on; and the power supply board supplies power to the main control board and the effect control board; A start instruction signal output means for outputting, and the control device inputs a start instruction signal via an instruction circuit, and the start instruction signal has a first state and a second state as its signal level. When the signal level of the input activation instruction signal is in the first state, the operation is restricted while the control device makes a transition from the first state to the second state. The instruction circuit is configured to start, and the instruction circuit has an internal clock signal having a cycle that can be output a plurality of times from when the power is turned on until the start instruction signal is input to the instruction circuit. First signal generating means for indicating circuit for generating and outputting the signal, and for the indicating circuit for updating the counter value within a predetermined range for each cycle of the internal clock signal output by the first signal generating means for indicating circuit A first updating means, an instruction circuit obtaining means for obtaining the counter value when the signal level of the input activation instruction signal is changed, and a predetermined period different from the update period of the jackpot determination random number A second signal generation means for indicating circuit that generates and outputs an update clock signal, and an update that is output by the second signal generation means for indicating circuit after the acquisition means for indicating circuit acquires the counter value. The instruction circuit second update means for updating the determination value for each cycle of the clock signal, the counter value acquired by the instruction circuit acquisition means, and the instruction circuit second update means are updated. When a constant value matches, the instruction circuit timing instruction means for instructing to change the signal level of the activation instruction signal output to the control device to a different state, and according to the instruction of the instruction circuit timing instruction means, Instruction circuit transition means for transitioning the signal level of the activation instruction signal output to the control device to a different state is provided .

(F) When the supply of power supply voltage to the storage means is stopped, the control device is configured to store the jackpot determination random number stored in the storage means when the power supply to the storage means is resumed. after setting the initial value as a value, to start the update of the jackpot determining random numbers, then that is configured to output the game state signal.

(G) When the activation instruction signal is input to the input means and the controller is activated in response to the input, the control device stores the initial value or the power-off random number value stored in the storage means when the power is stopped. after setting the backup data, Ru is configured to update the value of the jackpot determining random number at predetermined intervals.

  DESCRIPTION OF SYMBOLS 10 ... Pachinko machine (game machine), 18 ... Display device, 21 ... Power supply board, 22 ... Main control board, 22a ... Main CPU (control device), 22c ... RAM (storage means), 22d ... Reset input circuit (input) Means), 22e ... Game start signal generation circuit (tamper prevention means), 23 ... Sub control board, 23a ... Sub CPU, 24 ... Power supply circuit (operating power supply), 25 ... Power interruption monitoring circuit, 26 ... Reset signal circuit, 27 ... backup power supply (dedicated power supply), 36 ... RAM clear switch, 37 ... RAM clear switch circuit, 51 ... timing generator (timing instruction means, timing instruction means for instruction circuit), 52 ... delay circuit (transition means, instruction circuit) Transition means), 53... Oscillating circuit (first signal generating means, first signal generating means for instruction circuit), 54... First counter (first updating means) First updating means for instruction circuit), 55... Register (acquisition means, acquisition means for instruction circuit), 56... Second counter (second updating means, second updating means for instruction circuit), 60. ... third counter, 62 ... divider, 63 ... data selector, 64 ... selection switch, 70 ... external oscillation circuit (second signal generating means, second oscillation circuit), K1 ... game-ready state signal, K2 ... game start Signal, I ... Instruction circuit (tamper prevention means, second tamper prevention means), Re ... Reset signal (start instruction signal), Re1 ... Re-reset signal (restart instruction signal), Re2 ... Illegal reset signal (start instruction signal) ), S: Power-off signal (standby instruction signal), SE: Winning detection sensor (starting winning means).

Claims (1)

In a gaming machine comprising a main control board for controlling the entire gaming machine, and an effect control means for controlling an effect execution means based on a control signal from the main control board,
The main control board is
After the activation, the value of the jackpot determination random number is updated every predetermined period, the updated value of the jackpot determination random number is stored in the storage means, and when the game is possible, the update of the jackpot determination random number is updated. When a game start state signal for informing that a game is possible is started and a game start signal instructing the start of control related to the game effect is input, the control signal is output to the effect control means. At the same time, control related to the game effect is started, and a big hit determination is performed to determine whether or not the big hit is determined by using the value of the big hit determination random number acquired from the storage means when the game ball wins the start winning means. A control device for providing a jackpot gaming state when the determination result of the jackpot determination is affirmative;
Input means for inputting a start instruction signal for instructing start of the control device;
When the activation instruction signal is input to the input means, and the game ready state signal is input, the game start signal is sent to the control device after a randomized delay time has elapsed. With anti-fraud means to output,
The control device enters a standby state after inputting a standby instruction signal to enter a standby state until a start instruction signal is input to the input means,
The input means activates the control device based on the input activation instruction signal, and has the same function as the activation instruction signal when the control device enters a standby state beyond a predetermined time. being adapted to enter the re-activation instruction signal having,
The activation instruction signal is a binary signal indicating the first state and the second state as the signal level thereof,
The control device is controlled to operate when the signal level of the input activation instruction signal is in the first state, and to be activated when the signal transitions from the first state to the second state. Configured,
When the control device is in a standby state until a predetermined time has elapsed after inputting the standby instruction signal, the control device has a first state restart instruction having a function equivalent to that of the first state start instruction signal. Outputting a signal to the input means;
When the input means inputs the restart instruction signal in the first state, the input means outputs the start instruction signal in the first state to the control device for a predetermined time and regulates its operation, and then the second state A gaming machine , wherein a starting instruction signal is output to the control device to be started .

Images