JP5763440B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a status register.

  In general, as a semiconductor memory device, as shown in FIG. 6, a matrix structure of a plurality of word lines and bit lines (1024 word lines and 256 bit lines in FIG. 6) is formed. 2. Description of the Related Art There is known a semiconductor memory device including a memory cell array that stores information by a ferroelectric memory that is a memory element provided corresponding to a crossing portion.

  For example, a semiconductor memory device including a ferroelectric memory (memory cell array) compatible with an SPI (Serial Peripheral Interface) system for performing serial communication is known. As described above, the semiconductor memory device including the SPI type ferroelectric memory includes a so-called status register as a nonvolatile register for setting an operation state of the semiconductor memory device (memory cell array). For example, Patent Document 1 describes a ferroelectric memory that includes a status register and that supports the SPI system.

JP 2010-244675 A

  FIG. 7 shows a schematic configuration diagram of a specific example of a conventional semiconductor memory device. In the semiconductor memory device 100 shown in FIG. 7, a memory unit 122, an SPI interface 124, an external terminal 126, and an electric fuse 158 are formed on a semiconductor chip 120. In addition, the storage unit 122 includes a memory cell array 132 having the main storage capacity 140 and the status register 142 formed of the memory cell array shown in FIG. 6 and signal processing for outputting electric signals to the word lines and bit lines of the memory cell array 132. Circuit 130.

  In such a semiconductor memory device 100, it is generally performed to store (record) detailed information about itself in each semiconductor memory device 100. For example, information relating to production history, design information, and the like are stored (recorded) for the purpose of analyzing a failure or malfunction of the semiconductor storage device 100.

  As a method for storing (recording) information relating to the production history, in the wafer test process of the semiconductor memory device 100, the information relating to the production history of each semiconductor memory device 100 is converted into a binary number, and each semiconductor memory device 100 (semiconductor Generally, a method for storing a fuse (electric fuse 158) dedicated to recording information relating to production history provided on a chip 120 (also referred to as a die) by cutting the fuse according to the binary number using an electric fuse cutting device is performed. ing.

  As a method for referring to the information regarding the production history recorded in the electric fuse 158 in this way, the resin for sealing the die 120 of the semiconductor memory device 100 is removed, and the electric fuse 158 is visually checked. And the operation state of the semiconductor memory device 100 is set to a special state (for example, an operation state operated by a special command input) for referring to information relating to the production history, and is recorded in the electric fuse 158. A method of converting a binary number into a voltage and outputting it to an external terminal 126 is known.

  Thus, when recording the information regarding the production history in the electric fuse 158, since the electric fuse 158 is installed, there may be a problem that the area of the semiconductor chip (die) 120 increases.

  Further, when referring to the information recorded in the electrical fuse 158, the semiconductor memory device 100 must be destroyed, for example, by removing the resin that seals the die 120 in order to view the electrical fuse 158 as described above. There is a case that you dont have. In order to output to the external terminal 126, it is necessary to install a circuit (not shown) for converting the binary number recorded in the electrical fuse 158 into a voltage and outputting it to the external terminal. Further, there may be a problem that the area of the semiconductor chip (die) 120 increases.

  The present invention has been proposed to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device that can appropriately store device information related to the semiconductor memory device in the semiconductor memory device itself. And

In order to achieve the above object, a semiconductor memory device according to claim 1 includes a plurality of first memory elements arranged corresponding to each of intersections of a plurality of word lines and a plurality of bit lines. A main memory area, a partial area of a specific word line arranged outside the main memory area adjacent to the word line, and a specific bit line arranged outside the main memory area adjacent to the bit line A status register for setting an operation state of the main storage area, and the status register is provided on the specific word line. when on, the said status register of a particular word line provided in a region other than the partial region that is provided, wherein if said status register to a particular bit line is provided, Serial said status register of a specific bit line provided in the region other than the partial region that is provided, and the device information storage comprising at least one third storage element for storing the device information regarding its own semiconductor memory device A region.

  According to the present invention, there is an effect that device information relating to the semiconductor memory device can be appropriately stored in the semiconductor memory device itself.

1 is a schematic configuration diagram showing an example of a semiconductor memory device according to a first embodiment. 1 is a schematic configuration diagram showing a specific example of a memory cell array according to a first embodiment. It is a schematic block diagram which shows an example of the semiconductor memory device which concerns on 2nd Embodiment. It is a schematic block diagram which shows a specific example of the memory cell array based on 3rd Embodiment. It is a schematic block diagram which shows an example of the semiconductor memory device which concerns on 4th Embodiment. It is a schematic block diagram which shows a specific example of the conventional memory cell array. It is a schematic block diagram which shows an example of the conventional semiconductor memory device.

  [First Embodiment]

  Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that in this embodiment, a semiconductor memory device compatible with a serial communication (SPI) method will be described in detail.

  A schematic configuration diagram of an example of a schematic configuration of the semiconductor memory device of the present embodiment is shown in FIG. The semiconductor memory device 10 according to the present embodiment includes a storage unit 22, an SPI interface 24, and an external terminal 26 on a semiconductor chip (die) 20.

  The storage unit 22 includes a signal processing circuit 30 and a memory cell array 32, and is, for example, a ROM (Read Only Memory). The signal processing circuit 30 outputs an electrical signal for writing (storing) information in the memory cell array 32 and reading (referring) stored information in accordance with the input command and address. It has a function of outputting to 32 word lines and bit lines. The memory cell array 32 according to the present embodiment includes a main storage capacity 40, a status register 42, and a production history storage capacity 44, and is provided corresponding to the intersections of word lines and bit lines, respectively. A plurality of storage elements which are dielectric memories are provided (details will be described later). In FIG. 1, description of a drive circuit and the like for driving each of the word line and the bit line is omitted.

  The SPI interface 24 is an SPI (Serial Peripheral Interface) system, and is a 4-wire serial communication interface that performs data transfer serially (one bit at a time). In the SPI method, an SCK (Serial Clock) signal, which is a clock pulse necessary for exchanging data, an SS (Slave Select) signal for selecting a desired slave device (slave), and a MOSI (Master Out Slave In) that outputs data. ) Signal and a master in slave out (MISO) signal to which data is input, to communicate with the slave device (slave). The external terminal 26 is a terminal for transmitting / receiving data to / from an external device (slave device) using the SPI interface 24.

  FIG. 2 shows a schematic configuration diagram of a specific example of the memory cell array 32 of the present embodiment. As described above, the memory cell array 32 of the present embodiment includes the main storage capacity 40, the status register 42, and the production history storage capacity 44. In the memory cell array 32 of the present embodiment, as a specific example, a matrix structure is configured by 1025 (1024 + 1) (details will be described later) and 256 bit lines. A plurality (256 × 1025 = 262400) of ferroelectric memories (memory elements) provided corresponding to the intersections are provided.

  The semiconductor storage device 10 according to the present embodiment is a memory having a storage capacity of 256 kbits. Therefore, the main storage capacity 40 has 1024 word lines and 256 bits in order to form a storage capacity of 256 kbits. It has a matrix structure with lines. In the present embodiment, as shown in FIG. 2, as a specific example, strong corresponding to the intersection of the matrix structure composed of the 0th to 1023rd word lines and the 0th to 255th bit lines. A dielectric memory is provided.

  In this embodiment, since the memory is compatible with the SPI system, in addition to the main storage capacity 40, a status register 42 for setting the operation state of the storage unit 22 (main storage capacity 40) is provided. In general, a memory corresponding to the SPI system is provided with a non-volatile register called a status register for setting an operation state of a storage device according to specifications. In general, the status register requires an 8-bit storage capacity. For example, in the status register (status register 42), a WEL (Write Enable Latch) bit for write-protecting all the ferroelectric memories (storage elements) of the memory cell array (main storage capacity 40) or a specific ferroelectric It has BP (Memory Block Write Protection Bit) 0, BP1 bit, etc. for write-protecting the body memory (storage element) area. In the status register (status register 42), a WRDI (Write Disable) command or WREN (Set Write Enable Latch), which is different from a normal command for storing or referring data to the memory cell array 32 (main storage capacity 40), is used. ) “0” or “1” is stored or referred to by a specific command such as a command.

  In this embodiment, the 1025th word line is provided as a specific word line adjacent to the word line constituting the main storage capacitor 40, and is provided corresponding to the intersection of the specific word line and 256 bit lines. The obtained ferroelectric memory is used as the status register 42. Here, there are 256 (256 bits) ferroelectric memories on a specific word line. As described above, since the maximum number of bits used as the status register 42 is 8 bits, Of the 256-bit ferroelectric memory, the status register 42 is configured by 8 bits (in FIG. 2, eight ferroelectric memories corresponding to intersections with the 0th to 7th bit lines). Yes.

  In the present embodiment, the remaining ferroelectric memory on the specific word line that is not used as the status register 42 constitutes a production history storage capacity 44 for storing information relating to the production history. Specifically, in the present embodiment, as shown in FIG. 2, the production history storage capacity 44 is constituted by 248 (248 bits) ferroelectric memories corresponding to the intersections with the 8th to 255th bit lines. Is configured. In the present embodiment, the information relating to the production history is information relating to the production of the semiconductor memory device 10 (semiconductor chip 20) itself. For example, the history of the wafer, the wafer number, the lot number, the information relating to the previous process, and the operation Data of the factory and tester that performed the measurement, production progress, etc. are included.

  The storage and reference of information related to the production history of the production history storage capacity 44 is performed by normal commands for storing and referring to the information of the main storage capacity 40 and storage and reference of “0” or “1” for the status register 42. A special command is used that is different from the specific command (see above). The special command input to the signal processing circuit 30 is set to a special state where information relating to the production history of the production history storage capacity 44 is stored or referred to, and the specific word line and the corresponding bit line are enabled. When the electrical signal for output is output, information relating to the production history is stored or referred to. As described above, by performing recording / reference to the production history storage capacity 44 using a special command, a user using the semiconductor storage device 10 (semiconductor chip 20) is mistakenly stored in the production history storage capacity 44. It is possible to suppress rewriting of information related to production history.

  As described above, in the semiconductor memory device 10 of the present embodiment, it intersects with the eighth to 255th bit lines, which are areas where the status register 42 is not provided on the specific word line (1024th word line). The production history storage capacity 44 is constituted by a ferroelectric memory provided in the area to be stored, and information related to the production history of the semiconductor memory device 10 (semiconductor chip 20) is stored in the production history storage capacity 44. For the storage / reference to the production history storage capacity 44, a special command different from the normal command used for storage / reference to the main storage capacity 40 is used.

  In this way, by forming the production history storage capacity 44 by the ferroelectric memory on the specific word line, an electric fuse (electric fuse 158) is provided as in the conventional semiconductor memory device (see FIG. 7, semiconductor memory device 100). Since information relating to the production history can be stored without providing, an increase in the area of the semiconductor chip (die) 20 can be suppressed. Further, by using a special command, information related to the production history can be referred to from the production history storage capacity 44, so that the semiconductor memory device 10 is destroyed, for example, by removing the resin that seals the semiconductor chip (die) 20. It is possible to refer to the information related to the production history without doing so. Further, since information related to production history can be stored in the production history storage capacity 44 by using a special command, information related to the production history can be stored in a process other than a predetermined process such as a wafer test process or when desired. Can be stored.

  Therefore, production history information related to the own semiconductor memory device 10 can be appropriately stored as device information in the semiconductor memory device 10 itself.

  [Second Embodiment]

  Hereinafter, a semiconductor memory device according to a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 shows a schematic configuration diagram of an example of a schematic configuration of the semiconductor memory device of the present embodiment. In the present embodiment, the configuration and operation substantially similar to those of the first embodiment are described as such, and detailed description thereof is omitted.

  The semiconductor memory device 50 of the present embodiment is different from the semiconductor memory device 10 of the first embodiment in that an electric fuse 58 is further formed on a semiconductor chip (die) 60.

  In the semiconductor memory device 10 of the first embodiment, information related to the production history is stored only in the production history storage capacity 44, but physical destruction of the ferroelectric memory included in the production history storage capacity 44 is performed. For example, it may not be possible to refer to information related to accurate production history. For this reason, the semiconductor memory device 50 according to the present embodiment includes an electric fuse 58 for recording information relating to production history. The electric fuse 58 shown in FIG. 3 includes a group of electric fuses having a plurality of electric fuses, a circuit for referring to information recorded in the electric fuses, and the like.

  When recording information related to production history in the electric fuse 58, the electric fuse is cut in advance by an electric fuse cutting device. For example, when recording “0”, the electric fuse is cut so that the electric signal is not conducted. When recording “1”, the electric signal is conducted without cutting the electric fuse. That's fine. Further, recording may be performed depending on whether or not individual electric fuses determined in advance according to information on the production history are to be cut.

  The information relating to the production history to be recorded may be all the information stored in the production history storage capacity 44, but the production history storage capacity 44 is destroyed or the like, and information relating to the production history is recorded from the production history storage capacity 44. It is preferable to use a part of information (for example, the minimum necessary for failure analysis) determined in advance based on importance, etc., instead of all information. . Thus, by recording only a part of information, an increase in the area of the semiconductor chip (die) 60 can be suppressed.

  As described above, the semiconductor storage device 50 according to the present embodiment includes the electrical fuse 58 that records information relating to the production history. Therefore, even if the information cannot be referred from the production history storage capacity 44, the information relating to the production history is displayed. You can refer to it.

[Third Embodiment]

  Hereinafter, a semiconductor memory device according to a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 shows a schematic configuration diagram of an example of a schematic configuration of the memory cell array according to the present embodiment. In the present embodiment, the configuration and operation that are substantially the same as those in the first embodiment and the second embodiment are described as such, and detailed description thereof is omitted.

  The semiconductor memory device of this embodiment is different from the first and second embodiments in that it further includes a checksum storage capacity 46 for storing a checksum.

  In the semiconductor memory devices 10 and 50 of the first embodiment and the second embodiment, for example, they are stored in the production history storage capacity 44 due to misuse by a user or the like who uses the semiconductor memory devices 10 and 50. Information about production history may be rewritten, and accurate information about production history may not be referred to. Therefore, the semiconductor storage device of the present embodiment is configured to include a checksum storage capacity 46 for storing a checksum of information relating to the production history stored in the production history storage capacity 44.

  In this embodiment, as a specific example, as shown in FIG. 4, a checksum storage capacity 46 is configured by a ferroelectric memory that is not used for the status register 42 and the production history storage capacity 44 on a specific word line. ing. Specifically, as shown in FIG. 4, the production history storage capacity 44 is constituted by a ferroelectric memory corresponding to the intersection of the eighth to n + 1th bit lines and the specific word line, and n + 2 to 255th. A checksum storage capacitor 46 is constituted by a ferroelectric memory corresponding to the intersection of the bit line and the specific word line.

  As described above, the semiconductor storage device according to the present embodiment includes the checksum storage capacity 46 that stores the checksum of the information related to the production history stored in the production history storage capacity 44, and therefore is stored in the production history storage capacity 44. Whether the information relating to the production history is correct or incorrect can be determined.

  In the present embodiment, the checksum of the information relating to the production history stored in the production history storage capacity 44 is stored in the checksum storage capacity 46 attached to the production history storage capacity 44 on a specific word line. However, it is not limited to this. For example, the checksum may be recorded in the electric fuse 58 of the semiconductor memory device 50 of the second embodiment, or a separate storage unit for storing the checksum may be provided on the semiconductor chip (die). May be. The information production history storage capacity 44 and the checksum storage capacity 46 are arranged side by side on a specific word line except for the status register 42, thereby preventing an increase in the area of the semiconductor chip (die). This is preferable.

  In this embodiment, a checksum is stored as a specific example, but it is detected whether the information related to the production history stored in the production history storage capacity 44 is accurate (not rewritten). However, the information is not limited to the checksum, and may be other error detection codes.

[Fourth Embodiment]

  Hereinafter, a semiconductor memory device according to a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 5 shows a schematic configuration diagram of an example of a schematic configuration of the semiconductor memory device of the present embodiment. In the present embodiment, the configuration and operation substantially similar to those in the first to third embodiments are described as such, and detailed description thereof is omitted.

  In the first to third embodiments, the case where the present invention is applied to the storage unit 22 (memory cell 32) configured by a ferroelectric memory corresponding to the SPI method has been described in detail. You may make it apply to the memory | storage part 22 (memory cell 32) comprised by the ferroelectric memory corresponding to systems (serial communication systems other than SPI, a parallel communication system, etc.).

  The semiconductor memory device 70 according to the present embodiment includes a communication interface 84 and a plurality of external terminals 86 on a semiconductor chip (die) 80, and is configured to perform communication in parallel.

  Even in the storage unit 22 (memory cell 32) configured by a ferroelectric memory compatible with other interface methods, the same semiconductor chip (die) 80 may be configured to support a plurality of interface methods. Even if they are not the same semiconductor chip (die) 80, if they are configured by a design method using design assets, the ferroelectric memory (storage element) and control circuit (not shown) of the status register 42 Is formed on the semiconductor chip (die) 80 with its function stopped. Therefore, also in the memory cell array 32 of the semiconductor memory device 70 of the present embodiment, the production history storage capacity 44 is constituted by the ferroelectric memory (storage element) in the area where the status register 42 on the specific word line is not provided. Can do.

  Also in the semiconductor storage device 70 of the present embodiment, the storage and reference of the information related to the production history of the production history storage capacity 44 is the information of the main storage capacity 40 as described in the first embodiment. Can be executed by using a special command different from a normal command for storing and referencing and a specific command for storing and referencing “0” or “1” for the status register 42. The special command input to the signal processing circuit 30 is set to a special state where information relating to the production history of the production history storage capacity 44 is stored or referred to, and the specific word line and the corresponding bit line are enabled. When the electrical signal for output is output, information relating to the production history is stored or referred to.

  As described above, in the semiconductor memory device 70 of the present embodiment, the status register 42 on the specific word line is also stored in the memory unit 22 (memory cell 32) configured by the ferroelectric memory corresponding to the interface system other than the SPI system. The production history storage capacity 44 can be configured in the excluded area.

  In the first to fourth embodiments, a case has been described in which information relating to a production history is stored in the production history storage capacity 44 as device information relating to the own semiconductor memory device (10, 50, 70). However, the design information and the like of the semiconductor memory device 10 (semiconductor chip 20) itself may be stored. The information is not particularly limited as long as it is predetermined information required for analyzing a failure such as a failure or an operation failure of the semiconductor memory device 10 (semiconductor chip 20) itself. In addition to these pieces of information, information on the semiconductor storage device 10 (semiconductor chip 20) desired by the user using the semiconductor storage device 10 (semiconductor chip 20) (for example, installation of the semiconductor storage device 10 (semiconductor chip 20)). Location etc.) may be stored.

  In the first to fourth embodiments, the ferroelectric memory (storage capacity) other than the status register 42 on the specific word line is used as the production history storage capacity 44 for storing information related to the production history. The configuration is not limited to this, but a specific bit line (for example, the 256th bit line) is provided instead of the specific word line, and the status register 42 and the production history storage capacity 44 are configured on the bit line. May be. Which of the specific word line and the specific bit line is to be provided is selected from the viewpoint of suppressing an increase in the area of the semiconductor chip (die) 20 (for example, a signal line having a shorter length). If there is a lot of information relating to the production history to be stored, it is sufficient to provide one including more ferroelectric memories.

  The configurations of the semiconductor memory device 10 and the memory cell 32 described in the first to fourth embodiments are merely examples, and can be changed according to the situation without departing from the gist of the present invention. It goes without saying that it is done.

10, 50 Semiconductor memory device 24 SPI interface 30 Signal processing circuit 32 Memory cell array 40 Main memory capacity 42 Status register 44 Production history memory capacity 46 Checksum memory capacity 58 Electrical fuse

Claims (9)

A main storage area comprising a plurality of first storage elements arranged corresponding to each of the intersections of the plurality of word lines and the plurality of bit lines;
Some of the regions, and some regions of a specific bit lines disposed in the main storage area outside and adjacent to the bit line of the word lines specified word line arranged outside the main storage area adjacent to the A status register for setting an operating state of the main storage area, comprising at least one second storage element provided in at least one of
Wherein if said status register to a particular word line is provided, wherein said status register of a particular word line is provided in the region other than the partial region that is provided, said status register to said specific bit line If provided, the said status register of a specific bit line provided in the region other than the partial region that is provided, and at least one third storage for storing device information regarding its own semiconductor memory device A device information storage area comprising elements;
A semiconductor memory device.   2. The semiconductor memory device according to claim 1, wherein the device information is information used for at least one of failure analysis and malfunction analysis of the semiconductor memory device. A process for outputting an electrical signal to the word line and the bit line based on a storage command for storing information in the main storage area, a reference command for referring to information from the main storage area, and an address of the first storage element And the identification based on a predetermined command for storing or referring to the device information in the device information storage area and an address of the third storage element, which are different from the storage command and the reference command. 3. The semiconductor memory device according to claim 1, further comprising processing means for performing processing for outputting an electric signal to the word line and the bit line or the word line and the specific bit line.   4. The semiconductor memory device according to claim 1, further comprising a fuse for recording the device information stored in the device information storage area.   The semiconductor memory device according to claim 4, wherein the fuse records a predetermined part of the device information. 6. The semiconductor memory device according to claim 1, further comprising a storage unit that stores information for error detection of the device information stored in the device information storage area. 7.   The storage unit is provided in an area where the status register and the device information storage area of the specific word line are not provided when the status register and the device information storage area are provided in the specific word line. When the status register and the device information storage area are provided in the specific bit line, a fourth bit provided in the area where the status register and the device information storage area of the specific bit line are not provided. The semiconductor memory device according to claim 6, comprising a memory element.   The semiconductor memory device according to claim 6, wherein the error detection information is a checksum of the device information.   The semiconductor memory device according to claim 1, wherein the first memory element is a ferroelectric memory compatible with a serial communication method.

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