JP4257239B2 - Configuration data setting method and computer system - Google Patents

Description

  The present invention relates to a configuration data setting method for setting configuration data in an FPGA (Field Programmable Gate Array), and in particular, a plurality of FPGAs (Field Programmable Gate Arrays) having different interfaces for setting configuration data. The present invention relates to a computer system.

  In recent years, FPGAs capable of freely programming logic circuits have been widely used for products whose hardware configuration is complicatedly changed, products manufactured in small quantities, and the like (for example, Patent Document 1, 2). In order to program a logic circuit in such an FPGA, it is necessary to download setting data called configuration data to the FPGA.

Conventionally, configuration interfaces for setting configuration data are different for each manufacturer, so when using FPGAs of different manufacturers, separate interfaces must be prepared for each, resulting in complicated circuits. I was sorry. Therefore, a method has been adopted in which a serial PROM of a chipset is prepared and configuration data is downloaded. In this method, the circuit configuration is relatively simple, but as the number of FPGAs to be used increases, the number of components increases, and there is a problem that the mounting surface and the price must be taken into consideration. In addition, in order to solve such an adverse effect, it is possible to use only a specific manufacturer's FPGA. However, since the manufacturer is limited, the flexibility of the circuit configuration becomes poor. It was apt.
JP 2001-290758 A JP 2003-44303 A

  In the conventional computer system described above, there is a problem in that, when using FPGAs of different manufacturers in one system, the circuit becomes complicated and the number of parts increases.

  An object of the present invention is to provide a computer system capable of preventing a circuit from becoming complex and preventing the number of parts from greatly increasing even when different manufacturers' FPGAs are used in one system.

In order to achieve the above object, the present invention is a computer system comprising a plurality of FPGAs having different interfaces for setting configuration data,
A non-volatile memory storing a plurality of configuration data to which a configuration header portion including manufacturer type information and sequence type information indicating the storage order of the configuration data is added;
Each of the configuration data stored in the nonvolatile memory is read, the manufacturer type of the configuration data is identified from the manufacturer type information included in the configuration header portion of the read configuration data, and the read configuration An FPGA data distribution function unit that outputs data through an interface according to the manufacturer type that has identified the data;
And a plurality of FPGAs of different manufacturers that download and start the configuration data output from the FPGA data distribution function unit.

Further, in another computer system of the present invention, the FPGA data distribution function unit includes:
A non-volatile memory access control unit that reads configuration data stored in the non-volatile memory; and
A sequence identification unit that identifies a sequence type from a configuration header portion of configuration data read by the nonvolatile memory access control unit, and outputs the received configuration data to a path based on the identified sequence type;
The manufacturer type is identified from the configuration header part of the configuration data output for each path by the sequence identification part, and the configuration data after removing the configuration header part is output together with the recognition result of the identified manufacturer type. A plurality of manufacturer type identification units provided for each of the paths ;
Based on the recognition result of the manufacturer type from each manufacturer type identification unit, the configuration data from the manufacturer type identification unit is output by each manufacturer specific interface , and a plurality of FPGA interface units provided for each path and,
It has.

  In the present invention, the header is attached to the configuration data in a format different for each manufacturer, so that the data can be handled in the same layer regardless of the manufacturer, and one FROM can be used without using a plurality of serial PROMs. By preparing an interface corresponding to each manufacturer, it is possible to realize a flexible circuit configuration that is not conscious of the barrier of the manufacturer. In addition, by providing a label called a configuration header, it is possible to handle configuration data with different formats for each manufacturer without concern, and configuration data from different manufacturers can be stored in one nonvolatile memory. It becomes possible.

  The nonvolatile memory may be a sector erase type flash memory, and the nonvolatile memory access control unit may have a bus bridge function for connecting the nonvolatile memory and a CPU bus. Good.

  According to the present invention, by using a sector erase type flash memory as the non-volatile memory and arranging the memory in consideration of the sector configuration, erasing and writing for each FPGA can be performed.

  Furthermore, the configuration header part may include version information of the configuration data.

  According to the present invention, since version information is included in the configuration header portion, maintenance monitoring can be performed in consideration of the version information of the configuration data.

  As described above, according to the present invention, even when a plurality of FPGAs from different manufacturers are used in one system, each configuration data can be stored in one nonvolatile memory, so that the circuit configuration is complicated. In addition, it is possible to obtain an effect that the number of parts is not significantly increased.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of a computer system according to the first embodiment of this invention. The configuration of the first embodiment of the present invention will be described with reference to FIG. In this embodiment, for simplicity of explanation, a case where three FPGAs are used will be described. However, use of four or more FPGAs is allowed depending on a circuit configuration.

  As shown in FIG. 1, the computer system of the present embodiment includes a sector erase type FROM (flash memory) 1 that stores configuration data of FPGAs 4a to 4c, a CPU 2, an FPGA data distribution function unit 3, and an FPGA. It consists of FPGAs 4 a to 4 c that start by downloading configuration data from the data distribution function unit 3.

  The FROM 1 stores a plurality of configuration data to which a configuration header portion including manufacturer type information and sequence type information indicating the storage order is added.

  The FPGA data distribution function unit 3 reads the configuration data stored in the FROM 1, identifies the manufacturer type of the configuration data from the manufacturer type information included in the configuration header portion of the read configuration data, and reads the configuration data. The configuration data is output by replacing it with an interface corresponding to the identified manufacturer type.

  The format of FPGA configuration data stored in FROM 1 is shown in FIG. In FIG. 2, the configuration data of each FPGA takes two block configurations, and consists of a 6-byte configuration header part and a configuration data part of each FPGA.

  The configuration header portion includes a 4-byte start key indicating the start of data, 1-byte sequence type information indicating the storage order of the configuration data in the FROM 1, and a 1-byte manufacturer type. This configuration header part is data that has nothing to do with configuration data from the beginning, and is added later to handle configuration data with different formats for each manufacturer in the same layer in order to realize the present invention. It is a thing.

  The combination of the start key data in the configuration header part is arbitrary, but it is necessary to correctly recognize the head of each configuration data. Therefore, it is desirable that the data is not continuous in the configuration data part.

  Further, if the circuit configuration of the circuit for identifying the sequence type information in the FPGA data distribution function unit 3 is simplified, the start key is not prepared for each FPGA but all the same start key is used. Good. In the present embodiment, it is assumed that the start key is “404E4543”.

  As described above, the sequence type information represents the storage order of the configuration data, and has a role of determining the path of the configuration data. In the present embodiment, since there are three paths, at least three sequence types are required. Assume that the sequence type of route 1 is “1”, the sequence type of route 2 is “2”, and the sequence type of route 3 is “3”.

  In this embodiment, since the sequence type is represented by 1-byte information, the number of paths can be changed depending on how it is used. For example, since 1 byte has 256 combinations of numbers from 0 to 255 when converted to decimal numbers, it is possible to have 256 paths, and in another example, 1 byte is 8 bits. It is also possible to distinguish up to eight paths by associating each bit with a path.

  The manufacturer type information represents the manufacturer that manufactured the FPGA, and for example, there is a correspondence table as shown in FIG. In this embodiment, assuming that three manufacturers' FPGAs are used, 00 (hex) is Company A, 01 (hex) is Company B, and 02 (hex) is Company C. Further, FPGA 4a is manufactured by Company A, FPGA 4b is manufactured by Company B, and FPGA 4c is manufactured by Company C.

  Next, the configuration of the FPGA data distribution function unit 3 in FIG. 1 will be described with reference to FIG. As shown in FIG. 4, the FPGA data distribution function unit 3 includes a FROM access control unit 100 that functions as a nonvolatile memory access control unit, a sequence identification unit 101, first to third manufacturer type identification units 102, 103, 104, first to third FPGA interface units 105, 106, and 107, and a configuration completion detection unit 108.

  The FROM access control unit 100 reads the configuration data stored in the FROM 1 at the time of start-up, and notifies the fact that the setting of the configuration data has been completed normally. Has a bus bridge function that allows access.

  The sequence identification unit 101 identifies the sequence type from the configuration header part of the configuration data read from the FROM access control unit 100, and outputs the received configuration data to a path based on the identified sequence type.

  The manufacturer type identification units 102, 103, and 104 identify the manufacturer type from the configuration header part of the configuration data output for each path by the sequence identification unit 101, and remove the configuration header part. Is output together with the recognition result of the identified manufacturer type.

  The FPGA interface units 105, 106, and 107 correspond to the FPGA interfaces of a plurality of manufacturers, and the manufacturer identification units 102, 103, and 104 are based on the recognition results of the manufacturer types from the manufacturer type identification units 102, 103, and 104. The configuration data from is replaced with the interface specific to each manufacturer and output.

  The configuration completion detection unit 108 monitors the configuration state signals output from the FPGAs 4a to 4c, thereby monitoring the configuration states of the FPGAs 4a to 4c and notifying the FROM access control unit 100.

  Note that the manufacturer type identification units 102, 103, and 104 and the FPGA interface units 105, 106, and 107 have a configuration in which the number of paths increases according to the number of FPGAs to be used. In this embodiment, three FPGAs are used. It has three paths.

  Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

  First, the overall operation of the computer system of this embodiment will be described with reference to FIG. In FIG. 1, the FPGA data distribution function unit 3 reads configuration data from the FPGA 4a to the FPGA 4c stored in the FROM 1 at startup, detects manufacturer information from the header part of each configuration data, and each of the FPGA 4a to the FPGA 4c. The configuration data is output through the interface determined by the above, and the FPGA 4a to FPGA 4c are configured.

  Next, the operation of the FPGA data distribution function unit 3 will be described with reference to FIG. In FIG. 4, the FROM access control unit 100 reads the FROM 1 at startup, reads the configuration data stored from the FROM 1, and sends the configuration data to the sequence identification unit 101. At this time, the FROM access control unit 100 performs read access regardless of the memory configuration in the FROM 1 and stops the access to the FROM 1 when the configuration completion detection unit 108 recognizes the completion of configuration.

  In the sequence identification unit 101, the FROM access control unit 100 reads out the memory configuration in the FROM 1 without being aware of the memory configuration. Therefore, it is necessary to recognize the head of the configuration data. For this purpose, the sequence identification unit 101 first detects a start key (404E4543) which is special continuous data. When the configuration header portion is recognized after detecting the start key, the sequence type is detected next. If the sequence type is “1”, the configuration data is transmitted to the path 1 side. In other words, in this embodiment, the configuration data for FPGAa is output to path 1, the configuration data for FPGA 4b is output to path 2, and the configuration data for FPGA 4c is output to path 3.

  The configuration data transmitted to the first to third manufacturer type identification units 102, 103, and 104 is decomposed into a configuration header part and a configuration data part, and only the configuration data part is the first to third FPGA. The data are sent to the interface units 105, 106, and 107, respectively. The first to third manufacturer type identification units 102, 103, and 104 identify the manufacturer type in addition to data decomposition, and notify the first to third FPGA interface units 105, 106, and 107.

  The first to third FPGA interface units 105, 106, and 107 correspond to the FPGA interfaces of a plurality of manufacturers, and the configuration data unit is an interface that matches the manufacturer type received from the manufacturer type identification units 102, 103, and 104. Is output.

In the present embodiment, the configuration data for FPGAa passing through the path 1 is decomposed into a configuration header part and a configuration data part by the first manufacturer type identification unit 102 and sent to the first FPGA interface unit 105. Further, in the first type of maker identification unit 102, FPGA 4 a is recognized from the type of maker of configuration header portion that is made of the company A, the first FPGA interface unit to prepare the interface A company 105, the first FPGA interface unit 105 transmits a configuration data unit for the FPGA 4a according to the interface for the company A.

  Similarly, in the route 2, the second manufacturer type identification unit 106 recognizes that the FPGA 4b is the company B, and the second FPGA interface unit 106 outputs the configuration data unit for the FPGA 4b through the interface for the company B. In the path 3, the third manufacturer type identification unit 107 recognizes that the FPGA 4c is the company C, and the third FPGA interface unit 107 outputs the configuration data unit for the FPGA 4c through the interface for the company C.

  The configuration completion detection unit 108 monitors the configuration status signal output from each FPGA. When the configuration of all the FPGAs is normally completed, the configuration completion detection unit 108 notifies the FROM access control unit 100 to access the FROM 1. Stop. Further, since the configuration completion detection unit 108 notifies the FROM access control unit 100 of the configuration state of each FPGA, the CPU 2 monitors the configuration state of each FPGA via the FROM access control unit 100. be able to.

  Further, since the FPGA data distribution function unit 3 has a bus bridge function for connecting the FROM 1 and CPU 2 buses, the CPU 2 can access the FROM 1, and each configuration data is stored in the FROM 1 in consideration of the sector. Therefore, the CPU 2 can erase and write each configuration data. Therefore, when the configuration data stored in the FROM 1 needs to be changed, the CPU 2 can use the bus bridge function of the FPGA data distribution function unit 3 to access the FROM 1 and change the configuration data. It is.

  According to the computer system of this embodiment, the sequence identification unit 101 of the FPGA data distribution function unit 3 can recognize the start of the configuration data by detecting the start key prepared in the configuration header unit. Data can be stored without being conscious. Therefore, configuration data of different manufacturers can be managed by one FROM 1.

  Further, according to the computer system of the present embodiment, the manufacturer type can be distinguished by the manufacturer type information prepared in the configuration header portion, and therefore the configuration interface can be adjusted according to the configuration data. it can. Therefore, even when FPGAs from different manufacturers are used simultaneously in one system, configuration data can be stored in a low-cost FROM without preparing a high-priced dedicated memory for each FPGA. Therefore, cost reduction can be achieved without complicating the circuit configuration.

  Furthermore, according to the computer system of the present embodiment, since the configuration data is stored in the sector erase type FROM 1 in consideration of the sector configuration, the data can be erased and written from the CPU 2 for each data. Therefore, operations such as changing, deleting, and rewriting the FPGA configuration data can be performed independently.

(Second Embodiment)
Next, a computer system according to a second embodiment of this invention will be described.

  FIG. 5 shows a configuration of configuration data in this embodiment. The configuration data in this embodiment has a configuration in which 1-byte version information is further added to the configuration header portion with respect to the configuration data in the first embodiment shown in FIG.

  For example, when the first created configuration data is set to version 1, the version information is managed as “01 (hex)”, the configuration data added with a new function is managed as version 2, and the version information is set to “02”. (Hex) ". Since the CPU 2 can access the FROM 1 by the bus bridge function of the FROM access control unit 100, maintenance monitoring can be performed in consideration of the version information of the configuration data. For example, during operation, the CPU 2 accesses the FROM 1 to check the version information in the header portion of the FPGAa configuration data. If the version information is found to be old, the latest configuration data can be written. Therefore, the use of the present embodiment brings about a new effect that maintenance monitoring on data can be easily performed.

  In the first and second embodiments, the case where the FROM 1 is used as the memory for storing the configuration data has been described. However, the present invention is not limited to this, and the memory is stored even when the power is turned off. The present invention can be similarly applied even when another nonvolatile memory capable of holding the contents is used.

It is a block diagram which shows the structure of the computer system of the 1st Embodiment of this invention. It is a figure which shows the structure of the configuration data of this invention. It is a figure which shows the relationship between the manufacturer classification of this invention, and a manufacturer. It is a block diagram which shows the structure of the FPGA data distribution function part 3 in FIG. It is a figure showing the structure of the configuration data in the 2nd Embodiment of this invention.

Explanation of symbols

1 Flash memory (FROM)
2 CPU
3 FPGA data distribution function unit 4a, 4b, 4c FPGA
100 FROM access control unit 101 Sequence identification unit 102 First manufacturer type identification unit 103 Second manufacturer type identification unit 104 Third manufacturer type identification unit 105 First FPGA interface unit 106 Second FPGA interface unit 107 Third FPGA interface part 108 Configuration completion detection part

Claims (7)

A computer system including a plurality of FPGAs having different interfaces for setting configuration data,
A non-volatile memory storing a plurality of configuration data to which a configuration header portion including manufacturer type information and sequence type information indicating the storage order of the configuration data is added;
Each of the configuration data stored in the nonvolatile memory is read, the manufacturer type of the configuration data is identified from the manufacturer type information included in the configuration header portion of the read configuration data, and the read configuration An FPGA data distribution function unit that outputs data through an interface according to the manufacturer type that has identified the data;
A plurality of FPGAs of different manufacturers that download and start the configuration data output from the FPGA data distribution function unit;
Computer system with The FPGA data distribution function unit
A non-volatile memory access control unit that reads configuration data stored in the non-volatile memory; and
A sequence identification unit that identifies a sequence type from a configuration header portion of configuration data read by the nonvolatile memory access control unit, and outputs the received configuration data to a path based on the identified sequence type;
The manufacturer type is identified from the configuration header part of the configuration data output for each path by the sequence identification part, and the configuration data after removing the configuration header part is output together with the recognition result of the identified manufacturer type. A plurality of manufacturer type identification units provided for each of the paths ;
Based on the recognition result of the manufacturer type from each manufacturer type identification unit, the configuration data from the manufacturer type identification unit is output by each manufacturer specific interface , and a plurality of FPGA interface units provided for each path and,
The computer system according to claim 1, further comprising: The nonvolatile memory is a sector erase type flash memory,
The computer system according to claim 2, wherein the nonvolatile memory access control unit has a bus bridge function for connecting the nonvolatile memory and a CPU bus.   The computer system according to claim 1, wherein the configuration header portion includes version information of the configuration data. A configuration data setting method for setting configuration data in an FPGA,
The stored configuration data is read from the nonvolatile memory storing the configuration data to which the configuration header portion including the manufacturer type information and the sequence type information indicating the storage order of the configuration data is added. A first step;
A second step of identifying the manufacturer type of the configuration data from the manufacturer type information included in the configuration header portion of the read configuration data;
In the interface according to the type of maker identifying the read the configuration data, and a third step of outputting each of a plurality of different FPGA of manufacturers,
Configuration data setting method with The second and third steps are:
Identifying a sequence type from the configuration header portion of the configuration data read from the non-volatile memory, and outputting the received configuration data to a path based on the identified sequence type;
Identifies the type of maker from configuration header portion of the configuration data output for each path, the configuration data after removing the configuration header portion, the corresponding path with the recognition result of the type of maker was identified Output step;
A step based on the recognition result of the type of maker, the configuration data, provided for each said path, for outputting the respective manufacturer-specific interfaces,
The configuration data setting method according to claim 5, further comprising:   The configuration data setting method according to claim 5 or 6, wherein the configuration header portion includes version information of the configuration data.

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