JP2003216507A - Storage capacity processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify data processing of a memory control part and to reduce the cost. <P>SOLUTION: A nonvolatile semiconductor memory 5 stores addresses of a usable block and an unusable block in a memory inside and is provided with an address conversion table 3, or address conversion means for converting the address based on the addresses of the usable region and unusable regions, so as not to access to the address in the unusable region. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage capacity processing system provided with a storage device having a nonvolatile memory mounted thereon, and more particularly to a storage device capable of mounting a nonvolatile memory having a defective block as a program memory of a microcomputer. The present invention relates to a storage capacity processing system provided with.

[0002]

2. Description of the Related Art A storage device using a non-volatile memory as a storage medium has features such as good shock resistance, low power consumption, and small size and light weight. The use of the nonvolatile memory is rapidly increasing, and along with this, the nonvolatile memory is being increased in capacity and price.

As the capacity of a non-volatile memory increases, the frequency of occurrence of defective portions in the memory increases, which reduces the yield of the memory in the manufacturing process and may not reduce the price of the non-volatile memory. There is.

Therefore, the non-volatile memory is replaced with a non-volatile memory so that it can be used even when it includes a defective block produced at the time of manufacture or when it includes a block which cannot be used during use. Blocks are provided. The replacement block has a predetermined capacity set in advance, and the capacity is determined from the memory mounting area of the storage device, the price, and the like.

As a result, only the non-volatile memory in which the capacity of the defective block included in the non-volatile memory in the initial state is equal to or less than the capacity of the substitute block can be used as the non-volatile memory. When a block that becomes unusable occurs during use, the total capacity of bad blocks that occurs during manufacturing and use, or the total capacity of bad blocks that occurs only during use, is the capacity of the alternative block in the nonvolatile memory. Beyond that, the non-volatile memory becomes unusable. As a result, in the initial state, the capacity of the defective block allowed in the non-volatile memory needs to be smaller than the capacity of the substitute block, which is considerably limited. In order to deal with such a problem, the capacity of the alternative block preset in the nonvolatile memory may be increased. However, if the capacity of the alternative block is increased, the originally usable capacity of the nonvolatile memory is replaced. Since the capacity of the block is taken, there is a problem that the usable non-volatile memory capacity becomes smaller than in the initial state.

To solve such a problem, Japanese Patent Laid-Open No. 8-19
Japanese Laid-Open Patent Publication No. 0510 discloses a storage device equipped with a nonvolatile memory even if the nonvolatile memory includes a large number of defective blocks.

FIG. 5 is a block diagram showing the structure of the storage device. The storage device shown in FIG. 5 has a non-volatile memory 10 which is a storage medium, and a memory control unit 20 which controls the operation of the non-volatile memory 10 so as to function as the storage device.

The memory control unit 20 includes a nonvolatile memory 10
A memory controller 30 that directly controls the memory controller 30 and an input / output controller 40 that controls data communication between the memory controller 30 and an external device. The input / output controller 40 performs data communication with an external device via the system bus 70.

Further, the memory controller 30 has a CP for performing arithmetic processing in data management, memory control and the like.
U50 and ROM60 are arranged. Then, the memory controller 30 performs a test for confirming the availability or non-availability of each cell that constitutes the non-volatile memory 10, and adds the data indicating the total usable capacity to the non-volatile It has a function of writing in a predetermined area of the memory 10, creating an address conversion table for managing stored data in block units, and writing information of an unusable defective block in the address conversion table.

With such a configuration, the storage device shown in FIG. 5 can use the non-volatile memory 10 including a defective block without any problem, and thus it is possible to prevent the yield of the non-volatile memory 10 from decreasing. Non-volatile memory 10
The price can be reduced. Further, since the information of the defective block is registered in the address conversion table, it is not necessary to detect the defective block at the time of shipping the product, so that the work efficiency at the time of shipping the product can be improved.

[0011]

Generally, the number of times of rewriting of a non-volatile memory is guaranteed to be about 100,000 times. In a storage device using the non-volatile memory for a program memory of a microcomputer, the non-volatile memory is used. Since the data in the memory is not rewritten frequently, it is almost unlikely that the nonvolatile memory will be destroyed during use.

However, in the storage device shown in FIG.
In the memory controller 30 of the memory control unit 20,
The usable capacity and the unusable capacity of the non-volatile memory 10 are frequently detected, and the data is written by obtaining the total usable capacity of the non-volatile memory 10 each time. Therefore, the memory controller 30 requires the CPU 50 and the ROM 60 for data management, arithmetic processing, etc., which increases the cost of the storage device.

The present invention solves such a problem, and an object of the present invention is to provide a storage device which simplifies the data processing of the memory control unit and reduces the cost.

[0014]

A storage capacity processing system of the present invention is a storage capacity processing system in which an electrically rewritable semiconductor memory is provided in a storage device, and the semiconductor memory is used inside the memory. Addresses of a usable area and an unusable area are stored, and when the semiconductor memory operates, an address conversion of the semiconductor memory is performed based on the addresses of the usable area and the unusable area. To do.

The operation of the semiconductor memory is a data read operation.

In the data read operation, the address of the unusable area is not accessed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a storage capacity processing system which is an embodiment of the present invention. The storage capacity processing system of FIG. 1 has a nonvolatile memory 5 which is a storage medium, and a memory control unit 6 which controls the operation of the nonvolatile memory 5. The non-volatile memory 5 and the memory control unit 6 constitute a storage device.

The memory control section 6 comprises an address conversion table 3 and an address conversion device 4. The address conversion table 3 converts the information of the unusable blocks and the usable blocks in the non-volatile memory 5 into data in units of blocks, and the address conversion device 4 based on the information of the usable blocks converted into data by the address conversion table 3. Generate an address signal. Memory control unit 6
Writes / writes non-volatile memory via the system bus 2.
It is connected to the reading device 1.

Nonvolatile memory writing / reading device 1
When writing external data to the non-volatile memory 5, the writing unit of the non-volatile memory writing / reading device 1 is connected to the storage device, and when reading data from the non-volatile memory 5, the non-volatile memory writing / reading device The reading unit of the reading device 1 is connected to the storage device. Then, the non-volatile memory writing / reading device 1 uses the system bus 2 to transmit a data signal to an external device.

FIG. 2 is an example showing a list of usable / unusable information for each block stored in a predetermined area inside the nonvolatile memory 5. There are a total of 24 address signals in the non-volatile memory 5, and since one block has a common upper 8 bits of the address, one block has 64 kbytes (512 kbits) of data. As shown in FIG. 2, as the internal information of the non-volatile memory 5, the addresses of 256 (2 ⁸ ) blocks and the information of whether or not each block can be used (usable / unusable) are stored. Has been done. The address of each block corresponds to the upper 8 bits and is displayed in hexadecimal. In FIG. 2, the upper 8 bits 04h (h = hexadecimal) of the address corresponding to the block number 4 are shown as a defective block.

FIG. 3 shows the nonvolatile memory 5 shown in the table of FIG.
It is the address conversion table 3 created based on the internal information of. The numbers in the table are displayed in hexadecimal. As shown in FIG. 3, the address conversion table 3 includes:
The upper 8 bits 04h of the address on the system side is set to correspond to the upper 8 bits 05h of the address of the nonvolatile memory 5, and the address indicating the defective block in the nonvolatile memory 5 (the upper 8 bits 04h ) Is not displayed.

FIG. 4 is a flow chart showing the operation of the storage capacity processing system of the present invention. The operation of the storage capacity processing system will be described based on this flowchart.

First, the data writing operation to the non-volatile memory 5 will be described.

Nonvolatile memory writing / reading device 1
Of the memory controller 6 via the system bus 2
Connected to. Before writing data, the writing unit of the non-volatile memory writing / reading device 1 passes the address conversion table 3 and the address conversion device 4 of the memory control unit 6 and the usable / unusable information of the non-volatile memory 5. Is read (step S1).

Next, data is set in the address conversion table 3 based on the usable / unusable information of the non-volatile memory 5 (step S2). Here, the created data represents the upper 8 bits of the address in hexadecimal, and is created as shown in FIG. In the created conversion data of the address conversion table 3, an address (upper 8 bits) indicating a defective block existing inside the nonvolatile memory 5 is not displayed.

Next, the address is output from the writing unit of the nonvolatile memory writing / reading device 1 and transmitted to the address conversion table 3 via the system bus 2 (step S3). At this time, in the address translation device 4,
The address of the upper 8 bits is converted based on the address conversion table 3 and the address signal is transmitted to the nonvolatile memory 5 (step S4). In this case, the data signal and the write signal output from the writing unit of the non-volatile memory writing / reading device 1 are directly transmitted to the non-volatile memory 5.

Next, when the address signal of the upper 8 bits of the address output from the writing unit of the nonvolatile memory writing / reading device 1 is 00h (h = hexadecimal number), the address output from the address conversion table 3 The upper 8 bits of the address signal is 00h, and the data is written in the upper 8 bits of the address of the nonvolatile memory 5, 00h. When the address signal of the upper 8 bits of the address output from the writing unit of the nonvolatile memory writing / reading device 1 is 04h, the address signal of the upper 8 bits of the address output from the address conversion table 3 is 05h, which is non-volatile. Data is written to the upper 8 bits 05h of the address of the memory 5, and the data writing to the defective block (04h) of the nonvolatile memory 5 is avoided (step S5).

Next, the data read operation from the non-volatile memory 5 will be described.

Nonvolatile memory writing / reading device 1
Of the memory controller 6 via the system bus 2
Connected to. Then, before reading the data, the reading unit of the non-volatile memory writing / reading device 1 passes the address conversion table 3 and the address conversion device 4 of the memory control unit 6 and the usable / unusable information of the nonvolatile memory 5 is read. Is read (step S1).

Next, data is set in the address conversion table 3 based on the usable / unusable information of the non-volatile memory 5 (step S2). The created address conversion table 3 has the same contents as in the data write operation.

Next, the address is output from the reading section of the nonvolatile memory writing / reading device 1 and transmitted to the address conversion table 3 via the system bus 2 (step S3). At this time, in the address translation device 4,
The address of the upper 8 bits is converted based on the address conversion table 3 and the address signal is transmitted to the nonvolatile memory 5 (step S4). In this case, the data signal and the read signal output from the reading unit of the non-volatile memory writing / reading device 1 are directly transmitted to the non-volatile memory 5.

Next, as in the case of writing data, the address signal of the upper 8 bits of the address output from the reading section of the nonvolatile memory writing / reading device 1 is 00h.
If (h = hexadecimal number), the address conversion table 3
The address signal of the upper 8 bits of the address output from is 00h, and the upper 8 bits of the address of the nonvolatile memory 5
Data is read from bit 00h. When the address signal of the upper 8 bits of the address output from the reading unit of the non-volatile memory writing / reading device 1 is 04h, the upper 8 bits of the address output from the address conversion table 3 is 05h and the non-volatile memory 5 Data is read from the upper 8 bits 05h of the address, and data reading from the defective block (04h) of the nonvolatile memory 5 is avoided (step S5).

As described above, in the storage capacity processing system of the present invention, since the information of usable blocks and unusable blocks is stored in the non-volatile memory 5 in advance, only the reading operation of data (internal information) is performed. Thus, the usable block and the unusable block in the non-volatile memory 5 can be detected, and the processing during system operation is simplified.

Therefore, in the storage capacity processing system of the present invention, both the write operation and the read operation are performed by the memory control means such as the conventional storage device to detect the usable block and the unusable block of the non-volatile memory. It is not necessary to calculate the total usable capacity after detecting the usable block and the unusable block of the non-volatile memory.

Further, in the storage capacity processing system of the present invention, since the memory control unit is not provided with a calculation function, it is not necessary to use a CPU or the like, and it can be realized by a gate array or the like.
The cost of the entire system can be reduced.

Further, in the storage capacity processing system of the present invention, since the address converting means are the same in the data writing operation and the data reading operation, malfunction of the system can be prevented.

In the present embodiment, an example in which the number of defective blocks in the non-volatile memory is one is shown, but the same effect can be obtained even when there are a plurality of defective blocks.

[0039]

According to the storage capacity processing system of the present invention, the addresses of the usable area and the unusable area are stored inside the semiconductor memory, and when the semiconductor memory is operated,
Since the address conversion is performed based on the addresses of the usable area and the unusable area so that the addresses of the unusable area are not accessed, the data processing of the memory control unit can be simplified and the cost can be reduced. Can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a storage capacity processing system according to an embodiment of the present invention.

FIG. 2 is a list of usable / unusable information for each block stored in a nonvolatile memory.

3 is an address conversion table created based on the internal information of the nonvolatile memory 5 shown in the table of FIG.

FIG. 4 is a flowchart showing an operation of the storage capacity processing system of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional storage device.

[Explanation of symbols]

1 Non-volatile memory writing / reading device 2 system bus 3 Address conversion table 4 Address translation device 5 Non-volatile memory 6 Memory controller 10 Non-volatile memory 20 memory controller 30 memory controller 40 I / O controller 50 CPU 60 ROM 70 system bus

Claims (3)

[Claims] 1. A storage capacity processing system in which an electrically rewritable semiconductor memory is provided in a storage device, wherein the semiconductor memory stores addresses of usable and unusable areas inside the memory. A storage capacity processing system, wherein address conversion of the semiconductor memory is performed based on addresses of the usable area and the unusable area during operation of the semiconductor memory. 2. The storage capacity processing system according to claim 1, wherein the operation of the semiconductor memory is a data read operation. 3. The storage capacity processing system according to claim 2, wherein an address of the unusable area is not accessed in the data read operation.