JP2008107897A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems in a saving system due to an anti-fuse. <P>SOLUTION: A semiconductor storage device is provided with a memory module 30 loaded with DRAMs 10 and an SPD (EEPROM) 20 and storing the defective address information of the DRAMs 10 in the SPD 20 and a memory controller 40 for reading out the defective address information from the SPD 20 and transferring the defective address information to the DRAMs 10. Each DRAM 10 comprises a memory cell array 50, saving address register 12, 14 for storing the defective address information, and a redundant memory cell 11 to be substituted for a defective memory cell in the memory cell array 50. When external address information inputted from the external coincides with the defective address information of the saving address registers 12, 14 in normal access operation after storing the transferred defective address information in the saving address registers 12, 14, the DRAM 10 accesses the redundant memory cell 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a circuit for relieving a defective bit of a memory module.

  For DRAM (Dynamic Random Access Memory), a method for remedying defective bits (defects) using a laser trimmer has been generally used. However, since the repair method using the laser trimmer can be performed only in the wafer state, it is not possible to repair the defect generated after the package is enclosed. Therefore, in recent years, a repair method using an antifuse (electrically programmable ROM; Read Only Memory) has been used as a method of repairing 1 or 2 defective bits generated after the package is enclosed or after the module is mounted. As a DRAM using an antifuse relief method, conventionally, an antifuse is built in the DRAM, and defective address information is programmed in the antifuse, and when it matches the address at the time of normal access, the read / write is performed on the redundant memory cell. (For example, see Patent Documents 1, 2, and 3).

JP-A-8-235892 Japanese Patent Laid-Open No. 11-250691 JP 2002-299561 A

  DRAMs using the anti-fuse relief method have the advantage that they can be relieved even after being packaged, but (1) the circuit scale is large, such as the need to install a dedicated internal power supply for the program, (2) Anti-fuse circuit area is large, which hinders reduction of DRAM chip size, (3) Anti-fuse reliability is low because of programming due to destruction of MOS gate oxide film, etc. (4) Once programmed, cannot be rewritten However, there are problems such as (5) a large number of writing failures, and (6) a point where rewriting is impossible when writing is lost.

  The main object of the present invention is to solve the problem of the anti-fuse repair method.

  In one aspect of the present invention, in a semiconductor memory device, a DRAM and an EEPROM are mounted on a substrate, and the defective address information of the DRAM is stored in a predetermined address space of the EEPROM. A memory controller having a function of reading from the EEPROM and transferring the defective address information to the DRAM in a predetermined sequence, the DRAM having a memory cell array and the register for storing the defective address information; A redundant memory cell that is substituted for a defective memory cell in the memory cell array, and after storing the defective address information transferred from the memory controller in the register, during a normal access operation Input from outside Department address information, and having the ability to access the redundant memory cell when a match with the defective address information stored in the register.

  In the semiconductor memory device of the present invention, after the DRAM stores the defective address information transferred from the memory controller in the register, external address information input from the outside during a normal access operation is stored in the register. It is preferable to have a function of accessing the memory cell array when it does not match the stored defective address information.

  According to the present invention, as a medium for storing defective address information of a DRAM, instead of an antifuse (electrically programmable ROM; Read Only Memory) mounted on a DRAM chip, it is conventionally mounted on a memory module as a standard. By effectively utilizing the free memory area of the existing EEPROM (SPD; Serial Presence Detect), it is not necessary to mount a dedicated internal power supply for writing in the DRAM, and the circuit scale can be reduced.

  Further, since no antifuse is used, the writing reliability is increased. Moreover, even if it writes once, it can rewrite. In addition, writing errors are reduced. Furthermore, rewriting is possible when writing is lost.

(Embodiment 1)
A semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing a configuration of a semiconductor memory device according to Embodiment 1 of the present invention. FIG. 2 is a block diagram schematically showing an example of the configuration of the DRAM in the semiconductor memory device according to the first embodiment of the present invention.

  The semiconductor storage device 1 according to the first embodiment is a main storage device that is built in or externally connected to a computer such as a personal computer or a server. The semiconductor memory device 1 includes a memory module 30 and a memory controller 40.

  The memory module 30 has a plurality of semiconductor memory chips mounted on a substrate, wired, and provided with connection terminals for connection to a computer. The memory module 30 includes a plurality of DRAMs 10 and SPDs 20 as semiconductor memory chips.

  The DRAM 10 is a RAM that can be freely read and written, and includes a register that stores defective address information from the memory controller 40, an address comparator, and a redundant memory space. The DRAM 10 is equipped with a register, a comparison circuit, and a redundant memory cell that originally store the defective address information read from the antifuse, so that even a function for storing the defective address information sent from the memory controller 40 in the register is prepared. What is necessary is that an anti-fuse circuit including a dedicated power supply circuit is unnecessary. The operation of the DRAM 10 is controlled by various commands from the memory controller 40. Here, the defective address information means defective bit address information in the memory array of the DRAM 10.

  As shown in FIG. 2, for example, the DRAM 10 includes a redundant memory cell 11, a row relief address register 12, a row address comparison circuit 13, a column relief address register 14, a column address comparison circuit 15, and a row address register 16. Column address register 17, I / O control circuit 18, memory cell array 50, row decoder 51, sense amplifier 52, column decoder 53, data amplifier 54, AND circuits A1, A2, A3, OR And a circuit OR.

  The DRAM 10 stores the defective address information transferred in a predetermined sequence in the row relief address register 12 and the column relief address register 14, and then at any time during normal operation, external address information from the outside and the row relief address register 12. , And the defective address information stored in the column relief address register 14 are compared by the row address comparison circuit 13 and the column address comparison circuit 15, and if they do not match, the normal memory cell array is accessed. 11 is accessed.

  The redundant memory cell 11 is a memory cell that is substituted for a defective memory cell in the memory cell array 50. Based on the HI signal from the AND circuit A3 and the signal from the I / O control circuit 18, the redundant memory cell 11 writes the data DQ from the I / O control circuit 18 at the time of writing and reads the data DQ at the time of reading. Output to / O control circuit 18.

  The row relief address register 12 stores the row address related to the defective address information from the row address register 16 based on the HI signal and clock signal of the AND circuit A1, and directs the stored row address to the row address comparison circuit 13. Output.

  The row address comparison circuit 13 sequentially compares the row address related to the external address information from the row address register 16 and the row address related to the defective address information stored in the row relief address register 12. An LO signal is output toward A3, and if they match, an HI signal is output toward AND circuit A3.

  The column relief address register 14 stores the column address related to the defective address information from the column address register 17 based on the HI signal and clock signal of the AND circuit A2, and directs the stored column address to the column address comparison circuit 15. Output.

  The column address comparison circuit 15 sequentially compares the column address related to the external address information from the column address register 17 and the column address related to the defective address information stored in the column relief address register 14. An LO signal is output toward A3, and if they match, an HI signal is output toward AND circuit A3.

  Based on the active command (ACTV) from the memory controller (40 in FIG. 1) and the clock signal, the row address register 16 receives address information (ADD; external address information, defective address) from the memory controller (40 in FIG. 1). And the stored row address is output to the row relief address register 12, the row address comparison circuit 13, and the row decoder 51. Here, the active command (ACTV) is a command for activating the row address register 16 and reading the data in the memory cell array 50 to the sense amplifier 52.

  The column address register 17 stores a column address related to address information (ADD; including external address information and defective address information) from the memory controller (40 in FIG. 1) based on the HI signal of the OR circuit OR and the clock signal. The stored column address is output to the column relief address register 14, the column address comparison circuit 15, and the data amplifier 54.

  Based on various commands from the memory controller (40 in FIG. 1), the I / O control circuit 18 controls the data DQ to be written to the data amplifier 54 or the redundant memory cell 11 at the time of writing, and the data DQ to the data at the time of reading. Control is performed so that data is read from the amplifier 54 or the redundant memory cell 11.

  The memory cell array 50 is an array in which a plurality of memory cells form a matrix. In the memory cell array 50, a plurality of word lines (not shown) in the row direction driven by the control of the row decoder 51 and a plurality of bit lines (not shown) in the column direction driven by the control of the column decoder 53 are provided. And are wired. In a normal operation such as writing or reading, a normal memory cell located at the intersection of a word line (not shown) and a bit line (not shown) selected by the row decoder 51 and the column decoder 53 is accessed. Then, data reading and writing are performed on the memory cell.

  The row decoder 51 is for selecting a row of the memory cell array 50 based on the row address from the row address register 16, and drives a word line (not shown) of the memory cell array 50 based on the row. Configured.

  The sense amplifier 52 amplifies input / output data to / from a bit line (not shown) selected by the column decoder 53.

  The column decoder 53 is for selecting a column of the memory cell array 50 based on the row address input from the column address register 17 via the data amplifier 54, and a bit line (not shown) based on the column. Configured to select.

  The data amplifier 54 amplifies input / output data between the column decoder 53 and the I / O control circuit 18 or between the column decoder 53 and the column address register 17.

  The AND circuit A1 outputs an HI signal to the row relief address register 12 when the active command (ACTV) from the memory controller (40 in FIG. 1) and the internal signal A are both HI. Here, the internal signal A is an extended mode register set command (in order to store the defective address information fetched from the SPD (20 in FIG. 1) in the row relief address register 12 and the column relief address register 14 during the initialization sequence. EMRS).

  The AND circuit A2 outputs an HI signal to the column relief address register 14 when both the write command (WRIT) from the memory controller (40 in FIG. 1) and the internal signal A are HI. Here, the write command (WRIT) is a command set by the extended mode register set command (EMRS), and is a command for writing data to the memory cell at the designated column address.

  The AND circuit A3 outputs the HI signal toward the redundant memory cell 11 when the output signals of the row address comparison circuit 13 and the column address comparison circuit 15 are HI signals.

  The OR circuit OR outputs an HI signal to the column address register 17 when a write command (WRIT) or a read command (READ) from the memory controller (40 in FIG. 1) is an HI signal. Here, the read command (READ) is a command for reading the data of the memory cell at the designated column address in the operation mode (latency, burst length, burst type) set by EMRS.

  The SPD 20 is an EEPROM (Electric Erasable Programmable Read Only Memory) that is mounted on the memory module 30 as a standard and can be electrically rewritten, and is an anti-memory for storing defective address information that is conventionally mounted in a DRAM chip. It is a substitute for a fuse. The SPD 20 generally uses a 2 Kbit EEPROM, but has an unused area of about 1 Kbit, and has a free memory area (free capacity) that can be used as a substitute for an antifuse on a conventional DRAM. Therefore, in the SPD 20, a memory area for storing defective address information of the DRAM 10 is determined using an empty memory area.

  The memory controller 40 has a function of reading out defective address information written in the SPD 20 and transferring it to the DRAM 10. This is because when the storage medium related to the defective address information is provided outside the DRAM 10 as in the SPD 20, the defective address information needs to be transferred from the SPD 20 to the DRAM 10.

  Next, the operation of the semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. 3 to 6 are schematic views for explaining the operation of the semiconductor memory device according to the first embodiment of the present invention.

  When the memory module 30 is manufactured, defective address information of the DRAM 10 is written in a predetermined memory area of the SPD 20 (see X1 in FIG. 3).

  When the main storage system is activated, the memory controller 40 reads out defective address information of the DRAM 10 written in the SPD 20 (see X2 in FIG. 3). Note that the reading method conforms to the method of originally reading latency information and the like.

  During the initialization sequence of the DRAM 10, the memory controller 4 transfers the defective address information fetched from the SPD 20 to the DRAM 10 in a predetermined sequence (see X3 in FIG. 3). For example, referring to Y1 in FIG. 4, the address information respectively input by the ACTV command and the WRIT command following the EMRS command of code A is used as the row address and column address of the defective bit. At this time, in order to identify the defective chip, only the DQ (data) of the defective chip is set to HI, or / CS (chip select input signal) is set to LO.

  Next, the DRAM 10 operates as shown in the timing chart of FIG. 4 based on each signal and each command during the initialization sequence, and the defective address information is stored in the DRAM 10 at the timing Y2 in FIG. Store in the registers (row relief address register 12, column relief address register 14) (see FIG. 5). Thereafter, the same operation is performed for codeB (see Y3 in FIG. 4).

  During a normal access operation, the DRAM 10 receives external address information and a relief address register (a row relief address register 12 and a column relief address register 14) that are externally input via an address register (row address register 16, column address register 17). Are sequentially compared by the comparison circuit (the row address comparison circuit 13 and the column address comparison circuit 15). If they do not match, the normal memory cell array 50 is accessed, and if they match, the redundant memory cell 11 (Refer to FIG. 6 for access to the redundant memory cell 11). Thereafter, the data DQ read from the memory cell array 50 or the redundant memory cell 11 is output to the outside via the I / O control circuit 18.

  According to the first embodiment, by using the SPD 20 that is originally in the system as a medium for storing defective address information, the anti-fuse circuit including the dedicated power supply circuit is not required in the DRAM 10. The area can be saved and the advantage of reducing the chip size is great.

  Further, since the SPD 20 is an EEPROM (a rewritable programmable ROM), the reliability of programming such as an antifuse and the problem of yield reduction due to programming failure do not occur, and the cost of the entire system is lower. Can be.

1 is a block diagram schematically showing the configuration of a semiconductor memory device according to Embodiment 1 of the present invention. 1 is a block diagram schematically showing an example of a configuration of a DRAM in a semiconductor memory device according to Embodiment 1 of the present invention. FIG. 3 is a first schematic diagram for explaining an operation of the semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a second schematic diagram (timing chart) for explaining the operation of the semiconductor memory device according to the first embodiment of the present invention. FIG. 9 is a third schematic diagram for explaining the operation of the semiconductor memory device according to the first embodiment of the invention. FIG. 9 is a fourth schematic diagram for explaining the operation of the semiconductor memory device according to the first embodiment of the invention.

Explanation of symbols

1 Semiconductor memory device 10 DRAM
DESCRIPTION OF SYMBOLS 11 Redundant memory cell 12 Row relief address register 13 Row address comparison circuit 14 Column relief address register 15 Column address comparison circuit 16 Row address register 17 Column address register 18 I / O control circuit 20 SPD
30 memory module 40 memory controller 50 memory cell array 51 row decoder 52 sense amplifier 53 column decoder 54 data amplifier A1, A2, A3 AND circuit OR OR circuit

Claims (2)

A memory module in which DRAM and EEPROM are mounted on a substrate, and defective address information of the DRAM is stored in a predetermined address space of the EEPROM;
A memory controller having a function of reading the defective address information from the EEPROM and transferring the defective address information to the DRAM in a predetermined sequence;
With
The DRAM includes a memory cell array, the register for storing the defective address information, and a redundant memory cell substituted for a defective memory cell in the memory cell array, and the memory controller After storing the defective address information transferred from the register in the register, the redundant memory cell when the external address information input from the outside during a normal access operation matches the defective address information stored in the register A semiconductor memory device having a function of accessing   The DRAM stores the defective address information transferred from the memory controller in the register, and external address information input from the outside during a normal access operation matches the defective address information stored in the register. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a function of accessing the memory cell array when not.

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