JP2010198694A - Semiconductor memory device and method for determining replacement address in the semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a redundancy memory for repairing each memory cell prepared outside a memory cell array, applying a row address and a column address in time division, and performing a multi-bank operation to a plurality of banks, the semiconductor memory device suppressing an increase in circuit size of an address determination circuit determining replacement to the redundancy memory as the number of banks increases, and to provide a method for determining an address to be replaced to the redundancy memory. <P>SOLUTION: A holding circuit for storing a bank supplied from the outside, a bank of an address where a row address is to be replaced by a redundancy memory, and coincidence with the row address is provided for each bank. When a column address of the bank is supplied, the coincidence with the row address is determined by the holding circuit. Thus, it is not necessary to hold the row address. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a replacement address determination method in a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device that is provided with a redundant memory that can be replaced in units of cells and that is accessed by inputting a row address and a column address from the outside in a time division manner.

  In recent years, so-called combo chips that satisfy a plurality of standards as memory standards have attracted attention. As this combo chip, for example, ones used as memories of LPDDR1 (Low Power Double Data Rate 1 SDRAM) having a 4-bank configuration and LPDDR2 (Low Power Double Data Rate 2 SDRAM) having an 8-bank configuration are conceivable. At this time, the configuration of the X address and bank address is XDDR X0-12 and bank address BA0-2 when LPDDR2 is 8 banks and X address X0-13 and bank address BA0 when LPDDR1 is 4 banks. -1 will be used, and instead of reducing the bank address by one in four banks, the X address will be increased by one.

  Even in such a combo chip, the storage capacity is increasing year by year due to advances in microfabrication technology, and the number of defective memory cells contained in one chip is also increasing as miniaturization progresses. It is a fact. Such defective memory cells are replaced with redundant memory cells, thereby relieving defective addresses.

  In general, a defective address is stored in a fuse circuit including a plurality of program fuses, and when access to the address is requested, a redundant memory cell is accessed instead of a defective memory cell by the control of the fuse circuit. Will be done. Such a defect address is detected in a screening test performed in a wafer state, and the program fuse is cut by irradiating a laser beam in accordance with the detected defect address.

  Even after such address replacement, defective bits may occur sporadically due to, for example, thermal stress during packaging. If such a defective bit is found after packaging, address replacement by laser beam irradiation can no longer be performed, and it must be handled as a defective product.

  As a method for solving such a problem, in addition to primary relief by laser beam irradiation, a method for secondary relief of a small number of defective bits discovered after packaging has been proposed. In this case, as a circuit for storing a defective address to be secondarily repaired, an electrically writable nonvolatile memory circuit is used instead of a laser fuse circuit that requires laser beam irradiation. As such a memory circuit, a so-called “anti-fuse circuit” using dielectric breakdown of an oxide film can be used.

  Here, the number of defective bits found after packaging is very small compared to the number of defective bits found during the screening test. For this reason, in the secondary relief using the antifuse element, it is preferable to perform replacement in units of memory cells rather than replacement in units of word lines or bit lines.

  In order to perform replacement in units of memory cells, it is necessary to refer to both the row address and the column address in detecting a defective address and detect that they all match. This means that the number of bits of an address for designating a defective memory cell is very large. In other words, if the replacement is performed in units of word lines, it is sufficient to detect the coincidence of the row address, and it is not necessary to refer to the column address. Similarly, if the replacement is performed in units of bit lines, it is sufficient to detect the coincidence of the column address, and it is not necessary to refer to the row address. On the other hand, in replacement in units of memory cells, it is necessary to refer to both the row address and the column address, so that the number of bits necessary for the address comparison inevitably increases.

  In addition, there exists a thing described in patent document 1 and patent document 2 as related technology.

JP 2007-328914 A JP 2008-204519 A

  The following analysis is given in the present invention. In particular, in a semiconductor memory device having a plurality of banks and having a multi-bank operation function capable of accessing a plurality of banks in parallel, in order to determine replacement with redundant cells for each memory cell, for each bank If the row address is held until a column address is given and determined, the number of elements in the row address holding circuit for replacement determination increases as the number of banks increases.

  On the other hand, the anti-row row address latch circuit (X address latch circuit) of LPDDR1 is necessary for each bank because it is necessary to satisfy the conditions of tMRD = 2CLK and tRRD = 2CLK even when the power is turned on. Therefore, if an 8-bank configuration LPDDR2 and a 4-bank configuration LPDDR1 combo chip are to be realized, eight X-address latch circuits are required, so that eight X-address latch circuits are required, which increases the circuit scale.

  A semiconductor memory device according to one aspect of the present invention is a semiconductor memory device that inputs a row address and a column address in a time-sharing manner, and is arranged outside a memory cell array of a plurality of banks capable of multi-bank operation. A redundant memory that can be replaced in units of cells, a replacement address storage circuit that stores in advance the address of a memory cell to be replaced with the redundant memory, an externally input address, and an address stored in the replacement address storage circuit An address comparison circuit for comparison; a comparison result holding circuit provided for each bank; the bank and row address input from the outside by the address comparison circuit; and the bank and row address of the address stored in the replacement address storage circuit; The ratio that holds the result when a match is detected It has a result holding circuit.

  Further, a semiconductor memory device according to another aspect of the present invention compares a memory cell array of a plurality of banks capable of multi-bank operation with a replacement address stored in advance and a bank, row address, column address inputted from the outside, When all of them match, there is a redundant memory that can be replaced in units of one address. The row address and the column address are input in a time-sharing manner, and the timing restrictions for determining whether to replace the redundant memory are severe. A row address determination for determining a bank and a row address to be replaced by a redundant memory, which is a semiconductor memory device that can be used for both a specification of a small bank configuration and a specification of a multi-bank configuration with loose timing constraints A circuit further comprising: a row address determination circuit for each bank of the small bank configuration. A row address comparison circuit provided for each bank of the small bank configuration, and a row address comparison circuit for comparing a row address stored in the replacement address storage circuit with an output of the row address latch; and the multi-bank configuration And a comparison result holding circuit for holding the comparison result of the row address comparison circuit. In the small bank configuration, the output of the row address comparison circuit is used as the output of the row address determination circuit. In the multi-bank configuration, a plurality of banks share the row address latch and the address match detection circuit, and the output of the comparison result holding circuit is used as the output of the row address determination circuit.

  A replacement address determination method in a semiconductor memory device according to still another aspect of the present invention includes a plurality of banks of memory cell arrays capable of multi-bank operation, a redundant memory that replaces the memory cell array in units of cells, and replacement with the redundant memory A method for determining a replacement address in a semiconductor memory device having a replacement address storage circuit for storing a bank, a row address, and a column address in advance, and inputting the bank and row address in response to an ACT command And the bank of the address to be replaced with the redundant memory is compared with the row address, and the comparison result is updated to store whether or not the row address is hit for each bank, and activated by the ACT command. Read command or write command for each bank When it is input, the comparison result of the row address of the bank stored in the storing step is hit, and the column address input by the read command or write command is stored in the replacement address storage circuit. When the column address of the bank is hit, instead of the memory cell array, read or write access is made to the redundant memory, and either the row address or the column address of the bank is not hit Then, read access or write access is performed on the memory cell array of the bank.

  According to the present invention, since the comparison result holding circuit for holding the comparison result of whether or not the row address matches for each bank is provided, the replacement address can be determined even if the row address is not held for each bank. Therefore, the circuit scale required for replacement address determination accompanying the increase in the number of banks can be suppressed.

It is a block diagram which shows the main structures of the semiconductor memory device by one Example of this invention. (A) is a word line replacement by primary relief, (b) is a bit line replacement by primary relief, and (c) is a schematic diagram for explaining memory cell replacement by secondary relief. FIG. 3 is a schematic block diagram of a secondary relief circuit 12 and an antifuse circuit 12a. 1 is a block diagram around a row address comparison circuit in a semiconductor memory device according to an embodiment of the present invention; FIG. It is a block diagram around a row address comparison circuit in a semiconductor memory device as a comparative example. FIG. 4 is an operation timing diagram of address determination according to an embodiment of the present invention. FIG. 6 is a block diagram around a row address comparison circuit in a semiconductor memory device according to another embodiment of the present invention.

  Embodiments of the present invention will be described with reference to the drawings as necessary. In addition, drawing quoted in description of embodiment and the code | symbol of drawing are shown as an example of embodiment, and, thereby, the variation of embodiment by this invention is not restrict | limited.

  In the semiconductor memory device 10 according to the embodiment of the present invention, for example, as shown in FIGS. 1, 4, and 7, a row address and a column address are input in a time division manner (for example, input in synchronization with an ACT command). In the semiconductor memory device 10 that receives a row address and a column address that is input in synchronization with a read command or a write command, a plurality of banks of memory cell arrays 20 (only one bank is shown in FIG. 1), a memory A redundant memory 32 that is arranged outside the cell array and can be replaced in units of cells, a replacement address storage circuit 12a in which addresses of memory cells to be replaced with the redundant memory are stored in advance, and an externally input address and replacement address storage circuit 12a An address comparison circuit (150 in FIG. 3) for comparing the address stored in A comparison result holding circuit 190 provided for each of the banks, when the address comparison circuit 150 detects a match between an externally input bank and row address and an address bank and row address stored in the replacement address storage circuit 12a. And a comparison result holding circuit 190 for holding the result. When the row address and the column address are specified by time division (different timing or another command), generally, if the row address is not held until the column address is given, the replacement address No match can be detected. In particular, when performing multi-bank operation, the memory cell array of each bank is accessed in parallel, so that the row address for each bank from when the row address of the bank is given until the column address of the bank is given. Had to be kept. According to the above configuration, since the comparison result holding circuit 190 that holds whether or not the addresses match for each bank is provided, it is not necessary to hold the row address for each bank for the replacement address determination.

  Further, in the semiconductor memory device 10 according to the embodiment of the present invention, for example, as shown in FIG. 1, FIG. 3, FIG. 4, and FIG. When all the matches of the bank, row address, and column address are detected using the bank and row address comparison results held in 190, the redundant memory 32 is accessed instead of the memory cell array 20. The address comparison circuit 150 of FIG. 3 also includes a column address comparison circuit (not shown). The address comparison circuit 150 compares whether the bank, row address, and column address all match the replacement address.

  Further, for example, as illustrated in FIGS. 1 and 4, the semiconductor memory device 10 according to the embodiment of the present invention includes a semiconductor memory device 10 having a first specification (LPDDR1) with a small bank configuration and a first configuration with a multi-bank configuration. The semiconductor memory device 10 can be used for either of the two specifications (LPDDR2), the row address latch 170 provided for each bank of the small bank configuration (LPDDR1), and the small bank configuration (LPDDR1). And a row address comparison circuit 180 that compares the row address stored in the replacement address storage circuit 12a with the output of the row address latch 170. In the multi-bank configuration specification, the row address latch 170 and The row address comparison circuit 180 is shared by a plurality of banks. For example, in the specification of a small bank configuration such as LPDDR1, when there are many restrictions on the readout time of the replacement address from the replacement address storage circuit (antifuse circuit) 12a to the replacement address latch circuit 140, a plurality of banks are processed in parallel. It is necessary to perform row address comparison. For this reason, in the small bank configuration specification (LPDDR1), it is necessary to provide the row address latch 170 and the row address comparison circuit 180 for each bank. In the multibank configuration specification (LPDDR2), the replacement address storage circuit (antifuse) Circuit) 12a to replace address latch circuit 140 when replacement address read time can be sufficiently secured, row address latch 170 and row address comparison circuit 180 need not be provided for each bank. The address comparison circuit 180 can be shared by a plurality of banks. Therefore, with the above configuration, the circuit scale required for replacement address determination can be suppressed while supporting both specifications.

  Further, for example, as illustrated in FIG. 4, the semiconductor storage device 10 according to the embodiment of the present invention further includes a control circuit 200 that controls the entire semiconductor storage device 10, and is a specification with a small bank configuration (LPDDR1)? The multi-bank configuration specification (LPDDR2) is used, or switching is performed by a control signal (MODE) from the control circuit 200. With the above-described configuration, the same semiconductor memory device 10 can be used with a specification of a small bank configuration or a specification of a multi-bank configuration.

  In addition, the semiconductor memory device 10 according to the embodiment of the present invention is configured to compare the replacement address read from the replacement address storage circuit 12a with the address comparison circuit 150, for example, as shown in FIGS. A replacement address holding circuit 140 that temporarily holds is further included, and the replacement address is transferred from the replacement address storage circuit 12a to the replacement address holding circuit 140 in response to a reset command input from the outside. When the replacement address storage circuit is configured by a non-volatile memory such as an antifuse, it takes time to sense and amplify the signal read from the non-volatile memory cell, or the distance from the address comparison circuit on the semiconductor chip is increased. For example, a holding circuit arranged near the address comparison circuit is provided with a volatile replacement address holding circuit 140 that holds data while power is supplied. The replacement address data is transferred in response to the reset command. In this way, it is not necessary to provide the row address latch 170 and the row address comparison circuit 180 for each bank.

  In addition, the semiconductor memory device 10 according to the embodiment of the present invention temporarily stores the replacement address read from the replacement address storage circuit 12a in order to be compared by the address comparison circuit 150, for example, as shown in FIGS. A replacement address holding circuit 140 is further included. When a small bank configuration specification (LPDDR1) is selected, a replacement is performed from the replacement address storage circuit 12a in response to a mode register set command (MRS command) input from the outside. When the replacement address is transferred to the address holding circuit 140 and the multi-bank configuration specification (LPDDR2) is selected, the replacement address storage circuit 12a replaces the replacement address holding circuit 140 with the reset command input from the outside. Forward the address. When the replacement address is transferred to the replacement address holding circuit by the mode register set command, there are many timing restrictions. Therefore, a row address latch and a row address comparison circuit are provided for each bank, and each bank is compared with the replacement address in parallel. However, when the replacement address is transferred to the replacement address holding circuit in response to the reset command, there is a time allowance, so the row address latch 170 and the row address comparison circuit 180 must be provided for each bank. There is no.

  Further, in the semiconductor memory device 10 according to the embodiment of the present invention, for example, as shown in FIGS. 1 and 2, a plurality of banks of memory cell arrays 20 are replaced in units of word lines WL or bit lines BL in the memory cell arrays. When the redundant memory 32 including the redundant word line RWL and / or the redundant bit line RBL and being arranged outside the memory cell array cannot be replaced by the redundant word line RWL or the redundant bit line RBL included in the memory cell array This is a small capacity redundant memory used. For example, even if programming whether to use redundant word lines or redundant bit lines is performed by a laser, a nonvolatile semiconductor memory capable of electrically programming a replacement address storage circuit that stores an address to be replaced with a redundant memory If constituted by a circuit, after assembly into a package, it is possible to relieve a defect found after the redundant word line or redundant bit line can no longer be programmed by irradiating a laser.

  In the semiconductor memory device 10 according to an embodiment of the present invention, the redundant memory 32 arranged outside the memory cell array 20 is an SRAM. Since the redundant memory has a relatively small capacity, an SRAM can be used.

  The semiconductor memory device 10 according to an embodiment of the present invention includes a nonvolatile memory circuit 110 in which the replacement address memory circuit 12a can be electrically programmed. An electrically programmable nonvolatile memory circuit can be programmed even after packaging and is nonvolatile, so that a replacement address can be stored even when the power is turned off.

  In addition, the semiconductor memory device 10 according to an embodiment of the present invention includes an antifuse circuit in which the replacement address memory circuit 12a can be electrically programmed. If an antifuse is used, it can be electrically programmed and the replacement address can be stored even when the power is turned off.

The semiconductor memory device 10 according to an embodiment of the present invention includes, for example, a plurality of banks of memory cell arrays 20 capable of multi-bank operation, a replacement address stored in advance, and an external input as shown in FIGS. A redundant memory 32 that can be replaced in units of one address when all the same bank, row address, and column address are compared,
A low-bank configuration specification (LPDDR1) with strict timing constraints for row address determination as to whether or not to replace with the redundant memory 32, and a multi-bank configuration with loose timing constraints. The semiconductor memory device 10 that can be used for either of the specifications (LPDDR2), and further includes a row address determination circuit (170, 180, 190) that determines a bank and a row address to be replaced with a redundant memory. The row address determination circuit (170, 180, 190) is provided for each bank having a small bank configuration and the row address provided for each bank having a small bank configuration and stored in the replacement address storage circuit 12a. And a row address comparison circuit 180 for comparing the output of the row address latch 170; A comparison result holding circuit 190 which is provided for each bank of the bank configuration and holds the comparison result of the row address comparison circuit 180. In the small bank configuration (LPDDR1), the output of the row address comparison circuit 180 is determined as a row address. The output of the circuit (170, 180, 190) is output as it is. In a multi-bank configuration, the row address latch 170 and the address comparison circuit 180 are shared by a plurality of banks, and the output of the comparison result holding circuit 190 is determined as a row address. The output of the circuit (170, 180, 190).

  The semiconductor memory device 10 according to the embodiment of the present invention includes a column address determination circuit (not shown) that determines a bank and a column address to be replaced with a redundant memory, for example, as shown in FIGS. 3 is included in the address comparison circuit 150 in FIG. 3, and the bank and row address input in response to the ACT command are determined by the row address determination circuit and the determination result is held in the row address determination circuit. The bank and column address input in response to the read command or write command input after the ACT command are determined by the column address determination circuit, the row address determination circuit (170, 180, 190) of the corresponding bank, the column address When both judgment circuits hit, the redundant memory 32 is accessed instead of the memory cell array 20 That.

  The replacement address determination method in the semiconductor memory device 10 according to the embodiment of the present invention includes a plurality of banks of memory cell arrays 20 capable of multi-bank operation, a redundant memory 32 that replaces the memory cell array 20 in units of cells, A replacement address determination method in a semiconductor memory device 10 having a replacement address storage circuit 12a for storing a bank to be replaced with a memory, a row address, and a column address in advance, and the bank and row address in response to an ACT command , To activate the bank, compare the bank of the address to be replaced with the redundant memory and the row address, update the comparison result whether the row address hits for each bank, and store the result, ACT Read command for bank activated by command or When the write command is input, the row address comparison result stored in the storing step is hit, and the column address input by the read command or write command is stored in the replacement address storage circuit 12a. When the column address of the relevant bank is hit, read or write access is made to the redundant memory 32 instead of the memory cell array 20, and either the row address or the column address of the relevant bank is not hit At this time, read access or write access is performed to the memory cell array 20 of the bank. That is, in the ACT command, it is determined whether or not the row address portion of the replacement address has been hit, and the result is stored for each bank. Next, when a read command or a write command for the bank is input, a hit is finally made using information on whether or not the row address stored when the ACT command is received is hit It is possible to access the memory cell array or the redundant cell based on the determination result. According to the above method, it is not necessary to store the row address given by the ACT command for determining the replacement address.

  In addition, in the method for determining a replacement address in the semiconductor memory device 10 according to the embodiment of the present invention, the semiconductor memory device 10 includes the latch circuit 190 that stores the comparison result of the row address for each bank, and responds to the ACT command. Whether the row address matches by updating the stored contents of the latch circuit 190 of the bank according to the comparison result of the row address of the bank and referring to the stored contents of the latch circuit 190 in response to the read or write command Make a decision. That is, it is possible to store information on whether or not the row address is hit in the latch circuit 190 provided for each bank. Hereinafter, embodiments will be described in detail with reference to the drawings.

  FIG. 1 is a schematic diagram for explaining a two-stage repair method for the semiconductor memory device 10 according to the first embodiment.

  As shown in FIG. 1, the semiconductor memory device 10 according to the first embodiment refers to an input address ADD inputted from the outside, and a primary relief circuit 11 for relieving a defective address included therein, and a primary relief circuit 11. And a secondary relief circuit 12 for relieving a defective address further included in the address ADD1 after relief.

  The primary relief circuit 11 is a circuit for relieving a defective address found by an operation test performed in a wafer state, and the defective address is held in the laser fuse circuit 11a. On the other hand, the secondary relief circuit 12 is a circuit for relieving a defective address found after packaging, and the defective address is held in the antifuse circuit 12a. The writing of the defect address to the laser fuse circuit 11a is performed by laser beam irradiation. On the other hand, the writing of a defective address to the antifuse circuit 12a is performed by applying a high voltage to the insulating film included in the antifuse element and causing dielectric breakdown thereof. Both of the fuse circuits 11a and 12a are capable of nonvolatile and irreversible address storage.

  Of the address ADD1 after the relief by the primary relief circuit 11, the row address is supplied to the row decoder 21 and the column address is supplied to the column decoder 22. The row decoder 21 is a circuit for selecting a word line WL included in the memory cell array 20. The column decoder 22 is a circuit for selecting the bit line BL included in the memory cell array 20. Memory cells MC are arranged at the intersections of the word lines WL and the bit lines BL. The memory cell MC is a series circuit of a cell transistor T and a cell capacitor C, the gate of the cell transistor T is connected to the corresponding word line WL, and the source / drain of the cell transistor T is connected to the corresponding bit line BL. Yes. In FIG. 1, the memory cell array 20, the row decoder 21, and the column decoder 22 are described as a single bank. However, since the semiconductor memory device 10 includes a plurality of banks, in practice, A plurality of memory cell arrays 20, row decoders 21, and column decoders 22 are provided as many as the number of banks.

  As shown in FIG. 2A, the word line WL in the memory cell array 20 includes a redundant word line RWL, and is connected to a defective word line (or defective bit F) by an operation test performed in a wafer state. Is found, it is replaced with the redundant word line RWL. In this case, a row address (defective row address) indicating a defective word line is written into the laser fuse circuit 11a. When the row address included in the input address ADD coincides with the defective row address, the address conversion is performed by the primary relief circuit 11, thereby replacing the redundant word line RWL instead of the defective word line. Access is made.

  Further, as shown in FIG. 2B, the column selection line YS in the memory cell array 20 includes a redundant column selection line RYS line, and a defective bit line (or a defective line by an operation test performed in a wafer state). When a bit line connected to the defective bit F) is found, the corresponding column selection line YS is replaced with the redundant column selection line RYS. In this case, a column address (defective column address) indicating a defective bit line is written in the laser fuse circuit 11a. When the column address included in the input address ADD coincides with the defective column address, the address conversion is performed by the primary relief circuit 11, thereby not the column selection line YS corresponding to the defective bit line, The redundant column selection line RYS corresponding to the redundant bit line RBL is selected.

  As described above, in the address relief using the primary relief circuit 11, the redundant word lines and the redundant bit lines in the memory cell array 20 are used.

  Further, the address ADD1 after the relief by the primary relief circuit 11 is also supplied to the secondary relief circuit 12. The secondary relief circuit 12 is a circuit for relieving defective bits that occur sporadically due to thermal stress during packaging after address relief by the primary relief circuit 11. As shown in FIG. 2C, the replacement of defective bits by the secondary relief circuit 12 uses redundant memory cells 32 provided outside the memory cell array 20.

  Since the secondary repair circuit 12 repairs defective bits in units of memory cells, both a row address and a column address are required for detecting a defective address. Therefore, address data including both a row address and a column address is written in the antifuse circuit 12a in order to specify a defective bit. When the address ADD1 after the primary relief matches the address written in the antifuse circuit 12a, the hit determination signal HIT is activated. When the hit determination signal HIT is activated, the access path is switched from the defective memory cell to the redundant memory cell 32 by the switching circuit 31 included in the redundant latch circuit 30. As a result, instead of the defective bit included in the memory cell array 20, the redundant access is made to the redundant memory cell 32. The redundant memory cell 32 is composed of, for example, an SRAM cell, and is arranged in a circuit area where the main amplifier 40 is provided.

  As shown in FIG. 1, the semiconductor memory device 10 according to the present embodiment further includes an RST circuit and an MRS circuit 50. The RST circuit is a circuit that generates a reset signal (RST) to which a reset command is input from the outside. When a mode register set command (MRS command) is input from the outside, the MRS circuit 50 generates a signal for setting various operation modes of the semiconductor memory device 10 in accordance with a predetermined code input as an address signal from the outside. Circuit. In FIG. 1, a reset signal (RST) is shown as one of the signals generated by the MRS circuit 50. As will be described later, in this embodiment, the reset signal (RST) is used as a control signal for the antifuse circuit 12a.

  FIG. 3 is a schematic block diagram of the secondary relief circuit 12 and the antifuse circuit 12a. As shown in FIG. 3, the antifuse circuit 12 a includes M antifuse element groups 110-1 to 110 -M and a serial transfer circuit 120. The antifuse element groups 110-1 to 110-M are circuits that respectively hold address data RA1 to RAM that designate a defective memory cell, and constitute a nonvolatile address holding circuit. Therefore, the antifuse element groups 110-1 to 110-M can store M defective addresses.

  The address data RA1 to RAM1 output from the antifuse element groups 110-1 to 110-M are transferred to the secondary relief circuit 12 by the serial transfer circuit 120. Each of these address data RA1 to RAM is composed of row bits, column addresses, bank addresses, and enable bits indicating whether or not these addresses are valid. The total of these row address, column address, bank address, and enable bit is N bits.

  On the other hand, the secondary relief circuit 12 includes a serial reception circuit 130 that receives the address data RA1 to RAM transferred by the serial transfer circuit 120, and a replacement address latch circuit that holds the address data RA1 to RAM received by the serial reception circuit 130. 140, each of address data RA1 to RAM held in replacement address latch circuit 140 is compared with input address ADD1 after repair by primary repair circuit 11, and address comparison circuit 150 for determining the match or mismatch It has. An input address ADD1 to the address comparison circuit 150 includes a row address XA, a column address YA, and a bank address BA. If the address ADD1 matches any of the address data RA1 to RAM as a result of the comparison, the address comparison circuit 150 activates a hit determination signal HIT indicating that the address is a defective address. The hit determination signal HIT is supplied to the redundant latch circuit 30 shown in FIG.

  FIG. 4 is a block diagram around the row address comparison circuit 180 for comparing row addresses in the address comparison circuit 150 in the semiconductor memory device 10 according to the first embodiment. This circuit is a circuit that detects whether or not the row address of the antifuse circuit 12a matches the row address input from the outside. The entire circuit of FIG. 4 is controlled by the control circuit by a clock CLK and a command input to the control circuit 200. In particular, when an ACT (bank active) command is given, if the row address of the bank to be activated matches the row address of the replacement address latch circuit 140 and the bank, the row address hit signal X -Outputs a hit signal.

  The specification selection circuit 220 is a circuit that selects whether the semiconductor memory device 10 is used as a memory of the LPDDR1 having a 4-bank configuration or as a memory of the LPDDR2 having an 8-bank configuration. Based on the selection signal (LPDDR1 / LPDDR2) of the specification selection circuit, the control circuit 200 causes the entire semiconductor memory device 10 to function as a memory chip of the LPDDR1 or LPDDR2 specification.

  When an ACT command is given, the control circuit 200 activates the X address buffer 240 and takes in a row address (X address) input from the outside. Note that the row address captured by the X address buffer 240 may be the X address after being repaired by the primary repair circuit 11. The row address fetched by the X address buffer is stored in the address latch (row address latch) 170 of the corresponding bank. Four address latches 170 are provided in accordance with the number of banks 4 of LPDDR1. Since the number of banks of LPDDR2 is 8, eight banks A to H of LPDDR2 share one address latch 170 in the two banks. The row address fetched by the address latch 170 is the same as the bank and row address stored in the replacement address latch circuit 140 transferred from the antifuse circuit 12a by the row address comparison circuit 180 which is a part of the address comparison circuit 150. To be compared. As a result of comparison, if the bank and row address match, a hit signal X-hit signal of the row address is output. Note that a plurality of lower address comparison circuits 180 are provided corresponding to the address latches 170 as many as the number of banks of LPDDR1. Therefore, in LPDDR2, like the address latch 170, a plurality of banks share the row address comparison circuit 180.

  The X-hit signal output from the row address comparison circuit 180 is input to the mode selection switch 230. When LPDDR1 is selected, the mode selection switch 230 outputs the X-hit signal output from the row address comparison circuit 180 to a column address comparison circuit (not shown) as it is. On the other hand, when LPDDR2 is selected, the X-hit signal is latched in the bank address latch (comparison result holding circuit) 190 output from the control circuit 200. Note that there are as many X-hit signal latches as the number of banks of LPDDR2, and LPDDR2 latches the X-hit signal (a signal indicating whether or not a row address is hit) for each bank. The latched X-hit signal is output to a column address comparison circuit (not shown), and the column address specified by the read command or write command matches the column address of the replacement address stored in the replacement address latch circuit 140. It is compared whether or not. If all of the bank, row address, and column address match according to the comparison result of the row address comparison circuit and the comparison result of the column address comparison circuit, a redundant memory is selected and accessed instead of the cell of the memory cell array. The On the other hand, if at least one of the bank, row address, and column address does not match, the cell of the specified row address and column address of the memory cell array 20 of the specified bank is selected and accessed.

  FIG. 5 is a block diagram of the periphery of the lower address comparison circuit in the memory chip dedicated to LPDDR1 that is not a combo chip as a comparative example. As shown in FIG. 5, the memory chip dedicated to LPDDR 1 is not provided with a latch (comparison result holding circuit) 190 that holds the state of the X-hit signal for each bank. In the case of dedicated to LPDDR1, the row address latches 170 are provided for the number of banks, and the row address comparison circuits 180 are provided for the number of banks. Therefore, the X-hit signal for each bank is not particularly provided with the latch 190. Both are always output. Therefore, when dedicated to LPDDR1, the latch (comparison result holding circuit) 190 is unnecessary.

  The row address latch 170 provided for each bank is provided for redundant address determination. In addition to the row address latch 170, a row address decoding (not shown) is attached to the row decoder 21 of each bank. For this purpose, a row address holding circuit is provided. Although it is conceivable that the row address holding circuit associated with the row decoder 21 has the function of the row address latch 170, the row decoder 21 of each bank is laid out separately from the address comparison circuit 150 in terms of chip layout. Therefore, the number of wirings is increased, which is not desirable. Therefore, the row address latch 170 is not provided for row address decoding, but is a circuit provided for replacement address determination.

  Next, FIG. 6 is an operation timing chart of address determination after initialization in LPDDR1 and LPDDR2. In the case of LPDDR1, replacement address data recorded as an on / off state of an antifuse element in the antifuse circuit 12a by an MRS (mode register set) command is sense-amplified by a load amplifier and converted into digital data. The replacement address data converted into the digital data is taken into the replacement address latch circuit 140 via the transfer wiring 160. After two cycles, which is the minimum mode set command cycle time tMRD after the MRS command, the bank A is activated by the ACT command ACT_A for the bank A, and the row address of the bank A is designated. Further, after a time tRRD (minimum of 2 cycles) required from ACT_A to giving an ACT command to another bank has elapsed, a bank active command is given to bank B. Further, one cycle later, a write command for bank A is input. In the write command for the bank A, a column address is specified, and a write operation is performed by giving a bank, a row address, and a column address together with a row address previously given by an ACT_A command.

  Here, the ACT command for bank A is given two cycles after the start of reading of the antifuse by the MRS command, and the ACT command for bank B is given two cycles later. In four cycles from when the MRS command is given to when the ACT command for bank B is given, determination of the replacement address by the ACT command for bank A does not end. Therefore, as shown in FIG. 5, in the case of LPDDR1, an address latch 170 and a row address comparison circuit 180 are provided for each bank so that X-hit determination can be performed in parallel for each bank. With such a configuration, after the MRS command, before the comparison of the row address of the bank to which the ACT command is first given is completed, the ACT command is given to another bank and the comparison of the row address of the other bank is performed in parallel. Can proceed.

  On the other hand, in LPDDR2, the read operation to the replacement address latch circuit of the antifuse is started by the RESET command. In the case of the RESET command, there is sufficient time until the ACT command is input, and the replacement address reading operation from the antifuse circuit 12a to the replacement address latch circuit 140 is completed before the ACT command is input. . Therefore, in the case of LPDDR2, it is not necessary to detect matching of row addresses in parallel for a plurality of banks. In addition, in determining the replacement address, it is necessary to detect that the bank, row address, and column address all match. However, if the row address matches, it is necessary to store for each bank. The row address itself is not necessary for determining the replacement address. Therefore, in LPDDR2, the comparison result of the row address is held in a latch (comparison result holding circuit) 190 for each bank, and the address latch 170 and the row address comparison circuit 180 are shared with other banks, so that the number of elements can be increased. The increase is prevented.

  FIG. 7 is a block diagram around the row address comparison circuit in the semiconductor memory device dedicated to LPDDR2. Portions that are substantially the same as those in FIG. 4 of the first embodiment are given the same reference numerals, and detailed descriptions thereof are omitted. In the first embodiment, a plurality of address latches 170 and row address comparison circuits 180 are provided for LPDDR1, but when dedicated to LPDDR2, only one address latch 170 and row address comparison circuit 180 is sufficient. However, the comparison result in the row address comparison circuit 180 is held by a latch (comparison result holding circuit) 190 provided for each bank. Thereby, a circuit for detecting coincidence of row addresses can be simplified.

  Although the embodiments have been described above, the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. It is.

10: Semiconductor memory device 11: Primary relief circuit 11a: Laser fuse circuit 12: Secondary relief circuit 12a: Antifuse circuit (replacement address memory circuit)
20: Memory cell array 21: Row decoder 22: Column decoder 30: Redundant latch circuit 31: Switching circuit 32: Redundant memory cell 40: Main amplifier 50: MRS (mode register set) circuit 51: RST (reset) circuit 110-1 110-M: Antifuse element group 120: Serial transfer circuit 130: Serial reception circuit 140: Replacement address latch circuit (replacement address holding circuit)
150: Address comparison circuit 160: Transfer wiring 170: Address latch (row address latch)
180: Row address comparison circuit 190: Latch (comparison result holding circuit)
200: Control circuit 220: Specification selection circuit 230: Mode selection switch 240: X address buffer

Claims (14)

In a semiconductor memory device that inputs a row address and a column address in a time-sharing manner,
A multi-bank memory cell array capable of multi-bank operation;
A redundant memory that is arranged outside the memory cell array and can be replaced in cell units;
A replacement address storage circuit that stores in advance the address of a memory cell to be replaced with the redundant memory;
An address comparison circuit that compares an externally input address with an address stored in the replacement address storage circuit;
A comparison result holding circuit provided for each bank, when the address comparison circuit detects coincidence between an externally input bank and row address and an address bank and row address stored in the replacement address storage circuit A comparison result holding circuit for holding the result; and
A semiconductor memory device comprising: When the address comparison circuit detects all matches of the bank, row address, and column address using the column address input from the outside and the comparison result of the bank and row address held in the comparison result holding circuit,
A semiconductor memory device, wherein the redundant memory is accessed instead of the memory cell array. The semiconductor storage device is a semiconductor storage device that can be used for both the first specification of the small bank configuration and the second specification of the multiple bank configuration,
A row address latch provided for each bank of the small bank configuration;
A row address comparison circuit that is provided for each bank of the small bank configuration and compares the row address stored in the replacement address storage circuit with the output of the row address latch;
With
3. The semiconductor memory device according to claim 1, wherein in the specification of the multi-bank configuration, the row address latch and the row address comparison circuit are shared by a plurality of banks. A control circuit for controlling the entire semiconductor memory device;
4. The semiconductor memory device according to claim 3, wherein the specification is changed according to a control signal from the control circuit, whether the specification is the small bank configuration or the multi-bank configuration. A replacement address holding circuit that temporarily holds the replacement address read from the replacement address storage circuit for comparison by the address comparison circuit;
5. The semiconductor memory device according to claim 1, wherein a replacement address is transferred from the replacement address storage circuit to the replacement address holding circuit in response to a reset command input from the outside. A replacement address holding circuit that temporarily holds the replacement address read from the replacement address storage circuit for comparison by the address comparison circuit;
When the specification of the small bank configuration is selected, a replacement address is transferred from the replacement address storage circuit to the replacement address holding circuit in response to a mode register set command input from the outside,
4. The replacement address is transferred from the replacement address storage circuit to the replacement address holding circuit in response to an externally input reset command when the multi-bank configuration specification is selected. 4. The semiconductor memory device according to 4.   The plurality of banks of memory cell arrays each include a redundant word line and / or a redundant bit line to be replaced in the memory cell array in units of word lines or bit lines, and the redundant memory disposed outside the memory cell array includes: 7. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a small-capacity redundant memory used when the redundant word lines and redundant bit lines included in the memory cell array cannot be replaced.   8. The semiconductor memory device according to claim 1, wherein the redundant memory arranged outside the memory cell array is an SRAM.   9. The semiconductor memory device according to claim 1, wherein the replacement address memory circuit includes a nonvolatile memory circuit that can be electrically programmed.   The semiconductor memory device according to claim 1, wherein the replacement address memory circuit includes an electrically programmable antifuse circuit. A multi-bank memory cell array capable of multi-bank operation;
Compare the replacement address stored in advance with the bank, row address, and column address input from the outside, and if all match, a redundant memory that can be replaced in units of one address;
A row address and a column address are input in a time-sharing manner, and a specification of a small bank configuration with strict timing constraints for row address determination whether to replace with a redundant memory or a specification of a multi-bank configuration with loose timing constraints A semiconductor memory device that can be used for both specifications,
A row address determination circuit for determining a bank and a row address to be replaced with the redundant memory;
The row address determination circuit
A row address latch provided for each bank of the small bank configuration;
A row address comparison circuit that is provided for each bank of the small bank configuration and compares the row address stored in the replacement address storage circuit with the output of the row address latch;
A comparison result holding circuit which is provided for each bank of the multi-bank configuration and holds a comparison result of the row address comparison circuit;
With
In the small bank configuration, the output of the row address comparison circuit is directly output as the output of the row address determination circuit,
In the multi-bank configuration, a plurality of banks share both the row address latch and the address comparison circuit, and the output of the comparison result holding circuit is used as the output of the row address determination circuit. . A column address determination circuit for determining a bank and a column address to be replaced with the redundant memory;
The row address determination circuit determines the bank and row address input in response to the ACT command, and holds the determination result in the row address determination circuit.
When the column address determination circuit determines the bank and column address input in response to the read command or write command input after the ACT command, and both the row address determination circuit and the column address determination circuit of the corresponding bank are hit, 12. The semiconductor memory device according to claim 11, wherein the redundant memory is accessed instead of the memory cell array. A multi-bank memory cell array capable of multi-bank operation;
A redundant memory for replacing the memory cell array in cell units;
A replacement address storage circuit for storing in advance the bank, row address, and column address to be replaced with the redundant memory;
A method for determining a replacement address in a semiconductor memory device comprising: a bank and a row address are input in response to an ACT command, the bank is activated, and the bank and row of the address to be replaced with a redundant memory are activated. Comparing the address and updating and storing the comparison result whether or not the row address hit for each bank; and
When a read command or a write command is input for the bank activated by the ACT command, the row address comparison result stored in the storing step is hit, and the read command or When the column address input by the write command and the column address of the bank stored in the replacement address storage circuit hit, instead of the memory cell array, read or write access to the redundant memory, A method for determining a replacement address in a semiconductor memory device, wherein a read access or a write access is performed on a memory cell array of a bank when either a row address or a column address of the bank does not hit. The semiconductor memory device includes a latch circuit that stores a row address comparison result for each bank,
In response to the ACT command, the stored contents of the latch circuit of the bank are updated by the comparison result of the row address of the bank,
14. The determination of a replacement address in a semiconductor memory device according to claim 13, wherein the stored contents of the latch circuit are referred to in response to the read or write command to determine whether or not the row addresses match. Method.

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