JP5762230B2 - Schmitt inverter circuit and semiconductor device - Google Patents

Description

  The present invention relates to a Schmitt inverter circuit and a semiconductor device including the Schmitt inverter circuit.

  Conventionally, an inverter 2 that inverts and outputs an input signal, an inverter 3 that inverts and outputs an output signal of the inverter 2, and a control circuit 5 that generates an output signal based on the output signal of the inverter 3 and the control signal EN0. Based on the input signal and the output signal of the control circuit 5, the impedance adjustment circuit 4 a that adjusts the impedance between the output node of the inverter 2 and the power supply potential on the high potential side, and the input signal and the output signal of the inverter 3 Based on this, a Schmitt trigger circuit has been proposed that includes an impedance adjustment circuit 4b that adjusts the impedance between the output node of the inverter 2 and the low-potential power supply potential (see, for example, Patent Document 1).

  In such a Schmitt trigger circuit, chattering at the switching portion between the high level and the low level of the output signal is suppressed by providing a threshold voltage on the high potential side and a threshold voltage on the low potential side.

JP 2008-16908 A

  However, in the Schmitt trigger circuit described in Patent Document 1, although the threshold voltage is changed using the control signal, there are two threshold voltages on the high potential side and the low potential side that affect the oscillation. For this reason, there is a problem in that the output frequency changes due to the difference between the two points depending on the power supply voltage and temperature.

  Specifically, description will be made using a Schmitt inverter having a conventional configuration as shown in FIG. The Schmitt inverter circuit 100 of FIG. 5 includes a first inverter 112 composed of a P-channel MOS (PMOS) -P1 and an N-channel MOS (NMOS) -N1, PMOS-P2, P3, and NMOS-N2, N3. The impedance adjusting circuit 114 and the second inverter 116 are configured. In the Schmitt inverter circuit 100, when the input signal is at a low level, the PMOS-P1 to P3 are turned on and the NMOS-N1 to N3 are turned off. In a transient state where the input signal changes from the low level to the high level, the threshold voltage of the input signal shifts to the high potential side. When the input signal is at a high level, the NMOS-N1 to N3 are turned on and the PMOS-P1 to P3 are turned off. In a transient state where the input signal changes from the high level to the low level, the threshold voltage of the input signal shifts to the low potential side. This is shown in FIG.

  Here, VthH to VthL when the threshold voltage on the high potential side is VthH and the threshold voltage on the low potential side is VthL are hysteresis widths. The threshold voltages VthH and VthL that determine the hysteresis width are determined by the impedance between the output node of the first inverter and the high-potential-side power supply potential, and between the output node and the low-potential-side power supply potential, and thus vary depending on the power supply voltage and temperature. Along with this, the hysteresis width determined at two points of VthH and VthL also changes. When the hysteresis width changes, as shown in FIG. 6B, the output signal rises and falls, and the output frequency changes.

  The present invention has been made to solve the above problems, and a Schmitt inverter circuit and a semiconductor device capable of suppressing a change in output frequency due to the influence of a power supply voltage and temperature while maintaining chattering suppression characteristics. The purpose is to provide.

  In order to achieve the above object, the Schmitt inverter circuit of the present invention is connected to the high potential side, and is connected to the first switching means that is turned on when the input signal is at the low level, and to the low potential side, and A first inverter including a second switching unit that is turned on when an input signal is at a high level, and an output unit that outputs an output signal between the first switching unit and the second switching unit; From the rise of the output signal of the first inverter, a first control signal that is at a high level while the input signal is lower than a first threshold voltage that is lower than a reference threshold voltage determined only by the first inverter is set. From the fall of the output signal of the first inverter, the input signal is high while it exceeds the second threshold voltage higher than the predetermined reference threshold voltage. A control circuit for outputting a second control signal to be a bell; third switching means connected to the high potential side and turned on when the input signal is at a low level; connected to the low potential side; and The fourth switching means that is turned on when the input signal is at the high level, connected between the output of the first inverter and the third switching means, and the first control signal output from the control circuit is at the high level The fifth switching means that is turned on in the case of, and the second switching signal that is connected between the output of the first inverter and the fourth switching means and that is output from the control circuit is high level. And a setting circuit for setting a threshold voltage of the first inverter.

  Further, the semiconductor device of the present invention can be configured including the Schmitt inverter circuit.

  According to the Schmitt inverter circuit and the semiconductor device of the present invention, it is possible to suppress changes in the output frequency due to the influence of the power supply voltage and temperature while maintaining the chattering suppression characteristic.

It is a block diagram which shows the outline of the Schmitt inverter circuit which concerns on this Embodiment. It is a block diagram which shows an example of a control signal generation part. It is a time chart which shows operation | movement of a control signal production | generation part. It is a time chart which shows operation | movement of the Schmitt inverter circuit which concerns on this Embodiment. It is a block diagram which shows the outline of the conventional Schmitt inverter circuit. It is a figure for demonstrating the fluctuation | variation of the hysteresis width which is a conventional problem.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, a Schmitt inverter circuit 10 of the present invention includes a first inverter 12 that inverts and outputs an input signal, an operational amplifier 14 that amplifies the output of the first inverter and outputs an output signal OUT, It includes a control circuit 16 that outputs a control signal for controlling switches SWH and SWL, which will be described later, and a setting circuit 18 that sets a threshold voltage of the first inverter.

The first inverter 12 is a CMOS inverter formed by PMOS-P1 and NMOS-N1 connected in series between power supply potential _{V DD} and the ground potential _{V SS.} Input signals are respectively input to the gates of the PMOS-P1 and the NMOS-N1. The source of the PMOS-P1 is connected to the power supply potential _{V DD,} the source of the NMOS-N1 is connected to the ground potential _{V SS.} The first inverter 12 outputs the potential at the connection point between the drain of the PMOS-P1 and the drain of the NMOS-N1.

  The control circuit 16 outputs a signal SLH obtained by inverting the input signal based on the threshold voltage VthH, and a third inverter 22 outputs a signal SLL obtained by inverting the input signal based on the threshold voltage VthL. The control signal generation unit 24 is configured to generate the control signals CSH and CSL for controlling the switches SWH and SWL, with the output signal OUT, the signal SLH, and the signal SLL as inputs. The threshold voltage VthH is higher than a reference threshold voltage determined only by the first inverter, and the threshold voltage VthL is lower than the reference threshold voltage. The threshold voltages VthH and VthL correspond to the threshold voltage on the high potential side and the threshold voltage on the low potential side assumed in the conventional Schmitt inverter circuit.

  For example, as illustrated in FIG. 2, the control signal generation unit 24 includes a first D flip-flop (D-FF) 26 that outputs the signal A based on the input of the signal SLH and the output signal OUT, and the signal A and the output signal. The second D-FF 28 that outputs the control signal CSL based on the input of OUT, the third D-FF 30 that outputs the signal B based on the input of the signal SLL and the output signal OUT, and the input of the signal B and the output signal OUT And the fourth D-FF 32 that outputs the control signal CSH.

  FIG. 3 shows a time chart in the control signal generator 24 in the example of FIG. The control signal CSH is generated as a signal that rises when the output signal OUT rises and falls when the signal SLL falls. That is, the control signal CSH is a signal that is at a high level from the rising edge of the output signal OUT while the input signal is less than the threshold voltage VthL. The control signal CSL is generated as a signal that rises at the falling edge of the output signal OUT and falls at the rising edge of the signal SLH. That is, the control signal CSL is a signal that becomes high level while the input signal exceeds the threshold voltage VthH from the fall of the output signal OUT.

Setting circuit 18, PMOS-P2 are connected in series between power supply potential _{V DD} and the ground potential _{V SS,} switches SWH, it is composed of switches SWL, and NMOS-N2. Input signals are respectively input to the gates of the PMOS-P2 and the NMOS-N2. The source of the PMOS-P2 is connected to the power supply potential _{V DD,} the source of the NMOS-N2 is connected to the ground potential _{V SS.} The drain of the PMOS-P2 is connected to the switch SWH, and the drain of the NMOS-N2 is connected to the switch SWL. The output of the first inverter 12 is connected to the connection point between the switch SWH and the switch SWL, and the setting circuit 18 outputs the potential at this connection point to the operational amplifier 14.

  Further, the control signal CSH output from the control circuit 16 is input to the switch SWH, and the switch SWH is turned on while the control signal CSH is at a high level. The control signal CSL output from the control circuit 16 is input to the switch SWL, and the switch SWL is turned on while the control signal CSL is at a high level.

  Next, the operation of the Schmitt inverter circuit 10 of the present embodiment will be described with reference to the time chart of FIG. FIG. 4A shows the input signal and hysteresis width (threshold voltages VthH and VthL) in the prior art as a comparison. FIGS. 7B to 7G show the respective signals in the present embodiment, where FIG. 5B shows the input signal and threshold voltage, and FIG. 5C shows the output signal OUT output from the operational amplifier 14. , (D) is a signal SLH output from the second inverter 20, (e) is a signal SLL output from the third inverter 22, and (f) and (g) are control outputs from the control circuit 16. Signals CSH and CSH are shown.

Here, it is assumed that the reference threshold voltage determined only by the first inverter 12 is V _DD / 2. Thus, the threshold voltage VthH of the second inverter 20 _is higher than _{V DD} / 2, the threshold voltage VthL of the third inverter _22, is set as lower than _{V DD} / 2 values. In the initial state, it is assumed that the switches SWH and SWL are both off.

First, when an input signal greater than VthL and less than V _DD / 2 is input to the first inverter 12 (A in FIG. 4), PMOS-P1 is turned on and NMOS-N1 is turned off. Here, since the switches SWH and SWL are OFF, the threshold voltage of the first inverter 12 becomes the reference threshold voltage V _DD / 2, and the output signal OUT becomes the high level. Further, the signal SLH output from the second inverter 20 is at a high level, and the signal SLL output from the third inverter 22 is at a low level. As a result, both the control signals CSH and CSL generated by the control signal generation unit 24 remain at a low level, and the off state of the switch SWH and the switch SWL is maintained.

Next, when the input signal shifts to the high level and exceeds V _DD / 2 and less than VthH (B in FIG. 4), PMOS-P1 is turned off, NMOS-N1 is turned on, and the output signal OUT is Fall down. Along with this, the control signal CSL rises and the switch SWL is turned on. As a result, like the conventional Schmitt inverter, the threshold voltage of the first inverter 12 changes to the low potential side due to the relationship between the impedance of the NMOS-N1, NMOS-N2, and the switch SWL and the impedance of the PMOS-P1. To do. For this reason, chattering at the switching portion of the output signal OUT can be suppressed.

Next, when the input signal further shifts to the high level side and exceeds VthH (C in FIG. 4), the signal SLH falls and goes to the low level. When the input signal exceeds the peak and shifts to the low level side and again becomes lower than VthH (D in FIG. 4), the signal SLH rises, the control signal CSL falls, and the switch SWL is turned off. At this time, since the switches SWH and SWL are both turned off, the threshold voltage of the first inverter 12 changes to V _DD / 2 again.

Next, when the input signal further shifts to the low level and becomes less than V _DD / 2 and VthL or more (E in FIG. 4), PMOS-P1 is turned on, NMOS-N1 is turned off, and the output signal OUT is changed. stand up. Along with this, the control signal CSH rises and the switch SWH is turned on. As a result, the threshold voltage of the first inverter 12 changes to the high potential side according to the relationship between the impedance of the PMOS-P1, the PMOS-P2, and the switch SWH and the impedance of the NMOS-N1, as in the conventional Schmitt inverter. To do. For this reason, chattering at the switching portion of the output signal OUT can be suppressed.

Next, when the input signal further shifts to the low level side and becomes less than VthL (F in FIG. 4), the signal SLL rises and becomes high level. When the input signal exceeds the peak and shifts to the high bell side and again exceeds VthL, the threshold voltage of the first inverter 12 changes to V _DD / 2 again in the same manner as A described above.

  As described above, according to the Schmitt inverter circuit of the present embodiment, the threshold voltage for switching between the high level and the low level of the output signal is the same as that when both the switches SWH and SWL of the setting circuit are in the off state. Since this is one point, the hysteresis width does not fluctuate, and changes in the output frequency due to the influence of the power supply voltage and temperature can be suppressed. Moreover, since the threshold voltage is moved to the high potential side or the low potential side at the portion where the output signal is switched between the high level and the low level, the chattering suppression characteristic of the conventional Schmitt inverter can be maintained. .

  Note that a semiconductor device including the Schmitt inverter circuit of this embodiment mode may be used.

DESCRIPTION OF SYMBOLS 10 Schmitt inverter circuit 12 1st inverter 14 Operational amplifier 16 Control circuit 18 Setting circuit 20 2nd inverter 22 3rd inverter 24 Control signal generation part P1 PMOS-P1 (1st switching means)
P2 PMOS-P2 (third switching means)
N1 NMOS-N1 (second switching means)
N2 NMOS-N2 (fifth switching means)
SWH switch SWH (fourth switching means)
SWL switch SWL (sixth switching means)

Claims (4)

First switching means connected to the high potential side and turned on when the input signal is low level, and second switching means connected to the low potential side and turned on when the input signal is high level A first inverter provided with an output section for outputting an output signal between the first switching means and the second switching means;
From the rising edge of the output signal of the first inverter, a first control signal that is at a high level while the input signal is lower than a first threshold voltage lower than a reference threshold voltage that is determined only by the first inverter is determined. A control circuit that outputs a second control signal that is at a high level while the input signal exceeds a second threshold voltage that is higher than a predetermined reference threshold voltage from the falling edge of the output signal of the first inverter;
Third switching means connected to the high potential side and turned on when the input signal is at a low level, and fourth switching means connected to the low potential side and turned on when the input signal is at a high level. A fifth switching means connected between the output of the first inverter and the third switching means, and turned on when the first control signal output from the control circuit is at a high level; and A sixth switching means connected between the output of the first inverter and the fourth switching means and turned on when the second control signal output from the control circuit is at a high level; A setting circuit for setting a threshold voltage;
Including Schmitt inverter circuit. A second inverter that inverts and outputs the input signal based on the first threshold voltage; a third inverter that inverts and outputs the input signal based on the second threshold voltage; Based on an output signal of the first inverter and an output signal of the second inverter, a first flip-flop that outputs the first control signal, an output signal of the first inverter, and an output signal of the third inverter The Schmitt inverter circuit according to claim 1, comprising a second flip-flop that outputs the second control signal based on the second flip-flop.   The first switching means, the third switching means, and the fifth switching means are P-channel transistors, and the second switching means, the fourth switching means, and the sixth switching means are N-channel transistors. The Schmitt inverter circuit according to claim 1 or 2.   A semiconductor device comprising the Schmitt inverter circuit according to any one of claims 1 to 3.

Images