JP5758866B2 - Charge pump circuit and load drive system - Google Patents

Description

  The present invention relates to a charge pump circuit that generates and outputs a positive output voltage or a negative output voltage based on an input voltage, and a load drive system in which the charge pump circuit is applied to an amplifier circuit with two power supplies. .

Conventionally, as this type of charge pump circuit, as shown in FIG. 8, a circuit that generates a negative voltage that is ½ of the input voltage is known.
This charge pump circuit is driven under a single power source, that is, one positive power source 21, and generates a negative voltage that is 1/2 of the reference voltage (input voltage) output from the reference power source 22. Capacitors C11 and C12, a negative voltage output capacitor C13, switches S11 to S17 that electrically connect or disconnect capacitors C11 to C13, and a switch drive circuit unit 23 that controls on / off of the switches S11 to S17 are provided. Yes.

  In the charge pump circuit having such a configuration, the switches S11 to S13 are turned on and the switches S14 to S17 are turned off by the switch drive circuit unit 23 in the first period of the clock signal. Capacitors C11 and C12 are connected in series between them. At this time, if the capacitance values of the capacitor C11 and the capacitor C12 are equal, each of the capacitors C11 and C12 accumulates a charge of ½ of the reference voltage.

Next, in the second period of the clock signal, the switch drive circuit unit 23 turns off the switches S11 to S13, turns on the switches S14 to S17, and the capacitors C11, C12, and C13 are connected in parallel. At this time, the negative charges of the capacitors C11 and C12 are transferred to the capacitor C13.
The charge pump circuit of FIG. 8 generates a voltage that is ½ of the reference voltage output from the reference power supply 22 by repeating such a series of operations.

In this example, the case where there are two charging capacitors has been described. However, after charging N charging capacitors in series, the N charging capacitors are connected in parallel so as to have a negative voltage. Thus, a charge pump circuit that generates a negative voltage that is 1 / N times the reference voltage can be configured.
Such a charge pump circuit is disclosed in Patent Document 1, for example.

JP 2009-27880 A

  In the charge pump circuit described in Patent Document 1, for example, five capacitors are required to output a negative voltage that is 1/4 of the reference voltage. Therefore, in a charge pump circuit that generates a power supply voltage from a reference voltage and drives a driven circuit with the generated power supply voltage, an increase in the number of charging capacitors is inevitable in order to reduce power consumption. There is a problem that increases.

  In view of such a point, the present invention provides a charge pump circuit and a load driving system with a small circuit scale and low power consumption when generating a positive / negative output voltage that is ¼ of an input voltage, for example. The purpose is to do.

One aspect of the present invention is a charge pump circuit that generates positive and negative output voltages based on an input voltage, respectively, between a first capacitor, a second capacitor, a positive output terminal, and ground. Electrically connecting the third capacitor to be connected, the fourth capacitor connected between the negative output terminal and the ground, the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; A switching circuit for connecting or separating, wherein the switching circuit includes a first switching means for connecting a positive terminal of the first capacitor to the input voltage or a positive terminal of the second capacitor; A second switch that connects the negative terminal of the capacitor to the ground, the positive terminal of the second capacitor, or the positive terminal of the fourth capacitor And a third switching means for connecting the positive terminal of the second capacitor to the positive terminal of the third capacitor, and the negative terminal of the second capacitor is connected to the ground or the positive side of the third capacitor. Fourth switching means connected to the terminal , and repeatedly performing the operations of the first state, the second state, and the third state, and in the first state, the first capacitor, the second capacitor, and the second state 3 capacitors are connected in series, and each capacitor is charged by the input voltage. In the second state, the charges charged in the first capacitor, the second capacitor, and the third capacitor in the first state are charged. , The first capacitor, the second capacitor, and the third capacitor so as to be distributed to the first capacitor, the second capacitor, and the third capacitor. And in the third state, the charge distributed to the first capacitor, the second capacitor, and the third capacitor in the second state is changed to the first capacitor, the second capacitor, and the third capacitor. A charge pump circuit, wherein the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are connected so as to be distributed to the third capacitor and the fourth capacitor. is there.

Further, in the first state, the switching circuit applies the input voltage to the positive terminal of the first capacitor, connects the negative terminal of the first capacitor to the positive terminal of the second capacitor, Connecting the negative terminal of the second capacitor to the positive terminal of the third capacitor, and connecting the positive terminal of the first capacitor to the positive terminal of the second capacitor in the second state; 1 connect the negative terminal of the capacitor to ground, connecting the negative terminal of the second capacitor to the positive terminal of the third capacitor, in the third state, the positive electrode side terminal of the first capacitor The positive electrode side terminal of the second capacitor is connected to the positive electrode side terminal of the third capacitor, and the negative electrode side terminal of the first capacitor is connected to the positive electrode side terminal of the fourth capacitor. Connected to the negative terminal of the second capacitor may be adapted to connect to ground.
Another aspect of the present invention is a charge pump circuit that generates positive and negative output voltages based on an input voltage, respectively, between a first capacitor, a second capacitor, a positive output terminal, and ground. A third capacitor connected to the first capacitor, a fourth capacitor connected between a negative output terminal and the ground, and electrically connecting the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor. A switching circuit that is connected to or disconnected from the switching circuit, and the switching circuit repeatedly performs the operations of the first state, the second state, and the third state, and in the first state, the positive terminal of the first capacitor The input voltage is applied, the negative terminal of the first capacitor is connected to the positive terminal of the second capacitor, and the negative terminal of the second capacitor is connected to the third capacitor. Connecting the first capacitor, the second capacitor, and the third capacitor in series to charge each capacitor with the input voltage, and in the second state, The first capacitor, the second capacitor, and the third capacitor in the first state are distributed to the first capacitor, the second capacitor, and the third capacitor so that the charges charged in the first capacitor, the second capacitor, and the third capacitor are distributed to the first capacitor. The positive terminal of the capacitor is connected to the positive terminal of the second capacitor, the negative terminal of the first capacitor is connected to the ground, and the negative terminal of the second capacitor is connected to the positive terminal of the third capacitor. Connected and distributed in the third state to the first capacitor, the second capacitor, and the third capacitor in the second state. The positive terminal of the first capacitor and the positive terminal of the second capacitor and the second capacitor so that the electric charge is distributed to the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor. The first capacitor is connected to the positive terminal of the third capacitor, the negative terminal of the first capacitor is connected to the positive terminal of the fourth capacitor, and the negative terminal of the second capacitor is connected to the ground. It is a charge pump circuit.

The capacitance values of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor may be the same.
Another aspect of the present invention includes the charge pump circuit according to any one of the above aspects, and an output stage that operates using the positive and negative output voltages generated by the charge pump circuit based on an input voltage as a power supply voltage. And an amplifier circuit for driving the load.

  According to the present invention, for example, when a positive / negative output voltage that is 1/4 of the input voltage is generated, the number of capacitors can be increased to four. Therefore, it is possible to realize a charge pump circuit having a small circuit scale and low power consumption and a load driving system including the charge pump circuit.

It is a block diagram which shows the structural example of the load drive system with which embodiment of the charge pump circuit of this invention is applied. It is a wave form diagram which shows the example of a waveform of switch control signal SW1-SW8 which carries out on-off control of a switching element. It is an example of the circuit diagram which shows the structure of embodiment of an amplifier circuit. It is an example of the circuit diagram which shows the structure of embodiment of the circuit of the charge pump of this invention. FIG. 5 is an explanatory diagram for explaining an operation of the charge pump circuit of FIG. 4 and shows an operation in a first period (first state). FIG. 5 is an explanatory diagram for explaining the operation of the charge pump circuit of FIG. 4 and shows the operation in the second period (second state). FIG. 5 is an explanatory diagram for explaining an operation of the charge pump circuit of FIG. 4 and shows an operation in a third period (third state). It is a circuit diagram which shows the structure of the conventional charge pump circuit.

  Hereinafter, a charge pump circuit according to an embodiment of the present invention and a load driving system to which the charge pump circuit is applied will be described with reference to the drawings.

(Configuration of load drive system)
FIG. 1 is an example of a block diagram showing a configuration of a load driving system in which an embodiment of a charge pump circuit of the present invention is applied to an amplifier circuit with two power supplies.
As shown in FIG. 1, the load driving system 1 includes a clock generation circuit 2, a switch control circuit 3, a charge pump circuit 4, an amplifier circuit 5, and a load 6.
In this load driving system 1, the amplifier circuit 5 with two power supplies drives the load 6. The amplifier circuit 5 generates the positive output voltage VCC and the negative output voltage VEE generated by the charge pump circuit 4. Operates as power supply voltage.

  The clock generation circuit 2 includes a resonator such as a crystal resonator or a ceramic resonator, generates three clock signals CLK1 to CLK3 as shown in FIGS. Output to. As shown in FIGS. 2A to 2C, the clock signals CLK1 to CLK3 are signals having the same cycle and the same amplitude, and sequentially become high level from the clock signal CLK1, and at this time, the other two clock signals are low. It is a level. Therefore, the clock signals CLK1 to CLK3 are pulse signals having different phases.

The switch control circuit 3 generates switch control signals SW1 to SW8 as shown in FIGS. 2D to 2K based on the clock signals CLK1 to CLK3, and uses the switch control signals SW1 to SW8 as the charge pump circuit 4. Output to.
As will be described later, the charge pump circuit 4 includes a plurality of capacitors and a plurality of switching elements. The plurality of switching elements are ON / OFF controlled by switch control signals SW1 to SW8 output from the switch control circuit 3. Thereby, the charge pump circuit 4 generates positive and negative output voltages VCC and VEE by the charge pump method based on the input voltage VDD. The absolute values of the positive and negative output voltages VCC and VEE generated in this way are equal to approximately ¼ of the input voltage VDD.

The amplifier circuit 5 operates using the positive and negative output voltages VCC and VEE supplied from the charge pump circuit 4 as power supply voltages, and outputs an output signal SOUT from the input signal SIN and the level adjustment voltage VR. The load 6 is driven by the output signal SOUT.
The amplifier circuit 5 is an inverting amplifier circuit including an operational amplifier (operational amplifier), and includes an input signal SIN input to the inverting input terminal (−) and an offset input to the non-inverting input terminal (+). It has a function of outputting an output signal SOUT obtained by inverting and amplifying a signal of a difference from the voltage level adjustment voltage VR.

As the load 6, for example, a speaker, a headphone, or the like is applicable. At this time, the input signal SIN is an audio input signal. The load 6 also corresponds to a buffer circuit that drives a speaker, headphones, or the like.
FIG. 3 is an example of a circuit diagram showing a specific configuration of the amplifier circuit 5 of FIG.

As shown in FIG. 3, the amplifier circuit 5 includes an amplification stage 7 and an output stage 8. The amplification stage 7 operates using the input voltage VDD and the negative output voltage VEE of the charge pump circuit 4 as power supply voltages. However, the output stage 8 operates using the positive and negative output voltages VCC and VEE as power supply voltages. The amplification stage 7 amplifies the difference between the input signal SIN and the level adjustment voltage VR and outputs it as a drive signal. The output stage 8 is driven by the drive signal from the amplification stage 7 and outputs an output signal SOUT. For example, in the output stage 8, a P-channel MOS transistor M1 and an N-channel MOS transistor M2 connected in series are connected between the output voltages VDD and VEE, and a P-channel MOS transistor is driven by a drive signal from the amplifier stage 7. M1 and N-channel MOS transistor M2 are driven.
The amplifier circuit 5 may be configured so that both the amplification stage 7 and the output stage 8 operate using positive and negative output voltages VCC and VEE as power supply voltages.

(Charge pump circuit configuration)
FIG. 4 is a circuit diagram showing a specific configuration of the charge pump circuit 4 of FIG.
As shown in FIG. 4, the charge pump circuit 4 is driven under a single power source, that is, one positive power source 43, and a DC reference voltage generated by the reference power source 44 by the power source 43 is used as an input voltage VDD. Based on the input voltage VDD, positive and negative output voltages VCC and VEE each having a quarter of the input voltage VDD are generated.

  Therefore, as shown in FIG. 4, the charge pump circuit 4 includes charging capacitors C1, C2, a charging and positive voltage output capacitor C3, a negative voltage output capacitor C4, and capacitors C1 to C1. Eight switching elements S1 to S8 that electrically connect or disconnect C4 and two output terminals 41 and 42 that output a positive output voltage VCC and a negative output voltage VEE are provided.

The switching elements S1 to S8, which are switching circuits, are on / off controlled by switch control signals SW1 to SW8 output from the switch control circuit 3, respectively, and switch the connection state of the capacitors C1 to C4.
Here, the switch control signals SW1 to SW8 are as shown in FIGS. 2D to 2K, and perform on / off control of the corresponding switching elements S1 to S8. That is, the switch control signals SW1 to SW8 turn on the corresponding switching elements S1 to S8 when at the high level, and turn off the corresponding switching elements S1 to S8 when at the low level.

Each of the switching elements S1 to S8 is specifically composed of the following MOS transistors.
That is, the switching elements S3, S4, S6, and S8 are configured by N-channel MOS transistors, but may be configured by P-channel MOS transistors instead. The switching elements S1, S2, S5, and S7 are configured by P-channel type MOS transistors, but may be configured by N-channel type MOS transistors instead.

Next, specific connection between the capacitor and the switching element will be described with reference to FIG.
Here, the switching elements S3, S4, S6, and S8 are assumed to be N-channel MOS transistors, and the switching elements S1, S2, S5, and S7 are assumed to be P-channel MOS transistors.

  The positive terminal of the capacitor C1 is electrically connected to the drain terminal of the switching element S1 and the source terminal of the switching element S5. The source terminal of the switching element S1 is connected to the output terminal of the reference power supply 44, and an input voltage (reference voltage) VDD is applied. The drain terminal of the switching element S5 is electrically connected to the positive terminal of the capacitor C2, the drain terminal of the switching element S2, and the source terminal of the switching element S7.

  The negative electrode side terminal of the capacitor C1 is electrically connected to the source terminal of the switching element S2, the drain terminal of the switching element S4, and the drain terminal of the switching element S8. The source terminal of the switching element S4 is electrically connected to the ground terminal and the source terminal of the switching element S6. The negative terminal of the capacitor C2 is electrically connected to the drain terminal of the switching element S6 and the drain terminal of the switching element S3.

The positive terminal of the capacitor C3 is electrically connected to the source terminal of the switching element S3, the drain terminal of the switching element S7, and the output terminal 41, respectively. The negative electrode side terminal of the capacitor C3 is electrically connected to the negative electrode side terminal of the capacitor C4, and the common connection portion is connected to the ground. The positive terminal of the capacitor C4 is electrically connected to the source terminal of the switching element S8 and the output terminal 42, respectively.
Note that the potential of the ground (GND) is kept at the ground potential (0 [V]).

(Operation of charge pump circuit)
Next, an operation example of the charge pump circuit 4 configured as described above will be described with reference to the drawings.
As shown in FIG. 2, the charge pump circuit 4 operates in the first state in the first period T1, in the second state in the second period T2, and in the third state in the third period T3. Is one unit of operation, and these operations are repeated.

First, the operation in the first state in the first period T1 will be described with reference to FIGS.
In the first period T1, as shown in FIG. 2, the switch control signals SW1 to SW3 are at a high level, and the switch control signals SW4 to SW8 are at a low level. Therefore, as shown in FIG. 5, the switching elements S1 to S3 are turned on, and the switching elements S4 to S8 are turned off.

Therefore, in the first period T1, as shown in FIG. 5, the positive terminal of the capacitor C1 is connected to the output terminal of the reference power supply 44, and the negative terminal of the capacitor C1 and the positive terminal of the capacitor C2 are connected. Is done. Further, the negative terminal of the second capacitor C2 and the positive terminal of the third capacitor C3 are connected, and the negative terminal of the third capacitor C3 is connected to the ground.
As a result, the output terminal of the reference power supply 44, the switching element S1, the capacitor C1, the switching element S2, the capacitor C2, the switching element S3, the capacitor C3, and the ground path are formed, and the capacitors C1, C2, and C3 connected in series are formed. Is charged by the input voltage VDD.

At this time, the charge of VDD is accumulated in the capacitors C1 to C3 in total, and the charge of the capacitor C4 is held. If the capacitance values of the capacitors C1 to C3 are the same, a voltage that is 1/3 of the input voltage VDD is applied to each of the capacitors C1 to C3. Therefore, the input voltage VDD is applied to each of the capacitors C1 to C3. 1/3 of the charge is accumulated.
Therefore, in the first period T1, a positive output voltage VCC corresponding to the charge accumulated in the capacitor C3 is output from the output terminal 41, and a negative output voltage VEE corresponding to the charge held in the capacitor C4 is output. Output from terminal 42.

Next, the operation in the second state in the second period T2 will be described with reference to FIGS.
In the second period T2, as shown in FIG. 2, the switch control signals SW3 to SW5 are at a high level, and the switch control signals SW1, SW2, and SW6 to SW8 are at a low level. Therefore, as shown in FIG. 6, the switching elements S3 to S5 are turned on, and the switching elements S1, S2, and S6 to S8 are turned off.
Therefore, in the second period T2, as shown in FIG. 6, the positive terminal of the capacitor C1 and the positive terminal of the capacitor C2 are connected, and the negative terminal of the capacitor C1 is connected to the ground. Further, the negative terminal of the second capacitor C2 and the positive terminal of the third capacitor C3 are connected, and the negative terminal of the third capacitor C3 is connected to the ground.

  As a result, a ground, a switching element S4, a capacitor C1, a switching element S5, a capacitor C2, a switching element S3, a capacitor C3, and a ground closed loop are formed. As a result, the charges charged in the capacitors C1 to C3 in the first period are distributed to the capacitors C1 to C3. At this time, the charge is redistributed so that the voltage stored in the capacitor C1 and the voltage stored in the series connection of the capacitor C2 and the capacitor C3 are equal to each other, and the charge in the capacitor C4 is held. If the capacitance values of the capacitors C1 to C3 are the same, the capacitor C1 stores ½ charge of the input voltage VDD, and the capacitors C2 and C3 each store ¼ charge of the input voltage VDD. .

Therefore, in the second period T2, a positive output voltage VCC corresponding to the charge accumulated in the capacitor C3 after distribution is output to the output terminal 41, and a negative output voltage VEE corresponding to the charge held in the capacitor C4. Is output to the output terminal 42.
Next, the operation in the third state in the third period T3 will be described with reference to FIGS.

In the third period T3, as shown in FIG. 2, the switch control signals SW1 to SW4 are at a low level, and the switch control signals SW5 to SW8 are at a high level. Therefore, as shown in FIG. 7, the switching elements S1 to S4 are turned off, and the switching elements S5 to S8 are turned on.
Therefore, in the third period T3, as shown in FIG. 7, the positive terminal of the capacitor C1, the positive terminal of the capacitor C2, and the positive terminal of the third capacitor C3 are respectively connected. Further, the negative terminal of the capacitor C1 and the positive terminal of the fourth capacitor C4 are connected. Further, the negative terminal of the capacitor C2, the negative terminal of the third capacitor C3, and the negative terminal of the fourth capacitor C4 are connected to the ground.

As a result, the ground, the switching element S6, the capacitor C2, the switching element S7, the capacitor C3, and the first closed loop of the ground are formed. In addition, a second closed loop of the ground, the switching element S6, the capacitor C2, the switching element S5, the capacitor C1, the switching element S8, the capacitor C4, and the ground is formed.
As a result, the charges distributed to the capacitors C1 to C3 in the second period T2 are redistributed to the capacitors C1 to C4. At this time, the charge is redistributed so that the voltage accumulated in the series connection of the capacitors C1 and C4, the voltage accumulated in the capacitor C2, and the voltage accumulated in the capacitor C3 are equal. If the capacitance values of the capacitors C1 to C4 are equal, the capacitor C1 has a charge that is ½ of the input voltage VDD, the capacitors C2 and C3 each have a charge that is ¼ of the input voltage VDD, and the capacitor C4 has an input voltage VDD. -1/4 of the charge is accumulated.

Therefore, in the third period T3, the positive output voltage VCC corresponding to the charge accumulated in the capacitor C3 after redistribution is output from the output terminal 41, and the negative output corresponding to the charge after redistribution is output to the capacitor C4. The voltage VEE is output from the output terminal 42.
When such operations in the first to third periods T1 to T3 are repeated, the positive terminal of the capacitor C3 is charged to the voltage VCC that is ¼ of the input voltage VDD, and the positive terminal of the capacitor C4 is charged. The battery is charged to a voltage VEE that is -1/4 of the input voltage VDD.

As described above, in this embodiment, the four capacitors C1 to C4 and the switching elements S1 to S8 are provided, and the on / off control of the switching elements S1 to S8 is performed in each of the first to third periods T1 to T3. This was done as described above.
For this reason, according to this embodiment, based on the input voltage VDD from a single power supply, positive and negative output voltages VCC and VEE having a magnitude of 1/4 of the input voltage VDD are generated and output, respectively. be able to. Therefore, according to this embodiment, for example, in order to generate a negative output voltage that is ¼ of the input voltage, it is sufficient to have four capacitors. Therefore, a charge pump circuit with a small circuit scale and low power consumption can be realized. realizable.

In this embodiment, since the input power (input voltage VDD × input current I) is converted to output power of {(VDD / 4) × (4 × I)}, the output voltage is converted to the input voltage VDD. Therefore, an output current that is four times the input current I can be extracted.
(Modification of the embodiment)
The present invention is not limited to the above-described embodiment, and modifications, improvements, and the like are included in the present invention as long as the object of the present invention can be achieved.

  For example, when the input voltage is VDD, the output voltage to be output can be changed according to the magnitude of the output signal of the driven circuit to which the present invention is applied. For example, when the input voltage is set to VDD, a positive / negative voltage of ± VDD [V], ± 1/2 VDD [V], or ± 1/4 [V] is generated as an output voltage based on the input voltage. The form is mentioned.

  The charge pump circuit of the present invention can be applied to a drive circuit for driving a load, a semiconductor integrated circuit, and the like as a power source for various circuits that require two positive and negative power sources.

C1 to C4 Capacitors S1 to S8 Switching element 1 Load drive system 2 Clock generation circuit 3 Switch control circuit 4 Charge pump circuit 5 Amplifier circuit 6 Load 7 Amplification stage 8 Output stage

Claims (5)

A charge pump circuit that generates positive and negative output voltages based on an input voltage, respectively,
A first capacitor;
A second capacitor;
A third capacitor connected between the positive output terminal and ground;
A fourth capacitor connected between the negative output terminal and ground;
A switching circuit that electrically connects or disconnects the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor;
With
The switching circuit is
First switching means for connecting the positive terminal of the first capacitor to the input voltage or the positive terminal of the second capacitor;
A second switching means for connecting a negative terminal of the first capacitor to a ground, a positive terminal of the second capacitor, or a positive terminal of the fourth capacitor;
Third switching means for connecting the positive terminal of the second capacitor to the positive terminal of the third capacitor;
Fourth switching means for connecting the negative electrode side terminal of the second capacitor to the ground or the positive electrode side terminal of the third capacitor;
Including
Repeat the operations of the first state, the second state, and the third state,
In the first state, the first capacitor, the second capacitor, and the third capacitor are connected in series, and each capacitor is charged with the input voltage,
In the second state, the charges charged in the first capacitor, the second capacitor, and the third capacitor in the first state are distributed to the first capacitor, the second capacitor, and the third capacitor. Connecting the first capacitor, the second capacitor, and the third capacitor,
In the third state, the electric charge distributed to the first capacitor, the second capacitor, and the third capacitor in the second state is changed to the first capacitor, the second capacitor, the third capacitor, and the A charge pump circuit, wherein the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are connected so as to be distributed to a fourth capacitor. The switching circuit is
In the first state, the input voltage is applied to the positive terminal of the first capacitor, the negative terminal of the first capacitor is connected to the positive terminal of the second capacitor, and the negative side of the second capacitor Connecting the terminal to the positive terminal of the third capacitor;
In the second state, connect the positive terminal of the first capacitor to the positive terminal of the second capacitor, connects the negative terminal of the first capacitor to ground, the negative terminal of the second capacitor Is connected to the positive terminal of the third capacitor,
In the third state, the positive terminal of the first capacitor is connected to the positive terminal of the second capacitor and the positive terminal of the third capacitor, and the negative terminal of the first capacitor is connected to the fourth capacitor. of connected to the positive terminal, the charge pump circuit according to claim 1, characterized in that to connect the negative terminal of the second capacitor to ground. A charge pump circuit that generates positive and negative output voltages based on an input voltage, respectively,
A first capacitor;
A second capacitor;
A third capacitor connected between the positive output terminal and ground;
A fourth capacitor connected between the negative output terminal and ground;
A switching circuit that electrically connects or disconnects the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor;
With
The switching circuit is
Repeat the operations of the first state, the second state, and the third state,
In the first state, the input voltage is applied to the positive terminal of the first capacitor, the negative terminal of the first capacitor is connected to the positive terminal of the second capacitor, and the negative side of the second capacitor by connecting the terminal to the positive terminal of the third capacitor, said first capacitor, and connected to the second capacitor, and the third capacitor in series, each of said capacitor is charged by the input voltage,
In the second state, the charges charged in the first capacitor, the second capacitor, and the third capacitor in the first state are distributed to the first capacitor, the second capacitor, and the third capacitor. The positive terminal of the first capacitor is connected to the positive terminal of the second capacitor, the negative terminal of the first capacitor is connected to ground, and the negative terminal of the second capacitor is connected to the first capacitor. Connect to the positive terminal of 3 capacitors,
In the third state, the electric charge distributed to the first capacitor, the second capacitor, and the third capacitor in the second state is changed to the first capacitor, the second capacitor, the third capacitor, and the The positive electrode side terminal of the first capacitor is connected to the positive electrode side terminal of the second capacitor and the positive electrode side terminal of the third capacitor so as to be distributed to the fourth capacitor, and the negative electrode side terminal of the first capacitor is connected to the positive electrode side terminal. A charge pump circuit comprising: a positive electrode side terminal of a fourth capacitor; and a negative electrode side terminal of the second capacitor connected to a ground .   4. The capacitance value of each of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor is the same. 5. Charge pump circuit. The charge pump circuit according to any one of claims 1 to 4 ,
An amplifier circuit for driving a load, including an output stage that operates using the positive and negative output voltages generated by the charge pump circuit based on an input voltage as a power supply voltage;
A load drive system comprising:

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