JP2012210026A - Charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump circuit that can generate an output voltage of a target level even if a parasitic transistor occurs.SOLUTION: A charge pump circuit that generates an output voltage in response to an input voltage comprises: an integration circuit that outputs an integrated voltage in which the input voltage is integrated; an NMOS transistor that has an input electrode and a substrate electrode to which the integrated voltage is applied; a PMOS transistor that is connected in series to the NMOS transistor and is complementarily turned on or off with the NMOS transistor; a first capacitor that is charged based on a clock signal while the NMOS transistor is turned on and is discharged based on the clock signal while the PMOS transistor is turned on; and a second capacitor in which charges discharged from the first capacitor is charged while the PMOS transistor is turned on and generates the output voltage.

Description

  The present invention relates to a charge pump circuit.

  A charge pump circuit is known as a circuit for boosting the input voltage (see, for example, Patent Document 1). FIG. 6 is a diagram illustrating an example of the charge pump circuit 100. The charge pump circuit 100 includes an NMOS transistor M10, a PMOS transistor M11, and capacitors 110 and 111. In the charge pump circuit 100, the NMOS transistor M10 is turned on and the PMOS transistor M11 is turned off during a period φ1 in which the clock signal CLK is at a low level (hereinafter, “L” level). Therefore, the capacitor 110 is charged in the period φ1. On the other hand, in the period φ2 in which the clock signal CLK is at a high level (hereinafter, “H” level), the NMOS transistor M10 is turned off and the PMOS transistor M11 is turned on. As a result, the charge charged in the capacitor 110 is discharged to the capacitor 111. Therefore, when the input voltage is “Vin” and the amplitude of the clock signal CLK is “Vdd”, the output voltage Vout generated in the capacitor 111 is “Vin + Vdd”.

JP 2001-211637 A

  By the way, the charge pump circuit 100 is an integrated circuit manufactured using a triple well structure process. Therefore, the substrate electrode of the NMOS transistor M10 can be connected to an electrode (for example, a source electrode) to which the input voltage Vin is applied without grounding. However, when a triple well structure process is used, as shown in FIG. 6, for example, a PNP type is provided between the NMOS transistor M10 to which the input voltage Vin is applied and the capacitor 111 for generating the output voltage Vout. The parasitic transistor 150 is generated. In general, when the charge pump circuit 100 is activated, the output voltage Vout is approximately 0 V, so the input voltage Vin is higher than the output voltage Vout. In such a case, the parasitic transistor 150 may be turned on, and there is a problem that the charge pump circuit 100 cannot generate the target level output voltage Vout (Vout = Vin + Vdd).

  The present invention has been made in view of the above problems, and an object thereof is to provide a charge pump circuit capable of generating an output voltage of a target level even when a parasitic transistor is generated.

  In order to achieve the above object, according to one aspect of the present invention, a charge pump circuit that generates an output voltage according to an input voltage includes an integration circuit that outputs an integrated voltage obtained by integrating the input voltage, and the integrated voltage is applied. An NMOS transistor having an input electrode and a substrate electrode, a PMOS transistor connected in series with the NMOS transistor and turned on and off in a complementary manner with the NMOS transistor, and when the NMOS transistor is turned on, based on a clock signal The first capacitor discharged based on the clock signal when the PMOS transistor is turned on, and the charge discharged from the first capacitor charged when the PMOS transistor is turned on. And a second capacitor for generating the output voltage. .

  It is possible to provide a charge pump circuit that can generate an output voltage of a target level even when a parasitic transistor is generated.

It is a figure which shows the structure of the charge pump circuit 10 which is one Embodiment of this invention. 2 is a diagram showing a circuit excerpted from a part of the charge pump circuit 10. FIG. FIG. 4 is a diagram for explaining an operation at the time of activation of the charge pump circuit 10. It is a figure which shows the structure of the bias voltage generation circuit 40 to which this invention was applied. 6 is a diagram for explaining an operation at the time of starting the bias voltage generation circuit 40. FIG. 1 is a diagram showing a configuration of a general charge pump circuit 100. FIG.

  At least the following matters will become apparent from the description of this specification and the accompanying drawings.

  FIG. 1 is a diagram showing a configuration of a charge pump circuit 10 according to an embodiment of the present invention. The charge pump circuit 10 is a circuit that generates an output voltage Vout obtained by boosting the input voltage Vin. The integration circuit 20, capacitors 21 to 23, a control circuit 24, a clock signal output circuit 25, NMOS transistors M1 and M2, and a PMOS transistor It includes M3 and M4. The charge pump circuit 10 is an integrated circuit manufactured using a triple well structure process.

  The integrating circuit 20 is a circuit that integrates the input voltage Vin and outputs an integrated voltage Vbin indicating an integration result, and includes a resistor 30 and a capacitor 31. Here, the resistance value of the resistor 30 is “R1”, and the capacitance value of the capacitor 31 is “C1”.

  The clock signal output circuit 25 outputs a clock signal CLK1 and a clock signal CLK2 having a phase opposite to that of the clock signal CLK1. Therefore, the clock signal CLK2 is at the “L” level during the period when the clock signal CLK1 is “H” level, and the clock signal CLK2 is at the “H” level while the clock CLK1 is at “L” level.

  The NMOS transistor M1 and the PMOS transistor M3 connected in series are charge transfer transistors.

  The NMOS transistor M <b> 1 is provided between the integrating circuit 20 and the capacitor 21 in order to charge the capacitor 21. The integration voltage Vbin is applied to the source electrode (input electrode) and the substrate electrode of the NMOS transistor M1, and the capacitor 21 and the PMOS transistor M3 are connected to the drain electrode.

  The PMOS transistor M3 is provided between the capacitor 21 and the capacitor 23 in order to charge the capacitor 23 while discharging the capacitor 21. The NMOS transistor M1 and the capacitor 21 are connected to the drain electrode of the PMOS transistor M3, and the capacitor 23 is connected to the source electrode and the substrate electrode.

  One end of the capacitor 21 (first capacitor) is connected to a node to which the NMOS transistor M1 and the PMOS transistor M3 are connected, and the clock signal CLK1 is input to the other end. In this embodiment, the “L” level of the clock signal CLK1 is set to 0V, and the “H” level is set to Vdd (V: volts).

  The NMOS transistor M2 and the PMOS transistor M4 connected in series are charge transfer transistors similar to the NMOS transistor M1 and the PMOS transistor M3.

  The NMOS transistor M <b> 2 is provided between the integrating circuit 20 and the capacitor 22 in order to charge the capacitor 22. The integration voltage Vbin is applied to the source electrode and the substrate electrode of the NMOS transistor M2, and the capacitor 22 and the PMOS transistor M4 are connected to the drain electrode.

  The PMOS transistor M4 is provided between the capacitor 22 and the capacitor 23 in order to charge the capacitor 23 while discharging the capacitor 22. An NMOS transistor M2 and a capacitor 22 are connected to the drain electrode of the PMOS transistor M4, and a capacitor 23 is connected to the source electrode.

  One end of the capacitor 22 is connected to a node to which the NMOS transistor M2 and the PMOS transistor M4 are connected, and the clock signal CLK2 is input to the other end.

  The capacitor 23 (second capacitor) is charged with the electric charge from the capacitors 21 and 22, and the output voltage Vout is generated. In the present embodiment, the capacitance values of the capacitors 21 and 22 are “C2”, and the capacitance value of the capacitor 23 is “C3”. The capacitance value C1 of the capacitor 31 is greater than the capacitance value C2 of the capacitors 21 and 22.

  The control circuit 24 is a circuit that complementarily turns on and off the NMOS transistor M1 and the PMOS transistor M3 and complementarily turns on and off the NMOS transistor M2 and the PMOS transistor M4 based on the clock signal CLK1, for example.

  Specifically, the control circuit 24 turns on the NMOS transistor M1 during the period φ1 when the clock signal CLK1 is “L” level (0V), and the PMOS transistor M3 during the period φ2 when the clock signal CLK1 is “H” level (Vdd). Turn on. Therefore, the capacitor 21 is charged with a voltage corresponding to the integrated voltage Vbin in the period φ1, and the charge charged in the period φ2 is discharged. As a result, the output voltage Vout that is “Vbin + Vdd” is generated in the capacitor 23 in the period φ2.

  The control circuit 24 turns on the NMOS transistor M2 during the period φ2 when the clock signal CLK1 is “H” level, and turns on the PMOS transistor M4 during the period φ1 when the clock signal CLK1 is “L” level. Note that in the period φ2, the clock signal CLK2 becomes “L” level (0 V), and in the period φ1, the clock signal CLK2 becomes “H” level (Vdd). Therefore, the capacitor 22 is charged with a voltage corresponding to the integrated voltage Vbin during the period φ2, and the charge charged during the period φ1 is discharged. As a result, the output voltage Vout that becomes “Vbin + Vdd” is generated in the capacitor 23 in the period φ1.

  In this way, the charge pump circuit 23 generates the output voltage Vout that becomes “Vbin + Vdd” during the periods φ1 and φ2, that is, during one cycle of the clock signal CLK1. For example, the control circuit 24 controls the on / off of the NMOS transistor M1 and the like by providing a dead time so that the NMOS transistor M1 and the PMOS transistor M3 are simultaneously turned on and current does not flow from the capacitor 23 to the capacitor 31. .

<< Example of operation at start-up of charge pump circuit 10 >>
Here, an example of the operation at the time of starting the charge pump circuit 10 will be described. As described above, the NMOS transistor M1, the PMOS transistor M3, and the capacitor 21 in the charge pump circuit 10 of FIG. 1 generate the output voltage Vout in the period φ2, and the NMOS transistor M2, the PMOS transistor M4, and the capacitor 22 An output voltage Vout is generated at φ1. A circuit that generates the output voltage Vout in the period φ1 and a circuit that generates the output voltage Vout in the period φ2 operate in the same manner. For this reason, when describing the operation of the charge pump circuit 10, for the sake of convenience, as shown in FIG. 2, a circuit that generates the output voltage Vout in the period φ2 will be extracted and described.

  FIG. 3 is a diagram for explaining the operation when the charge pump circuit 10 is activated. In the state before the charge pump circuit 10 is activated, that is, the state before the clock signal CLK1 is input, the voltage value of the integrated voltage Vbin of the capacitor 31 is “Vin (voltage value of the input voltage)”. The voltages of 21 and 23 are assumed to be 0V. Here, it is assumed that the time constant τ1 (τ1 = R1 × C1) of the integrating circuit 20 is sufficiently longer than the cycle T of the clock signal CLK1.

  First, when the clock signal CLK1 is input at time t0 and the NMOS transistor M1 is repeatedly turned on and off, the integrated voltage Vbin decreases transiently. Since the input voltage Vin is applied to the integration circuit 20, the charging current to the capacitor 31 increases when the integration voltage Vbin decreases. Therefore, the integration voltage Vbin decreases, for example, from time t0 to time t1 when the time constant τ1 of the integration circuit 20 has elapsed, and then increases.

  Further, as described above, there is a relationship of “Vout = Vbin + Vdd” between the output voltage Vout and the integrated voltage Vbin. Therefore, when the integrated voltage Vbin decreases, the output voltage Vout also decreases similarly until, for example, time t1. Then, after time t1, the output voltage Vout rises according to the integrated voltage Vbin. Further, the integrated voltage Vbin rises to “Vin”, and as a result, the output voltage “Vout = Vin + Vdd” at the target level is generated.

  Thus, in the charge pump circuit 10, when the clock signal CLK1 is input at time t0, the output voltage Vout can be boosted while the integrated voltage Vbin is made lower than the output voltage Vout.

  In the charge pump circuit 10 shown in FIG. 1, the output voltage Vout is boosted during both periods φ1 and φ2. Therefore, the output voltage Vout of the charge pump circuit 10 rises faster than when the output voltage Vout rises only in the period φ2 illustrated in FIG.

<< Application Example of the Present Invention >>
FIG. 4 is a diagram showing an example of the bias voltage generation circuit 40 to which the present invention is applied. The bias voltage generation circuit 40 is a circuit that generates a bias voltage Vb for operating, for example, a MEMS (Micro Electro Mechanical Systems) microphone 41.

  The bias voltage generation circuit 40 includes an integration circuit 20, a clock signal output circuit 25, charge pump circuits 50 to 52, and an LPF (Low Pass Filter) 53. The integrating circuit 20 is the same as the circuit shown in FIG.

  Each of the charge pump circuits 50 to 52 includes the capacitors 21 to 23, the control circuit 24, NMOS transistors M1 and M2, and PMOS transistors M3 and M4 in the charge pump circuit 10 shown in FIG. Then, the clock signals CLK1 and CLK2 are input to the charge pump circuits 50 to 52, respectively.

  For this reason, the output voltage Vo1 of the charge pump circuit 50 is Vo1 = Vbin + Vdd. Similarly, the output voltage Vo2 of the charge pump circuit 51 is Vo2 = Vo1 + Vdd = Vbin + 2 × Vdd, and the output voltage Vo3 of the charge pump circuit 52 is Vo3 = Vo2 + Vdd = Vbin + 3 × Vdd.

  The LPF 53 is a filter for removing noise included in the output voltage Vo3. Specifically, the LPF 53 removes, for example, noise of frequency components of the clock signals CLK1 and CLK2 and noise generated by the resistor 30 of the integration circuit 20. Further, since the DC level of the bias voltage Vb is equal to the DC level of the output voltage Vo3, the bias voltage Vb = Vbin + 3 × Vdd.

  Here, the operation when the bias voltage generation circuit 40 is activated will be described with reference to FIG.

  First, when the bias voltage generation circuit 40 is activated and the boosting operation is started at time t10, the integrated voltage Vbin decreases transiently as in the case described with reference to FIG. For example, at time t11 when the time constant τ1 of the integrating circuit 20 has elapsed from time t10, the integrated voltage Vbin rises. For this reason, each of the output voltages Vo1 to Vo3 also rises after dropping according to the integrated voltage Vbin. The output voltages Vo1 to Vo3 have a relationship of Vo3> Vo2> Vo1. Therefore, the voltage on the input side of each of the charge pump circuits 50 to 52 does not become higher than the voltage on the output side.

  The charge pump circuit 10 and the bias voltage generation circuit 40 according to this embodiment have been described above. In the charge pump circuit 10, a PNP type parasitic transistor is generated between the substrate electrode of the NMOS transistor M1 and the capacitor 23 to which the output voltage Vout is applied (for example, FIG. 6). Therefore, when the integrated voltage Vbin becomes higher than the output voltage Vout, the parasitic transistor may be turned on. However, since the charge pump circuit 10 includes the integration circuit 20, the integration voltage Vbin can be made lower than the output voltage Vout. Therefore, the charge pump circuit 10 can generate the output voltage Vout (= Vin + Vdd) at the target level while preventing the parasitic transistor from being turned on. Also in the bias voltage generation circuit 40, as described above, the input side voltages of the charge pump circuits 50 to 52 do not become higher than the output side voltage. Therefore, the bias voltage generation circuit 40 can also generate the target level bias voltage Vb (= Vin + 3 × Vdd) without being affected by the parasitic transistor.

  Further, for example, when the time constant τ1 of the integrating circuit 20 is sufficiently shorter than the cycle T, the integrated voltage Vbin may immediately rise and become higher than the output voltage Vout even when the integrated voltage Vbin decreases during startup. . However, in the charge pump circuit 10, the time constant τ1 of the integrating circuit 20 is set longer than the cycle T of the clock signal CLK1. Therefore, the charge pump circuit 10 can more reliably prevent the parasitic transistor generated in the charge pump circuit 10 from being turned on.

  In addition, after the charge pump circuit 10 generates the output voltage Vout (= Vin + Vdd) at the target level, the parasitic transistor described above is not turned on. Therefore, for example, after a sufficiently long time (predetermined time) has elapsed and the output voltage Vout of the target level has been generated, the clock signal CLK1, having a cycle longer than the time constant τ1 of the integration circuit 20, is sent to the clock signal output circuit 25. CLK2 may be output. At this time, the capacitors 21 and 22 are charged and discharged based on the clock signals CLK1 and CLK2 having a cycle longer than the time constant τ1 of the integrating circuit 20. For this reason, the power consumption of the charge pump circuit 10 can be reduced.

  The integrating circuit 20 can be configured by using, for example, an operational amplifier, but generally increases the chip area and the like. In the present embodiment, since the integrating circuit 20 is configured by the resistor 30 and the capacitor 31, the chip area can be reduced.

  Further, when the time constant τ1 of the integration circuit 20 is set longer than the period T, for example, the resistance value R1 can be increased without increasing the capacitance value C1. However, when the resistance value R1 is increased, the time constant τ2 (= R1 × (C1 + C2)) becomes very large. As a result, for example, the charge charged in the capacitor 21 in the period φ1 decreases, and the increase in the output voltage Vout is delayed. In the present embodiment, the capacitance value C1 is larger than the capacitance value C2. Therefore, it is possible to prevent a decrease in the charging speed of the capacitor 21 during the period φ1, and the output voltage Vout can be increased quickly.

  The input voltage Vin may be the lowest voltage (for example, “0 V”) among the voltages applied to the integrated circuit in which the charge pump circuit 10 is formed. In such a case, it is possible to prevent the parasitic transistor from being turned on more reliably.

  Further, since the elements included in the charge pump circuits 50 to 52 are manufactured using a triple well structure process, there is no need to ground the substrate of the NMOS transistor included in the charge pump circuits 50 to 52. Therefore, for example, even when the number of stages of the charge pump circuit is increased, a high bias voltage Vb can be generated without using a high breakdown voltage transistor.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

  For example, when the input voltage Vin is the lowest voltage (for example, “0V”) among the voltages applied to the integrated circuit in which the charge pump circuit 10 is formed, the input voltage Vin is directly applied to the NMOS transistors M1 and M2. Even if it is applied, the same effect as in the present embodiment can be obtained. That is, for example, when the input voltage Vin is “0 V”, it is possible to prevent the parasitic transistor from being turned on without using the integration circuit 20.

  In the bias voltage generation circuit 40, for example, when the bias voltage Vb is grounded, the bias voltage Vb decreases from “Vin + 3 × Vdd” to 0V. Even in such a case, for example, by setting the input voltage Vin to the lowest voltage (for example, “0 V”) described above, the bias voltage generation circuit 40 can be reliably started.

10, 50, 51, 52 Charge pump circuit 20 Integration circuit 21-23, 31, 110, 111 Capacitor 24 Control circuit 25 Clock signal output circuit 30 Resistance 40 Bias voltage generation circuit 41 MEMS microphone 53 LPF
150 PNP transistor M1, M2, M10 NMOS transistor M3, M4, M11 PMOS transistor

Claims (6)

A charge pump circuit that generates an output voltage according to an input voltage,
An integrating circuit that outputs an integrated voltage obtained by integrating the input voltage;
An NMOS transistor having an input electrode and a substrate electrode to which the integration voltage is applied;
A PMOS transistor connected in series to the NMOS transistor and turned on and off in a complementary manner with the NMOS transistor;
A first capacitor that is charged based on a clock signal when the NMOS transistor is on, and that is discharged based on the clock signal when the PMOS transistor is on;
When the PMOS transistor is turned on, a charge discharged from the first capacitor is charged, and a second capacitor that generates the output voltage;
A charge pump circuit comprising: The charge pump circuit according to claim 1,
The time constant of the integration circuit is
Longer than the period of the clock signal;
A charge pump circuit. The charge pump circuit according to claim 1,
The first capacitor is:
Until the output voltage reaches the target level, charging and discharging are performed based on the clock signal having a cycle shorter than the time constant of the integration circuit. After the output voltage reaches the target level, the time constant of the integration circuit is reached. Charging and discharging based on the clock signal having a longer period;
A charge pump circuit. A charge pump circuit according to claim 2 or claim 3, wherein
The integration circuit includes:
A resistor to which the input voltage is applied;
A third capacitor connected to the resistor;
A charge pump circuit comprising: The charge pump circuit according to any one of claims 1 to 4,
The third capacitor is
Having a capacitance value greater than the capacitance value of the first capacitor;
A charge pump circuit. The charge pump circuit according to any one of claims 1 to 5 is an integrated circuit,
The input voltage is
Being the lowest voltage applied to the integrated circuit,
A charge pump circuit.

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