JP5751626B2 - Memory test apparatus, memory test method, and memory test program - Google Patents

Description

  The present invention relates to a memory test apparatus, a memory test method, and a memory test program, and in particular, automatically reuses a memory area address space that is blocked by a page for a large-capacity or small-capacity memory provided in an information processing apparatus. The present invention relates to a memory test apparatus, a memory test method, and a memory test program that enable and prevent potential failure of a memory area address space.

  In order to continue operation as an information processing apparatus even when a failure occurs in a memory provided in the information processing apparatus, for example, Japanese Patent Laid-Open No. 9-81464 of Patent Document 1 is disclosed. Various techniques have been proposed in the past as described in "Memory failure recovery method and recovery system for computer system" and Japanese Patent Application Laid-Open No. 11-259374 "Memory test apparatus and method and recording medium" in Patent Document 2. Has been.

JP-A-9-81464 (page 6-8) JP 11-259374 A (page 4-6)

  However, in the conventional memory test methods such as Patent Document 1 and Patent Document 2, in the case of an information processing device having a large-capacity memory, from the viewpoint of shortening the startup time of the information processing device, There is a case where sufficient memory test is not performed, there is a problem that a memory failure cannot be effectively detected when the information processing apparatus is started up, and an information processing apparatus having a small capacity memory (in general, In the case of an embedded information processing device), if a certain memory area address space where a failure is detected is blocked (page blocking), the usable memory area is greatly reduced, resulting in a system operation failure. There is also a problem that it may become stable.

  Even if a memory failure is detected during operation of the information processing apparatus, the memory failure cannot be reproduced in a reproduction test performed to diagnose the memory failure, and an effective analysis of the memory failure is performed. There are many cases where this is not possible.

  More specifically, the following first to fourth problems exist in the conventional memory test system. The term “memory area address space” used here is not only a DIMM (Dual Inline Memory Module) and main storage device, but also an OS (Operating System) such as a non-volatile memory and SRAM (Static Random Access Memory). : Operating system, hereinafter referred to as OS) is a general term for memory spaces that can be used. Further, when a large number of correctable failures occur in a short time in a specific memory area address space (referred to as a page), an uncorrectable failure may occur if the specific memory area address space is continuously accessed. Therefore, in general, when the number of occurrences of correctable failures exceeds a predetermined threshold, the OS or the like is controlled so as not to access this memory area address space (Page: page) by software. This process is called “page blocking process”.

  First, in a memory area address space (page) in which a large number of correctable failures have occurred, writing is performed only once at an initial stage, and thereafter, when only a read operation is performed, a correctable failure state is entered. It is not always appropriate to perform page blocking as it is for the memory area address space.

  For example, it is assumed that a certain memory address is written once and no further writing is performed thereafter. In such a case, the read operation is performed several hundred times in a short time without performing rewriting to the memory address, and it is determined that the correctable failure exceeds a predetermined threshold value. There is a case.

  Second, even if a certain cell in the memory is stacked at a certain value, if the data having the same value as the stacked state is written, the written data is read. Even an error cannot be detected. However, when data having a value opposite to the stacked value is written, an error always occurs when the data written in the stacked memory area is read.

  Therefore, although the frequency of occurrence of correctable faults is less than a predetermined threshold value, faults are hidden in the memory, and currently the page block state is not set, but the page is blocked in the future. This means that there is a memory area that is likely to be stored.

  Third, even if only a suspected failure part such as a DIMM / memory is replaced and mounted on a memory testing machine, a failure test may not be reproduced.

  For example, the failure may not be reproduced due to compatibility between the DIMM / memory and the board, and there are cases where it is important to perform a reproduction test in an environment where the failure occurs. In other words, if a so-called “compatibility problem” occurs, if the reproducibility test is performed in an environment where a failure has occurred, the suspected failure component is not a DIMM / memory, but a board. It becomes easy to analyze.

  Also, if the same memory test result is obtained every time even if the DIMM / memory is replaced when a reproduction test is performed in an environment where a failure has occurred, it is determined that the suspected faulty part is a board. be able to.

  Fourthly, with the increase in memory capacity in recent years, there is a problem that the startup time also increases when careful memory tests are performed on all memory area address spaces at the time of startup of the information processing apparatus. The memory test may not be performed on all memory area address spaces at the time of startup. Therefore, at the time of start-up, there may be a case where the error address and error data pattern of the memory cannot be found before the OS is activated.

(Object of the present invention)
The present invention has been made in view of the above-described circumstances, and enables a memory area address space in which a page is blocked to be reused and a memory test apparatus and a memory test capable of preventing a failure from occurring. It is an object to provide a method and a memory test program.

  In order to solve the above-described problems, the memory test apparatus, the memory test method, and the memory test program according to the present invention mainly adopt the following characteristic configuration.

  (1) A memory test apparatus according to the present invention is a memory test apparatus provided in the information processing apparatus for testing the memory of the information processing apparatus, and can be corrected in the memory during operation of the information processing apparatus. When detecting that a failure has occurred, failure registration means for registering the memory area address space including the memory address in which the correctable failure has occurred as a failure page, and the startup of the information processing apparatus thereafter A memory test execution means for performing a special memory test having a predetermined test pattern for the memory area address space corresponding to the failure occurrence page registered by the failure registration means during the raising operation; As a result of the special memory test performed by the test execution means, the memory corresponding to the failure page is recorded. When no failure is detected in the re-area address space, the OS (Operating System) is used after the memory area address space corresponding to the failed page is incorporated into the system as a normal memory area address space. And at least normal return means for returning to a state in which it can be performed.

  (2) A memory test method according to the present invention is a memory test method in a memory test apparatus provided in the information processing apparatus for testing a memory of the information processing apparatus. When detecting that a correctable failure has occurred in the memory, a failure registration step of registering the memory area address space containing the memory address in which the correctable failure has occurred as a failed page, and the information after that A memory test execution step for performing a special memory test consisting of a predetermined test pattern for the memory area address space corresponding to the failed page registered by the failure registration means during the startup operation of the processing device And as a result of the special memory test performed in the memory test execution step, If no failure is detected in the memory area address space corresponding to the failed page, the memory area address space corresponding to the failed page is incorporated into the system as a normal memory area address space and And at least a normal return step for returning to a state that can be used by the operating system (OS).

  (3) A memory test program according to the present invention is characterized in that at least each step of the memory test method described in (2) is implemented as a program executable by a computer.

  According to the memory test apparatus, the memory test method, and the memory test program of the present invention, the following effects can be obtained.

  The first effect is that the memory area address space in which the page is temporarily blocked can be automatically reused particularly when the data on the memory is intermittently stacked / fixed to a certain value. It is to become.

  The second effect is as follows. Recent embedded information processing devices already have a page-blocking function or are in the process of being incorporated in the future. However, the memory of embedded information processing devices is not large in capacity but mostly small in capacity. It is. In addition, the page blocking function is also implemented for a small-capacity RAM such as an SRAM. When page blocking is performed for such a small-capacity memory, the usable memory capacity is greatly reduced, and the system operation may become unstable. In the present invention, every time the system is started up, it can be set so as not to block the page as much as possible, so that an effect of stabilizing the system operation can be obtained.

  The third effect is that the memory address and data pattern when an error (failure) is detected in a special memory test executed at start-up, the memory DIMM (Dual Inline Memory Module) SPD (Special Presence Detect), diagnostic function Because it is held in the non-volatile memory, SRAM (Static Random Access Memory), etc., even if the failure is not reproduced in the reproduction test to be carried out for failure diagnosis later, based on the detailed failure state being held, It is easy to perform failure analysis. Furthermore, for example, detailed information may be necessary for customer supporters who need the analysis results of troubles and trouble reporters to customers, and provide useful information even in such situations. Can do.

It is a block block diagram for demonstrating an example of the apparatus structure of the memory test apparatus based on this invention. 10 is a flowchart illustrating an example of an operation when a correctable failure occurs in a memory when the CPU is using the memory as the information processing apparatus. A special memory test is performed on the memory area address space of the correctable failure that occurred in FIG. 2 when the information processing apparatus is restarted, and the page block of the memory area address space is blocked based on the execution result of the memory test. It is a flowchart which shows an example of operation | movement which cancels | releases or conversely performs a page block | close and collects and stores failure information. It is a table which shows an example of a table structure of a failure occurrence frequency registration table. It is a table which shows an example of a table structure of a memory test result registration table.

  Preferred embodiments of a memory test apparatus, a memory test method, and a memory test program according to the present invention will be described below with reference to the accompanying drawings. In the following description, the memory test apparatus and the memory test method according to the present invention will be described. However, the memory test method may be implemented as a memory test program that can be executed by a computer, or the memory test method may be used. Needless to say, the test program may be recorded on a computer-readable recording medium.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention relates to a memory area address space in a memory (such as a memory using a DIMM (Dual Inline Memory Module) or an SRAM (Static Random Access Memory)) provided in various information processing apparatuses including an embedded base. Even if the OS performs a so-called page blockage in which the OS does not use the memory area address space because a short-term correctable failure has occurred in the (page) exceeding a predetermined threshold value, When the memory area address space that has been blocked is restarted, a special memory test is performed. If no correctable failure occurs, it can be re-installed in the system, and the total available memory Prevents capacity loss and retains detailed data if correctable faults are reproduced when performing special memory tests. The main feature is that it is stored as failure analysis information.

  That is, in the present invention, information related to the memory area address space where the page is blocked during operation and the memory area address space where the correctable failure is detected is registered, and is registered when the system is restarted. By executing a special memory test consisting of a test pattern prepared in advance for the memory area address space, if a correctable failure is not detected, the memory area address space that is blocked by the page is made usable. Restore it and set it again as an OS asset (memory area address space that can be used by the OS), and if a failure occurs again during a special memory test, the failure pattern is retained for failure analysis The main feature is to do.

  Here, the special memory test is not only the case of all “0” write or all “1” write, but also “0” write / read → “1” write / read → “0”. Write / read → "0" like "1" write / read, reverse write / read sequence, or "0x5555" write / read-> "0xAAAA" write / read-> "0x5555" write / read A memory test including a “01 pattern”, a “10 pattern” inversion write / read sequence, etc., and a memory test using a test pattern in which a correctable failure may occur.

  In the present invention, before the information processing apparatus is restarted, information related to the memory area address space where the page is blocked during the previous operation and the memory area address space where the correctable failure has occurred is registered in the table. After that, when the information processing apparatus is restarted, the memory area address space where the page is blocked and the memory area address where the correctable failure has occurred are referred to at the time of memory initialization at the time of restart. A special memory test as described above is performed on the space.

  As a result of executing a special memory test, if the fault is not detected and the special memory test is passed, the memory area address space to be tested (the memory area address space in which the page is blocked, the correctable fault is The generated memory area address space) is incorporated into the system as it is and becomes a memory area that can be used by the OS.

  On the other hand, when a failure is detected again and the special memory test is failed, the memory area address space to be tested (a memory area address space in which a page is blocked, a memory area address space in which a correctable failure has occurred) ) Is isolated without being incorporated into the system, and the memory address and data pattern when an error occurs again in the special memory test, for example, when the memory is a DIMM, various specifications of the DIMM Are stored in a SPD (Special Presence Detect) which is a ROM area in which is stored, or in a nonvolatile memory or SRAM of the diagnostic function unit. The retained memory address and data pattern are used during failure analysis.

  By executing a special memory test such as this when the information processing device is restarted, if the normal memory test results are normal, the memory area address space that was blocked and correctable faults were detected. The memory area address space that has been used is re-installed in the system to prevent the total amount of memory that can be used by the OS from being reduced. On the other hand, if a correctable fault is reproduced, the detailed data is retained. It can be used for failure analysis.

(Configuration example of embodiment)
Next, an example of a specific embodiment of the memory test apparatus according to the present invention will be described. FIG. 1 is a block diagram for explaining an example of the configuration of a memory test apparatus according to the present invention. The memory test apparatus is composed of a general information processing apparatus, and the information processing apparatus is operated. This shows a case where the memory used inside is the test target of this memory test apparatus.

  The information processing apparatus of FIG. 1 that constitutes the memory test apparatus of the present embodiment includes a central processing unit (CPU) 10, a memory 11, a nonvolatile memory 12, a chipset 20, and a baseboard management controller (BMC: Baseboard). Management Controller) 30, memory 31, and SRAM (Static Random Access Memory) 32.

  A central processing unit (CPU) 10 is a processing unit for controlling the overall operation of the information processing apparatus. The memory 11 is a main storage device for storing various data used in the central processing unit 10, and is a memory using a DIMM (Dual Inline Memory Module) or the like. One of the target memories. The non-volatile memory 12 is a memory that retains data even when the power is turned off, and stores various data and firmware used in the central processing unit 10 as a diagnostic function unit. Data and tables necessary for the memory test apparatus are also stored. The chip set 20 is an integrated circuit group that manages an interface between the central processing unit 10 and various IO (Input / Output) devices. In FIG. 1, the central processing unit 10, the baseboard management controller 30, and the like. The case where it manages the interface between is illustrated.

  The baseboard management controller (BMC) 30 is a processing device that operates independently of the OS on the central processing unit 10, and performs failure processing of the memory 31, the SRAM 32, etc., and recovery processing from the failure. To do. In FIG. 1, at least a function capable of notifying the outside that a failure has occurred in the memory 31 and a function capable of collecting and holding information indicating a symptom when the failure has occurred are provided. Yes. The memory 31 is a storage device for storing various data used by the baseboard management controller 30, and is a memory using a DIMM (Dual Inline Memory Module) or the like. Another target memory. The SRAM 32 is a storage device for holding data necessary for the baseboard management controller 30 even when the power is turned off, and various data used by the baseboard management controller 30 as a diagnostic function unit. And a memory for storing firmware, and also stores data and tables necessary for the memory test apparatus. Note that the SRAM 32 may be a nonvolatile memory similar to the nonvolatile memory 12.

  Further, the central processing unit 10 is provided with a BIOS (Basic Input / Output System) 40 as firmware for performing input / output with the hardware at the lowest level. It also has a function of performing a special memory test, which is one of important functions, on the memory 11 and the like. On the other hand, the baseboard management controller 30 is provided with a BMCFW (BMC Firmware) 41 as firmware that performs input / output at the lowest level with the hardware. A special memory test, which is one of the important functions of the apparatus, is also performed on the memory 31 and the like.

  In this embodiment, the base board management controller 30, the memory 31 for the base board management controller 30, and the SRAM 32 for holding data of the base board management controller 30 will be described. However, if only the memory 11 used in the central processing unit 10 is used, it may not be mounted in some cases.

(Description of operation of embodiment)
Next, an example of the operation of the memory test apparatus shown in FIG. 1 will be described in detail with reference to the flowcharts of FIGS. FIG. 2 shows that when the central processing unit 10 is using the memory 11 as an information processing device, or when the baseboard management controller 30 is using the memory 31, the memory 11 or the memory 31 can be corrected. 7 is a flowchart illustrating an example of an operation when a memory failure occurs, and illustrates an operation example in which a memory area address space in which a correctable failure has occurred is registered or a page is blocked for the memory area address space.

  Also, FIG. 3 shows a memory area based on the result of the memory test performed by performing a special memory test on the memory area address space of the correctable failure that occurred in FIG. It is a flowchart which shows an example of operation | movement which cancels | releases the page block of address space, and conversely performs a page block and collects and stores failure information. In the flowchart of FIG. 3, when the information processing apparatus is started up, a special memory test is performed using a failure occurrence number registration table in which the failure state of the memory during the previous operation is registered in advance. An example of operation in which the OS operating on the apparatus 10 notifies the OS of a memory test execution result indicating whether the page block should be released or the page block should be performed is shown.

  The “memory area address” used below has the following meaning. That is, the “memory area address” is an address when the central processing unit 10 accesses the memory 11 (memory access address), or an address when the baseboard management controller 30 accesses the memory 31 (memory access address). ) Is divided into page block units.

  Here, the “page block unit” has a different capacity depending on the type of OS running on the central processing unit 10 and the baseboard management controller 30. For example, in the case of a certain OS, the unit is 1,024 bytes, and in the case of another different OS, the unit is 4,096 bytes. When the page block unit is 4,096 bytes, the address of the memory area next to the memory area address “1000 (hexadecimal number display)” is “2000 (hexadecimal number display)”.

  Therefore, when the page block unit is 4,096 bytes, the memory area address from “1000 (hexadecimal number display)” to “1FFF (hexadecimal number display)” is “1000 (hexadecimal number). The address of the memory area from “2000 (hexadecimal display)” to “2FFF (hexadecimal display)” is “2000 (hexadecimal display)”. The address of the memory area from “F000 (hexadecimal number display)” to “FFFF (hexadecimal number display)” is “F000 (hexadecimal number display)”.

  Next, an example of an operation when a correctable failure occurs during operation as an information processing apparatus, that is, when the central processing unit 10 uses the memory 11, will be described with reference to the flowchart of FIG.

  In the flowchart of FIG. 2, during operation in which the central processing unit 10 uses, for example, the DIMM 11 / memory as an information processing device, whether or not a correctable failure has occurred in the memory 11 is detected. Monitoring is always performed by hardware (step A101).

  Unless the hardware detects that a correctable fault has occurred in the memory 11 accessed by the central processing unit 10 (No in step A201), the operation of step A201 is repeated, and the access state of the memory 11 is monitored by hardware. Will continue. On the other hand, when it is detected by hardware that a correctable fault has occurred in the memory 11 accessed by the central processing unit 10 (Yes in step A201), the correctable fault has occurred in the hardware in which the fault has been detected. A process of registering the address of the memory area, for example, the address “A1” of the memory area in the table for managing information relating to the number of occurrences of correctable faults, that is, the fault occurrence count registration table 100 shown in FIG. 4 is controlled (step A202).

  In step A202, which forms the failure registration means (failure registration main step), the process of registering the address of the memory area where the correctable failure has occurred, for example, the address "A1" of the memory area in the failure occurrence number registration table 100 shown in FIG. By controlling with the BIOS 40 or the BMCFW 41, the correctable fault relating to the address of the memory area of the fault occurrence number registration table 100 that records the correctable fault occurrence count for each address of the memory area, for example, the address “A1” of the memory area The number of occurrences of is updated.

  FIG. 4 is a table showing an example of the table configuration of the failure occurrence count registration table 100. The valid display 101 indicates whether the registration record is valid, and the memory area address 102 for registering the memory area address where the correctable failure has occurred. The number of occurrences 103 for registering the number of occurrences of correctable faults is included at least.

  Here, the failure occurrence frequency registration table 100 shown in FIG. 4 is arranged in the non-volatile memory 12 used in the central processing unit 10 when the read / write operation is controlled by the BIOS 40 operating on the central processing unit 10. On the other hand, when the read / write operation is controlled by the BMCFW 41 operating on the baseboard management controller 30, it is arranged in the SRAM 32 used in the baseboard management controller 30.

  Note that the failure occurrence frequency registration table 100 shown in FIG. 4 shows an example in which the number of registered records of the memory area address where a correctable failure has occurred is up to 9, but the present invention sets the number of registered records in this example. The number is not limited to nine, and any number of registered records can be used as long as there is no hardware restriction for detecting a correctable fault.

  In the initial state, “0” indicating invalidity is set for each of the “valid bit-m (m = 1 to 9)” shown in the valid display 101 of the failure occurrence count registration table 100. . That is, when the value of “valid bit-m” shown in the valid display 101 is “0” indicating invalidity, “memory area address-m” of the memory area address 102 corresponding to the registration record and “number of occurrences 103” The counter-m ″ indicates invalid information. On the other hand, when “valid bit-m (one of m = 1 to 9)” of the valid display 101 is set to “1” indicating that the registration record is valid, it corresponds to the registration record. This indicates that “memory area address-m” of the memory area address 102 and “counter-m” of the number of occurrences 103 are set as significant information.

  In step A202, when registering the address of the memory area in which the correctable fault has occurred, for example, the address “A1” of the memory area, in the fault occurrence count registration table 100 in FIG. Since all “valid bit-m (m = 1 to 9)” of 101 are set to “0” indicating that the registration record is invalid, any “valid bit- m "For example," valid bit-1 "is rewritten to" 1 "indicating that it is valid. Further, as a registration record in the “valid bit-1” column, “memory area address-1” of the memory area address 102 is updated to the address of the memory area where the correctable failure has occurred, for example, the address “A1” of the memory area. The “counter-1” of the occurrence count 103 is incremented by 1 from “0” and updated to “1”.

  Thereafter, it is confirmed whether or not the number of failure occurrences of the address of the memory area where the correctable failure has occurred, for example, the address “A1” of the memory area has exceeded a predetermined threshold (step A203). If the number of failure occurrences of the address of the memory area, for example, the address “A1” of the memory area does not exceed the threshold value (No in Step A203), the process returns to Step A201, and the address of the memory area, for example, the address of the memory area ” The state of monitoring the occurrence of the next correctable fault for A1 "is continued.

  On the other hand, when the number of failure occurrences of the address of the memory area, for example, the address “A1” of the memory area exceeds the threshold (Yes in Step A203), the process proceeds to Step A102 and the OS operating on the central processing unit 10 To the address of the memory area, for example, the page (memory area address space) of the address “A1” of the memory area, is notified that the allowable number of failures has been exceeded. The OS on the central processing unit 10 that has received the notification closes the page relating to the address of the memory area where the correctable failure has occurred a number of times exceeding the threshold, for example, the page (memory area address space) of the memory area address “A1”. The process is executed, and the page is separated from the active system and isolated (step A102).

  Next, the update process of the failure occurrence number registration table 100 in step A202 will be described in more detail. When the address “A1” of the memory area in which the correctable failure is detected in step A201 is transferred in the initial state where there is no registration record in the failure occurrence number registration table 100, as described above, the valid display 101 is displayed. Any "valid bit-m", for example, "valid bit-1" is rewritten to "1" indicating validity, and the transferred memory area is transferred to "memory area address-1" of the corresponding memory area address 102 Address "A1" is stored, and "counter-1" of the number of occurrences 103 is incremented by +1 and set to "1".

  Thereafter, when the address “A1” of the memory area is transferred again as the address of the memory area in which the correctable fault is detected in step A201, first, the validity is displayed from the valid display 101 of the fault occurrence count registration table 100. Search for “valid bit-m” in which “1” is set. In this embodiment, for example, “valid bit-1” is set to “1”, so that “valid bit-1” is extracted, and then the registration record of “valid bit-1” is confirmed. Move to the operation. That is, it is confirmed whether or not the “memory area address-1” of the memory area address 102 registered in “valid bit-1” matches the address “A1” of the memory area transferred this time.

  In the present embodiment, since the “memory area address-1” of the memory area address 102 matches the address “A1” of the memory area transferred this time, the address “A1” of the memory area transferred this time. It is determined that “is already registered in the failure occurrence frequency registration table 100. Therefore, in order to register in the failure occurrence number registration table 100 that the second correctable failure has occurred at the address “A1” of the memory area, “counter-1” of the occurrence number 103 is incremented by +1. Update from 1 "to" 2 ".

  In other words, when a plurality of correctable failures occur at the address “A1” in the same memory area, the registered contents in the failure occurrence number registration table 100 are “valid bit−” of the valid display 101 when the first failure occurs. m “for example, an operation for setting“ valid bit-1 ”to a valid state“ 1 ”; an operation for registering the memory area address“ A1 ”in“ memory area address-1 ”of the corresponding memory area address 102; The operation of setting “counter-1” corresponding to the number of occurrences 103 to “1” is performed. On the other hand, when the second and subsequent failures of the address “A1” in the same memory area occur, only the operation of incrementing the “counter-1” of the corresponding occurrence count 103 by +1 is performed.

  If the address “A2” of the memory area different from the address “A1” of the memory area detected first is transferred as the address of the memory area where the next correctable failure is detected in step A201, "Valid bit-m (m = 1 to 9)" in which "1" indicating validity is set is searched from the valid display 101 of the failure occurrence count registration table 100 and set to "1". As for any of the “valid bit-m”, a case where the “memory area address-m” of the corresponding memory area address 102 does not match the address “A2” of the memory area transferred this time is new. It becomes registration operation.

  Therefore, “valid bit-i” in which “0” indicating invalidity is searched for among “valid bit-m (m = 1 to 9)” of the valid display 101, and the “valid bit- As described above, “i” is rewritten to “1” indicating validity, and the memory area address “A2” transferred this time is stored in “memory area address-i” of the corresponding memory area address 102. Then, “counter-i” of the number of occurrences 103 is incremented by +1 and set to “1”.

  Since a correctable failure has occurred at the address “A3” of a new memory area that is not registered in the failure occurrence number registration table 100, an effective display 101 is displayed in order to newly register in the failure occurrence number registration table 100. When “valid bit-i” in which “0” indicating invalidity is searched for among “valid bit-m (m = 1 to 9)”, “valid bit-m (m = 1 to 9)” is searched. 9) If all of "1" are set to "1" indicating validity and are full, the registration record that can be replaced is extracted from the valid registration records. Then, a new registration may be performed by replacing the registered record.

  For example, the “counter-j” having the smallest count value is detected from the “counter-m (m = 1 to 9)” of the number of occurrences 103 of each registered record, and the memory having the smallest number of occurrences is detected. The "memory area address-j" of the memory area address 102 detected as the area address is rewritten to the address "A3" of the newly registered memory area transferred this time, and the "counter-j" of the occurrence count 103 is changed to the first. It may be rewritten to “1” indicating the second time. In addition, when there are a plurality of memory area addresses with the lowest occurrence frequency, the memory area address with the lowest occurrence frequency may be selected as the replacement candidate from the youngest number side, or the oldest The memory area address with the smallest number of occurrences may be selected as the replacement candidate from the number side.

  Alternatively, although not described in the failure occurrence number registration table 100 of FIG. 4 as other replacement candidates, the most recent correctable failure occurrence date and time is registered in the failure occurrence number registration table 100 for each registered record. In other words, the memory area address with the oldest correctable failure occurrence date and time may be selected as a replacement candidate for the newly registered memory area address.

  Next, an example of a memory check operation performed during the start-up operation of the information processing apparatus using a special memory test having a predetermined test pattern will be described with reference to the flowchart of FIG.

  When an instruction to start up the information processing apparatus is issued (step B100), the BIOS 40 operating on the central processing unit 10 and the BMCFW 41 operating on the baseboard management controller 30 are provided in the nonvolatile memory 12 and the SRAM 32, respectively. The registered contents are confirmed with reference to the failure occurrence frequency registration table 100 in FIG. 4 (step B101). As a confirmation operation of the registered contents, first, it is checked whether or not all registered records in the failure occurrence number registration table 100 have been confirmed (step B102). If all of the registration records have not been checked yet (No in step B102), “valid bit-m (any of m = 1 to 9)” of the valid display 101 of the registration record to be checked next is displayed. Then, it is confirmed whether or not “1” indicating validity is set (step B103).

  If “1” indicating validity is not set (No in Step B103), the data is invalid, and the process returns to Step B102 to check the next registration record. On the other hand, when “valid bit-m (any of m = 1 to 9)” in the valid display 101 of the registered record is set to “1” indicating validity (Yes in step B103), the “valid” bit-m (one of m = 1 to 9) ”is initialized to“ 0 ”indicating invalidity, and“ memory area address-m ”of the memory area address 102 corresponding to the registration record is extracted (step B104) A special memory test as described above is performed on the address of the memory area indicated by the "memory area address-m" (step B105).

  Here, as described above, the address of the memory area indicated by the “memory area address−m” is a certain range of memory area address space as a page block unit. It will be implemented exhaustively for the area address space. Further, the special memory test performed in step B105 forming the memory test execution means (memory test execution step) is a test using a test pattern in which a correctable failure may occur. Specifically, As described above, not only for all “0” write and all “1” write, but also “0” write / read → “1” write / read → “0” write / read → “1” write / read “0”, “1” inversion write / read sequence such as “0x5555” write / read → “0xAAAA” write / read → “0x5555” “01 pattern”, “10 pattern” inversion, etc. This is a memory test including a write / read sequence.

  In this embodiment, in the special memory test, “valid bit-m (one of m = 1 to 9)” of the valid display 101 of the registered record is set to “1” indicating validity. Although the description has been given of the case where the present invention is applied to the address space of all the memory areas (that is, the address space of the memory area in which a correctable failure is detected), the present invention is not limited to this case. For example, for only the address space of the memory area that is in a page-blocked state, in other words, “valid bit-m (any of m = 1 to 9)” of the valid display 101 is “1” indicating that it is valid. Of the address space of the set memory area, only the address space of the memory area in which the count value of “counter-m (m = 1 to 9)” of the number of occurrences 103 exceeds a predetermined threshold value. You may make it implement.

  In addition, when there are a plurality of address spaces in a memory area to be subjected to a special memory test, the order of execution of the special memory test is sequentially indicated from the lowest number as “1”. The ordering is performed so as to be performed for the address space of the memory area where "" is set (that is, the address space of the memory area where the correctable failure is detected) or the address space of the memory area where the page is blocked. Anyway.

  Returning to the flowchart of FIG. 3, the special processing performed in step B <b> 105 is performed on the address space of the memory area indicated by a certain “memory area address−m” extracted from the failure occurrence frequency registration table 100 in step B <b> 104. The quality of the memory test execution result is determined (step B106).

  If no failure is detected as a result of the special memory test (No in Step B106), it is assumed that the address space of the memory area is in a normal state, and a fault is detected as the test result of the special memory test. In order to check the next registration record in the failure occurrence number registration table 100 without performing the registration operation in the memory test result registration table 200 of FIG. 5 for registering the detected memory area address, the process returns to Step B102. As a result, even if the page block state is set during the previous operation, after the information processing apparatus is restarted, the page block state is released and the OS can be returned to a usable state. Become.

  On the other hand, when a failure is detected as a result of the special memory test (Yes in step B106), the address space in the memory area is assumed to have failed, and the OS is not As a page blocking candidate that cannot be incorporated into the system, the BIOS 40 or BMCFW 41 updates the registration contents of the memory test result registration table 200 of FIG. 5 provided in the nonvolatile memory 12 or the SRAM 32 (step B107).

  FIG. 5 is a table showing an example of a table configuration of the memory test result registration table 200. The memory test result registration table 200 includes at least a valid display 201 indicating whether or not a registration record is valid, and a memory area address 202 for registering a memory area address in which a failure is detected. It is configured to include.

  Here, the memory test result registration table 200 shown in FIG. 5 is a non-volatile memory of the diagnostic function unit used in the central processing unit 10 when the read / write operation is controlled by the BIOS 40 operating on the central processing unit 10. On the other hand, when the BMCFW 41 operating on the baseboard management controller 30 controls the read / write operation, it is disposed in the SRAM 32 of the diagnostic function unit used in the baseboard management controller 30. Yes.

  Note that the memory test result registration table 200 shown in FIG. 5 is the case of the fault occurrence frequency registration table 100 shown in FIG. Unlike the above, the number of registered records is not limited to nine. In general, it is desirable that the number of records that can be registered in the memory test result registration table 200 in FIG. 5 is larger than that in the failure occurrence number registration table 100 in FIG.

  In an initial state in which an information processing apparatus is newly installed, all “valid bit-m (m = 1 to n)” shown in the valid display 201 of the memory test result registration table 200 are invalid for each registration record. “0” is set. That is, when the value of “valid bit-m” shown in the valid display 201 is “0” indicating invalidity, “memory area address-m” of the memory area address 202 corresponding to the registration record is invalid information. It is shown that. On the other hand, when “valid bit-m (any of m = 1 to n)” of the valid display 201 is set to “1” indicating that it is valid for the registration record, it corresponds to the registration record. This indicates that “memory area address-m” of the memory area address 102 is set as significant information.

  Note that “valid bit-m (m = 1 to n)” shown in the valid display 201 of the memory test result registration table 200 indicates invalid only when a special operation such as an erasing operation by the operator is performed. It can be set to “0”, and is not set to “0” indicating invalidity every time the information processing apparatus is started up. Also, it is automatically determined by determination of hardware, BIOS 40 or BMCFW 41 If a failure is detected as a result of a special memory test that is performed when the information processing apparatus is started up without being erased, the memory capacity that can be used as a system reaches a certain predetermined amount. Until then, it will be accumulated sequentially.

That is, the memory test result registration table 200 in FIG. 5 is almost the same as the failure occurrence number registration table 100 in FIG. 4, but mainly differs in the following points.
(1) The number of records that can be registered in the memory test result registration table 200 is generally larger than that in the failure occurrence number registration table 100 of FIG.
(2) The registered content of the memory test result registration table 200 in FIG. 5 is not erased unless a specific operation (that is, an erase operation by the operator) is performed. That is, “valid bit-m (m = 1 to n)” shown in the valid display 201 of the memory test result registration table 200 in FIG. 5 does not become “0” indicating invalidity unless a specific operation is performed.
(3) The “valid bit-m (m = 1 to n)” shown in the valid display 201 of the failure occurrence count registration table 100 in FIG. 4 is invalidated in step B104 in FIG. By setting “0” to indicate, all “valid bit-m (m = 1 to n)” are set to “0” indicating invalidity, but on the other hand, the memory test result registration table of FIG. The “valid bit-m (m = 1 to n)” shown in the valid display 201 of 200 is not automatically set to “0” indicating invalidity by the determination of the hardware, the BIOS 40 or the BMCFW 41.

  In step B107, when the registration process to the memory test result registration table 200 of FIG. 5 is performed with respect to the address of the memory area where the failure is detected, for example, the address “A1” of the memory area, in the initial state, as described above, the valid display 201 Since all “valid bit-m (m = 1 to n)” are set to “0” indicating that the registration record is invalid, any “valid bit-m” in the valid display 201 is displayed. For example, “valid bit-1” is rewritten to “1” indicating that it is valid. Further, as a registration record in the “valid bit-1” column, “memory area address-1” of the memory area address 202 is used as a page blocking candidate to prevent the OS that is currently started from being incorporated into the system in a special memory test. The address of the memory area where the failure is detected, for example, the address “A1” of the memory area is updated.

  Further, the memory area address space in which the failure is detected (that is, the memory area address space in which the page is blocked in the flowchart of FIG. 2 or the memory area address space in which the correctable failure has occurred) The detected memory area address space) is not limited to a page block candidate for being kept in an isolated state without being incorporated into the system, but also as a failure information holding means (fault information holding step). In order to effectively perform the fault diagnosis of the space, for example, the memory 11 or the memory 31 uses the memory address and data pattern when an error occurs in the special memory test as information for failure analysis. In the case of a DIMM, various specifications of the DIMM are stored. Is OM region SPD (Special Presence Detect), or the special memory test firmware held in the nonvolatile memory 12 or SRAM32 such diagnostics unit stored (step B 108).

  It should be noted that the test result of the special memory test may be retained only by the DIMM SPD, the nonvolatile memory 12 or the SRAM 32 of the diagnostic function unit, or both the DIMM SPD, the nonvolatile memory 12 or the SRAM 32. May be. The DIMM SPD, the nonvolatile memory 12 and the SRAM 32 can hold a plurality of test results (memory addresses and data patterns). The held memory address and data pattern are used at the time of failure analysis. Thereafter, in order to check the next registration record in the failure occurrence count registration table 100, the process returns to Step B102.

  When it is determined in step B102 that all the registered records have been checked (Yes in step B102), the registered contents of the memory test result registration table 200 in which the results of the special memory test are registered are confirmed. Then, it is checked whether or not there is a registration record set to “1” indicating that “valid bit-m (m = 1 to n)” of the valid display 201 is valid (step B109). .

  If there is a registration record in which “valid bit-m (m = 1 to n)” of the valid display 201 is set to “1” (Yes in step B109), the OS being started up is As a page blocking means (page blocking step), the memory area address space set in the “memory area address-m” of the corresponding memory area address 202 is set to the page blocking state, so that the current startup The OS is prevented from being incorporated into the system, and the memory area address space is isolated so that it cannot be used during operation after startup (step B110).

  On the other hand, the memory area address space set in “memory area address-m” of the memory area address 202 in which “valid bit-m (m = 1 to n)” in the valid display 201 is set to “1”. For the other memory area address spaces, the OS is incorporated into the system at the start-up as a normal return means (normal return step) so that the memory area address space can be used during operation after the start-up. Make it possible. That is, for the memory area address space that is not registered in the memory test result registration table 200, even if the page block state was set during the previous operation in the flowchart of FIG. As a result of the memory test, since no failure was detected, it is considered that the system has returned to a normal state, and the OS is incorporated into the system and set to a usable state at this start-up.

  By performing a special memory test as described above, when the information processing device is started up, the memory area address space that has been page-blocked during the previous operation or the memory area address space that has detected a correctable fault In the case where a correctable fault is reproduced in a special memory test, the memory area address space is blocked, and detailed data (memory Address and test pattern) and can be used effectively for failure analysis.

(Explanation of effect of embodiment)
As described in detail above, the following effects are obtained in the present embodiment.

  The first effect is that the memory area address space in which the page is temporarily blocked can be automatically reused particularly when the data on the memory is intermittently stacked / fixed to a certain value. It is to become.

  The second effect is as follows. Recent embedded information processing devices already have a page-blocking function or are in the process of being incorporated in the future. However, the memory of embedded information processing devices is not large in capacity but mostly small in capacity. It is. In addition, the page blocking function is also implemented for a small-capacity RAM such as an SRAM. When page blocking is performed for such a small-capacity memory, the usable memory capacity is greatly reduced, and the system operation may become unstable. In the present invention, every time the system is started up, it can be set so as not to block the page as much as possible, so that an effect of stabilizing the system operation can be obtained.

  The third effect is that a memory address and a data pattern when an error (failure) is detected in a special memory test performed at start-up are displayed as SPD (Special Presence Detect) of DIMM (Dual Inline Memory Module) of the memory 11 or the memory 31. ), Since it is held in the nonvolatile memory 12 of the diagnostic function unit, SRAM (Static Random Access Memory) 32, etc., even if the failure is not reproduced in the reproduction test to be performed later for failure diagnosis, it is held in detail. It is easy to perform failure analysis based on the failure state.

  The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that the embodiments described above are merely illustrative of the present invention and do not limit the present invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

10 Central Processing Unit (CPU)
11 Memory 12 Non-volatile memory 20 Chipset 30 Baseboard Management Controller (BMC)
Controller)
31 Memory 32 SRAM
40 BIOS (Basic Input / Output System)
41 BMCFW (BMC Firmware)
100 Fault occurrence count registration table 101 Valid display 102 Memory area address 103 Occurrence count 200 Memory test result registration table 201 Valid display 202 Memory area address

Claims (10)

  A memory test apparatus provided in the information processing apparatus for testing the memory of the information processing apparatus, and when detecting that a correctable failure has occurred in the memory during operation of the information processing apparatus, A failure registration unit that registers a memory area address space including a memory address in which the correctable failure has occurred as a failed page, and is registered by the failure registration unit during the subsequent startup operation of the information processing apparatus. Further, a memory test execution means for executing a special memory test having a predetermined test pattern for the memory area address space corresponding to the failed page, and the special memory test executed by the memory test execution means As a result of the operation, a failure is detected in the memory area address space corresponding to the failed page. If not, the memory area address space corresponding to the failed page is incorporated into the system as a normal memory area address space and returned to a state that can be used by the operating system (OS) after startup. A memory test apparatus comprising at least normal return means.   If a failure is detected in the memory area address space corresponding to the failed page as a result of the special memory test performed by the memory test execution means, the memory area address space corresponding to the failed page Failure information that holds, as information for failure analysis, a page blocking means for setting a page blocking state that cannot be used by the OS after the OS is started, and a test pattern and memory address in which a failure has occurred in the special memory test The memory test apparatus according to claim 1, further comprising a holding unit.   When a failure is detected as a result of executing the special memory test, the memory test execution means stores information on the memory area address space corresponding to the page where the failure has been detected in a memory test result registration table. The registered page, and the page block means sets the page block state based on information on the memory area address space corresponding to the failed page registered in the memory test result registration table. 2. The memory test apparatus according to 2.   The fault information holding means holds a test pattern and a memory address in which a fault has occurred in the special memory test in a nonvolatile memory or SRAM (Static Random Access Memory) used for fault diagnosis, or the memory 4. The memory test according to claim 2, wherein the memory test is held in a SPD (Special Presence Detect) which is a ROM area for storing the specifications of the DIMM when the memory is a DIMM (Dual Inline Memory Module). apparatus.   When the failure registration unit detects that a correctable failure has occurred in the memory during operation of the information processing apparatus, the failure registration unit stores a memory area address space including the memory address in which the correctable failure has occurred. Register as a failure page in the failure occurrence number registration table together with the number of correctable failure occurrences in the memory area address space, and the number of correctable failure occurrences registered in the failure occurrence number registration table exceeds a predetermined threshold 5. The memory area address space is set to a page blocking state that cannot be used by the OS until the information processing apparatus is restarted thereafter. Memory test equipment. A memory test method in a memory test apparatus provided in the information processing apparatus for testing a memory of the information processing apparatus, wherein a correctable fault is detected in the memory during operation of the information processing apparatus when the, and fault registration step of registering the memory area address space in which the correctable fault contains memory address generated as a failure page, during start-up operation of thereafter of the information processing apparatus is registered A memory test execution step for performing a special memory test having a predetermined test pattern for the memory area address space corresponding to the failed page, and the special memory test performed in the memory test execution step. As a result of the above, the memory area address space corresponding to the failed page If no harm is detected, the memory area address space corresponding to the failed page can be incorporated into the system as a normal memory area address space and used by a booted OS (Operating System). And a normal return step for returning to the state.


  When a failure is detected in the memory area address space corresponding to the failed page as a result of the special memory test performed in the memory test execution step, the memory area address space corresponding to the failed page Failure information that holds, as information for failure analysis, a page blocking step for setting a page blocking state that cannot be used by the OS after starting up, and a test pattern and memory address in which a failure has occurred in the special memory test The memory test method according to claim 6, further comprising a holding step.   In the memory test execution step, when a failure is detected as a result of executing the special memory test, information on the memory area address space corresponding to the failure occurrence page where the failure is detected is stored in a memory test result registration table. In the page block step, the page block state is set based on information on the memory area address space corresponding to the failed page registered in the memory test result registration table. The memory test method according to claim 7.   In the fault information holding step, a test pattern and a memory address in which a fault has occurred in the special memory test is held in a nonvolatile memory or SRAM (Static Random Access Memory) used for fault diagnosis, or 9. The memory according to claim 7, wherein when the memory is a DIMM (Dual Inline Memory Module), the memory is held in a SPD (Special Presence Detect) which is a ROM area for storing the specifications of the DIMM. Test method.   10. A memory test program, wherein each step of the memory test method according to claim 6 is implemented as a program executable by a computer.

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