JP3314719B2 - Flash EEPROM and its test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEP.
ROM (Electrically Erasable and Programmable Read)
Only Memory) and its test method.

[0002]

2. Description of the Related Art EEPROM is a non-volatile memory, which is widely used because the memory does not evaporate and the rewriting is relatively easy even when the power is turned off, but the number of rewriting is limited. There is. Because of this problem, when using an EEPROM, it is common to test the EEPROM and confirm that it is in a normal state before using the EEPROM.

If a cyclic code for correcting a code error (or for detecting a code error) is generated for data stored in an EEPROM and the cyclic code is stored in the EEPROM, testing of the EEPROM can be easily performed. It can be carried out. It is also desirable that even if a part of the EEPROM is destroyed, only the healthy part can be used if the remaining part is healthy. For this reason, the entire memory area of the EEPROM may be divided into a plurality of blocks so that which block of the EEPROM has a defect can be easily determined based on the test result.
The test method for PROM was not so.

Conventionally, when writing data to a flash EEPROM, one cyclic code is generated for all blocks without generating a cyclic code for each block. Also, the flash EEPROM does not have a determination unit for determining whether data is written or not.

[0005]

Therefore, the conventional flash EEPROM has the following problems. First
The problem is that flash EEPROM with data written
There is a risk of erroneously testing all blocks of the OM and corrupting the data being written. The reason is Flash EE
After performing the PROM test and confirming the normality, the data is written. After the data is written, it is necessary to ensure that the data is not damaged. This is because the test program cannot automatically judge whether or not it is not.

[0006] The second problem is that a flash EEPROM is used.
Means that the time required for generating a cyclic code at the time of data writing or data rewriting becomes longer as the capacity becomes larger. The reason is that the conventional method does not generate a cyclic code for each block, but generates one cyclic code for all blocks. Therefore, it is necessary to generate a cyclic code from the data of all the blocks at the time of data writing or data rewriting.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the conventional method, to prevent accidental destruction of data in a written EEPROM, and to prevent a local defect from occurring even when the EEPROM has a local defect. It is an object of the present invention to provide a flash EEPROM and a test method thereof in which only a certain portion can be excluded and another normal portion can be used.

[0008]

For this reason, in the flash EEPROM of the present invention, data to be stored is decomposed into a plurality of data blocks, a cyclic code is generated for each data block, and each data block and each cyclic code are assigned to each data block. A flag is provided that is stored in a memory block and indicates whether data is written in each memory block.

That is, the flash EEPROM of the present invention
The memory area of M is divided into a data storage unit into which data is written by being divided into block units, and a block unit corresponding to the block unit in the data storage unit. Each block stores data in a corresponding block in the data storage unit. A block write completion flag in which information indicating whether or not the data has been written is written, and a correction for correcting a code error of data stored in a corresponding block of the data storage unit when the writing of the block is completed. Management unit composed of a block cyclic code unit in which a cyclic code for use (or detection for detecting a code error) is written, and a flag indicating that data is written in all blocks in the data storage unit (Hereinafter referred to as the all-block data write completion flag) and data in any block in the data storage unit. Flag indicating that data is not stored (hereinafter, referred to all block data without flag) and a write detector to be stored.

[0010] The step of writing data to the flash EEPROM includes the step of writing data to the flash EEPROM.
In the initialization state where no data is written to any of the blocks, the all-block no-data flag indicating that no data is stored in any of the blocks and the fact that data has been written to all the blocks Resetting the all-block data written flag shown, and determining that writing is not possible if the all-block data written flag is set when writing data to the flash EEPROM;
When writing data to the flash EEPROM, if the all-block data absent flag is reset, the flag is set; A code generation step;
Information indicating whether data is written in the block is written. The block-based data is written in a block in which a block write completion flag is not set, and the cyclic code generation is performed in a block cyclic code unit corresponding to the block. A writing step of writing the cyclic code generated in the step, and the block writing of the block in which the writing of the cyclic code is completed in the writing step .
A step of setting the completion flag write attempts, when the block write completion flag is set in all the blocks, and a step of setting the entire block data written flag.

[0011] A switch for testing this flash EEPROM .
Step checks the all block data no flag
The flag check step and the all block data no flag
If reset, the flash EEPROM
There is no write over the entire M memory area.
After the test is completed, all block data
The test results (O
Reporting K or NG) and all block data
If the None flag is set, the block
Check the write completion flag and if this flag is set
Test only for the block that
Data is read out, and a cyclic code is read from the read data.
And the generated cyclic code and the block cyclic code
Compare with the cyclic code read from the encoder,
If the results do not match, the test result of the block is NG.
Reporting.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a flash EEP of the present invention.
FIG. 1 is a block diagram showing a ROM and a peripheral portion thereof, wherein reference numeral 1 denotes a writing device, reference numeral 2 denotes a flash EEPROM mounting device, and this mounting device 2 is a flash EEPROM.
3, data receiving means 4, write control means 5, read control means 6, and test means 7. The peripheral device includes a host device 8 and an input / output device 9.

The test means 7 comprises a processor controlled by a program, and comprises a test control section 71, a test program 7
It is displayed as 2. The test program 72 is started depending on whether the operator gives a command from the input / output device 9, a command from the host device 8, or a command related to reading from the reading control means 6. The test result is reported to the host device 8 or displayed on a display unit (not shown) of the input / output device 9.

The memory area of the flash EEPROM 3 includes a data storage section (a data storage section in units of blocks) 31,
It is divided into a data management unit (a data management unit for each block) 32 and a write determination unit 33. The data storage unit 31 is divided into N (31 to 31N) unit blocks (N is an arbitrary natural number), and the data management unit 32 is divided into N unit blocks 321 to 32N. 311 and 321, 3
12 and 322,..., 31N and 32N are blocks corresponding to each other.

Blocks 321, 322,..., 3
2N each have two parts, 3210, 3211;
, 32N0, 32N1, 3210, 3220,..., 32N0 are block write completion flags, respectively, 3211,
, 32N1 are block cyclic code units.

The writing device 1 is a flash EEPROM.
3, the data to be written is divided into blocks and sent to the data receiving means 4, where the data is temporarily stored. The write control unit 5 calculates a cyclic code from the data in block units in the data receiving unit 4 and stores the data in block units in the data receiving unit 4 in the block of the selected block number in the data storage unit 31 (this selection). For example, it is assumed that the block 312 is selected), and the calculated cyclic code is stored in the block (that is, the block of the data management unit 32 corresponding to the block storing the data of the data storage unit 31 (for example, the block 312)). The data is written to the block cyclic encoder 3221 of the block 322) corresponding to the block 312. Then, the block write completion flag 3220 of the block 322
(That is, the logic of the flag is set to “1”). The write addresses in the blocks 312 and 322 are generated by the write control means 5.

The read control means 6 selects a selected block in the data storage unit 31 (this selection will be described later).
For example, block 311 is selected). The read address in the block 311 is generated by the read control means 6. However, writing is always performed for one entire block at the same time. In the reading, the selected data in the block is read, but since the present invention is only concerned with reading for testing,
In that case, the data of the entire selected one block is always read. In the case of reading for a test, the test program 72 is started. The processing executed by the test means upon activation of the test program 72 will be described later.

The write judging section has two flags. The first flag is an all-block data absence flag. When this flag is in a reset state (logic “0”), it indicates that data is not written in any block in the data storage unit 31. Is in the set state (logic "1"), it indicates that data is written in any of the blocks in the data storage unit 31. The second flag is an all-block data written flag. When this flag is in a reset state (logic “0”), it indicates that no data is written in any block in the data storage unit 31. When this flag is set (logic "1"), it indicates that data is written in all blocks in the data storage unit 31. Therefore, when no data is written in the flash EEPROM in the initial state, the all block data no flag, the all block data written flag, and the all block write completion flag are reset.

Hereinafter, a test of the flash EEPROM of the present invention will be described. FIG. 2 is a flowchart showing a process of writing data to the flash EEPROM 3 in the device shown in FIG. Flash EEP of the present invention
Before writing to the ROM, data for the test is prepared in advance. Hereinafter, the write operation will be described with reference to FIGS.

Before step A1 in FIG. 2, it must be determined whether writing to the ROM 3 is possible. Although this determination process is not shown in FIG. 2, the write determination unit 33 checks the all-block write completion flag, and if the flag is set (if the logic of the flag is “1”), the ROM 3 Since data has been written to any of the blocks, indicating that there is no room for new writing, it is necessary to erase data in any of the blocks and then perform new writing. Therefore, the data of the block storing the data that is no longer used is erased and new data is written therein, but this processing is omitted here because it is not directly related to the test.

In step A1, one block of data to be written is received by the data receiving means 4. The writing control means 5 creates a cyclic code for one block of data received by the data receiving means 4 (step A).
2). Next, the block write completion flags 3210, 3220,..., 32N0 of the data management unit 32 are checked in numerical order, the first number (for example, 3220) in which this flag is reset is detected, and the corresponding number is detected. The data of the data receiving means 4 is written into the number of the number data storage unit 31 (the number corresponding to 3220 is 312) (step A3), and the generated cyclic code is stored in the number of the data storage unit 31 (312 in this example). Is written to the cyclic code part of the number (3221) corresponding to
4).

When the step A4 is completed, the write completion flag of the number (3220 in this example) is set, and if the all block data absence flag of the write judging unit 33 is in a reset state at this time, it is set (step S4). A4) The process proceeds to step A6. In step A6, when checking the block write completion flags 3210, 3220,..., 32N0 of the data management unit 32 in step A3, a case is encountered where it is detected that any tag is set. This means that the determination as to whether or not the writing of all blocks has been completed is YES in step A6.
3 is set to an all block data write completion flag.

If the determination in step A6 is NO, the process proceeds to step A8. If the determination in step A8 is YES, the writing is terminated. If the determination is NO, the process returns to step A1. 4 to receive. In the writing in the initial state, flash EEPROM
Since the amount of data to be written to all the blocks of M is prepared as the write data, after writing to the last block and executing step A5, the determination in step A6 is YE.
In step S7, the process is terminated through step A7. At this time, the determination in step A8 is also YES.

FIG. 3 is a flowchart showing the flow of processing in the test method of the present invention. The test method of the present invention will be described with reference to FIGS. The test control unit 71 of the test means 7 starts the test program 72 when receiving the test start command from the host device 8 or the input / output device 9. The test program 72 checks the all block data absent flag of the write judging section 33 through the read control means 6 (steps B1 and B2). If the flag is in a reset state, data has been written to the flash EEPROM 3 anywhere. Then, the process goes to step B3 to test all areas of the ROM, to test whether or not the data has been written anywhere, and to leave the all block data absence flag in a reset state (step B4). The result is reported to the host device 8 or the input / output device 9 (steps B5, B12, B1).
3). The test result is expressed as OK or NG, and the input / output device 9
Is reported on the display unit.

If the all-block data no flag is set, it indicates that data has been written to any of the blocks, and it is checked whether the data of the written block has been correctly stored. I do. The test of the block to which no data is written is omitted. That is, the process proceeds to step B4, where the block write completion flags 3210, 3220,.
N0 is read out in numerical order. For the block in which the read block write completion flag is in the reset state (the determination in step B7 is NO), the test is omitted, and the process proceeds to step B11.

For the block in which the block write completion flag is set, the data of the corresponding block (for example, block 311) in the data storage unit 31 is read, and a cyclic code for this data is generated (step B8). The generated cyclic code and a corresponding block cyclic code unit (in this example, block cyclic code unit 3211)
(Step B9). If the results of the comparison do not match (the determination in step B10 is NO), a test result NG is reported in step 13, and then the use of the data of this block is prohibited. In some cases, the use of the entire flash EEPROM may be prohibited.

If the determination in step B10 is YES, the process moves to step B11 to determine whether all blocks have been executed. In the example shown in FIG. 1, since the number of the last block write completion flag is 32N0, the block write completion flag 32N0 is read in step B6, and when the process of step B11 is started for the block,
The determination is YES, the process moves to step B12, the test result is reported, and the test ends.

[0028]

As described above, according to the present invention, the write judgment unit 33 is provided in the flash EEPROM 3,
In addition, since a block write completion flag is provided for each block of the data storage unit 31, this flash EE
Along with the state of data writing throughout the PROM,
The state of data writing of each block is clearly recognized by the test program 72, and there is no danger of accidentally destroying written useful data, and unnecessary testing is not performed.

The cyclic code corresponding to the data of each block of the data storage unit 31 is changed to the block cyclic code unit 3 of the corresponding block of the data management unit 32.
, 32N1, the test for judging the normality of the stored data can be executed easily and without affecting the life of the flash EEPROM. In addition, since a cyclic code is not generated for all data stored in a flash EEPROM as in the related art, the time required for generating the cyclic code can be reduced, and the broken portion of the flash EEPROM can be determined based on test results. There are effects such as being able to be limited.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a flash EEPROM of the present invention and a peripheral portion thereof.

FIG. 2 is a flowchart showing a writing process of the flash EEPROM of FIG. 1;

FIG. 3 is a flowchart showing a test process of the flash EEPROM of FIG. 1;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 writing device 2 flash EEPROM mounting device 3 flash EEPROM 4 data receiving means 5 writing control means 6 reading control means 7 testing means 8 host device 9 input / output device 31 data storage unit 32 data management unit 33 write determination unit 71 test control unit 72 , 32N Each block of the data storage unit 321, 322, ..., 32N Each block of the data management unit 3210, 3220, ..., 32N0 Block write completion flag 3211, 3221, ... .., 32N1 block cyclic code section

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 16/02 G01R 31/28 G06F 12/00 G06F 12/16

Claims (5)

(57) [Claims] 1. A flash EEPROM (Electrically)
A data storage unit provided in a memory area of an Erasable and Programmable Read Only Memory and divided into blocks to which data is written; a data storage unit provided in a memory area of the flash EEPROM and a block unit in the data storage unit And a block write completion flag in which information indicating whether or not data has been written in the corresponding block in the data storage unit is written, and each block has been written. And a block cyclic code unit to which a cyclic code for correction (or detection for detecting a code error) for correcting a code error of data stored in a corresponding block of the data storage unit is written. A data management unit, provided in a memory area of the flash EEPROM; A flag indicating that data has been written to all blocks in the data storage unit (hereinafter referred to as an all-block data written flag) and indicating that no data has been stored in any block in the data storage unit A flash EEPROM, comprising: a write determination unit in which a flag (hereinafter, referred to as an all block data absence flag) is stored; and a unit for accessing the flash EEPROM in units of blocks. 2. The flash EEPROM according to claim 1, wherein:
, Data receiving means for receiving and temporarily storing data to be written out of a memory area of the flash EEPROM, writing control means for writing data to the memory area of the flash EEPROM, and reading data from the memory area of the flash EEPROM A flash EEPROM comprising: read control means; and test means for testing a memory area of the flash EEPROM. 3. The flash EEPROM according to claim 2, wherein
In the flash EEPROM, the test means includes a test program and a test control unit for executing the test program. 4. In a flash EEPROM test method, in an initialization state in which no data is written in any block of the flash EEPROM, no block data indicating that no data is stored in any block is present. Resetting a flag and an all-block data written flag indicating that data has been written to all blocks; and when the all-block data written flag is set when writing data to the flash EEPROM. Is a step of determining that writing is not possible; a step of setting the all-block data absence flag when the data is written to the flash EEPROM if the flag is reset; dividing the data to be written into blocks; A cyclic code generation step of generating a cyclic code for data in a block unit, and information indicating whether data is written in the block is written in the block in which a block write completion flag is not set. And writing the cyclic code generated in the cyclic code generation step to a block cyclic code unit corresponding to the block. Writing of the cyclic code is completed in this writing step.
Said set block write completion flag <br/> Tosuru step of the block, when the block write completion flag is set in all the blocks, the step of setting the entire block data written flag, the flash EEPROM A test step for testing the performance of the flash EEPROM. 5. The flash EEPROM according to claim 4, wherein :
In the test method of (1), the testing step includes a flag checking step of checking the all-block data absence flag, and that when the all-block data absence flag is reset, writing does not exist in the entire memory area of the flash EEPROM. performed to confirm the test, after the test, in the state of resetting all the block data without flag, a step of reporting test results (OK or NG), when the entire block data without flag is set, Inspect the block write completion flag , perform a test only on the block for which the flag is set, read data of the block, generate a cyclic code from the read data, and generate the generated cyclic code; the ratio of the cyclic code read from the block cyclic code portion And a method of testing a flash EEPROM, characterized in that in the case of the results mismatch of the comparison and a step of reporting the test results of the block as NG.