JP2008090969A - Debugging system of redundancy operation program and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a debugging system which can debug a redundancy operation program without using a real device of an IC test device and in which its operation can be confirmed simply and quickly. <P>SOLUTION: The debugging system of the redundancy operation program 109 performs fail relief operation of a device 104 to be tested, and is provided with a fail information informing means 11 informing fail information including an address of a virtual defective cell to the redundancy operation program 109 in accordance with request from the redundancy operation program 109, a relief pattern receiving means 12 receiving relief pattern data operated by the redundancy operation program 109, and an output means 13 outputting at least the relief pattern data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a debugging system and program for a redundancy calculation program that generates data for relieving a failure of an IC having a spare circuit therein.

  A spare memory cell (spare) is prepared for an IC such as a memory device which is a device under test (DUT), and a failure is detected when a failure (fail) is detected in the test by the IC test apparatus. By replacing the cell with a spare cell, the defect is relieved. A unit that creates data necessary for such defect repair is called a redundancy arithmetic unit (redundancy unit: RDU).

  FIG. 4 is a diagram for explaining an example of a conventional IC test apparatus, and FIG. 5 is a conceptual diagram for simply explaining a DUT memory cell. The IC test apparatus 100 includes a fail detection apparatus 101, a redundancy calculation apparatus (hereinafter referred to as RDU 102), and a control unit 103.

  The fail detection apparatus 101 detects a failure (failure) of a memory cell included in a device under test (hereinafter referred to as DUT 104), and sends fail information to the RDU 102. A DUT 104 shown in FIG. 5 is a memory device, and a memory cell is divided into a plurality of cell arrays 120. Each cell array 120 is provided with a column spare 121 and a row spare 122 as an example of a spare cell. The fail detection device 101 searches each cell of the cell array 120 in order, and if the read / write test fails, it is detected as a defective cell 123.

  The RDU 102 performs a process called redundancy calculation (failure repair calculation) in order to create data necessary for defect repair of the DUT 104 based on the fail information sent from the fail detection apparatus 101.

  In the RDU 102, a fail memory 105 for storing fail information sent from the fail detecting device 101, an FPGA 106 (Field Programmable Gate Array: programmable LSI) for accessing the fail memory 105, and a redundancy CPU (hereinafter referred to as RDC 107). .), A memory 108 is provided. The redundancy calculation program 109 and the redundancy library 110 for controlling the FPGA 106 are read from the memory 108 and operated by the RDC 107.

  The fail information stored in the fail memory 105 is mainly the address of a defective cell, but also includes DUT information (DUT identifier) and page information (memory page identifier). The redundancy calculation program 109 drives the FPGA 106 via the redundancy library 110 and reads fail information of a defective cell from the fail memory 105. The FPGA 106 has a function of reading / writing fail information from / to an arbitrary address in the fail memory. Further, when reading, a function of sequentially searching the matrix memory addresses in the X direction or the Y direction (a function of reading in the order of addresses) is provided.

  The redundancy calculation program 109 assigns each defective cell detected from the DUT 104 in combination with a column spare and a row spare of a spare circuit, and determines whether or not all failures can be relieved. If it is determined that the repair is possible, the pattern of the assigned replacement cell 124 (see FIG. 5) (a set of a plurality of replacement information, hereinafter referred to as a repair pattern) is output to the control unit 103.

  The control unit 103 cuts a predetermined pattern in the DUT 104 using a laser or the like according to the sent relief pattern, and replaces a defective cell with a spare cell. Note that the DUT 104 includes a spare memory cell (spare) for repairing a defect.

Conventionally, various proposals have been made for the redundancy calculation device. For example, in Japanese Patent Laid-Open No. 2002-367396 (Patent Document 1), after a spare is assigned to a fail, it is replaced with a spare on the opposite side, and the released spare is assigned to an unrelieved fail, thereby improving the repair rate. Possible redundancy computing devices have been proposed.
JP 2002-367396 A

  However, the redundancy calculation program is not necessarily general-purpose, and needs to be specialized for the DUT that the user of the IC test apparatus 100 tests. This is for optimizing the algorithm of how to allocate spare cells to a specific defective cell group and effectively using spare cells to relieve even one DUT and make it non-defective. Therefore, debugging of a redundancy operation program is an important issue.

  Conventionally, the redundancy arithmetic program is debugged in the following procedure. First, modify and compile the source program of the redundancy calculation program. The actual IC test apparatus 100 is used to write a virtual defective cell bit pattern in the fail memory 105 (see FIG. 4). Then, the redundancy calculation program 109 is read into the memory 108 and executed, and the repair pattern is calculated by the above-described setup to check whether or not the expected data has been created. Needless to say, in this debugging operation, the replacement processing to the DUT 104 by the control unit 103 is not performed.

  Thus, conventionally, the redundancy operation program 109 cannot be debugged without the actual device of the IC test apparatus 100. However, the IC test apparatus 100 must also perform actual test work, and also requires debugging time for other programs such as the redundancy library 110, and ensuring sufficient usage time for debugging the redundancy operation program 109 is not possible. difficult. In addition, in an actual machine, functions that can be used are limited due to a hardware failure or the like, and the redundancy arithmetic program 109 may not be debugged. Further, a program for writing a bit pattern of a defective cell to the fail memory 105 is required, and management becomes difficult as the number of test items increases.

  Therefore, an object of the present invention is to provide a debugging system that enables debugging of a redundancy calculation program and can easily and quickly confirm the operation without an actual IC test apparatus.

  In order to solve the above problems, a typical configuration of a debugging system for a redundancy operation program according to the present invention is a debugging system for a redundancy operation program that performs a fail-relief operation of a device under test, and a request from the redundancy operation program A failure information notifying means for notifying the redundancy calculation program of fail information including the address of the virtual defective cell in response to the error, a relief pattern receiving means for receiving the relief pattern data calculated by the redundancy calculation program, and outputting at least the relief pattern data And an output means.

  According to the above configuration, the redundancy calculation program can be operated and the calculation result can be confirmed without an actual IC test apparatus. Therefore, it is not necessary to secure the use time of the actual machine, debugging can be performed easily and quickly, and the degree of completion can be increased before operating with the IC test apparatus. Further, since the actual machine usage time is not occupied, the actual machine can be used for original tests and debugging of other programs, and the limited use time of the actual machine can be effectively utilized.

  Furthermore, it comprises a virtual fail memory whose area is secured on the memory of the host computer, fail information writing means for writing fail information to the virtual fail memory, and a virtual driver for reading from and writing to the virtual fail memory. The notification means may read the fail information from the virtual fail memory via the virtual driver and notify the redundancy calculation program in response to a request from the redundancy calculation program. According to the said structure, the structure similar to the hardware structure of a real machine can be virtually constructed | assembled with a program.

  The debug system further includes a fail information database for storing fail information corresponding to the device under test targeted by the redundancy calculation program. When a request is received from the redundancy calculation program, the fail information database is referred to for fail information. And fail information may be notified to the redundancy calculation program. According to the above configuration, only the interface (API: Application Program Interface) accessed by the redundancy calculation program can be made the same as that of the actual machine, and the configuration of other parts can be greatly simplified.

  The fail information notifying unit may further notify the fail information according to a specified address range, address search direction, or presence / absence of compression in response to a request from the redundancy calculation program.

  A typical configuration of a program according to the present invention is a program for debugging a redundancy calculation program for performing fail-relief calculation of a device under test, and in response to a request from the redundancy calculation program, an address of a virtual defective cell is set. Any program that causes a computer to execute the process of notifying the redundancy calculation program of the included fail information, the process of receiving the relief pattern data calculated by the redundancy calculation program, and the process of outputting at least the relief pattern data may be used. According to the above configuration, the debugging system according to the present invention can be realized as a program operating on a computer. The program according to the present invention may be recorded on a computer-readable recording medium and distributed.

  According to the present invention, the redundancy calculation program can be operated and the redundancy calculation program can be debugged easily and quickly without an actual IC test apparatus.

[Example 1]
A first embodiment of a debugging system for a redundancy calculation program according to the present invention will be described. FIG. 1 is a diagram for explaining a main part of the debug system, and FIG. 2 is a diagram for explaining an overall configuration of the debug system according to the first embodiment. Portions overlapping with the above background art will be assigned the same reference numerals and description thereof will be omitted.

  The debug system 10 shown in FIG. 1 is realized as a program that runs on a host computer. The redundancy calculation program 109 compiled by the compiler 111 is read into the main memory of the host computer, and is operated together with the debug system 10 by the CPU of the host computer.

  In the debug system 10 according to the present embodiment, the redundancy calculation program 109 is connected to the virtual library 11 as an example of a fail information notification unit and the output receiving unit 12 as an example of a repair pattern receiving unit. The virtual library 11 notifies fail information to the redundancy calculation program 109 in response to a request from the redundancy calculation program 109, and corresponds to the redundancy library 110 of FIG.

  The output receiving unit 12 receives the relief pattern data calculated by the redundancy calculation program, and corresponds to the control unit 103 in FIG. 4 in that sense. The output receiving unit 12 outputs the relief pattern data as a calculation result to the monitor 13 as an example of an output unit instead of the replacement process for the DUT 104 shown in FIG.

  The data to be output to the monitor 13 may output not only the relief pattern but also the bit pattern of the defective cell and other information. Here, the bit pattern of a defective cell is a set of fail information, and can be grasped as a DUT unit or a memory page unit. The output means may be not only a monitor but also a printer or a file (data).

  According to the above configuration, the redundancy calculation program 109 can issue a request to the virtual library 11 and acquire fail information in the same manner as for the redundancy library 110 in the actual machine. The fail information includes a defective cell address, DUT information (DUT identifier), and page information (memory page identifier). Further, the virtual library 11 may notify the fail information according to the specified address range, the address search direction (X direction or Y direction), or the presence or absence of compression in response to a request from the redundancy operation program 109. .

  When the redundancy calculation program 109 calculates the repair pattern data for replacing the defective cell and the spare cell, the redundancy calculation program 109 outputs it to the output receiving unit 12 in the same manner as the control unit 103. The output receiving unit 12 outputs the received data to the monitor 13, and an operator can observe this to determine whether or not an appropriate result has been obtained.

  In other words, if the API of the virtual library 11 or the output receiving unit 12 is the same for the redundancy calculation program 109, it operates in the same manner regardless of whether the destination is a real machine or a virtual module by a program, and the result is obtained. Can be calculated. Therefore, the calculation result of the redundancy calculation program 109 can be confirmed without an actual IC test apparatus. Thereby, it is not necessary to secure the use time of the actual machine, debugging can be performed easily and quickly, and the degree of completion can be increased before the IC test apparatus is operated. Further, since the actual machine usage time is not occupied, the actual machine can be used for original tests and debugging of other programs, and the limited use time of the actual machine can be effectively utilized.

  Further, as described above, since the debugging system according to the present embodiment can be realized as a program that operates on a computer, fail information including the address of a virtual defective cell is received as a redundancy calculation program in response to a request from the redundancy calculation program. 109, a process for receiving the relief pattern data calculated by the redundancy calculation program 109, and a process for outputting at least the relief pattern data can be provided as a program for causing a computer to execute the process. This program may be distributed by being recorded on a computer-readable recording medium, or may be distributed online from a server on a network.

  FIG. 2 is a diagram for explaining the overall configuration of the debug system, and shows a configuration for giving fail information to the virtual library 11. Although the fail information can be stored as a constant in the virtual library 11, it is necessary to correct the virtual library 11 for each DUT 104 as in the redundancy calculation program 109. Therefore, it is preferable to give the fail information to the virtual library 11 from the outside.

  The virtual fail memory 14 corresponds to the fail memory 105 of FIG. 4, and is configured by securing an area on the memory of the host computer. Data read / write on the virtual fail memory 14 is read / written by the virtual driver 15 corresponding to the FPGA 106 of FIG. Accordingly, the virtual library 11 reads the fail information from the virtual fail memory 14 via the virtual driver 15 in response to a request from the redundancy calculation program 109 and notifies the redundancy calculation program 109 of the fail information.

  The monitor 13 displays an operation interface 13a for operating the system. The operation interface 13a is a GUI (Graphical User Interface), which is advantageous for performing display and input of information together. An operator can input a bit pattern of a defective cell and perform other operations using the input unit 16 such as a keyboard or a pointing device while looking at the operation interface 13a.

  Further, the fail information can be written into the virtual fail memory 14 by operating the fail bit pattern input unit 17 as an example of the fail information writing means from the operation interface 13a. Specifically, the fail bit pattern input unit 17 can be realized as an input screen as a part of the operation interface 13a. The bit pattern of the defective cell may be read from a file using input / output (not shown), or may be input or corrected using the operation interface 13a. At this time, the memory address in the form of a matrix is displayed as an image, and a defective cell can be visually set (specified and input) for this. Compared to the above, a bit pattern can be easily created. In the case of an actual machine, it is necessary to manage the bit pattern of the defective cell in units of programs. However, in this embodiment, since it can be created, saved, and read as a file, management can be facilitated. .

  That is, according to the configuration shown in FIG. 2, a configuration similar to the hardware configuration of the actual machine can be virtually constructed by a program. Therefore, the redundancy operation program 109 can be debugged simply and quickly without an actual IC test apparatus, and the creation and management of the defective cell bit pattern can be facilitated.

[Example 2]
A second embodiment of the redundancy arithmetic program debugging system according to the present invention will be described. FIG. 3 is a diagram for explaining the overall configuration of the debugging system according to the second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the first embodiment, it has been described that the virtual fail memory 14 is constructed as a configuration for giving fail information to the virtual library 11, but this embodiment further simplifies the configuration of the debug system.

  As shown in FIG. 3, in this embodiment, the virtual library 11 reads the fail information from the fail information database 20 instead of reading the fail information from the virtual fail memory 14 via the virtual driver 15 (see FIG. 2). . The fail information database 20 stores fail information similar to that read from the virtual fail memory 14. In the fail information database 20, the fail information can be written by operating the fail bit pattern input unit 17 from the operation interface 13a.

  That is, if the interface (API: Application Program Interface) of the virtual library 11 or the output receiving unit 12 accessed by the redundancy calculation program is the same as that of the actual machine, a debug system for the redundancy calculation program 109 can be configured. In addition to the effects of the first embodiment, the configuration shown in FIG. 3 can greatly simplify the configuration of the debug system.

  Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  INDUSTRIAL APPLICABILITY The present invention can be used for debugging a redundancy calculation program that generates data for relieving a defect in an IC having a spare circuit therein.

It is a figure explaining the principal part of a debugging system. 1 is a diagram illustrating an overall configuration of a debug system according to Embodiment 1. FIG. It is a figure explaining the whole structure of the debugging system which concerns on Example 2. FIG. It is a figure explaining the conventional IC test apparatus. It is a conceptual diagram explaining the memory cell of DUT simply.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Debug system 11 ... Virtual library 12 ... Output receiving part 13 ... Monitor 13a ... Operation interface 14 ... Virtual fail memory 15 ... Virtual driver 16 ... Input means 17 ... Fail bit pattern input part 20 ... Fail information database 100 ... IC test Device 101 ... Fail detection device 102 ... RDU
103 ... Control unit 104 ... DUT
105 ... Fail memory 106 ... FPGA
107 ... RDC
108 ... Memory 109 ... Redundancy calculation program 110 ... Redundancy library 111 ... Compiler 120 ... Cell array 121 ... Column spare 122 ... Row spare 123 ... Defective cell 124 ... Replacement cell

Claims (5)

A redundancy arithmetic program debugging system for performing a fail-relief operation of a device under test,
Fail information notification means for notifying the redundancy calculation program of fail information including an address of a virtual defective cell in response to a request from the redundancy calculation program;
Relief pattern receiving means for receiving relief pattern data calculated by the redundancy calculation program;
Output means for outputting at least the relief pattern data;
A redundancy arithmetic program debugging system comprising: further,
A virtual fail memory with an area reserved on the memory of the host computer;
Fail information writing means for writing the fail information to the virtual fail memory;
A virtual driver for reading from and writing to the virtual fail memory,
The fail information notifying unit reads the fail information from the virtual fail memory via the virtual driver and notifies the redundancy operation program in response to a request from the redundancy operation program. The debugging system for the described redundancy calculation program. The debug system further includes a fail information database that stores fail information according to a device under test targeted by the redundancy calculation program,
The redundancy calculation program according to claim 1, wherein when there is a request from the redundancy calculation program, the fail information is read with reference to the fail information database, and the failure information is notified to the redundancy calculation program. Debug system. The fail information notifying unit further notifies the fail information according to a specified address range, an address search direction, or presence / absence of compression in response to a request from the redundancy operation program. A debugging system for a redundancy calculation program according to claim 1. A program for debugging a redundancy calculation program for performing fail-relief calculation of a device under test,
A process for notifying the redundancy calculation program of fail information including an address of a virtual defective cell in response to a request from the redundancy calculation program;
Processing for receiving relief pattern data calculated by the redundancy calculation program;
Processing to output at least the relief pattern data; and
A program that causes a computer to execute.

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