JP3171325B2 - Memory test apparatus and method and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control firmware (hereinafter, referred to as FW) for controlling the entire system in a system comprising hardware (hereinafter, referred to as HW) such as a CPU and a main storage device (hereinafter, referred to as memory). ) Relates to a memory test method at the time of system startup.

[0002]

2. Description of the Related Art A memory test at the time of starting a system by a FW is for starting a system as a first purpose. Therefore, it is considered that the test should be performed only in the area indispensable for system startup. further,
In recent years, since the memory capacity tends to increase more and more, the test execution of the entire memory area has a strong influence on the time required for system startup. However, the conventional method does not solve such a problem.

[0003] For example, an example of a conventional memory test method at the time of system startup is described in Japanese Patent Application No. 1-098945 . The conventional memory test method at the time of starting the system includes a memory test unit for performing a memory test, a memory access control unit for accessing a memory, a main storage device, and a control unit for controlling the entire system.

[0004] The conventional memory test method at the time of starting up the system having such a configuration operates as follows.

When the memory test section receives the test start signal, the memory test section accesses the main storage device via the memory access control section and tests the startup area and the memory control section. When the memory test unit receives the test start signal from the main control unit, the memory test unit accesses the main storage device via the memory access control unit, tests the extended area in the same manner, and starts the software. The present technology is a method in which the memory test is executed in parallel with the start-up processing of the program by the control means.

Japanese Patent Application Laid-Open No. 2-255925 discloses a "memory test method and apparatus" by using a memory test using a built-in memory test function and a test based on a normal memory access route.
A method capable of executing a reliable and faster memory test with a small amount of hardware is disclosed.

[0007]

However, this prior art has a problem that it takes time depending on the memory capacity as described above.

The reason is that all memories are tested,
This is because the case where the memory capacity is significantly increased is not considered.

[Object of the Invention] An object of the present invention is to realize a memory test method at the time of system startup by control firmware, which can be executed in a short time even when the memory capacity is greatly increased.

[0010]

SUMMARY OF THE INVENTION The present invention is directed to a system setup.
A row that stores error information generated during startup or operation.
Cal memory and when launching a new system
A system for accessing local memory and acquiring error information
In a memory test device with firmware
The local memory can perform a test according to the error information.
Error information and test pattern
A memory test pattern table to be stored.
The firmware refers to the memory pattern table.
To determine the test pattern corresponding to the acquired error information
Memory test pattern determining means to perform
I do.

In a memory test at the time of system startup by the control firmware, an error information table 31 in which error information of a memory generated at the time of previous system startup and operation is recorded, a memory test pattern file 32, A local memory 30 for storing a memory test pattern table 33; an error information acquiring unit 115 for acquiring memory error information from the error information table 31; an error information analyzing unit 113 for analyzing the memory error information; Memory test area determination table 50 for registering the result of counting the number of errors for each certain area, memory test pattern determination means 116, memory test execution means 112 for executing a memory test, and error for recording memory error information Information recording means 1 4 is also a memory test device and having said control firmware (FW) 11 having a a.

The present invention is also applicable when the system is started up.
Stores error information generated during operation in local memory
Control firmware when starting up a new system.
Error stored in the local memory by the
Memory test method to acquire information and execute memory test
Error so that a test corresponding to the error information can be performed.
-The information and the test pattern correspond to the local memory.
And stored and obtained by the control firmware
A test pattern corresponding to the error information based on the error information;
Is determined.

Still further, according to the present invention, in a memory test at the time of system startup by the control firmware, error information generated at the time of previous system startup and operation is retained, and at the time of system startup, the error information is stored. The memory test method is characterized in that the memory test area is limited to only the memory error frequent area and the area where the OS is loaded with reference to the information.

In a memory test at the time of system startup by the control firmware (FW), the FW 11
When the control is transferred from the main routine 111 to the memory test process, the error information acquiring unit 115 refers to the error information table 31 in the local memory 30 via the system bus 40 and acquires the error information as internal information of the FW. (Step A1 in FIG. 3), a step of analyzing error information by the error information analysis means 113 and first checking for the presence or absence of error information (step A2 in FIG. 3). Address 3
12, a step of counting the number of errors for each fixed area and error type (step A3 in FIG. 3), a step for determining the end of the error information (step A4 in FIG. 3), and a memory test pattern determination unit 116. By using the error type 52 of the memory test area determination table 50 as a key, a memory test pattern of each test area is determined from the memory test pattern table 33 in the local memory 30 (step A5 in FIG. 3); The test area 51 of the determination table 50 and the determined memory test pattern are input to the memory test execution unit 11.
Starting a memory test in the error-prone area (Step A6 in FIG. 3);
2, the step of executing the test of the OS use area and the important area (Step A7 in FIG. 3), and the error information generated by the memory test is
Recording the error information in the error information table 31 via the system bus 40 (step A8 in FIG. 3).

If a memory error occurs during operation, control is temporarily transferred to the FW, and error information is recorded by the error information recording means 114 via the system bus 40 (step A9 in FIG. 4). It is also a test method.

The present invention is also a storage medium storing a computer program describing the above method.

[Operation] According to the present invention, in order to solve the above-mentioned problem, the memory test at the next start-up is held by retaining the error information generated at the previous start-up and operation of the system. It is possible to specify an area and shorten the memory test time without affecting the system startup.

Further, since a memory test pattern corresponding to an error type, an area used by the OS, and other important areas is prepared, reliability can be maintained.

The present invention is implemented by a control firmware (hereinafter, referred to as FW) controlling the entire system in a system including hardware (hereinafter, referred to as HW) such as a CPU and a main storage device (hereinafter, referred to as memory). It provides a memory test method at the time of system startup.

FIG. 1 is a block diagram of an embodiment of the present invention.
In FIG. 1, an FW for performing a memory test is executed on the CPU 10.
Is working. The error information table 31 stored in the local memory 30 records error information of the memory that occurred at the time of the previous system startup and operation. When the memory test is started, the FW refers to the error information table 31 to analyze in which area of the memory 20 errors frequently occur, and determine a memory test area. In this test method, as shown in the structure diagram of the memory 20 in FIG.
Only the memory error-prone area and the important area where the OS is loaded are tested. In addition, a test pattern suitable for each area is prepared.

As described above, the present invention narrows the memory test area to a memory error frequent area and an important area where the OS is loaded, so that the error detection rate of the important area is not reduced and the memory test time is reduced. And the start-up time of the entire system is shortened.

[0022]

An embodiment of the present invention will be described below.

[Explanation of Configuration] FIG. 1 is a configuration diagram of an embodiment of the present invention. Referring to FIG. 1, an embodiment of a memory test method at the time of system startup by the FW of the present invention is as follows.
The CPU 10 on which the FW 11 operates, a memory (main storage) 20 to be tested, an error information table 31, a local memory 30 for storing a memory test pattern file 32 and a memory test pattern table 33, and a system bus 40 It is configured.

The system bus 40 connects the CPU 10, the memory 20, and the local memory 30.

The FW 11 includes a main routine 111, a memory test execution unit 112 for performing a memory test, an error information analysis unit 113 for analyzing memory error information,
Error information recording means 114 for recording memory error information
An error information acquiring unit 115 for acquiring memory error information from a memory error information table 31 stored in the local memory 30; a memory test pattern determining unit 116; And a memory test area determination table 50 for registering the counted result.

The local memory 30 stores an error information table 31 for recording error information when a memory error occurs, a memory test pattern file 32 for executing different tests depending on an error type and a test area, and a memory test pattern table 33. I have.

FIG. 6 is a configuration diagram of the error information table 31 and the memory test area determination table. Referring to FIG. 6, the error information table 31 includes an error type 311 and an error address 312.

FIG. 5 shows a memory test pattern table 33.
3 is a configuration diagram of a memory test pattern table 32. FIG. Referring to FIG. 5, the memory test pattern table 33 is
An error type 331 and a memory test pattern 332 are provided.

[Explanation of Operation] Next, the overall operation of the present embodiment will be described in detail with reference to FIGS.

When the control is transferred from the main routine 111 to the memory test processing, the FW 11 first refers to the error information table 31 in the local memory 30 via the system bus 40 by the error information acquisition means 115 and reads the error information. It is acquired as FW internal information (step A1 in FIG. 3).

Next, error information is analyzed by the error information analyzing means 113. First, the presence or absence of error information is checked (step A2 in FIG. 3). The presence / absence of error information is shown in FIG.
Can be determined by the error type 311 of the error information table 31 shown in FIG. For example, in this embodiment, when the error type 311 of the first entry is “F”, it is determined that there is no error information.

If there is error information, the number of errors is counted for each fixed area and error type with reference to the error address 312 (step A3 in FIG. 3). For example,
Assuming that the fixed area is 64 MB, the memory area is divided for each 64 MB, and the number of errors occurring in each area is counted. As shown in FIG. 6, since the error address 312 of the first entry is 4800000 (H),
It belongs to the area of 4000000 (H) -7ffffff (H). The number of times is added to the area and 1 of the error type 311. In this manner, all error information is analyzed, and as a result, a memory test area determination table 50 shown in FIG. 6 is created. Note that an area where the number of errors is 0 is not registered in the memory test area determination table 50.

The end of the error information is determined by the error type 311 of the error information table 31 as in the confirmation of the presence or absence of the error information.
(Step A4 in FIG. 3). That is, in this embodiment, when the error type is “F”, the entry is regarded as the end of the error information.

Next, the memory test pattern determining means 116
Thus, the memory test pattern of each test area is determined.
This means determines a memory test pattern from the memory test pattern table 33 in the local memory 30 using the error type 52 of the memory test area determination table 50 as a key (step A5 in FIG. 3).

For example, the first entry of the memory test area determination table 50 in FIG.
000 (H) -7ffffff (H) indicates that an error of the error type 52′1 ′ has occurred five times.

Therefore, from the memory test pattern table 33 of FIG. 5, the test area 400000 (H) -7fff
In the memory test of fff (H), a memory test of a test pattern “A” is executed.

Further, a test area in which an error has occurred 10 times or more is 10000000 (H) -1400000.
For (H), a test pattern “D” is executed.

Next, the test area 51 of the memory test area determination table 50 and the memory test pattern determined in step A5 of FIG.
Starts a memory test in the error prone area (FIG. 3)
Step A6).

Next, the memory test execution means 112
A test for the OS use area and other important areas is executed (step A7 in FIG. 3). A memory test pattern is prepared in the local memory 30 in this area as well as in the error-prone area.

Finally, the error information generated in the memory test is stored in the system bus 4 by the error information recording means 114.
0 (step A8 in FIG. 3).

As for memory errors during operation,
As shown in FIG. 4, when a memory error occurs during operation, control is temporarily transferred to the FW, and the error information recording unit 114
As a result, error information is recorded via the system bus 40 (step A9 in FIG. 4).

[Other Embodiments] Next, other embodiments of the present invention will be described in detail with reference to the drawings.

[Explanation of Configuration] FIG. 7 is a system configuration diagram of another embodiment of the present invention. Referring to FIG. 7, in another embodiment of the present invention, a plurality of CPUs 010 to n1N on which the FW operates, and a memory (main storage) 2 to be tested.
1, a local memory 30 storing an error information table 31, a memory test pattern 32, and a memory test pattern table 33, as in FIG.
0.

In the above-described embodiment, the number of CPUs is one. In the present embodiment, a memory test is executed in parallel by a plurality of CPUs to further reduce the time.

FIG. 8 is a diagram showing a configuration of control firmware (FW) of another embodiment. Referring to FIG. 8, in addition to the configuration of the FW in the embodiment shown in FIG.
The difference is that a means 117 for determining the role assignment of each CPU is provided. Means 117 for determining the role assignment of each CPU is as follows:
This is means for a parent CPU to determine which test area is to be tested by another child CPU before executing a memory test.

[Explanation of Operation] The operation of this embodiment will be described with reference to FIG.
This will be described in detail with reference to FIG.

FIG. 9 is a flowchart showing the operation of another embodiment. The error information analysis means 113 according to the present embodiment, which is shown by steps A1 to A5 and A8 in FIG.
Error information recording means 114, error information acquisition means 115
Further, the memory test pattern determining means 116 includes the means 113, 114, 115 and 11 of the embodiment shown in FIG.
6, the description is omitted.

In the embodiment shown in FIG. 1, the test of each test area is executed by one CPU 10, but in this embodiment, the role assignment determining means 117 of each CPU determines that the parent CPU After the test pattern of each test area is determined (FIG. 9
In step A5), the number of mounted CPUs is checked, and a test is assigned to each CPU (step B1 in FIG. 9). At this time, tests for the OS use area and other important areas are also assigned.

In this embodiment, the CPU 0 is the parent and the CPU
1 to CPUn are children. If parent CPU0 is the other child C
After the assignment of the memory test to the PU, the CPUs start the memory test in parallel by the memory test execution means 112 (step B2 in FIG. 9).

If there is no error information (step A2 in FIG. 9), the parent CPU tests only the OS use area and other important areas (step B3 in FIG. 9).

The present invention relates to a CD-RO storing a computer program describing the above-mentioned method of the present invention.
The present invention can also be realized by writing a program into the FW from this recording medium such as M.

[0052]

An advantage of the present invention is that the time for the memory test can be shortened and the start-up time for the entire system can be shortened.

The reason is that the memory test area is narrowed down based on the memory error information recorded during the previous operation of the system.

Further, since the memory test is also performed on the area used by the OS and other important areas, a memory test method that can sufficiently maintain the reliability at the time of starting the system can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a memory test method at the time of system startup by a FW of the present invention.

FIG. 2 is a configuration diagram of a memory 20 according to the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation when a memory error occurs during operation.

5 is a configuration diagram of a memory test pattern table 33. FIG.

FIG. 6 is a configuration diagram of an error information table 31 and a memory test area determination table 50.

FIG. 7 is a configuration diagram of another embodiment of the present invention.

FIG. 8 shows a control firmware (F) according to another embodiment of the present invention.
It is a block diagram of W).

FIG. 9 is a flowchart showing the operation of another embodiment of the present invention.

[Explanation of symbols]

 10 CPU, 11 FW (firmware), 20 memory (main memory) to be tested, 30 local memory, 31 error information table, 32 memory test pattern file, 33 memory test pattern table, 40 system bus 50 memory test area determination Table, 111 main routine 112 memory test execution means, 113 error information analysis means, 114 error information recording means, 115 error information acquisition means, 116 memory test pattern determination means 311 error type, 312 error address, 331 error type, 332 memory test pattern,

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/16 G06F 11/22

Claims (8)

(57) [Claims] (1) The error occurs when the system is started or operated.
Local memory for storing error information
Access local memory when booting system
Control firmware to obtain error information
In the memory test apparatus, the local memory can perform a test according to error information.
Error information and test pattern
A memory test pattern table for storing the memory pattern table.
Test pattern corresponding to the acquired error information
Memory test pattern determination means for determining the
And a memory test apparatus. 2. The method according to claim 1, wherein the local memory is a memory test.
Error information and test patterns stored in the pattern table
And a memory test pattern file for generating
2. The memory test apparatus according to claim 1, wherein: 3. The control firmware according to claim 1, further comprising :
A memory test area determination table for registering the number of occurrences, and a memory test according to the number of registered errors
And a memory test execution means for executing.
The memory test apparatus according to claim 1. 4. A plurality of CPUs each having the control firmware and executing a memory test by parallel processing, and before executing the memory test, a parent CPU assigns which test area to another child CPU. The memory test apparatus according to any one of claims 1 to 3, further comprising means for determining a role assignment of each CPU to determine whether to perform the test. 5. A system which is generated when the system is started or operated.
Error information stored in local memory, and a new system
When starting up the system, the control firmware
Acquires the error information stored in the local memory and
In the memory test method for executing the memory test , the error information and the
Test patterns are stored in association with the local memory.
The error information acquired by the control firmware
A test pattern corresponding to the error information is determined based on the error information
A memory test method, characterized in that: Wherein the control firmware acquired et
Counting the number of error occurrences based on the error information, and determining the test pattern according to the number of error occurrences
Perform memory test based on steps and determined memory test pattern
And storing the result of the executed memory test in the local memory.
Memory testing method according to claim 5, characterized in that a step. 7. A when the system of operation that an error has occurred
Error information before the control firmware
Serial claims, characterized in that recorded in the local memory
The memory test method according to any one of claims 4 to 6 . 8. A recording medium storing a computer program describing the method according to claim 4. Description: