JP2007241840A - Memory diagnostic apparatus, method and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory diagnostic apparatus for specifying a defective memory IC by evenly diagnosing each bit that constitutes the memory, using random numbers as diagnostic data, and counting the occurrences of an abnormality in bit units, i.e., the minimum storage units of the memory. <P>SOLUTION: The apparatus includes a CPU for generating random number data for the diagnosis of memory; a memory comprising a plurality of ICs having memory areas specified by a plurality of access addresses and a plurality of bits and integrated for every predetermined bit width, the memory being connected to the CPU via a data bus; and a counting means for comparing, for every bit of the memory, the random number data written in the respective memory area with the random number data read, and counting the occurrences of an abnormality if the comparison result shows that the data do not match. The defective memory IC is specified based on the count value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory diagnostic apparatus, a memory diagnostic method, and a memory diagnostic system that can diagnose a memory connected to a CPU via a data bus and easily identify a memory in which a failure has occurred.

  Conventionally, an information processing apparatus stores data in a memory, but if a memory element in the memory fails, the written data may not be stored correctly, and the apparatus can operate normally. Disappear. Therefore, an apparatus equipped with a memory can diagnose whether or not a memory element has failed.

  Conventionally, a generally known memory diagnosis method is to write test data stored in a register in a CPU (Central Processing Unit) continuously to all addresses of a memory to be diagnosed, and then from all addresses of the memory. Data is read continuously, and the written data and the read data are compared with each other to confirm the presence or absence of a failure.

  For example, in Patent Document 1, a write data storage unit that stores data continuously written in a memory, and a comparison circuit that compares and collates read data continuously read after data writing with contents stored in the write data storage unit And a memory diagnostic system having a specific circuit for specifying an error memory when a mismatch occurs in the comparison result.

In the conventional memory diagnosis method, it is necessary to change all the bits in order to check whether each bit in all the address areas of the memory operates normally. For this reason, Patent Document 2 describes an example in which two or more data patterns in which the values of each bit are contradictory are used as test data. The memory for writing and reading 32-bit width data uses two patterns of 555555555h and AAAAAAAAAh (h is a hexadecimal notation: the same applies hereinafter) as test data, and writing, reading, and comparison for each test data By performing processing, each bit in the entire address area of the memory is checked. As a result, the quality of all memory ICs or memory boards and modules as a whole is judged.
JP-A-11-102328 JP 2002-312252 A

  Conventional memory diagnosis is a memory diagnosis method that focuses on an accidental failure of a memory element. Diagnosis has been performed in units of word length that can be read and written by a processor (CPU) or a data comparison circuit at a time. For this reason, detailed information less than the access word length of the processor is discarded, and detailed failure analysis cannot be performed due to insufficient information. In addition, since test data set in advance is used, there is a case where a correct data value cannot be written depending on the transmission path characteristic of the data bus, and there is a limit to a case where more accurate diagnosis is required.

  The present invention has been made in consideration of the above circumstances, using random numbers as diagnostic data, uniformly diagnosing each bit constituting the memory, and measuring the number of abnormal occurrences in units of bits, which is the minimum storage unit of the memory Thus, an object of the present invention is to provide a memory diagnostic apparatus that can quickly identify a faulty memory IC.

  The memory diagnostic device of the present invention according to claim 1 has a CPU (central processing unit) capable of generating random number data for memory diagnosis, a memory area defined by a plurality of access addresses and a plurality of bits, A memory composed of a plurality of ICs integrated for each predetermined bit width, connected to the CPU via a data bus, and means for controlling the writing and reading of the random number data to the memory; Counting means for comparing random number data written in each memory area with read random number data for each bit of the memory, and determining that there is an abnormality when the comparison result does not match, and counting the number of occurrences of abnormality for each bit And an abnormal IC is identified based on the count value obtained by the counting means.

  According to a fifth aspect of the present invention, there is provided a method for diagnosing a memory having a memory area defined by a plurality of access addresses and a plurality of bits, and comprising a plurality of ICs integrated for each predetermined bit width. And generating random number data for memory diagnosis, writing step for writing the random number data to the memory, reading step for reading the random number data written to the memory, and For each bit of the memory, the random number data written in each memory area is compared with the read random number data, and a comparison step for determining an abnormality when there is a mismatch in the comparison result, and the number of occurrences of abnormality for each bit A counting step for counting, and it is possible to identify an abnormal memory IC based on the count value obtained by the counting step. And butterflies.

  Furthermore, the memory diagnostic system of the present invention as claimed in claim 6 is connected to a CPU (central processing unit) capable of generating random number data for memory diagnosis and to the CPU via a data bus, each of which has a plurality of accesses. A plurality of memories each having a memory area defined by an address and a plurality of bits and integrated with a predetermined bit width, and random data for memory diagnosis generated by the CPU Is written to and read from the memory to be diagnosed of the plurality of memories, and the written random number data is compared with the read random number data for each bit of the memory to be diagnosed. And counting means for counting the number of occurrences of abnormality for each bit, and storing means for storing the counting result by the counting means, By using the stored count result, and identifies the memory IC with abnormalities.

  According to the memory diagnostic device of the present invention, it is possible to identify the memory IC in which an error has occurred based on the bit number by performing a diagnosis in consideration of the physical arrangement of each mounted memory.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of a memory diagnostic apparatus of the present invention. In FIG. 1, 11 is a CPU (central processing unit), and 12, 13, and 14 are data buses. A bus bridge 15 connects different data buses and includes a direct memory access controller (DMAC) 16. The DMAC 16 exchanges data between the peripheral device and the memory without going through the CPU 11. The CPU 11 is connected to the bus bridge 15 via the data bus 12, and the memories 17, 18, and 19 are connected to the bus bridge 15 and the data buses 13 and 14, respectively.

  Each of the memories 17, 18, and 19 is a memory to be diagnosed, and is a large-capacity memory such as a page memory. Data exchange between the memories is all performed by DMA transfer (direct memory access transfer) under the control of the DMAC 16. The DMA transfer is performed using the maximum bit length in the target data bus. An input device 20 is connected to the data bus 12.

  FIG. 2 is a diagram illustrating an internal configuration of the memories 17, 18, and 19. The memories 17, 18 and 19 have the same configuration, and will be described as the memory M. The memory M is composed of a plurality of memory ICs (IC1 to IC4), the vertical direction indicates an access address, and addresses N to (N + M−1) in the access unit of the processor (CPU). The horizontal direction indicates the processing direction, and has a memory area with a total of 64 bits (bits), for example, 0 to 63.

  IC1 to IC4 have physical IC arrangements determined by, for example, bit positions divided every 16 bits. The memory IC1 has a memory area of 0 to 15 bits at each address, and the memory IC2 has 16 to 16 at each address. It has a 31-bit memory area. Similarly, the memory IC3 has a 32-47 bit memory area at each address, and the memory IC4 has a 48-64 bit memory area at each address. The memory ICs (IC1 to IC4) are integrated circuits having the same configuration. The memory ICs (IC1 to IC4) constitute a set to form one bank, and the memory M is configured by a plurality of banks.

  FIG. 2 shows an example composed of bank 1 and bank k, where the first address of bank 1 is N address and the first address of bank k is P address. Each bank is constituted by an independent integrated circuit.

  Next, the memory diagnosis method of the present invention will be described with reference to the flowcharts of FIGS. The memory diagnosis is performed under the control of the CPU 11, and the memory diagnosis is started in step S1 of FIG. In step S <b> 2, the diagnosis count i is input via the input unit 20. For example, if i = 1000, diagnosis is performed 1000 times. The greater the number of diagnoses, the higher the accuracy of the diagnosis.

  In the next step S3, the CPU 11 generates random number data as diagnostic data. Previously, test data set in advance was used, but there was a case where detailed failure analysis could not be performed due to lack of information, but in the present invention, random number data is used and diagnosis is performed uniformly by increasing the number of diagnosis, and sufficient analysis can be performed. I am doing so. In step S4, the number of divisions j is set in order to diagnose the memory M in units of banks.

  In step S5, diagnostic data (random number data) is written into the target memory using the DMAC 16, and in step S6, the diagnostic data written using the DMAC 16 is read.

  For example, assume that the memory 17 in FIG. 1 is a temporary memory for diagnosis, the memory 18 in FIG. 1 is a diagnosis target memory, and the diagnosis size is 1 Mbyte. The CPU 11 creates and writes, for example, 1 Mbytes of random data in the diagnostic temporary memory 17 and writes 1 Mbytes of diagnostic data in the temporary memory 17 to the diagnosis target memory 18 using the DMAC 16 (step 5). ). Then, the DMAC 16 is used to read 1 Mbytes from the diagnosis target memory 18 to the reading area (readback memory) of the diagnostic temporary memory 17 (step S6).

  Next, the process proceeds to step S7 in FIG. 4, where the size k of the diagnostic memory is input, and the memory size k determined by the unit of the memory IC1, IC2, IC3, IC4 is set.

  In step S8, an exclusive OR process is performed on the diagnosis data stored in the temporary memory 17 for diagnosis and the data read into the readback memory. If the result is “0”, it is determined as normal, and the next memory Diagnose. If the result is other than “0”, that is, if the result of the exclusive OR is “1”, it is determined that the data bus or the memory is abnormal, the error counting process is called in step S9, and the abnormal (error) counting process is performed. I do.

  FIG. 5 shows a flow of the error counting process in step S9. When the error counting process starts in step S91, the bank number A is obtained from the abnormality occurrence address in step S92. As shown in FIG. 2, since the addresses of each bank are assigned different addresses such as N address and P address, the corresponding bank can be obtained from the abnormality occurrence address.

  In step S93, the word length y of the diagnosis target memory is input. That is, here, y = 64 is input, and the memory area of 0 to 63 bits is diagnosed sequentially. In the next step S94, the exclusive OR result is checked bit by bit, and if it is “0”, the process proceeds to step S96, and if there is a bit that is “1”, the bit number is determined. In step S95, the value of the number of abnormal occurrences is incremented by +1 in the abnormal area identified from the memory bank number A and the bit number y. Confirmation of the exclusive OR result and counting of the number of occurrences of abnormality are performed for all bits (y) in the memory area in step S96.

  When the error counting process is completed in step S97, the process proceeds to step S10 in FIG. 4, and the diagnosis process is executed as many times as the memory size k, and the IC1 to IC4 are diagnosed. In step S11, the diagnosis process is performed as many times as the number of divisions j, and the diagnosis process is executed for all banks. Further, in step S12, the same diagnosis processing is executed as many times as the number of diagnosis i (= 1000).

  Thus, the above-described diagnosis process is performed over the entire memory area of the diagnosis target memory, and is repeated 1000 times when the set number of times is set, for example, i = 1000.

  FIG. 6 is an example of a graph showing the number of abnormalities (number of error occurrences) when the diagnosis process is performed 1000 times. FIG. 6 shows the result of counting the number of errors for each bit in bank 1. There are no errors for 0 to 15 bits and 15 to 31 bits, and there are many errors for 32 to 47 bits and 48 to 63 bits. I understand. As a result, when the memory M has the configuration as shown in FIG. 2, it can be determined that there is no abnormality in IC1 and IC2, and abnormality has occurred in IC3 and IC4.

  The self-diagnosis result (abnormal number count value) is stored in a memory area in the CPU 11 or a memory area of a memory determined to have no abnormality by the self-diagnosis. The memory area for storing the self-diagnosis result is defined by, for example, the number of bits constituting the access unit of the processor × the number of memory banks × 4 bytes, and is not related to the size of the capacity. For example, if the access unit of the processor is 64 bits and the number of memory banks is 1, the memory area to be stored is 64 bits × 1 bank × 4 bytes = 256 bytes.

  As described above, the memory diagnostic device according to the present invention has a bank number and a bit in which an error has occurred by performing a diagnosis in consideration of the physical arrangement of each mounted memory as compared with the conventional memory diagnostic method. It is possible to identify a faulty memory IC from the number. Therefore, the failure abnormality information is fed back to the development department or the like, so that the failed memory can be easily replaced and workability can be improved.

  Further, the present invention is not limited to the above-described embodiment, and other modifications are conceivable within the scope not departing from the scope of the claims.

The block diagram which shows one Embodiment of the memory diagnostic apparatus of this invention. Explanatory drawing which shows the internal structure of the memory used in the embodiment. 6 is a flowchart for explaining an operation of memory diagnosis in the embodiment. 6 is a flowchart for explaining an operation of memory diagnosis in the embodiment. 6 is a flowchart for explaining an operation of memory diagnosis in the embodiment. Explanatory drawing which shows an example of the memory diagnostic result in the embodiment.

Explanation of symbols

11 ... CPU (processor)
12, 13, 14 ... data bus 15 ... bus bridge 16 ... DMAC
17, 18, 19 ... Memory 20 ... Input part M ... Memory IC1, IC2, IC3, IC4 ... Memory IC

Claims (8)

A CPU (Central Processing Unit) capable of generating random number data for memory diagnosis;
A memory having a memory area defined by a plurality of access addresses and a plurality of bits, configured by a plurality of ICs integrated for each predetermined bit width, and connected to the CPU via a data bus;
Means for writing and reading the random number data to and from the memory;
For each bit of the memory, the random number data written in each memory area is compared with the read random number data, and when there is a mismatch in the comparison result, it is determined that there is an abnormality, and the count for counting the number of occurrences of abnormality for each bit Means,
A memory diagnostic apparatus, wherein an abnormal IC is identified based on a count value obtained by the counting means.   The memory diagnostic apparatus according to claim 1, wherein the CPU controls the writing and reading of the random number data with respect to the memory.   2. The memory diagnosis apparatus according to claim 1, wherein the memory diagnosis is performed a preset number of times, and the counting means accumulates and adds the number of occurrences of abnormality in each diagnosis result.   2. The memory diagnosis apparatus according to claim 1, wherein the memory comprises one bank with the plurality of IC groups, and the memory is diagnosed for each bank. A memory diagnostic method comprising a plurality of ICs having a memory area defined by a plurality of access addresses and a plurality of bits and integrated for each predetermined bit width,
Generating random data for memory diagnosis;
A writing step of writing the random number data to the memory;
A reading step of reading the random number data written in the memory;
For each bit of the memory, comparing the random number data written in each memory area and the read random number data, a comparison step of determining an abnormality when there is a mismatch in the comparison results;
A counting step for counting the number of occurrences of abnormality for each bit, and
A memory diagnostic method that makes it possible to identify an abnormal memory IC based on the count value obtained in the counting step. A CPU (Central Processing Unit) capable of generating random number data for memory diagnosis;
A plurality of memories connected to the CPU via a data bus, each having a memory area defined by a plurality of access addresses and a plurality of bits, and composed of a plurality of ICs integrated for each predetermined bit width When,
The random number data for memory diagnosis generated by the CPU is written to and read from the diagnosis target memory of the plurality of memories, and the written random number data and the read random number data are read for each bit of the diagnosis target memory. A counting means for comparing, and determining that there is an abnormality when the comparison result is inconsistent and counting the number of occurrences of abnormality for each bit;
Storing means for storing the counting result by the counting means,
A memory diagnostic system characterized in that an abnormal memory IC is identified using a counting result stored in the storage means.   7. The memory diagnosis system according to claim 6, wherein an exclusive OR process is performed to compare the written random number data with the read random number data.   7. The memory diagnosis system according to claim 6, wherein the counting result by the counting means is stored in a memory in the CPU or a memory determined not to be abnormal based on the diagnosis result.

Images