JP5279641B2 - Test apparatus and diagnosis method thereof - Google Patents

Description

  The present invention relates to a diagnostic technique for a semiconductor test apparatus.

  A semiconductor test apparatus (hereinafter simply referred to as a test apparatus) is provided to determine whether a digital circuit such as a memory or a DSP (Digital Signal Processor) or an analog circuit is good or bad. For example, a memory tester for testing a memory includes a large number of input / output pins (I / O pins) in order to test a large number of devices under test (DUT) in a short time during mass production. It is modularized as a unit. The module for each I / O pin may be modularized into smaller functional blocks.

  The test apparatus incorporates a diagnostic program (DIAG) that periodically diagnoses whether or not the system of the test apparatus is functioning normally.

  Diagnosis is performed in units of a certain module. Specifically, the diagnostic read data (hereinafter, also simply referred to as read data) obtained as a result of executing the operation / process in the module is compared with the expected value data to determine whether the module functions normally. Is done.

  As described above, the test apparatus is provided with a plurality of modules having the same configuration, and therefore it is necessary to diagnose all of the plurality of modules. FIG. 1 is a block diagram showing a configuration of a test apparatus 200 having a function of diagnosing a plurality of modules. The test apparatus 200 includes a plurality of modules mod to be diagnosed, an expected value comparison unit 202, and an OR gate 204.

Modules are layered. The pin modules mod pin-1 to mod pin-n are modules having I / O pins as a unit and have the same configuration.
Sub-modules mod_i-A to mod_i-D are provided below the i-th (1 ≦ i ≦ n) pin module mod_pin-i, and the sub-modules mod_i-A to mod_i-D are configured similarly.

  The submodule generates diagnostic read data read_data [31: 0] indicating the diagnostic result. Enable data EN [31: 0] is given to each submodule. The AND gate 208 generates a logical product of the read data read_data and the enable data EN, and outputs the logical product as the read data ORDATA_MOD.

  Each pin module mod_pin includes an OR gate 206 that generates a logical sum of read data ORDATA_MOD of submodules included therein. The output of the OR gate 206 is referred to as pin read data RDATA_mod_pin.

  The OR gate 204 generates a logical sum of pin read data RDATA_mod_pin output from each pin module mod_pin, and generates top read data RDATA_mod_top. The expected value comparison unit 202 compares the top read data RDATA_mod_top with the expected value data EXP.

The above is the overall configuration of the test apparatus 200.
In the test apparatus 200, when all submodules are diagnosed, the following processing is performed.
1. Select one submodule as the diagnosis target.
For example, the enable data EN of the submodule mod_1-A of the first pin module mod_pin-1 is asserted (1), and the enable data EN of other submodules is negated (0).

  As a result, all the read data ORDATA from the submodules other than the diagnosis target are zero, and the calculation result of the OR gate 206 is not affected. That is, read data from the submodule to be diagnosed is output as pin read data RDATA_mod_pin. The same processing is further performed in the OR gate 204 in the upper layer, and the read data RDATA_mod_top of the sub-module to be diagnosed is input to the expected value comparison unit 202.

  2. Expected value data EXP corresponding to the sub-module to be diagnosed is set in the expected value comparing unit 204.

  3. The expected value comparison unit 202 compares the read data RDATA_mod_top with the expected value data EXP to determine the pass / fail of the submodule to be diagnosed.

  4). The test apparatus diagnoses all the sub modules in order by repeating the same processing while switching the sub modules to be diagnosed one by one.

  In the test apparatus of FIG. 1, each time the submodule is switched, it is necessary to read the diagnostic data to the expected value comparison unit 202 and compare it with the corresponding expected value data each time. That is, the reading time increases in proportion to the number of submodules, and a huge amount of time is required for diagnosis.

  The present invention has been made in view of such a situation, and an exemplary object of an embodiment thereof is to provide a test apparatus capable of shortening diagnosis time.

  One embodiment of the present invention relates to a test apparatus. The test apparatus includes a plurality of modules and a first logic gate. Each module includes an expected value comparison unit that compares diagnostic data indicating the diagnosis result with expected value data corresponding thereto, and outputs comparison determination data indicating a comparison result by the expected value comparison unit. The first logic gate generates a logical sum of comparison determination data for each of the plurality of modules.

The comparison judgment data is designed to take 0 when the expected value data matches the diagnostic data, and take 1 when the data does not match. When the first logic gate is an OR gate, there is a mismatch (error) in at least one module. If it occurs, “1” indicating an error also occurs in the logical sum of a plurality of comparison determination data, and it can be diagnosed as fail as a whole.
Alternatively, the comparison determination data is designed to take 1 when the expected value data and the diagnostic data match, and 0 when they do not match. Even when the first logic gate is an AND gate, at least one module does not match ( If an error) occurs, “0” also occurs in the logical sum of a plurality of comparison determination data, and it can be diagnosed as a failure as a whole.

  Therefore, according to this aspect, since a plurality of modules can be diagnosed simultaneously in parallel, the diagnosis time can be shortened.

The expected value comparison unit of each module may include a second logic gate that generates a logical product of control data for setting whether or not the module is to be diagnosed and expected value data. The expected value comparison unit may compare the output data of the second logic gate with the diagnostic data.
According to this aspect, by controlling the control data for each module, it is possible to switch between diagnosing arbitrary modules at the same time or diagnosing them individually.

  Each of the plurality of modules includes a plurality of submodules and a third logic gate. Each of the plurality of submodules outputs diagnostic data indicating the diagnostic result. The third logic gate generates a logical sum of the diagnosis data of the plurality of submodules. Each sub-module may output diagnostic data when it is a diagnosis target and may output zero data when it is a non-diagnosis target. The expected value comparison unit may compare the output signal of the third logic gate with expected value data.

  Another aspect of the present invention relates to a diagnostic method for a test apparatus including a plurality of modules. In this diagnostic method, a diagnosis is performed in at least two modules for which common expected value data is scheduled, and diagnostic data indicating the diagnostic results of at least two modules are respectively compared with the common expected value data. A step, a step of generating a logical sum of comparison determination data indicating a comparison result for each module, and a step of determining a pass fail of the test apparatus based on the logical sum.

  According to this aspect, by referring to the logical sum of a plurality of comparison determination data, it is possible to determine the pass and fail of the entire test apparatus in a short time.

The diagnosis method of an aspect may further include a step of individually diagnosing at least two modules in order and determining a pass fail for each module when the test apparatus is determined to fail.
According to this aspect, it is possible to specify a module that has been determined to fail.

  It should be noted that any combination of the above-described constituent elements and the expression of the present invention converted between methods, apparatuses, etc. are also effective as an aspect of the present invention.

  According to the present invention, the diagnosis time can be shortened.

It is a block diagram which shows the structure of the test apparatus provided with the function which diagnoses several modules. It is a block diagram which shows the structure of the test apparatus which concerns on embodiment. It is a flowchart which shows the operation | movement at the time of the diagnosis of the test apparatus of FIG. It is a part of flowchart which shows the operation | movement at the time of the diagnosis of the test apparatus of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 2 is a block diagram illustrating a configuration of the test apparatus 100 according to the embodiment.
The test apparatus 100 includes a plurality of n pin modules mod_pin-1 to mod_pin-n and a first logic gate 10.

  Each pin module mod_pin is a module having a plurality of I / O pins (Pio1 to Pion) of the test apparatus 100 as a unit. At least one of a driver (not shown) that outputs a test signal to the device under test and a timing comparator (not shown) that determines the level of the signal from the device under test is connected to the I / O pin. .

  As a result of diagnosing the i-th (1 ≦ i ≦ n) pin module mod_pin_i based on the diagnostic program, diagnostic data RDATA_pin_i is generated.

  Each of the pin modules mod_pin_1 to mod_pin_n includes a simultaneous read control unit 50. The simultaneous read control unit 50 includes an expected value comparison unit 20, a third logic gate 26, an expected value register 54, and a decoder 52. The third logic gate 26 will be described later.

  The expected value comparison unit 20 of the i-th pin module compares the diagnostic data RDATA_pin_i with the corresponding expected value data EXP_i ′. The diagnostic data RDATA_pin_i and the expected value data EXP_i ′ are multi-bit data (for example, 32 bits), and the expected value comparison unit 20 associates the diagnostic data RDATA_pin_i [31: 0] with the expected value data EXP_i ′ [31: 0]. The bits to be compared are compared to generate 32-bit comparison determination data CDATA_pin_i indicating the match or mismatch of each bit.

Specifically, the expected value comparison unit 20 includes an exclusive OR gate 22. The exclusive OR gate 22 generates an exclusive OR of corresponding bits of the diagnostic data RDATA_pin_i [31: 0] and the expected value data EXP_i ′ [31: 0], and compares the 32-bit comparison determination data CDATA_pin [31 : 0] is output.
The upper j-th bit of the comparison determination data RDATA_pin_i is “0” when the upper j-th bit of the diagnostic data RDATA_pin_i matches the upper j-th bit of the expected value data EXP_i ′, and “1” when they do not match.

  Thus, in each of the plurality of pin modules mod_pin_1 to mod_pin_n, the comparison determination data CDATA_pin_1 to CDATA_pin_n is generated and read out to the first logic gate 10.

  The first logic gate 10 generates a logical sum of a plurality of comparison determination data CDATA_pin_1 to CDATA_pin_n. The first logic gate 10 generates a logical sum of corresponding bits of 32-bit CDATA_pin_1 to CDATA_pin_n, and generates 32-bit final comparison determination data CDATA_mod_top [31: 0].

  The decoder 52 controls writing of expected value data to the expected value register 54. The decoder 52 receives an address IADR [23: 0] and a write command IWCMD. Based on these data, expected value data IWDATA [31: 0] is written to the expected value register 54.

  The decoder 52 is further input with pin enable data IPINEN. The decoder 52 generates enable data READ_EN based on the enable data IPINEN. The enable data READ_EN will be described later.

  The overall configuration of the test apparatus 100 has been described above.

Next, the operation will be described. FIG. 3 is a flowchart showing an operation at the time of diagnosis of the test apparatus 100 of FIG.
After starting the test system (S100) and initializing the test apparatus 100 (S102), diagnosis starts (S104) and test pattern generation starts (S106).

  Subsequently, the process proceeds to a diagnostic reading step (S108). In each pin module pin_mod, the comparison determination data CDATA_pin is generated, and the first logic gate 10 generates final comparison determination data CDATA_mod_top which is a logical sum of them. The diagnostic program (DIAG) of the test apparatus 100 refers to the final comparison determination data CDATA_mod_top. When all bits are “0”, the test apparatus 100 is determined to function normally (pass determination). When “1” indicating an error occurs in any of the bits, it is determined that an error has occurred in any of the pin modules, and the test apparatus 100 as a whole makes a fail determination.

  Thereafter, the flow is completed through a diagnosis end process (S110).

  According to the test apparatus 100 of FIG. 2, multiple modules are diagnosed and expected value comparisons are performed in parallel, and comparison determination data of the plurality of modules is logically operated, so that the plurality of modules can be simultaneously read by one reading. Can be diagnosed.

  Returning to FIG. 2, a more detailed configuration and other features of the test apparatus 100 will be described.

  The expected value comparison unit 20 includes a second logic gate 24. Each pin module is set with enable data READ_EN for setting whether or not the pin module mod_pin is a target for diagnostic reading. When enable data READ_EN is “1”, it is a diagnosis target, and when it is “0”, it is not a diagnosis target. The second logic gate 24 generates a logical product of the expected value data EXP_i set in the expected value register 54 and the enable data READ_EN.

  When the i-th pin module mod_pin_i is excluded from the diagnosis target, all bits of the diagnosis data RDATA_pin_i are set to 0. As a result, all the bits of the comparison determination data CDATA_pin_i of the pin module are zero. That is, the i-th pin module can be excluded from the reading target without affecting the logic operation of the first logic gate 10.

  FIG. 4 is a part of a flowchart showing an operation at the time of diagnosis of the test apparatus 100 of FIG. FIG. 4 shows the details of the diagnostic readout (S108) process of FIG.

  In each of the plurality of pin modules mod_pin_1 to mod_pin_n, enable data READ_EN is set to assert (1), and a pin module to be diagnosed is set (S200).

  Subsequently, expected value data EXP1 is set in the expected value register 54 (S202). Then, comparison determination data CDATA_pin is read from the pin module mod_pin to be diagnosed (S204). Subsequently, it is determined whether all the bits of the final comparison determination data CDATA_mod_top are 0 (S206). If true (Y in S206), a path determination is made (S208). If it is false (N in S206), a fail determination is made (S210).

  When a fail determination is made, a diagnostic read is performed for each pin module pin_mod to determine a pass fail (S212). This process is the same as steps S200 to S206. Specifically, the pass fail for each pin module can be determined by sequentially switching the pin module to be subjected to the read diagnosis from the 1st pin to the nth pin. As a result, it is possible to identify which pin module is defective.

Returning to FIG.
Each of the plurality of pin modules pin_mod is divided into a plurality of submodules smod_1-A to smod_1-D, smod_2, and smod_3. The submodule smod is assigned for each of a plurality of functions that the pin module has. For example, one submodule is a timing comparator and another submodule is a driver. In FIG. 2, the submodule smod_3 corresponds to the above-described simultaneous diagnosis readout function (simultaneous readout control unit 50).

  In the submodule smod, diagnostic data read_data [31: 0] (or rd_xxxx [31: 0]) indicating the diagnostic result is generated.

The third logic gate 26 generates a logical sum of the diagnosis data ORDATA_smod of the plurality of sub modules smod.
Each submodule smod includes a fourth logic gate 30 and a decoder 32. The decoder 32 generates enable data READ_EN for setting whether or not the submodule smod is to be diagnosed. The enable data is “1” when it is a diagnosis target, and “0” when it is not a target. The fourth logic gate 30 generates a logical product (diagnosis data ORDATA_smod) of the diagnosis data read_data and the enable data READ_EN of the submodule smod.

  That is, the submodule smod outputs valid diagnostic data ORDATA_smod when it is a diagnosis target, and outputs invalid (zero data) diagnostic data ORDATA_smod when it is a non-diagnosis target.

  The third logic gate 26 of the simultaneous reading control unit 50 generates a logical sum of the diagnostic data ORDATA_smod output from each submodule smod, and uses the logical sum as diagnostic data RDATA_pin of the pin module mod_pin to which the submodule smod belongs. When some diagnostic data is invalid (zero data), it does not affect the diagnostic data RDATA_pin and is ignored.

  According to this configuration, diagnosis for each submodule smod is possible.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  In the embodiment, the case where the simultaneous reading control unit 50 is provided for each pin module mod_pin has been described, but the present invention is not limited to this. For example, a simultaneous reading control unit 50 may be provided for each of a plurality of submodules (functional modules) smod to perform simultaneous reading.

It is understood by those skilled in the art that there are various variations in the signal processing described in the embodiments. For example, in the embodiment, the case has been described in which the comparison determination data CDATA_pin takes 0 when the expected value data EXP and the diagnostic data RDATA_pin match, and takes 1 when they do not match, but the reverse is also effective as an aspect of the present invention. is there.
That is, the first logic gate 10 may be an AND gate, and the comparison determination data CDATA_pin may be designed to be 1 when the expected value data EXP and the diagnostic data RDATA_pin match, and to be 0 when they do not match.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and arrangement changes are possible without departing from the scope.

DESCRIPTION OF SYMBOLS 10 ... 1st logic gate, 20 ... Expected value comparison part, 22 ... Exclusive OR gate, 24 ... 2nd logic gate, 26 ... 3rd logic gate, 30 ... 4th logic gate, 32 ... Decoder, 50 ... Simultaneously Read controller 52. Decoder 54 54 Expected value register 100 Test apparatus mod_pin Pin module smod Sub module

Claims (4)

A plurality of modules each including an expected value comparing unit that compares the diagnostic data indicating the diagnostic result with the corresponding expected value data, and outputting comparison determination data indicating the comparison result by the expected value comparing unit;
A first logic gate for generating a logical sum of comparison determination data of each of the plurality of modules;
Bei to give a,
The expected value comparison unit of each module includes a second logic gate that generates a logical product of control data for setting whether or not the module is to be diagnosed and the expected value data. A test apparatus for comparing output data with the diagnostic data . Each of the plurality of modules is
A plurality of submodules each outputting diagnostic data indicating the diagnostic result; and
A third logic gate for generating a logical sum of the diagnostic data of the plurality of submodules;
Each sub-module outputs the diagnostic data when it is a diagnostic object, outputs zero data when it is a non-diagnostic object, and the expected value comparison unit expects an output signal of the third logic gate. The test apparatus according to claim 1 , wherein the test apparatus is compared with value data.   A plurality of modules each including an expected value comparing unit that compares the diagnostic data indicating the diagnostic result with the corresponding expected value data, and outputting comparison determination data indicating the comparison result by the expected value comparing unit;
  A first logic gate for generating a logical sum of comparison determination data of each of the plurality of modules;
  With
  Each of the plurality of modules is
  A plurality of submodules each outputting diagnostic data indicating the diagnostic result; and
  A third logic gate for generating a logical sum of the diagnostic data of the plurality of submodules;
  Each sub-module outputs the diagnostic data when it is a diagnostic object, outputs zero data when it is a non-diagnostic object, and the expected value comparison unit expects an output signal of the third logic gate. Test apparatus characterized by comparing with value data. A test apparatus diagnostic method comprising a plurality of modules,
Performing a diagnosis on at least two modules for which common expectation data is expected;
Comparing each of diagnostic data indicating diagnostic results of the at least two modules with the common expected value data;
Generating a logical sum of comparison determination data indicating a comparison result of each module;
Determining a pass fail of the test apparatus based on the logical sum;
When the test apparatus is determined to fail, the step of individually diagnosing the at least two modules in order and determining a pass fail for each module;
A diagnostic method comprising:

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