JP6356544B2 - Information processing apparatus, memory inspection method, and program - Google Patents

Description

  The present invention relates to a memory inspection technique in an information processing apparatus.

  Various related techniques are known for memory inspection of information processing apparatuses.

  For example, Patent Document 1 discloses an example of a memory test apparatus. The memory test apparatus of Patent Document 1 includes an error information table, error information analysis means, memory test execution means, and error information recording means.

  In the error information table, error information including the type and error address of a memory error that occurred during the previous system startup and operation is recorded and stored in the local memory 30.

  The error information analysis means refers to the error information table when the system is started up and analyzes a memory error frequent occurrence area.

  The memory test execution means performs a memory test using a preset test pattern only in the memory error occurrence area and the area where the operating system is loaded.

  The error information recording means records the generated error information in the error information table.

  Patent Document 1 states that the memory test apparatus having the above-described configuration realizes a memory test method at system startup that can be executed in a short time even when the memory capacity is greatly increased.

  Patent Document 2 discloses an example of an inspection apparatus. The inspection apparatus of Patent Document 2 includes a control unit, an HDD (Hard disk drive), a LAN (Local Area Network) interface, and the like.

  The control unit controls each function of a PC (Personal Computer) inspection apparatus. Specifically, when the connection between the communication means of the personal computer and the LAN interface is detected, the control unit causes the personal computer to execute an inspection program including a plurality of inspection processes. Further, the control unit takes in the inspection result by the execution of the inspection program via the LAN interface and stores it in the HDD.

  Patent Document 2 states that the memory test apparatus having the above-described configuration can reduce the burden on the inspector, shorten the inspection work time, and prevent erroneous determination of the inspection result.

JP-A-11-259374 JP 2002-268913 A

  However, the technique described in the above-described prior art document has a problem that work efficiency is low when operations are confirmed for a plurality of memory operation modes of the information processing apparatus.

  The reason is as follows.

  In recent years, the capacity of a single memory module (for example, a DIMM (Dual Inline Memory Module)) has increased. Therefore, the time required for initialization of an information processing apparatus equipped with the memory module has increased. The types of memory operating modes are increasing.

  On the other hand, the operation mode of the memory is changed by an operator in, for example, a BIOS (Basic Input / Output System) Setup Menu. Therefore, the operator is restrained for a change operation of the memory operation mode for a long time. Further, manual intervention generally increases the possibility of incurring a reduction in efficiency, such as making a mistake or taking a long time to operate.

  However, both of the techniques described in Patent Document 1 and Patent Document 2 described above have the problem of improving the efficiency related to the operation confirmation of the information processing apparatus for a plurality of memory operation modes (reducing the operation confirmation time). It cannot be solved.

  That is, the technique disclosed in Patent Document 1 is a technique for shortening the test time by limiting the memory area where the test is performed.

  Further, the technique disclosed in Patent Document 2 is a technique for inspecting a personal computer via a LAN interface.

  That is, neither Patent Document 1 nor Patent Document 2 discloses a technique for changing the memory operation mode without human intervention.

  An object of the present invention is to provide an information processing apparatus, a memory inspection method, and a program that can solve the above-described problems.

  An information processing apparatus according to one aspect of the present invention updates a plurality of memory operation mode execution histories that specify a mode for operating a memory, and determines and determines the memory operation mode based on the execution history. The execution history is retained, including an operation mode determining means for setting the mode specified in the memory operation mode as a means for operating the memory, and a period in which the external power supply is cut off. Execution history storage means, and memory test means for executing a test of the memory.

  According to another aspect of the present invention, there is provided a memory test method for determining a memory operation mode based on an execution history of a plurality of memory operation modes, in which a computer including a nonvolatile storage means specifies a mode in which the memory is operated. The mode specified by the determined memory operation mode is set in a means for operating the memory, the test of the memory is executed, the execution history is updated, and the execution history is stored in the nonvolatile memory Record on means.

  A program according to an embodiment of the present invention determines a memory operation mode based on execution history of a plurality of memory operation modes, which specifies a mode in which a computer including a nonvolatile storage means operates a memory. The mode specified in the memory operation mode is set in a means for operating the memory, the test of the memory is executed, the execution history is updated, and the execution history is stored in the nonvolatile storage means. Execute the recording process.

  The present invention has an effect of improving the efficiency of operation confirmation for a plurality of memory operation modes of the information processing apparatus.

FIG. 1 is a block diagram showing the configuration of the memory test apparatus according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a memory operation mode table in the first embodiment. FIG. 3 is a diagram illustrating an example of a counter according to the first embodiment. FIG. 4 is a block diagram illustrating a configuration of the information processing apparatus including the memory test apparatus according to the first embodiment. FIG. 5 is a flowchart showing the operation of the memory test apparatus according to the first embodiment. FIG. 6 is a flowchart showing the operation of the information processing apparatus of the related art. FIG. 7 is a block diagram showing a configuration of a memory test apparatus according to the second embodiment of the present invention. FIG. 8 is a block diagram showing a configuration of an information processing apparatus including the memory test apparatus according to the second embodiment. FIG. 9 is a flowchart showing the operation of the memory test apparatus according to the second embodiment. FIG. 10 is a flowchart showing the operation of the memory test apparatus according to the second embodiment. FIG. 11 is a block diagram showing a configuration of a memory test apparatus according to the third embodiment of the present invention. FIG. 12 is a diagram illustrating an example of a result table according to the third embodiment. FIG. 13 is a block diagram illustrating a configuration of an information processing apparatus including a memory test apparatus according to the third embodiment. FIG. 14 is a flowchart showing the operation of the memory test apparatus according to the third embodiment. FIG. 15 is a block diagram showing a configuration of a memory test apparatus according to the fourth embodiment of the present invention.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings. In each embodiment described in each drawing and specification, the same reference numerals are given to the same components, and the description thereof is omitted as appropriate.

<<<< first embodiment >>>>
FIG. 1 is a block diagram showing a configuration of a memory test apparatus (also called an information processing apparatus) 100 according to the first embodiment of the present invention.

  As shown in FIG. 1, the memory test apparatus 100 according to the present embodiment includes an operation mode determination unit 110, an execution history storage unit 120, and a memory test unit 130.

  Next, each component provided in the memory test apparatus 100 in the first embodiment will be described. Each component shown in FIG. 1 may be a hardware unit circuit, a module included in a microchip, or a component divided into functional units of a computer device. Here, the components shown in FIG. 1 will be described as components divided into functional units of the computer apparatus.

=== Operation Mode Determination Unit 110 ===
The operation mode determination unit 110 updates execution histories for a plurality of memory operation modes that specify the manner in which the memory is operated. Specifically, the operation mode determination unit 110 counts up (adds “1”) a count value (also referred to as an execution history) of a counter 810 described later.

  Further, the operation mode determination unit 110 determines a memory operation mode based on the execution history, and sets the mode specified by the determined memory operation mode in a means (not shown) for operating the memory. To do. Specifically, the operation mode determination unit 110 determines the content of the record 821 included in a memory operation mode table 820, which will be described later, with the count value as a mode identifier as the memory operation mode. Here, the count value is a count value of a counter 810, which will be described later, stored in the execution history storage unit 120. Subsequently, the operation mode determination unit 110 sets the mode specified in the memory operation mode in a means (not shown) for operating the memory.

  Since the technique for setting the mode for operating the memory to the means for operating the memory is a well-known technique, detailed description thereof is omitted.

  After that, setting the mode specified by the memory operation mode to the means for operating the memory, “setting the memory operation mode”, “setting the memory operation mode”, “the The description is omitted such as “memory operation mode is set”.

=== Memory Operation Mode Table 820 ===
FIG. 2 is a diagram illustrating an example of the memory operation mode table 820. As shown in FIG. 2, the memory operation mode table 820 includes a plurality of records 821 including a mode identifier, voltage, frequency, mode 1 and mode 2. The memory operating mode includes the voltage, the frequency, the mode 1 and the mode 2 as the mode.

  The mode identifier is a hexadecimal numerical value assigned to each record 821 in ascending order.

  The voltage is a voltage of a power source supplied to the memory for operating the memory. For example, when the memory is a DIMM (Dual Inline Memory Module), the voltage is also referred to as a DIMM voltage.

  The frequency is a frequency of a clock supplied to the memory for operating the memory. The frequency is also called a DIMM frequency when the memory is a DIMM, for example.

  Mode 1 and mode 2 are memory control modes in the control circuit for operating the memory. The control mode is, for example, a lockstep memory mode, an independent mode, a performance mode, a rank sparing mode, a mirrored channel mode, or the like.

  Since the above-described voltage, frequency, and memory control mode are well-known techniques, a detailed description thereof will be omitted.

  The operation mode determination unit 110 may assign each mode of the memory operation mode to the bit position of the count value. Specifically, bit 0 is voltage mode (1.5 volts for 0, 1.35 volts for 1), Bit 1 is performance mode (independent mode for 0, performance for 1) Mode). In this case, the memory operation mode table 820 is not necessary.

=== Counter 810 ===
FIG. 3 is a diagram illustrating an example of the structure of the counter 810. As shown in FIG. 3, the counter 810 includes, for example, an 8-bit hexadecimal count value. The count value included in the counter 810 is the execution history.

  Specifically, the count value corresponds to the mode identifier in the memory operation mode table 820 shown in FIG. For example, the count value indicates that the memory operation mode of the record 821 that includes a value less than the count value as a mode identifier is the memory operation mode set by the operation mode determination unit 110.

  Here, the execution history may be a pointer to each record 821 of the memory operation mode table 820, for example. In this case, each record 821 may not include a mode identifier. In this case, the pointer indicates that the memory operation mode of the record 821 corresponding to the pointer less than the pointer is the memory operation mode set by the operation mode determination unit 110.

  The execution history may be a flag indicating whether or not the memory operation mode of the record 821 corresponding to each record 821 of the memory operation mode table 820 has been set by the operation mode determination unit 110. In this case, each record 821 may not include a mode identifier. Each record 821 may include the flag.

  Regardless of the above-described example, the execution history may be information in an arbitrary format indicating whether or not each memory operation mode is set by the operation mode determination unit 110.

=== Execution History Storage Unit 120 ===
The execution history storage unit 120 stores a counter 810 as shown in FIG. The execution history storage unit 120 holds the execution history (count value of the counter 810 shown in FIG. 2) including a period in which the external power supply is cut off. Specifically, the execution history storage unit 120 may be an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash memory. The execution history storage unit 120 may be a DRAM (Dynamic Random Access Memory) backed up by a battery, a magnetic storage medium, or the like.

  Regardless of the above-described example, the execution history storage unit 120 may be any nonvolatile storage unit.

=== Memory Test Unit 130 ===
The memory test unit 130 executes a test of the memory. Here, the memory is composed of, for example, a DIMM or SDRAM (Synchronous Dynamic Random Access Memory).

  The test includes the following operations. In the first operation, “0 (zero)” data is written to all addresses in the memory. The second operation writes a specific value for each address in the memory. In the third operation, the written value is read to check whether it is an expected value. The third operation may be omitted to shorten the test time. Since the memory test is a well-known technique, a detailed description thereof is omitted.

  This completes the description of each component of the functional unit of the memory test apparatus 100.

  Next, the components of the hardware unit of the memory test apparatus 100 will be described.

  FIG. 4 is a diagram illustrating a hardware configuration of the information processing apparatus 101 including the memory test apparatus 100 according to the present embodiment.

  As shown in FIG. 4, the information processing apparatus 101 includes a CPU (Central Processing Unit) 710, a control LSI (Large Scale Integration) 730, a Bmchw (Baseboard Management Controller Hardware) 740, a nonvolatile storage unit 770, a memory controller 78. 782.

  The CPU 710 is a central processing unit of the information processing apparatus 101. The CPU 710 operates the BIOS 720 to control the overall operation of the information processing apparatus 101. Here, the BIOS 720 is a program for causing the information processing apparatus 101 to execute an operation of a flowchart shown in FIG.

  Then, the CPU 710 executes various processes as the operation mode determination unit 110 and the memory test unit 130 illustrated in FIG. 1 according to the BIOS 720.

  The control LSI 730 controls access to the Bmchw 740 and the nonvolatile storage unit 770 by the CPU 710.

  The Bmchw 740 is hardware for managing the information processing apparatus 101. Bmchw 740 has a processor. The Bmcfw (Baseboard Management Controller Firmware) 750 operates on this processor, thereby realizing a function as a BMC (Baseboard Management Controller). Each of Bmchw and Bmcfw may be referred to as a service processor and service firmware.

  The Bmchw 740 may include a non-volatile storage unit (not shown), and the non-volatile storage unit may include the execution history storage unit 120. In this case, the nonvolatile storage unit 770 is not necessary.

  The nonvolatile storage unit 770 includes an execution history storage unit 120 that stores a counter 810.

  The memory controller 781 controls access to the memory 782 by the CPU 710.

  The memory 782 includes the above-described memory to be controlled by the memory test apparatus 100.

  The information processing apparatus 101 may include a storage device (for example, a hard disk), an input unit (for example, a keyboard or a mouse), an output unit (for example, a display), a communication unit (for example, a network controller), etc., not shown. .

  That is, the information processing apparatus 101 may be a server, a computer, a communication control apparatus, or the like. Such a general structure and function in the information processing apparatus 101 are well-known techniques, and thus detailed description thereof is omitted.

  The above is an explanation of each hardware component of the information processing apparatus 101 including the memory test apparatus 100 according to this embodiment.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings.

  FIG. 5 is a flowchart showing the operation of the memory test apparatus 100 of the present embodiment. The process according to this flowchart may be executed based on the control of the BIOS 720 by the CPU 710 described above. Further, the step name of the process is described by a symbol as in S601.

  FIG. 5 shows a flowchart when the memory test apparatus 100 operates as part of the information processing apparatus 101. Here, since the operation of the information processing apparatus 101 (for example, initialization of the control LSI 730 and Bmchw 740) other than the operation related to the memory test apparatus 100 is a well-known technique, description and description thereof are omitted.

  The memory test apparatus 100 starts the operation of the flowchart shown in FIG. 5 when power is supplied (power on).

  The operation mode determination unit 110 determines a memory operation mode based on the count value of the counter 810 and the memory operation mode table 820, and sets the memory operation mode (step S611).

  Next, the operation mode determination unit 110 adds “1” to the count value of the counter 810 (step S612).

  Next, the memory test unit 130 executes a test of the memory 782 (step S613).

  Next, the memory test unit 130 determines whether or not an error is detected in the test (step S614).

  If an error is detected (YES in step S614), the memory test unit 130 outputs error information indicating the content of the error (step S615). Thereafter, the process ends.

  If no error is detected (NO in step S614), the process ends.

  After the operation of the flowchart shown in FIG. 5 ends, when the power to the memory test apparatus 100 is turned off and the power is turned on again, the operation mode determination unit 110 executes the process of the flowchart shown in FIG. 5 again. . At this time, the operation mode determination unit 110 executes the processing from step S611 onward based on the count value of the counter 810 updated (added by “1”) in step S612 of the previous operation.

  In other words, each time the power is turned on, the memory test apparatus 100 executes a memory test in the memory operation mode corresponding to the updated execution history.

  Note that the power-off / on control is instructed to the information processing apparatus 101 from an external apparatus. The operator may turn off / on the power.

  In addition, the information processing apparatus 101 may be rebooted after the processing illustrated in FIG.

  The above is the description of the operation of the present embodiment.

  In order to compare with the operation of the present embodiment, the operation of the information processing apparatus of the related technology to which the present invention is not applied will be described.

  FIG. 6 is a flowchart showing the operation of the information processing apparatus of the related technology to which the present invention is not applied.

  The BIOS 720 sets the memory operation mode based on the set value of the memory operation mode held in the non-volatile storage unit (not shown) of the Bmchw 740 (step S661).

  Next, the BIOS 720 executes a test of the memory 782 (step S613).

  Next, the BIOS 720 determines whether or not an error is detected in the test (step S614).

  If an error is detected (YES in step S614), the BIOS 720 outputs error information indicating the content of the error (step S615).

  If no error is detected (NO in step S614), the process proceeds to step S666.

  Next, the BIOS 720 determines whether or not there is an instruction to start the Setup Menu by the operator (step S666).

  If there is an instruction to start up the Setup Menu (YES in step S666), the BIOS 720 changes the above-described memory operation mode based on the instruction from the operator (step S667). Thereafter, the process ends.

  If there is no instruction for launching the Setup Menu (NO in step S666), the process ends.

  After the operation of the flowchart shown in FIG. 6 is completed, when the power to the related information processing apparatus is turned off and the power is turned on again, the BIOS 720 executes the process of the flowchart shown in FIG. 6 again. At this time, the BIOS 720 executes the processing from step S661 onward based on the changed memory operation mode in step S667 of the previous operation.

  As described above, when the operation is confirmed for a plurality of memory operation modes, if the present invention is not applied, an operation by the operator (setup menu activation instruction and memory operation mode change) is required. In particular, since an instruction for starting up the Setup Menu is accepted only when the information processing apparatus 101 is started up, the operator needs to spend a long time to confirm the operation.

In addition, after the processing of the flowchart illustrated in FIG. 6 is completed, the OS of the related information processing apparatus may be started and a diagnosis program for the related information processing apparatus may be executed. In this case, in order to change the memory operation mode, the power of the related information processing apparatus must be turned off / on and the processing of the flowchart shown in FIG. 6 must be performed.
Thereafter, it is necessary to turn off / on the power of the related information processing apparatus again and start up in the changed memory operation mode.

  The above is description of operation | movement of the information processing apparatus of related technology to which this invention is not applied.

  This embodiment is applied as follows, for example. When the operation is confirmed for a plurality of memory operation modes, the BIOS 720 that executes the operation of the present embodiment is implemented in the information processing apparatus 101. When the information processing apparatus 101 is normally operated, a BIOS 720 to which the present embodiment is not applied is implemented in the information processing apparatus 101.

  The first effect of the present embodiment described above is that it is possible to improve the efficiency of operation confirmation for a plurality of memory operation modes of the information processing apparatus 101.

  The reason is that the operation mode determination unit 110 determines the memory operation mode based on the count value of the counter 810 stored in the execution history storage unit 120 and sets the memory operation mode.

  Therefore, an operation by the operator for changing the memory operation mode is unnecessary. Further, unlike the related art information processing apparatus, it is not necessary to restart the related information processing apparatus in order to change the memory operation mode.

<<< Modification of First Embodiment >>>
When an error is detected in step S614, the operation mode determination unit 110 subtracts “1” from the count value of the counter 810. That is, the operation mode determination unit 110 returns the execution history to the previous value.

  In other words, when the memory test unit 130 detects an error, the operation mode determination unit 110 updates the execution history so as to indicate that the test in the memory operation mode in which the error is detected is not performed. .

  The memory test apparatus 100 may further include means for instructing whether or not to execute the process of subtracting “1” from the count value.

  The effect of the above-described modification of the present embodiment is that it becomes possible to confirm error reproducibility.

  This is because the operation mode determination unit 110 sets the count value for determining the memory operation mode at the next startup to the same value as at the current startup.

<<< Second Embodiment >>>
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, the description overlapping with the above description is omitted as long as the description of the present embodiment is not obscured.

  FIG. 7 is a block diagram showing a configuration of a memory test apparatus 200 according to the second embodiment of the present invention.

  As shown in FIG. 7, the memory test apparatus 200 according to this embodiment is different from the memory test apparatus 100 according to the first embodiment in that it further includes a determination instruction unit 240 and an operation mode change unit 250. Further, the memory test apparatus 200 differs from the memory test apparatus 100 in the operation of the operation mode determination unit 110.

=== Decision Instructing Unit 240 ===
The determination instruction unit 240 instructs whether or not it is necessary to determine the memory operation mode based on the count value of the counter 810.

  In other words, the determination instruction unit 240 is either when confirming the operation for a plurality of memory operation modes (the instruction is necessary) or when the information processing apparatus 101 is normally operated (the instruction is not). Indicates.

=== Operation Mode Changing Unit 250 ===
The operation mode changing unit 250 changes the memory operation mode based on an instruction from the operator.

  The operation mode changing unit 250 maintains the memory operation mode including a period in which the external power supply is cut off. The operation mode change unit 250 records the memory operation mode in the nonvolatile storage unit 770, for example. Further, the operation mode changing unit 250 may record the memory operation mode in a nonvolatile storage unit (not shown) in the Bmchw 740.

=== Operation Mode Determination Unit 110 ===
The operation mode determination unit 110 determines the memory operation mode based on the count value (execution history) of the counter 810 when the determination instruction unit 240 needs to be instructed.

  The operation mode determination unit 110 initializes the count value of the counter 810 (sets it to “0”) when the determination instruction unit 240 does not indicate necessity. Then, the operation mode determination unit 110 sets the mode specified by the memory operation mode changed by the operation mode change unit 250 as a unit for operating the memory 782.

  This completes the description of each component of the functional unit of the memory test apparatus 200.

  Next, components in hardware units of the memory test apparatus 200 will be described.

  FIG. 4 is a diagram illustrating a hardware configuration of the information processing apparatus 201 including the memory test apparatus 200 according to the present embodiment.

  As illustrated in FIG. 4, the information processing apparatus 201 is different from the information processing apparatus 101 illustrated in FIG. 4 in that it further includes a Switch 760.

=== Switch 760 ===
The Switch 760 implements the determination instruction unit 240 illustrated in FIG. The Switch 760 is, for example, a DIP (Dual In-line Package) Switch. The Switch 760 may be a rotary switch.

  Note that the determination instruction unit 240 may be realized by, for example, Bmcfw750. In this case, the Bmcfw 750 may store the necessity described above in, for example, a nonvolatile storage unit (not shown) of the Bmchw 740.

  In the present embodiment, the BIOS 720 is a program for causing the information processing apparatus 201 to execute operations of flowcharts illustrated in FIGS. 9 and 10 to be described later, for example.

  Then, the CPU 710 executes various processes as the operation mode determination unit 110 and the memory test unit 130 illustrated in FIG. 7 according to the BIOS 720.

  The above is a description of each component of the information processing apparatus 201 including the memory test apparatus 200 in this embodiment in units of hardware.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings.

  FIG. 9 is a flowchart showing the operation of the memory test apparatus 200 of the present embodiment.

  FIG. 9 shows a flowchart when the memory test apparatus 200 operates as a part of the information processing apparatus 201.

The operation mode determination unit 110 confirms the instruction from the determination instruction unit 240 (step S621).
If the instruction is “necessary” (YES in step S621), operation mode determination unit 110 determines a memory operation mode based on the count value of counter 810 and memory operation mode table 820, and determines the memory operation mode. Setting is made (step S611).

  Next, the operation mode determination unit 110 adds “1” to the count value of the counter 810 (step S612). Thereafter, the process proceeds to step S613.

  If the instruction is “NO” (NO in step S641), operation mode determination unit 110 initializes the count value of counter 810 (step S622).

  Next, the operation mode determination unit 110 sets the memory operation mode held by the operation mode change unit 250 (step S623).

  Next, the memory test unit 130 executes a test of the memory 782 (step S613).

  Next, the memory test unit 130 determines whether or not an error is detected in the test (step S614).

  If an error is detected (YES in step S614), the memory test unit 130 outputs error information indicating the content of the error (step S615).

  If no error is detected (NO in step S614), the process proceeds to step S624.

  Next, the operation mode determination unit 110 determines whether or not there is an instruction to start the Setup Menu by the operator (Step S624).

  If there is an instruction to start up the Setup Menu (YES in step S624), the operation mode determination unit 110 changes the memory operation mode described above based on the operator's instruction (step S625). Thereafter, the process ends.

  If there is no instruction to start up the Setup Menu (NO in step S624), the process ends.

  The above is the description of the operation of the present embodiment.

  The first effect of the present embodiment described above is easily switched between the case of checking the operation for a plurality of memory operation modes and the case of operating the information processing apparatus 101 in addition to the effect of the first embodiment. This is where it becomes possible.

  The reason is that the determination instruction unit 240 instructs whether or not it is necessary to determine the memory operation mode based on the count value of the counter 810.

<<< Third Embodiment >>>
Next, a third embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, the description overlapping with the above description is omitted as long as the description of the present embodiment is not obscured.

  FIG. 11 is a block diagram showing a configuration of a memory test apparatus 300 according to the third embodiment of the present invention.

  As illustrated in FIG. 11, the memory test apparatus 300 according to the present embodiment is different from the memory test apparatus 100 according to the first embodiment in that it further includes a result storage unit 360. In addition, the memory test apparatus 300 differs from the memory test apparatus 100 in the operation of the operation mode determination unit 110 and the memory test unit 130.

=== Result Storage Unit 360 ===
The result storage unit 360 stores a result table 830 as shown in FIG. The result storage unit 360 holds the result table 830 including a period in which the external power supply is cut off. Specifically, the result storage unit 360 may be an EEPROM, a flash memory, a DRAM backed up by a battery, a magnetic storage medium, or the like.

  Regardless of the above-described example, the result storage unit 360 may be any nonvolatile storage unit.

=== Result Table 830 ===
FIG. 12 is a diagram illustrating an example of the result table 830. As illustrated in FIG. 12, the result table 830 includes a record 831. The record 831 includes a start time, an end time, an error content, and a memory operation mode.

  The start time and the end time are respectively the start time and the end time of the process shown in FIG.

  The error content is information indicating the content of the error of S when the result of the memory test is an error.

  The memory operation mode is a memory operation mode corresponding to the start time and the end time. The memory operation mode may be information specifying the memory operation mode, such as a memory operation mode identifier or a pointer to the corresponding record 821 in the memory operation mode table 820.

  Regardless of the above example, the result table 830 may store at least the error content and any other information.

=== Operation Mode Determination Unit 110 ===
The operation mode determination unit 110 may record the start time and the end time in the result storage unit 360. Furthermore, the operation mode determination unit 110 may record information specifying the memory operation mode in the result storage unit 360.

=== Memory Test Unit 130 ===
The memory test unit 130 records at least the error content in the result storage unit 360. Further, the memory test unit 130 may record information in the result storage unit 360 that the result of the memory test is normal.

  This completes the description of each component of the functional unit of the memory test apparatus 300.

  Next, the components of the hardware unit of the memory test apparatus 300 will be described.

  FIG. 14 is a diagram illustrating a hardware configuration of the information processing apparatus 301 including the memory test apparatus 300 according to the present embodiment.

  As illustrated in FIG. 14, the information processing apparatus 301 further includes a result storage unit 360 that stores a result table 830 in the nonvolatile storage unit 770.

  In the present embodiment, the BIOS 720 is a program for causing the information processing apparatus 301 to execute an operation of a flowchart shown in FIG.

  Then, the CPU 710 executes various processes as the operation mode determination unit 110 and the memory test unit 130 illustrated in FIG. 11 according to the BIOS 720.

  The above is an explanation of each hardware component of the information processing apparatus 101 including the memory test apparatus 100 according to this embodiment.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings.

  FIG. 14 is a flowchart showing the operation of the memory test apparatus 300 of this embodiment.

  FIG. 14 shows a flowchart when the memory test apparatus 300 operates as a part of the information processing apparatus 301.

  The operation mode determination unit 110 records the current time as a start time in the result table 830 (step S631). Here, the operation mode determination unit 110 may acquire the current time from, for example, clock means (not shown) mounted on the Bmchw 740, for example.

  The operations from step S611 to step S615 are the same as the operations shown in FIG.

  Next, the memory test unit 130 records the result of the memory test in the result table 830 (step S632).

  Next, the operation mode determination unit 110 adds “1” to the count value of the counter 810 (step S612).

  Next, the operation mode determination unit 110 records the current time as the end time in the result table 830 (step S633). Thereafter, the process ends.

The above is the description of the operation of the present embodiment.
The result table 830 may be displayed on output means (for example, a display) (not shown) of the information processing apparatus 301. Alternatively, the result table 830 may be read by the Bmcfw 750 and output as a text data file or a binary data file.

In addition to the effect of the first embodiment, the first effect in the present embodiment described above can facilitate the result confirmation in the operation confirmation for the plurality of memory operation modes of the information processing apparatus 301. Is a point.
The second effect of the present embodiment described above is to detect and analyze some error characteristic (such as high error occurrence frequency when the DIMM / SDRAM voltage is 1.5 V) existing in the information processing apparatus 301 (for example, intermittent failure). Or a fixed failure).

  The reason for these effects is that the result storage unit 360 stores the result table 830.

<<< Fourth Embodiment >>>
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, the description overlapping with the above description is omitted as long as the description of the present embodiment is not obscured.

  FIG. 15 is a block diagram showing a configuration of a memory test apparatus 400 according to the fourth embodiment of the present invention.

  As shown in FIG. 15, a memory test apparatus 400 according to the present embodiment is a combination of the memory test apparatus 200 according to the second embodiment and the memory test apparatus 300 according to the third embodiment.

  The operation mode determination unit 110 of the memory test apparatus 400, when an instruction to determine whether the determination instruction unit 240 is necessary or not, includes information specifying the start time, the end time, and the memory operation mode, as a result storage unit 360. May be recorded.

  The memory test unit 130 of the memory test apparatus 400, when an instruction of necessity of the decision instruction unit 240 is necessary, at least information about the error and information that the result of the memory test is normal, optionally result Record in the storage unit 360.

  The effects in the present embodiment described above include the effects of the second embodiment and the third embodiment.

  Each of the second to fourth embodiments may be applied with the modification shown in the modification of the first embodiment.

  Each component described in each of the above embodiments does not necessarily have to be individually independent. For example, a plurality of arbitrary constituent elements may be realized as one module. Any one of the constituent elements may be realized by a plurality of modules. Further, any one of the components may be any other one of the components. Further, any one part of the constituent elements may overlap with any other part of the constituent elements.

  In the embodiments described above, each component and a module that realizes each component may be realized as hardware as necessary. Moreover, each component and the module which implement | achieves each component may be implement | achieved by a computer and a program. Each component and a module that realizes each component may be realized by a mixture of a hardware module, a computer, and a program.

  The program is recorded on a computer-readable non-transitory recording medium such as a magnetic disk or a semiconductor memory, and provided to the computer. The program is read from the non-transitory recording medium by the computer when the computer is started up. The read program causes the computer to function as a component in each of the above-described embodiments by controlling the operation of the computer.

  Further, in each of the embodiments described above, a plurality of operations are described in order in the form of a flowchart, but the described order does not limit the order in which the plurality of operations are executed. For this reason, when each embodiment is implemented, the order of the plurality of operations can be changed within a range that does not hinder the contents.

  Furthermore, in each embodiment described above, a plurality of operations are not limited to being executed at different timings. For example, other operations may occur during execution of an operation. In addition, the execution timing of one operation and another operation may partially or entirely overlap.

  Further, in each of the embodiments described above, it is described that a certain operation becomes a trigger for another operation, but the description does not limit the relationship between the certain operation and another operation. For this reason, when each embodiment is implemented, the relationship between the plurality of operations can be changed within a range that does not hinder the contents. The specific description of each operation of each component does not limit each operation of each component. For this reason, each specific operation | movement of each component may be changed in the range which does not cause trouble with respect to a functional, performance, and other characteristic in implementing each embodiment.

  Although the present invention has been described with reference to each embodiment, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 Memory test apparatus 101 Information processing apparatus 110 Operation mode determination part 120 Execution history memory | storage part 130 Memory test part 200 Memory test apparatus 201 Information processing apparatus 240 Determination instruction | indication part 250 Operation mode change part 300 Memory test apparatus 301 Information processing apparatus 360 Result storage Part 400 memory test device 710 CPU
720 BIOS
730 Control LSI
740 Bmchw
750 Bmcfw
760 Switch
770 Nonvolatile storage unit 781 Memory controller 782 Memory 810 Counter 820 Memory operation mode table 821 record 830 Result table 831 record

Claims (9)

Update the execution history for multiple memory operating modes that identify the way in which the memory is operating,
An operation mode determining means for determining the memory operation mode based on the execution history, and setting the mode specified in the determined memory operation mode in a means for operating the memory;
Execution history storage means for holding the execution history, including a period in which the external power supply is cut off,
An information processing apparatus comprising: memory test means for executing a test of the memory. The operation mode determination means initializes the execution history when the execution history indicates that each of the plurality of memory operation modes has been set at least once. 1. An information processing apparatus according to 1. A determination instruction means for instructing whether or not it is necessary to determine the memory operation mode based on the execution history;
An operation mode changing means for changing the memory operation mode based on an instruction from an operator and holding the memory operation mode, including a period in which power supply from outside is cut off,
The operation mode determining means includes
When the necessity instruction of the determination instruction means is necessary, the memory operation mode is determined based on the execution history,
When the determination instruction means is not required, the execution history is initialized, and the mode specified by the memory operation mode updated by the operation mode change means is used to operate the memory. The information processing apparatus according to claim 1, wherein the information processing apparatus is set to a means. Including a result storage means for holding a test result by the memory test means, including a period in which the external power supply is cut off,
4. The information processing apparatus according to claim 1, wherein the memory test unit writes the test result in the result storage unit. 5. The operation mode determination unit updates the execution history to indicate that the test in the memory operation mode in which the error is detected is not performed when the memory test unit detects an error. The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus. A computer comprising non-volatile storage means
Determining the memory operation mode based on a plurality of execution history for the memory operation mode, which specifies a manner of operating the memory;
Setting the mode specified by the determined memory operation mode to the means for operating the memory;
Performing a test of the memory;
A memory inspection method for updating the execution history and recording the execution history in the nonvolatile storage means. The computer is
Changing the memory operation mode based on an operator's instruction, recording the memory operation mode in the nonvolatile storage means,
If it is necessary to determine whether or not to determine the memory operation mode based on the execution history, determine the memory operation mode based on the execution history;
If the necessity instruction is negative, the execution history is initialized, and the mode specified by the memory operation mode recorded in the nonvolatile storage means is set in the means for operating the memory. The memory inspection method according to claim 6. A computer including non-volatile storage means;
Determining the memory operation mode based on a plurality of execution history for the memory operation mode, which specifies a manner of operating the memory;
Setting the mode specified by the determined memory operation mode to the means for operating the memory;
Performing a test of the memory;
A program for executing a process of updating the execution history and recording the execution history in the nonvolatile storage means. In the computer,
Changing the memory operation mode based on an operator's instruction, recording the memory operation mode in the nonvolatile storage means,
If it is necessary to determine whether or not to determine the memory operation mode based on the execution history, determine the memory operation mode based on the execution history;
Processing for initializing the execution history and setting the format specified by the memory operation mode recorded in the nonvolatile storage means in the means for operating the memory when the necessity instruction is negative The program according to claim 8, wherein the program is executed.

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