JP5745125B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device.

  Display devices using liquid crystals are actively applied to products that take advantage of their low power consumption and thinness as one of flat panel displays that replace CRTs.

  Liquid crystal displays (LCDs) include simple matrix LCDs and TFT-LCDs that use thin film transistors (TFTs) as switching elements. TFT-LCDs are superior to CRTs and simple matrix LCDs in terms of portability and display quality, and are widely put into practical use in notebook personal computers and the like. In general, in a TFT-LCD, a liquid crystal layer is sandwiched between a TFT array substrate in which TFTs are formed in an array and a counter substrate. A polarizing plate is provided outside the TFT array substrate and the counter substrate, and a light source is provided on one side. With such a configuration, a good display can be obtained on the TFT-LCD.

  In addition to a transmissive type that displays an image by transmitting light from a backlight built in as a light source, a TFT-LCD includes a reflective type that displays an image by reflecting light incident from the outside with a reflector. is there. In addition, the TFT-LCD includes a transflective type having both functions of a transmissive type and a reflective type. A transflective liquid crystal display device uses external light reflection when ambient light is bright, and uses backlight when it is dark, so it can obtain good display characteristics in both indoor and outdoor environments. it can. In recent years, with the increase in mobile display devices, there is a great demand for transflective TFT-LCD panels for small displays such as mobile phones and portable music players, and medium-sized displays such as portable video players, PDAs and car navigation systems. It has become to.

  In the TFT-LCD, when manufacturing a TFT array substrate, it is necessary to form TFTs in an array on a glass substrate using a semiconductor technology, which requires a large number of processes. Therefore, there is a problem that the number of devices required for manufacturing increases and the manufacturing cost increases. In particular, in a transflective TFT-LCD, it is necessary to form both a reflective pixel electrode and a transmissive pixel electrode. Therefore, the number of processes is increased compared to a normal transmissive TFT-LCD and a reflective TFT-LCD, and the manufacturing cost is increased. Will increase.

  Thus, for example, Patent Document 1 discloses a technique for reducing the number of photomasks used for manufacturing a TFT array substrate of a transflective TFT-LCD. In Patent Document 1, the reflection pixel electrode and the transmission pixel electrode of the pixel electrode are formed by one photolithography using a halftone exposure technique. Accordingly, in Patent Document 1, a TFT array substrate that has been conventionally formed by six photolithography processes can be formed by five photolithography processes, and the number of photomasks can be reduced.

JP 2005-215277 A

  When the reflective pixel electrode and the transmissive pixel electrode are formed by a single photolithography by the method of Patent Document 1, after forming the transparent conductive layer to be the transmissive pixel electrode and the reflective metal layer to be the reflective pixel electrode, First, a resist pattern having a film thickness difference is formed. The reflective metal layer is etched using the resist pattern having this film thickness difference as a mask. Next, the thin film portion of the resist pattern having a film thickness difference is removed by oxygen plasma treatment. Thereafter, the transparent conductive layer is etched using the reflective metal layer and the resist pattern from which the thin film portion has been removed as a mask. Then, the reflective metal layer is etched again using the resist pattern from which the thin film portion has been removed as a mask. As a result, the reflective metal layer in the transmissive pixel portion is removed, and a reflective pixel electrode and a transmissive pixel electrode are formed.

  In general, in order to remove a thin film portion of a resist pattern having a difference in film thickness, ashing removal (ashing) for oxidizing and decomposing the resist by a dry etcher such as oxygen plasma treatment is performed. However, in the method of Patent Document 1, ashing is performed in a state where the transparent conductive layer is exposed on the surface, and thus abnormal discharge may occur. The abnormal discharge damages not only the transparent conductive layer but also the organic film provided therebelow. In addition, the wiring provided in the lower layer may cause a failure such as disconnection.

  On the other hand, in order to prevent abnormal discharge during ashing, there is a method in which the transparent conductive layer exposed before ashing is removed in advance. Specifically, the transparent conductive layer and the reflective metal layer are etched using a resist pattern having a film thickness difference as a mask, and then ashing is performed, and the reflective metal layer is etched again using the resist pattern from which the thin film portion has been removed as a mask. . Also in this method, similarly to Patent Document 1, the reflective pixel electrode and the transmissive pixel electrode can be formed by one photolithography.

  However, in this method, the transparent conductive layer is removed, and the underlying organic film is exposed on the surface. In the transflective liquid crystal display device, an organic film having a concavo-convex pattern on the surface is provided below the pixel electrode in order to obtain good scattering characteristics. The exposed portion of the organic film is reduced in thickness in the same manner as the resist pattern by ashing for removing the thin film portion of the resist pattern having a film thickness difference. Therefore, the film thickness of the organic film differs greatly between the portion covered by the transparent conductive layer and the portion not covered.

  FIG. 19 shows a cross-sectional view of a conventional liquid crystal display device using the TFT array substrate thus formed. In FIG. 19, the TFT array substrate 10 and the counter substrate 30 are arranged to face each other. The liquid crystal layer 36 is held in a space between the sealing material 37 for bonding these two substrates. The sealing material 37 is formed in a frame shape so as to surround the display area of the liquid crystal display device.

  In the TFT array substrate 10, gate wirings (not shown) and source wirings (not shown) are formed on the substrate via insulating films (not shown). An organic film 18 is provided on the upper layer of the gate wiring, source wiring, insulating film, and the like. On the organic film 18, a pixel electrode 19 in which a transmissive pixel electrode 191 and a reflective pixel electrode 192 are stacked is formed in each pixel. A region where the pixel electrodes 19 are arranged in a matrix is a display region 41. As described above, the film thickness of the organic film 18 is different between the portion covered with the transparent conductive layer and the portion not covered. Therefore, the film thickness of the organic film 18 is thinner than the pixel region in the portion not covered with the transparent conductive layer, that is, in the inter-pixel region and the frame region 42.

  In the counter substrate 30, a BM 32, a color material 33, a counter electrode 34, and the like are formed on the substrate. A columnar spacer 35 for determining a gap with the opposing TFT array substrate 10 is provided on the counter electrode 34. The columnar spacers 35 are formed in the display area 41 and the frame area 42. Specifically, in the display area 41, the display area 41 is disposed in a portion facing the reflective pixel electrode 192. On the other hand, in the frame area 42, the frame area 42 is disposed in an area extending from the outside of the display area 41 to the inside of the sealing material 37. However, since the organic film 18 in this portion is thinner than the pixel region as described above, the gap between the two substrates cannot be kept uniform as shown in FIG. Become. Due to this gap defect, display defects such as display unevenness (peripheral gap unevenness) occur in the periphery of the display area 41, and the display quality of the liquid crystal display device is deteriorated.

  In recent years, in order to realize the reduction in thickness and weight required for liquid crystal panels, both the TFT array substrate 10 and the counter substrate 30 have become thinner and the mechanical strength has become weaker. As a result, a plastic substrate is sometimes used although it is not mainstream at present. Under such circumstances, the substrate is deformed by the pressure from inside and outside the cell when the TFT array substrate 10 and the counter substrate 30 are bonded to form a panel, and the distance between the two substrates can be kept uniform. It has become a difficult situation.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a liquid crystal display device having excellent display quality.

  A liquid crystal display device according to an aspect of the present invention is a liquid crystal display device having a pixel electrode including a transmissive pixel electrode and a reflective pixel electrode formed on a part of the transmissive pixel electrode. An array substrate on which pixel electrodes are formed, a counter substrate disposed opposite to the array substrate, and a frame region outside the display region so as to surround the display region, and is opposed to the array substrate. A sealing material for bonding the substrate; a pixel thick film portion formed in the display region and provided under the pixel electrode; a pad thick film portion formed inside the sealing material in the frame region; And an organic film having an inter-region thin film portion formed between the display film region and the frame region and provided between the pixel thick film portion and the pad thick film portion, and the pad thickness Gap retention with film part It comprises a use pads, on the counter substrate, and a position facing the pixel electrode, and the position facing the gap retaining pad, a columnar spacer formed, the.

  According to the present invention, it is possible to provide a liquid crystal display device with excellent display quality.

1 is a front view illustrating a configuration of a liquid crystal display device according to a first embodiment. 2 is a plan view showing a pixel configuration of a TFT array substrate according to Embodiment 1. FIG. FIG. 3 is a sectional view taken along line III-III in FIG. 2. FIG. 3 is an enlarged plan view showing the configuration of the periphery of the display area of the liquid crystal display panel according to Embodiment 1 and the outside thereof. It is VV sectional drawing of FIG. 5 is a cross-sectional view showing a manufacturing process of the TFT array substrate according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the TFT array substrate according to the first embodiment. FIG. FIG. 6 is an enlarged plan view showing a configuration of the periphery of the display area of the liquid crystal display panel according to another example of Embodiment 1 and the outside thereof. FIG. 6 is a cross-sectional view schematically showing the configuration of the periphery of the display region and the outside of the liquid crystal display panel according to another example of Embodiment 1. FIG. 6 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of the liquid crystal display panel according to Embodiment 2. 12 is a cross-sectional view showing a manufacturing process of the TFT array substrate according to the second embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the TFT array substrate according to the second embodiment. FIG. FIG. 6 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of the liquid crystal display panel according to Embodiment 3. FIG. 10 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of a liquid crystal display panel according to another example of Embodiment 3. FIG. 6 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of the liquid crystal display panel according to Embodiment 4. FIG. 10 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of a liquid crystal display panel according to another example of Embodiment 4. FIG. 10 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of the liquid crystal display panel according to Embodiment 5. FIG. 10 is a cross-sectional view schematically showing the configuration of the periphery of the display area and the outside of the liquid crystal display panel according to Embodiment 6. It is sectional drawing which showed typically the display area periphery part of the liquid crystal display panel which concerns on a prior art example, and the structure of the outer side.

  The preferred embodiments of the present invention will be described below. The following description explains the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. For the sake of clarification, duplicate explanation is omitted as necessary. In addition, what attached | subjected the same code | symbol in each figure has shown the same element, and description is abbreviate | omitted suitably.

Embodiment 1 FIG.
First, the liquid crystal display device according to the present embodiment will be described with reference to FIG. FIG. 1 is a front view showing the configuration of the liquid crystal display device according to the first embodiment. The liquid crystal display device according to this embodiment is a transflective liquid crystal display device having a transmissive region and a reflective region in one pixel. The overall configuration of the liquid crystal display device is common to the first to sixth embodiments described below.

  The liquid crystal display device according to the present invention includes a liquid crystal display panel 1. In the liquid crystal display panel 1, a thin film transistor (TFT) array substrate 10 and a counter substrate 30 are arranged to face each other.

  The TFT array substrate 10 is provided with a display area 41 and a frame area 42 provided so as to surround the display area 41. In the display area 41, a plurality of gate lines (scanning signal lines) 12 and a plurality of source lines (video signal lines) 16 are formed. The plurality of gate lines 12 are provided in parallel. Similarly, the plurality of source lines 16 are provided in parallel. The gate wiring 12 and the source wiring 16 are formed so as to cross each other. The gate wiring 12 and the source wiring 16 are orthogonal to each other. A region surrounded by the adjacent gate wiring 12 and source wiring 16 is a pixel 49. Therefore, in the TFT array substrate 10, the pixels 49 are arranged in a matrix.

  Further, a flexible substrate 47 on which a control circuit 45 is mounted and a flexible substrate 48 on which a control circuit 46 is mounted are connected to the frame region 42 of the TFT array substrate 10. The gate line 12 extends from the display area 41 to the frame area 42. The gate wiring 12 is connected to the control circuit 46 through a gate wiring terminal (gate terminal) 44 at the end of the TFT array substrate 10. Similarly, the source line 16 extends from the display area 41 to the frame area 42. The source wiring 16 is connected to the control circuit 45 via a source wiring terminal (source terminal) 43 at the end of the TFT array substrate 10.

  Various signals are supplied to the control circuits 45 and 46 from the outside. The control circuit 46 supplies a gate signal (scanning signal) to the gate wiring 12 based on an external control signal. By this gate signal, the gate lines 12 are sequentially selected. The control circuit 45 supplies a display signal to the source line 16 based on an external control signal or display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 49. The control circuit 45 may be divided and mounted on the liquid crystal display panel 1, the flexible substrate 47, and an FPC (Flexible Printed Circuit) (not shown). Similarly, the control circuit 46 may be divided and mounted on the liquid crystal display panel 1, the flexible substrate 48, and the FPC. Further, part of the control circuits 45 and 46 may be formed on the TFT array substrate 10.

  In the pixel 49, at least one TFT 50 is formed. The TFT 50 is disposed near the intersection of the source line 16 and the gate line 12. For example, the TFT 50 supplies a display voltage to the pixel electrode. That is, the TFT 50 which is a switching element is turned on by the gate signal from the gate wiring 12. As a result, a display voltage is applied from the source line 16 to the pixel electrode connected to the drain electrode of the TFT 50. An electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode. An alignment film (not shown) is formed on the surface of the TFT array substrate 10. A detailed configuration in the pixel 49 will be described later.

  On the other hand, the counter substrate 30 is a color filter substrate, for example, and is disposed on the viewing side. On the counter substrate 30, a color filter (color material), a black matrix (BM), a counter electrode, an alignment film, and the like are formed. The detailed configuration of the counter substrate 30 will be described later. The counter electrode may be disposed on the TFT array substrate 10 side. The TFT array substrate 10 and the counter substrate 30 are bonded together with a sealing material 37 interposed therebetween. The sealing material 37 is provided in a frame shape so as to surround the display area 41. A liquid crystal layer 36 is sandwiched between the TFT array substrate 10 and the counter substrate 30. That is, liquid crystal is introduced between the TFT array substrate 10 and the counter substrate 30. Further, a polarizing plate, a phase difference plate, and the like are provided on the outer surfaces of the TFT array substrate 10 and the counter substrate 30. Further, a backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel 1.

  The liquid crystal is driven by the electric field between the pixel electrode and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer changes. That is, the polarization state of light that has been linearly polarized after passing through the polarizing plate is changed by the liquid crystal layer. Specifically, in the transmissive region, light from the backlight unit becomes linearly polarized light by the polarizing plate provided on the TFT array substrate side. The linearly polarized light passes through the retardation plate on the TFT array substrate 10 side, the liquid crystal layer, and the retardation plate on the counter substrate 30 side, so that the polarization state changes. On the other hand, in the reflection region, external light incident from the viewing side of the liquid crystal display panel is linearly polarized by the polarizing plate on the counter substrate 2 side. And this light changes a polarization state by reciprocating the phase difference plate and the liquid crystal layer on the counter substrate 30 side.

  The amount of light passing through the polarizing plate on the counter substrate 30 side changes depending on the polarization state. That is, the amount of light passing through the polarizing plate on the viewing side among the transmitted light transmitted through the liquid crystal display panel 1 from the backlight unit and the reflected light reflected by the liquid crystal display panel 1 changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel.

  Next, the pixel configuration of the TFT array substrate 10 will be described in detail with reference to FIGS. FIG. 2 is a plan view showing a pixel configuration of the TFT array substrate 10 according to the first embodiment. 3 is a cross-sectional view taken along the line III-III in FIG. FIG. 2 is a plan view showing one of the pixels 49 on the TFT array substrate 10. A plurality of such pixels 49 are arranged in a matrix on the TFT array substrate 10. Here, a case where a channel etch type TFT 50 is formed will be described as an example.

  2 and 3, the TFT array substrate 10 is formed with a gate wiring 12 partially forming a gate electrode 121 on a transparent insulating substrate 11 such as glass or plastic. Therefore, the gate wiring 12 is electrically connected to the gate electrode 121 of the TFT 50.

  On the substrate 11, the auxiliary capacitance electrode 122 is formed of the same layer as the gate wiring 12. The auxiliary capacitance electrode 122 is provided apart from the gate line 12 and extends in parallel with the gate line 12. That is, the auxiliary capacitance electrode 122 is disposed between the adjacent gate lines 12. Here, the auxiliary capacitance electrode 122 is disposed in the reflection region of the pixel 49. The auxiliary capacity electrode 122 constitutes a storage capacity for enabling stable display with the pixel electrode 19 described later. The storage capacitor holds the drive voltage from the TFT 50 even after the TFT 50 connected to each pixel 49 is turned off.

  The gate wiring 12, the gate electrode 121, and the auxiliary capacitance electrode 122 are made of, for example, Mo having a thickness of 250 nm.

  A gate insulating film 13 is provided so as to cover the gate wiring 12, the gate electrode 121, and the auxiliary capacitance electrode 122. The gate insulating film 13 is made of, for example, SiN having a thickness of 400 nm. A semiconductor layer 14 is provided on the opposite side of the gate electrode 121 through the gate insulating film 13. The semiconductor layer 14 is formed of, for example, amorphous silicon (a-Si (i)) having a thickness of 130 nm.

  In addition, ohmic contact films 15 doped with conductive impurities are respectively formed on both ends of the semiconductor layer 14. The region of the semiconductor layer 14 corresponding to the ohmic contact film 15 becomes a source / drain region. Specifically, the region of the semiconductor layer 14 corresponding to the left ohmic contact film 15 in FIG. 3 becomes the source region. The region of the semiconductor layer 14 corresponding to the right ohmic contact film 15 in FIG. 3 becomes the drain region. Thus, source / drain regions are formed at both ends of the semiconductor layer 14. A region sandwiched between the source / drain regions of the semiconductor layer 14 becomes a channel region. The ohmic contact film 15 is not formed on the channel region of the semiconductor layer 14. The ohmic contact film 15 is formed with a film thickness of 50 nm using, for example, n-type amorphous silicon (a-Si (n)) doped with an impurity such as phosphorus (P) at a high concentration.

  A source electrode 161 and a drain electrode 162 are formed on the ohmic contact film 15. Specifically, the source electrode 161 is formed on the ohmic contact film 15 on the source region side. A drain electrode 162 is formed on the ohmic contact film 15 on the drain region side. In this way, the channel etch type TFT 50 is configured. The source electrode 161 and the drain electrode 162 are formed so as to extend outside the channel region of the semiconductor layer 14. That is, the source electrode 161 and the drain electrode 162 are not formed on the channel region of the semiconductor layer 14 like the ohmic contact film 15.

  The source electrode 161 extends outside the channel region of the semiconductor layer 14 and is connected to the source wiring 16. Therefore, the source wiring 16 is electrically connected to the source electrode 161 of the TFT 50. The source wiring 16 is formed on the gate insulating film 13 and is arranged on the substrate 11 so as to extend linearly in a direction intersecting with the gate wiring 12. Therefore, the source line 16 branches at the intersection with the gate line 12 and then extends along the gate line 12 to become the source electrode 161. Although not shown in FIG. 2, as shown in FIG. 3, a stacked film having a pattern of the same layer as the semiconductor layer 14 and a pattern of the same layer as the ohmic contact film 15 is formed of the gate wiring 12 and the source wiring 16. You may arrange | position in a cross | intersection part. Thereby, the insulation tolerance between the gate wiring 12 and the source wiring 12 can be improved.

  On the other hand, the drain electrode 162 has an extending portion that extends to the outside of the channel region of the semiconductor layer 14 and extends to the outside of the TFT 50. The source electrode 161, the drain electrode 162, and the source wiring 16 are made of, for example, Mo with a film thickness of 300 nm.

An interlayer insulating film 17 is provided so as to cover the source electrode 161, the drain electrode 162, and the source wiring 16. Therefore, the interlayer insulating film 17 covers the TFT 50.
The interlayer insulating film 17 is made of SiN having a thickness of 100 nm. Further, an organic film 18 is laminated on the interlayer insulating film 17. A contact hole 181 is provided in the organic film 18 and the interlayer insulating film 17 on the drain electrode 162 of the TFT 50. The contact hole 181 passes through the organic film 18 and the interlayer insulating film 17 and reaches the drain electrode 162 of the TFT 50.

  The organic film 18 is an organic resin film serving as a base layer for forming the pixel electrode 19, and planarizes unevenness on the substrate 11 caused by the source wiring 16, the gate wiring 12, the auxiliary capacitance electrode 122, the TFT 50, and the like. To do. The liquid crystal display device according to the present embodiment is a transflective type, and the pixel 49 has a transmissive region and a reflective region. In the reflection region, an uneven pattern 185 is formed on the surface of the organic film 18 in order to make the reflected light have an appropriate scattering distribution. Note that the organic film 18 in a region not covered with the pixel electrode 19 described later has a smaller film thickness than the region covered with the pixel electrode 19. Here, the film thickness of the organic film 18 in the region covered with the pixel electrode 19 is, for example, about 3600 nm.

  A pixel electrode 19 connected to the drain electrode 162 through the contact hole 181 is provided on the organic film 18. The pixel electrode 19 has a single-layer structure of the transmissive pixel electrode 191 in the transmissive region, and has a laminated structure in which the reflective pixel electrode 192 is laminated on the transmissive pixel electrode 191 in the reflective region. That is, the transmissive pixel electrode 191 is provided in both the transmissive region and the reflective region. Here, the transmissive pixel electrode 191 is formed to a thickness of 80 nm by a transparent conductive layer such as ITO, IZO, ITZO, ITSO, or the like. On the other hand, the reflective pixel electrode 192 is provided only in the reflective region. Here, for example, the reflective pixel electrode 192 is formed of a reflective metal layer in which an AlCu film having a thickness of 300 nm is laminated on a Mo film having a thickness of 50 nm. Further, in order to adjust the work function with the liquid crystal layer 36 between the transmissive region and the reflective region, the pixel electrode 19 has a configuration in which an upper transparent conductive layer 193 is further laminated on the reflective pixel electrode 192 as shown in FIG. It is good. In this case, the upper transparent conductive layer 193 is formed of a transparent conductive layer made of ITO, IZO, ITZO, ITSO or the like having a thickness of 5 nm, for example.

  Next, the configuration of the periphery of the display area 41 of the liquid crystal display panel 1 and the outside thereof will be described with reference to FIGS. FIG. 4 is an enlarged plan view showing the configuration of the periphery of the display area 41 and the outside of the liquid crystal display panel 1 according to the first embodiment. FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 4, schematically showing the configuration of the periphery of the display area 41 of the liquid crystal display panel 1 according to Embodiment 1 and the outside thereof. In FIG. 4, only the configuration on the TFT array substrate 10 side is shown for convenience of explanation, and the configuration on the counter substrate 30 side is omitted. In FIG. 5, the configuration of the TFT array substrate 10 is schematically described, and components such as the gate wiring 12, the source wiring 16, and the TFT 50 are omitted as appropriate.

  4 and 5, as described in detail in FIGS. 2 and 3, the organic film 18 is disposed on the substrate 11 of the TFT array substrate 10 in an upper layer such as the gate wiring 12, the source wiring 16, and the TFT 50. ing. The organic film 18 is formed over substantially the entire surface of the substrate 11 from the display area 41 to the frame area 42. On the organic film 18, a pixel electrode 19 formed by stacking a transmissive pixel electrode 191 and a reflective pixel electrode 192 is formed in each pixel 49. As shown in FIG. 5, the region (pixel region) in which the pixel electrode 19 is provided is more organic than the region between adjacent pixel electrodes 19 (inter-pixel region) as in the conventional example shown in FIG. The film 18 is thick. That is, in the display region 41, the thick film portion of the organic film 18 is formed in the pixel region, and the thin film portion of the organic film 18 is formed in the inter-pixel region.

  In the organic film 18, a thin film portion similar to the inter-pixel region is formed in the frame region 42 outside the display region 41. Here, in the present embodiment, a thick film portion of the organic film 18 similar to the pixel region is provided in the frame region 42 in the region from the outside of the display region 41 to the inside of the sealing material 37. . A transparent conductive layer 191 d that is the same layer as the transmissive pixel electrode 191 is formed on the thick film portion of the organic film 18. As described above, in the present embodiment, the gap holding pad 20 in which the transparent conductive layer 191 d is laminated on the thick film portion of the organic film 18 is provided in the region outside the display region 41 and inside the sealing material 37. It has been.

  For example, as shown in FIG. 4, the gap holding pad 20 is formed in a strip shape along each side of the frame-shaped sealing material 37.

  The counter substrate 30 is bonded to the facing surface of the TFT array substrate 10 with a sealing material 37 interposed therebetween. As shown in FIG. 5, the counter substrate 30 is formed with a black matrix 32 made of a metal such as a pigment or chromium on the surface of the substrate 31 facing the TFT array substrate 10 to block light. The black matrix 32 is provided in a region facing the source wiring 16 and the gate wiring 12 and has a lattice shape. The black matrix 32 is formed in a frame shape so as to surround the display area 41. A color material 33 made of a pigment or a dye is formed so as to fill the space between the black matrices 32. The color material 33 is, for example, an R (red), G (green), or B (blue) color filter.

Further, a counter electrode 34 is formed so as to cover the black matrix 32 and the color material 33. The counter electrode 34 generates an electric field between the pixel electrode 19 of the TFT array substrate 10 and drives the liquid crystal of the liquid crystal layer 36. A protective film made of SiN or the like may be provided between the color material 33 and the counter electrode 34. Similar to the counter electrode 34, the protective film is formed on the entire substrate 31 of the counter substrate 30. A columnar spacer 35 is provided on the counter electrode 34. The columnar spacer 35 is provided in the display area 41 and the frame area 42 in a space surrounded by the TFT array substrate 10, the counter substrate 30, and the sealing material 37, and maintains a gap between the two substrates.
The columnar spacers 35 provided in the display area 41 are disposed in a portion facing the reflective pixel electrode 192. The columnar spacers 35 provided in the frame region 42 are disposed in a portion facing the gap holding pad 20. The columnar spacer 35 is formed of a material such as resin and has a columnar shape. The columnar spacers 35 in the display area 41 are formed at the same height in the display area 41 and the frame area 42.

  In the liquid crystal display panel 1 according to the present embodiment configured as described above, the distance between the surface of the TFT array substrate 10 and the surface of the counter substrate 30 facing each other is such that the gap holding pad 20 part and the pixel region And almost the same. Therefore, the distance between the substrates can be kept equal to the display area 41 by the columnar spacer 35 provided at the position facing the gap holding pad 20 portion, and the distance between the substrates can be maintained over the entire liquid crystal display panel 1. It is kept uniform. Thus, the gap holding pad 20 has a function of adjusting the substrate interval outside the display area in the liquid crystal display panel 1 according to the substrate interval on the pixel electrode 19.

  Next, a method for manufacturing the liquid crystal display device according to the present embodiment will be described with reference to FIGS. 6 and 7 are cross-sectional views showing manufacturing steps of the TFT array substrate 10 according to the first embodiment. 6 and 7, the right side of each drawing shows a cross-sectional view inside the pixel 49 corresponding to the III-III cross section of FIG. 2. 6 and 7, the left side is a sectional view of the gate terminal 44, the source terminal 43, and the gap holding pad 20.

  First, an electrode film to be the gate electrode 121 or the like is formed on the substrate 11 made of a transparent insulating substrate such as glass. For example, Mo having a thickness of 250 nm is formed on the entire surface of the substrate 11 using a sputtering apparatus or the like. Next, a resist pattern is formed on the electrode film by a photolithography process (a photolithography process). Then, the electrode film exposed from the resist pattern is removed by wet etching or the like, and the electrode film is patterned. Thereafter, a resist stripping process is performed to remove the resist pattern, whereby the gate wiring 12, the gate electrode 121, the auxiliary capacitance electrode 122, and the gate terminal 44 are formed as shown in FIG.

  A gate insulating film 13 is formed so as to cover the gate wiring 12, the gate electrode 121, the auxiliary capacitance electrode 122, and the gate terminal 44. For example, using a CVD apparatus, SiN having a film thickness of 400 nm is formed on the entire surface of the substrate 11 as the gate insulating film 13. Subsequently, the semiconductor layer 14 and the ohmic contact film 15 are formed in this order on the gate insulating film 13. For example, a 130-nm-thick a-Si (i) film is formed as the semiconductor layer 14 over the entire surface of the substrate 11 by using a CVD apparatus, and then a 50-nm-thick a-Si (doped with an impurity such as phosphorus (P)). n) is formed as an ohmic contact film 15 on the entire surface of the substrate 11.

  Thereafter, a resist pattern is formed on the ohmic contact film 15 by a photolithography process. Then, the ohmic contact film 15 and the semiconductor layer 14 are patterned in an island shape by a dry etching process or the like. When the resist pattern is removed, as shown in FIG. 6B, the semiconductor layer 14 and the ohmic contact film 15 are formed on the opposite surface of the gate electrode 121 with the gate insulating film 13 interposed therebetween. As shown in FIG. 6B, a stacked pattern of the semiconductor layer 14 and the ohmic contact film 15 may be formed on a region of the gate wiring 12 that intersects with the source wiring 16.

  Next, an electrode film to be the source electrode 161, the drain electrode 162, and the like is formed so as to cover the semiconductor layer 14 and the ohmic contact film 15. For example, Mo having a film thickness of 300 nm is formed on the entire surface of the substrate 11 using a sputtering apparatus or the like. Next, a resist pattern is formed on the electrode film by a photolithography process. Then, this electrode film is patterned by wet etching or the like. Thereby, the source wiring 16, the source electrode 161, the drain electrode 162, and the source terminal 43 are formed. Subsequently, the ohmic contact film 15 which is not covered with the source electrode 161 or the drain electrode 162 and exposed on the surface is removed by a dry etching process or the like. As a result, the semiconductor layer 14 between the source electrode 161 and the drain electrode 162 is exposed, and a channel region is formed. Thereafter, a resist stripping process is performed to remove the resist pattern, resulting in a configuration as shown in FIG.

  Next, the interlayer insulating film 17 is formed so as to cover the source wiring 16, the source electrode 161, the drain electrode 162, and the source terminal 43. For example, a 100 nm-thickness SiN film is formed as the interlayer insulating film 17 on the entire surface of the substrate 11 using a CVD apparatus. Subsequently, an organic film 18 having photosensitivity is applied on the interlayer insulating film 17 so that the film thickness of the flat portion is about 3600 nm. Thereafter, a photolithography process is performed to pattern the organic film 18. Thereby, the organic film 18 on the drain electrode 162, the gate terminal 44, and the source terminal 43 is removed to form an opening, and an uneven pattern 185 is formed in the organic film 18 in the reflective region.

  Thereafter, using the organic film 18 as a mask, the interlayer insulating film 17 and the gate insulating film 13 are patterned by dry etching or the like. As a result, as shown in FIG. 6D, the interlayer insulating film 17 on the drain electrode 162 is removed, and a contact hole 181 reaching the drain electrode 162 is formed. Further, the interlayer insulating film 17 on the source terminal 43 is removed, and a contact hole 182 reaching the source terminal 43 is formed. Further, the interlayer insulating film 17 and the gate insulating film 13 on the gate terminal 44 are removed, and a contact hole 183 reaching the gate terminal 44 is formed.

  Next, a transparent conductive layer 191d to be a transmissive pixel electrode 191 and a reflective metal layer 192d to be a reflective pixel electrode 192 are sequentially formed on the organic film 18. For example, an ITO film having a thickness of 80 nm is formed on the entire surface of the substrate 11 as the transparent conductive layer 191d using a sputtering apparatus. In addition to ITO, IZO, ITZO, ITSO, or the like can be used for the transparent conductive layer 191d. Then, Mo having a thickness of 50 nm and AlCu having a thickness of 300 nm are formed in this order on the entire surface of the substrate 11 as a reflective metal layer. Here, ITO having a film thickness of 5 nm is continuously formed on the entire surface of the substrate 11 as the upper transparent conductive layer 193. For the upper transparent conductive layer 193, IZO, ITZO, ITSO or the like can be used in addition to ITO. Thereby, as shown in FIG. 6E, the contact holes 181, 182, and 183 are covered with the transparent conductive layer 191d, the reflective metal layer 192d, and the upper transparent conductive layer 193.

  Subsequently, after applying a resist on the upper transparent conductive layer 193 by spin coating or the like, a resist pattern 25 having a film thickness difference is formed by a photolithography process using multi-tone exposure such as halftone. In the pixel region, the resist pattern 25 is formed so that the thickness of the transmissive pixel electrode portion is smaller than the thickness of the reflective pixel electrode portion. That is, the resist pattern 25 is provided with a thick film portion 25 a in the reflective pixel electrode portion of the pixel 49 and a thin film portion 25 b in the transmissive pixel electrode portion. At this time, in this embodiment, a resist pattern 25 is formed which becomes a thick film portion 25a in the gate terminal portion and the source terminal portion and a thin film portion 25b in the gap holding pad portion.

  Then, using the resist pattern 25 as a mask, the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d are sequentially or collectively patterned by wet etching or the like. Thereby, as shown in FIG. 7F, the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d in the region not covered with the resist pattern 25 are removed, and the organic film 18 is exposed.

  Next, an ashing process is performed to remove the thin film portion 25b of the resist pattern 25. The thick film portion 25a of the resist pattern 25 becomes thin and remains as a resist pattern 25c. That is, as shown in FIG. 7G, the resist pattern 25 from which the thin film portion 25b has been removed becomes a resist pattern 25c. As a result, the resist pattern 25 on the gap holding pattern portion is removed. In addition, the organic film 18 exposed from the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d is simultaneously reduced by the ashing process, and a thin film portion is formed in the organic film 18. At this time, in the present embodiment, the organic film 18 in the gap holding pad portion is covered with the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d, and thus the film is not reduced. In this manner, the organic film 18 in which the thick film portion similar to the pixel region is provided in the gap holding pad portion is formed.

  After ashing, wet etching or the like is performed using the resist pattern 25c as a mask to selectively pattern the upper transparent conductive layer 193 and the reflective metal layer 192d. As a result, the upper transparent conductive layer 193 and the reflective metal layer 192d of the transmissive pixel electrode portion and the gap holding pad portion are removed, and the transparent conductive layer 191d is exposed. Thereafter, the resist pattern 25c is removed using a resist stripping solution. As a result, as shown in FIG. 7H, the pixel electrode 19 in which the reflective pixel electrode 192 and the upper transparent conductive layer 193 are laminated on a part of the transmissive pixel electrode 191 is formed. The source terminal pad and the gate terminal pad connected to the source terminal 43 and the gate terminal 44 through the contact holes 182 and 183 are formed by a laminated film of the transparent conductive layer 191d, the reflective metal layer 192d, and the upper transparent conductive layer 193. Is done. Further, a gap holding pad 20 in which a transparent conductive layer 191 d is laminated on the thick film portion of the organic film 18 is formed.

  By patterning the upper transparent conductive layer 193 and the reflective metal layer 192d by the above method, the pixel electrode is such that the pattern end portions of the upper transparent conductive layer 193 and the reflective pixel electrode 192 are inside the pattern end portion of the transmissive pixel electrode 191. 19 is formed in steps. That is, the reflective pixel electrode 192 does not protrude from the transmissive pixel electrode 191 and does not have a bowl shape (overhang shape). Therefore, it is possible to prevent the occurrence of defects in subsequent processes due to the pixel electrode 19 having a bowl shape. The TFT array substrate 10 according to this embodiment is completed through the above steps.

  An alignment film is formed on the TFT array substrate 10 thus manufactured by a transfer method or the like. Next, after the alignment film is cured by applying heat, the alignment film is subjected to an alignment process (rubbing process) that makes micro scratches in one direction on the contact surface with the liquid crystal layer 36.

  On the other hand, a black matrix 32 is formed on another substrate 31 by a photolithography process. For the black matrix 32, a resin containing a pigment or a metal such as chromium can be used. The color material 33 is formed by a photolithography process so as to fill the space between the black matrixes 32 from above the black matrix 32. As the color material 33, a photosensitive resin made of a pigment or a dye can be used. Here, a protective film such as SiN is formed on substantially the entire surface of the substrate 31 so as to cover the black matrix 32 and the color material 33. A counter electrode 34 is formed on the entire surface of the substrate 31 on the protective film. As the counter electrode 34, a transparent conductive film made of ITO or the like is used.

  In the same manner as the TFT array substrate 10, an alignment film is formed on the counter substrate 30 provided with the counter electrode 34, and a rubbing process is performed. Then, a photoresist (tourist resin) to be the columnar spacer 35 is applied on the alignment film. Then, the photoresist is patterned by a photolithography process to form columnar spacers 35. At this time, columnar spacers 35 are formed at positions facing the reflective pixel electrodes 192 of the TFT array substrate 10 and positions facing the gap holding pads 20 in the substrate bonding step described later. Through the steps described above, the counter substrate 30 having the columnar spacers 35 is formed.

  Next, the sealing material 37 is applied and the TFT array substrate 10 and the counter substrate 30 are bonded together (substrate bonding step). At this time, the TFT array substrate 10 and the counter substrate 30 are bonded so that the columnar spacer 35 is disposed at a position facing the reflective pixel electrode 192 and the gap holding pad 20. After the TFT array substrate 10 and the counter substrate 30 are bonded together, liquid crystal is injected from a liquid crystal injection port by a vacuum injection method or the like (liquid crystal injection step). Then, the liquid crystal injection port is sealed (sealing step). In this way, the liquid crystal display panel 1 of the present embodiment is completed.

  As described above, in the present embodiment, the columnar spacer 35 of the counter substrate 30 is disposed so as to face the reflective pixel electrode 192 and the gap holding pad 20 of the TFT array substrate 10, and holds the distance between the two substrates. Therefore, pressure is applied between the TFT array substrate 10 and the counter substrate 30 through the substrate bonding step, the liquid crystal injection step, and the sealing step, but the distance between the substrates can be kept uniform throughout the liquid crystal display panel 1. it can.

  Thereafter, a polarizing plate is attached to the outside of the TFT array substrate 10 and the counter substrate 30. And a control board is mounted and a backlight unit etc. are attached. Through the above steps, the liquid crystal display device according to this embodiment is completed.

  As described above, in the present embodiment, the transparent conductive layer 191d that is the same layer as the transmissive pixel electrode 191 is provided in the region outside the display region 41 and inside the sealing material 37 on the TFT array substrate 10 to provide a gap holding pad. 20 is formed. As a result, a thick film portion of the organic film 18 is formed under the transparent conductive layer 191d as in the case of under the reflective pixel electrode 192. Then, both substrates are bonded together so that the columnar spacer 35 of the counter substrate 30 is located on the opposite side of the reflective pixel electrode 192 and the gap holding pad 20. Thus, the distance from the surface of the counter substrate 30 on the gap holding pad 20 is substantially the same as that on the reflective pixel electrode 192, and the columnar spacer 35 holds the distance between the substrates at these portions. Therefore, the distance between the two substrates is the same between the outside and inside of the display area 41. Therefore, display unevenness occurring in the periphery of the display area 41 can be suppressed, and a liquid crystal display device with excellent display quality can be provided.

  In the above description, the gap holding pad 20 is formed in a strip shape along each side of the sealing material 37, and the plurality of columnar spacers 35 are arranged opposite to each gap holding pad 20. The shape of the pad 20 is not limited to this. FIG. 8 is an enlarged plan view showing the configuration of the periphery of the display region 41 and the outside of the liquid crystal display panel 2 according to another example of the first embodiment. FIG. 9 is a cross-sectional view schematically showing the configuration of the periphery and the outside of the display area 41 of the liquid crystal display panel 2 according to another example of the first embodiment. In FIG. 8, only the configuration on the TFT array substrate 10 side is shown, and the configuration on the counter substrate 30 side is omitted. In FIG. 9, the configuration of the TFT array substrate 10 is schematically shown. For example, as shown in FIGS. 8 and 9, the gap holding pad 20 is formed to a size that can contain the columnar spacer 35, and each of the columnar spacers 35 is disposed opposite to the gap holding pad 20. Also good.

Embodiment 2. FIG.
A liquid crystal display device according to this embodiment will be described with reference to FIGS. Since the basic configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment, the description of the same contents is omitted. In the present embodiment, the configuration of the gap holding pad 20 is different from that of the first embodiment. FIG. 10 is a cross-sectional view schematically showing the configuration of the periphery of the display area 41 and the outside of the liquid crystal display panel 3 according to the second embodiment. 10, a cross section corresponding to the VV cross sectional view of FIG. 4 is shown.

  10, the same components as those in FIG. 5 are denoted by the same reference numerals, and differences will be described. As shown in FIG. 10, as in the first embodiment, a gap holding pad 20 is provided on the TFT array substrate 10 in the region outside the display region 41 and inside the sealing material 37. In the present embodiment, the gap holding pad 20 has a transparent conductive layer 191d in the same layer as the transmissive pixel electrode 191 and a reflective metal layer 192d in the same layer as the reflective pixel electrode 192 on the thick film portion of the organic film 18. Are laminated. In the case where the pixel electrode 19 has an upper transparent conductive layer 193 for adjusting the work function on the reflective pixel electrode 192, the gap holding pad 20 is disposed on the reflective metal layer 192d. Are further laminated.

  Then, the TFT array substrate 10 and the counter substrate 30 are interposed via the sealing material 37 so that the columnar spacers 35 of the counter substrate 30 are disposed opposite to the reflective pixel electrode 192 and the gap holding pad 20 of the TFT array substrate 10. It is pasted together.

  Next, a method for manufacturing the liquid crystal display device according to the present embodiment will be described with reference to FIGS. 11 and 12 are cross-sectional views showing the manufacturing process of the TFT array substrate 10 according to the second embodiment. 11 and 12, on the right side, as in FIGS. 6 and 7, a cross-sectional view inside the pixel 49 corresponding to the III-III cross section of FIG. 2 is shown. 11 and 12, the left side is a cross-sectional view of the gate terminal 44 part, the source terminal 43 part, and the gap holding pad 20 part. In the present embodiment, the gap holding pad 20 forming step is different from that in the first embodiment, and the other steps are the same as those in the first embodiment, and thus the description thereof is omitted.

  As in the first embodiment, first, an electrode film to be the gate electrode 121 is formed over the entire surface of the substrate 11. This electrode film is patterned through the steps of photolithography, etching, and resist removal. As a result, the gate line 12, the gate electrode 121, the auxiliary capacitance electrode 122, and the gate terminal 44 are formed on the substrate 11, and the structure shown in FIG. A gate insulating film 13, a semiconductor layer 14, and an ohmic contact film 15 are formed so as to cover them. Thereafter, the semiconductor layer 14 and the ohmic contact film 15 are patterned by a photolithography process to obtain the configuration of FIG.

  Next, an electrode film covering these is formed in the same manner as in the first embodiment. Then, the source wiring 16, the source electrode 161, the drain electrode 162, and the source terminal 43 are formed through photolithography and etching processes. Subsequently, as in Embodiment 1, the ohmic contact film 15 between the source electrode 161 and the drain electrode 162 is removed by etching to form a channel region. Thereafter, the structure shown in FIG. 11C is obtained through a resist removal step.

  After the channel region is formed, an interlayer insulating film 17 is formed thereon as in the first embodiment. Subsequently, an organic film 18 having an uneven pattern 185 and an opening is formed on the interlayer insulating film 17 by a photolithography process. Etching is performed using the organic film 18 as a mask. Thus, as shown in FIG. 11D, a contact hole 181 reaching the drain electrode 162, a contact hole 183 reaching the gate terminal 44, and a contact hole 182 reaching the source terminal 43 are formed.

  As in the first embodiment, a transparent conductive layer 191d and a reflective metal layer 192d are sequentially formed on the organic film 18. As in the first embodiment, an upper transparent conductive layer 193 is further formed on the reflective metal layer 192d here. As a result, as shown in FIG. 11E, the contact holes 181, 182, and 183 are covered with the transparent conductive layer 191d, the reflective metal layer 192d, and the upper transparent conductive layer 193.

  Subsequently, after applying a resist on the upper transparent conductive layer 193 by spin coating or the like, a resist pattern 25 having a film thickness difference is formed by a photolithography process using multi-tone exposure such as halftone. In the present embodiment, as shown in FIG. 12F, a thick film portion 25a of the resist pattern 25 is formed on the reflective pixel electrode portion, the gate terminal portion, the source terminal portion, and the gap holding pad portion. Further, a thin film portion 25b of the resist pattern 25 is formed on the transmissive pixel electrode portion. That is, the thin film portion 25b is formed in the gap holding pad portion in the first embodiment, but the thick film portion 25a is formed in the present embodiment.

  Then, using the resist pattern 25 as a mask, the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d are sequentially or collectively patterned by wet etching or the like. As a result, as shown in FIG. 12F, the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d in the region not covered with the resist pattern 25 are removed, and the organic film 18 is exposed.

  Next, an ashing process is performed to remove the thin film portion 25b of the resist pattern 25. The resist pattern 25 from which the thin film portion 25b has been removed becomes a resist pattern 25c as shown in FIG. As a result, the thick film portion 25a of the resist pattern on the gap holding pattern portion becomes thin and remains as the resist pattern 25c. In addition, the organic film 18 exposed from the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d is simultaneously reduced by the ashing process, and a thin film portion is formed in the organic film 18. At this time, in the present embodiment, the organic film 18 in the gap holding pad portion is covered with the upper transparent conductive layer 193, the reflective metal layer 192d, and the transparent conductive layer 191d, and thus the film is not reduced. In this manner, the organic film 18 in which the thick film portion similar to the pixel region is provided in the gap holding pad portion is formed.

  After ashing, wet etching or the like is performed using the resist pattern 25c as a mask to selectively pattern the upper transparent conductive layer 193 and the reflective metal layer 192d. As a result, the upper transparent conductive layer 193 and the reflective metal layer 192d of the transmissive pixel electrode portion are removed, and the transparent conductive layer 191d is exposed. Thereafter, the resist pattern 25c is removed using a resist stripping solution. As a result, as shown in FIG. 12H, a pixel electrode 19 in which the reflective pixel electrode 192 and the upper transparent conductive layer 193 are laminated on a part of the transmissive pixel electrode 191 is formed. The source terminal pad and the gate terminal pad connected to the source terminal 43 and the gate terminal 44 through the contact holes 182 and 183 are formed by a laminated film of the transparent conductive layer 191d, the reflective metal layer 192d, and the upper transparent conductive layer 193. Is done. Further, a gap holding pad 20 in which a transparent conductive layer 191d, a reflective metal layer 192d, and an upper transparent conductive layer 193 are laminated on the thick film portion of the organic film 18 is formed.

  The TFT array substrate 10 according to this embodiment is completed through the above steps. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  As described above, in this embodiment, the same conductive layer as the conductive layer constituting the pixel electrode 19 is provided in the region outside the display region 41 on the TFT array substrate 10 and inside the sealing material 37 to provide a gap holding pad. 20 is formed. As a result, a thick film portion of the organic film 18 is formed under the conductive layer of the gap holding pad 20 in the same manner as under the reflective pixel electrode 192. Then, both substrates are bonded together so that the columnar spacer 35 of the counter substrate 30 is located on the opposite side of the reflective pixel electrode 192 and the gap holding pad 20. Thus, the distance from the surface of the counter substrate 30 on the gap holding pad 20 is substantially the same as that on the reflective pixel electrode 192, and the columnar spacer 35 holds the distance between the substrates at these portions. Therefore, the distance between the two substrates is the same between the outside and inside of the display area 41. Therefore, display unevenness occurring in the periphery of the display area 41 can be suppressed, and a liquid crystal display device with excellent display quality can be provided.

Embodiment 3 FIG.
A liquid crystal display device according to this embodiment will be described with reference to FIGS. Since the basic configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment, the description of the same contents is omitted. In the present embodiment, the configuration of the gap holding pad 20 is different from those of the first and second embodiments. FIG. 13 is a cross-sectional view schematically showing the periphery of the display area 41 of the liquid crystal display panel 4 according to the third embodiment and the configuration outside thereof.

  In FIG. 13, the same components as those in FIG. 5 are denoted by the same reference numerals, and differences will be described. In the present embodiment, as shown in FIG. 13, the gap holding pad 20 is provided on the counter substrate 30 outside the display area 41 and inside the sealing material 37. That is, the gap holding pad 20 is provided not on the TFT array substrate 10 side but on the counter substrate 30 side. Therefore, as in the conventional example shown in FIG. 19, the same thin film portion of the organic film 18 as the inter-pixel region is formed outside the display region 41 of the TFT array substrate 10.

  The gap holding pad 20 is formed by laminating a plurality of color materials 33 on a substrate 31, and a counter electrode 34 is formed so as to cover them. Here, three color materials 33 of red (R), green (G), and blue (B) are laminated on the gap holding pad 20. The number of the color materials 33 to be laminated is the counter substrate 30. The distance is appropriately determined according to the distance between the surface 20 of the gap holding pad 20 and the surface of the TFT array substrate 10 facing it. That is, the distance between the opposing surfaces of the TFT array substrate 10 and the counter substrate 30 is equivalent to the gap holding pad 20 of the counter substrate 30 and the reflective pixel electrode 192 of the TFT array substrate 10. In addition, the color material 33 to be stacked on the gap holding pad 20 is determined.

  The shape of the gap holding pad 20 is not particularly limited as in the first embodiment. For example, as described in the first embodiment, a plurality of columnar spacers 35 may be provided on one gap holding pad 20 by being formed in a strip shape along each side of the sealing material 37. Alternatively, the gap holding pad 20 may be formed in a size that allows the columnar spacer 35 to be included, and each of the columnar spacers 35 may be provided on one gap holding pad 20. In the case where the counter substrate 30 has a configuration in which a protective film is provided between the color material 33 and the counter electrode 34 in the display area 41, the protective film extends from the display area 41 and is also applied to the gap holding pad 20. Form.

  Thus, on the counter electrode 34 of the counter substrate 30 provided with the gap holding pad 20, the columnar spacer 35 is provided on the position facing the reflective pixel electrode 192 and on the gap holding pad 20. . The TFT array substrate 10 and the counter substrate are arranged so that the columnar spacers 35 of the counter substrate 30 are disposed to face the reflective pixel electrode 192 of the TFT array substrate 10 and the region outside the display region 41 and inside the sealing material 37. 30 are bonded to each other through a sealing material 37.

  The gap holding pad 20 is not limited to the above configuration. FIG. 14 is a cross-sectional view schematically showing the configuration of the periphery of the display region 41 of the liquid crystal display panel 5 according to another example of the third embodiment and the outside thereof. As shown in FIG. 14, a black matrix 32 may be formed between the color material 33 and the substrate 31 in the gap holding pad 20. Here, the two color materials 33 are laminated on the black matrix 32 on the gap holding pad 20, but the number of the color materials 33 to be laminated is as described above for holding the gap of the counter substrate 30. It is determined appropriately according to the distance between the surface of the pad 20 and the surface of the TFT array substrate 10 facing the pad 20 surface.

  As described above, in the present embodiment, at least two layers of the black matrix 32 and the color material 33 are stacked on the area outside the display area 41 and inside the sealing material 37 on the counter substrate 30 to maintain the gap. The pad 20 is formed. Thus, the height of the gap holding pad 20 from the surface of the counter substrate 30 on the substrate 31 is higher than the height in the display area 41. That is, the distance from the surface of the TFT array substrate 10 on the gap holding pad 20 is substantially the same as the distance from the surface of the counter substrate 30 on the reflective pixel electrode 192, and the columnar spacers 35 are spaced from each other at these portions. Will be held. Therefore, the distance between the two substrates is the same between the outside and inside of the display area 41. Therefore, display unevenness occurring in the periphery of the display area 41 can be suppressed, and a liquid crystal display device with excellent display quality can be provided.

Embodiment 4 FIG.
A liquid crystal display device according to this embodiment will be described with reference to FIG. Since the basic configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment, the description of the same contents is omitted. In the present embodiment, the configuration of the TFT array substrate 10 is different from that of the first embodiment. FIG. 15 is a cross-sectional view schematically showing the configuration of the periphery of the display area 41 and the outside of the liquid crystal display panel 6 according to the fourth embodiment.

  15, the same components as those in FIG. 5 are denoted by the same reference numerals, and differences will be described. As shown in FIG. 15, the thin film portion of the organic film 18 that is the same as the inter-pixel region is formed outside the display region 41 of the TFT array substrate 10 as in the conventional example shown in FIG. In the present embodiment, a planarizing film 21 is further formed on the pixel electrode 19 of the TFT array substrate 10. The planarizing film 21 is formed so as to cover the pixel electrode 19 and the organic film 18, and planarizes unevenness generated on the TFT array substrate 10. The planarizing film 21 is formed to be larger than the display area 41 in an area inside the frame-shaped sealing material 37. That is, the planarizing film 21 is not provided under the sealing material 37. As described above, the planarization film 21 functions as the gap holding pad 20 in the region outside the display region 41 and inside the sealing material 37 as in the first embodiment. The planarizing film 21 is formed of a planarizing film such as an organic insulating film or an inorganic insulating film.

  In the TFT array substrate 10 provided with the planarizing film 21 in this way, the columnar spacers 35 of the counter substrate 30 are disposed to face the reflective pixel electrode 192 and the region outside the display region 41 and inside the sealing material 37. As described above, the counter substrate 30 is bonded with the sealant 37 interposed therebetween.

  The planarizing film 21 is not limited to the above shape. FIG. 16 is a cross-sectional view schematically showing the configuration of the periphery of the display area 41 and the outside of the liquid crystal display panel 7 according to another example of the fourth embodiment. As shown in FIG. 16, the planarization film 21 may be formed in a shape that fills the thin film portion of the organic film 18. However, also in this case, as described above, the planarizing film 21 under the sealing material 37 is removed.

  As described above, in the present embodiment, the planarization film 21 is further formed on the pixel electrode 19 of the TFT array substrate 10. At this time, the planarization film 21 is formed such that the height of the surface of the planarization film 21 provided on the thin film portion of the organic film 18 from the substrate 11 is equal to or higher than the height of the surface of the transmissive pixel electrode 191 from the substrate 11. Form. As a result, the height of the surface from the substrate 11 is substantially equal between the region outside the display region 41 and the region inside the sealing material 37 and the reflective pixel electrode 192, and the columnar spacer 35 is located at these portions on the TFT array substrate. The distance between 10 and the counter substrate 30 is maintained. Therefore, the distance between the two substrates is the same between the outside and inside of the display area 41. Therefore, display unevenness occurring in the periphery of the display area 41 can be suppressed, and a liquid crystal display device with excellent display quality can be provided.

Embodiment 5 FIG.
A liquid crystal display device according to this embodiment will be described with reference to FIGS. Since the basic configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment, the description of the same contents is omitted. In the present embodiment, the configuration of the TFT array substrate 10 is different from that of the first embodiment. FIG. 17 is a cross-sectional view schematically showing the configuration of the periphery of the display region 41 and the outside of the liquid crystal display panel 8 according to the fifth embodiment.

  In FIG. 17, the same components as those in FIG. 5 are denoted by the same reference numerals, and differences will be described. As shown in FIG. 17, in this embodiment, an inorganic insulating film 22 is further formed between the organic film 18 and the transmissive pixel electrode 191. Therefore, unlike the first to fourth embodiments, the organic film 18 of the present embodiment is not provided with a thin film portion. That is, the organic film 18 is covered with the inorganic insulating film 22 and is not reduced during ashing of a resist pattern having a film thickness difference formed as a mask for patterning the transmissive pixel electrode 191 and the reflective pixel electrode 192. Therefore, by providing the inorganic insulating film 22 on the organic film 18, it is possible to prevent the organic film 18 from being reduced during ashing and forming a thin film portion. The inorganic insulating film 22 may be formed on the entire surface of the substrate 11 by using, for example, a CVD apparatus to form SiN having a thickness of 100 nm.

  In the TFT array substrate 10 provided with the inorganic insulating film 22 as described above, the columnar spacers 35 of the counter substrate 30 are disposed to face the reflective pixel electrode 192 and the region outside the display region 41 and inside the sealing material 37. As described above, the counter substrate 30 is bonded with the sealant 37 interposed therebetween.

  As described above, in this embodiment, the inorganic insulating film 22 is further formed between the organic film 18 and the transmissive pixel electrode 191 of the TFT array substrate 10. Accordingly, it is possible to prevent the organic film 18 from being reduced and a thin film portion from being formed by ashing when the transmissive pixel electrode 191 and the reflective pixel electrode 192 are formed by one photolithography. That is, the height of the surface from the substrate 11 is substantially the same between the area outside the display area 41 and the area inside the sealing material 37 and the reflective pixel electrode 192, and the columnar spacer 35 is located at these portions in the TFT array substrate 10. And the distance between the counter substrate 30 are maintained. Therefore, the distance between the two substrates is the same between the outside and inside of the display area 41. Therefore, display unevenness occurring in the periphery of the display area 41 can be suppressed, and a liquid crystal display device with excellent display quality can be provided.

Embodiment 6 FIG.
A liquid crystal display device according to this embodiment will be described with reference to FIG. Since the basic configuration of the liquid crystal display device according to the present embodiment is the same as that of the first embodiment, the description of the same contents is omitted. In the present embodiment, the configuration of the region outside the display region 41 and inside the sealing material 37 is different from that in the first embodiment. FIG. 18 is a cross-sectional view schematically showing the configuration of the periphery of the display region 41 and the outside of the liquid crystal display panel 9 according to the sixth embodiment.

  18, the same components as those in FIG. 5 are denoted by the same reference numerals, and differences will be described. As shown in FIG. 18, the gap holding pad 20 is not provided on the TFT array substrate 10 in the region outside the display region 41 and inside the sealing material 37. Therefore, as in the conventional example shown in FIG. 19, the same thin film portion of the organic film 18 as the inter-pixel region is formed outside the display region 41 of the TFT array substrate 10.

  In this embodiment, columnar spacers 35 and 35 a having different heights are provided on the counter substrate 30. The columnar spacer 35 a is formed in a region outside the display region 41 and inside the sealing material 37, and has a height higher than that of the columnar spacer 35 disposed to face the reflective pixel electrode 192 in the display region 41. That is, outside the display area 41, the film thickness of the organic film 18 is thinner than that of the pixel area, so that the distance from the surface of the counter substrate 30 to the surface of the TFT array substrate 10 is wider than that of the pixel area. Accordingly, the columnar spacers 35 and 35a having a height corresponding to the distance between the substrates 11 and 31 are formed so that the substrates 11 and 31 are opposed in parallel over the entire liquid crystal display panel 9. That is, the columnar spacer 35 a is formed higher than the columnar spacer 35 in accordance with the difference between the substrate interval outside the display region 41 and the substrate interval on the pixel electrode 19. These columnar spacers 35 and 35a may be formed by separate photolithography processes.

  Thus, the counter substrate 30 provided with the columnar spacers 35 and 35 a is disposed so as to face the TFT array substrate 10, and is bonded via a seal material 37.

  As described above, in the present embodiment, the columnar spacers 35 a provided in the region outside the display region 41 and inside the sealing material 37 are more than the columnar spacers 35 disposed opposite to the reflective pixel electrode 192 in the display region 41. It forms according to each space | interval so that height may become high. As a result, both the substrates are held while the distance between the surface of the TFT array substrate 10 and the surface of the counter substrate 30 is wider than that on the reflective pixel electrode 192 in the region outside the display region 41 and inside the sealing material 37. That is, the columnar spacers 35a having a high height are used to offset the reduction in the thickness of the organic film 18 by ashing when the transmissive pixel electrode 191 and the reflective pixel electrode 192 are formed by one photolithography. Is retained. Therefore, the TFT array substrate 10 and the counter substrate 30 are the liquid crystal display panel 9 that is disposed to face each other in parallel inside and outside the display region 41. Therefore, display unevenness occurring in the periphery of the display area 41 can be suppressed, and a liquid crystal display device with excellent display quality can be provided.

  Although the liquid crystal display device in which the channel etch type TFT 50 is formed has been described in the first to sixth embodiments, another TFT 50 such as a top gate type may be provided. Further, the configuration in which the upper transparent conductive layer 193 is provided on the reflective pixel electrode 192 for the purpose of preventing burn-in has been exemplarily described, but the same effect can be obtained even if the upper transparent conductive layer 193 is not provided. be able to. Further, the present invention is not limited to a configuration in which columnar spacers are provided on the counter substrate 30. A similar effect can be achieved by a configuration in which columnar spacers are provided on the TFT array substrate 10.

  The above description describes the embodiment of the present invention, and the present invention is not limited to the above embodiment. Moreover, those skilled in the art can easily change, add, and convert each element of the above embodiment within the scope of the present invention.

1, 2, 3, 4, 5, 6, 7, 8, 9 liquid crystal display panel,
10 TFT array substrate, 12 gate wiring, 13 gate insulating film,
14 semiconductor layer, 15 ohmic contact film, 16 source wiring,
17 interlayer insulation film, 18 organic film, 19 pixel electrode,
20 Gap retaining pad, 21 Planarizing film, 22 Inorganic insulating film,
25 resist pattern, 25a thick film part, 25b thin film part,
25c resist pattern, 30 counter substrate, 31 substrate,
32 black matrix, 33 color material, 34 counter electrode,
35, 35a Columnar spacer, 36 liquid crystal layer, 37 sealing material,
41 display area, 42 frame area, 43 source terminal,
44 gate terminal, 45, 46 control circuit,
47, 48 Flexible substrate, 49 pixels, 50 TFT,
121 gate electrode, 122 auxiliary capacitance electrode,
161 source electrode, 162 drain electrode,
181, 182, 183 contact hole, 185 uneven pattern,
191 transparent pixel electrode, 191d transparent conductive layer,
192 reflective pixel electrode, 192d reflective metal layer,
193 Upper transparent conductive layer

Claims (6)

A liquid crystal display device having a pixel electrode including a transmissive pixel electrode and a reflective pixel electrode formed on a part of the transmissive pixel electrode,
An array substrate on which the pixel electrode is formed in a display area;
A counter substrate disposed opposite to the array substrate;
A seal material that is formed in a frame shape so as to surround the display region in a frame region outside the display region, and bonds the array substrate and the counter substrate;
A pixel thick film portion formed in the display region and provided under the pixel electrode;
A pad thick film portion formed inside the seal material in the frame region, and formed between the display region and the frame region, and between the pixel thick film portion and the pad thick film portion. The inter-region thin film portion provided in the
An organic film having
A gap holding pad having the thick film portion for the pad;
A columnar spacer formed on the counter substrate at a position facing the pixel electrode and a position facing the gap holding pad ;
The organic film further includes a thin film portion between pads formed in the frame region,
The inter-pad thin film portion is provided between the pad thick film portions adjacent to each other and is not covered with a transparent conductive layer and a reflective metal layer .
Liquid crystal display device. The gap holding pad includes the same transparent conductive layer as the transmissive pixel electrode formed on the pad thick film portion,
The inter-region thin film portion is not covered with a transparent conductive layer,
The liquid crystal display device according to claim 1. The gap holding pad further includes a reflective metal layer formed on the transparent conductive layer, the same reflective metal layer as the reflective pixel electrode,
The inter-region thin film portion is not covered with a reflective metal layer,
The liquid crystal display device according to claim 2. Among the columnar spacers formed at positions facing the gap holding pads, a plurality of the columnar spacers are arranged to face one gap holding pad.
The liquid crystal display device according to claim 1. The gap holding pad is formed in a strip shape along each side of the sealing material.
The liquid crystal display device according to claim 4 . The columnar spacers formed at positions facing the gap holding pads are respectively arranged to face one gap holding pad.
The liquid crystal display device according to claim 1.

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