JP5739734B2 - Power converter - Google Patents

Description

  The present invention relates to a power converter, and more particularly to a power converter that converts one of DC power and AC power into the other power.

  For example, Japanese Patent Laying-Open No. 2003-70262 (Patent Document 1) discloses a power conversion device including a three-level PWM converter and a three-level PWM inverter. In this power conversion device, in order to prevent a frequently used switch from being damaged by heat generation, the frequently used switch is composed of two semiconductor switching elements connected in parallel.

JP 2003-70262 A

  In the case of a power converter equipped with a neutral point switch type three-level main circuit, if the AC switch element connected to the neutral point fails, the operation of the main circuit becomes a two-level operation. In this case, a large surge voltage is generated as compared with the normal time, and the main element constituting the main circuit may be damaged.

  Therefore, a main object of the present invention is to provide a power conversion device capable of suppressing a failure range.

In summary, the present invention is a power conversion device, which is connected between a first capacitor connected between a DC positive phase and a neutral phase, and between a DC negative phase and a neutral phase. A second capacitor; first and second switch elements connected in series between a positive phase and a negative phase of the DC; and first and second switches connected in reverse parallel to the first and second switch elements, respectively. A second diode; a third switch element having one end connected to a connection point of the first and second switch elements; a first end connected to the neutral phase; The fourth switch element connected to the other end of the switch element, the third and fourth diodes connected in antiparallel to the third and fourth switch elements, respectively, and the first and second switch elements are 3 The first to fourth switches are operated so as to operate as a level conversion circuit. A control unit for controlling the device, a current sensor for detecting the current to be input to one end of the third switch element, that at least one of the third and fourth switching elements has been opened failure And a failure detection circuit for detection. The failure detection circuit compares the integration value of the current value detected by the current sensor with the integration value of the current value from the integration circuit and a predetermined positive limit value of the integration value. A first comparison circuit that outputs a failure detection signal for turning off the first to fourth switch elements when the positive limit value is exceeded, an integration value of the current value from the integration circuit, and the integration value A second comparison circuit that compares a predetermined negative limit value and outputs a failure detection signal for turning off the first to fourth switch elements when the integral value is lower than the predetermined negative limit value. Including. Control unit, in response to the failure detection signal from the first or second comparison circuit is output to stop the power conversion device.

  According to the present invention, the power converter can be stopped when a failure of the switch element connected to the neutral point is detected. Therefore, according to this invention, the range of failure of the power converter can be suppressed.

It is a schematic block diagram which shows the structure of the power converter device by Embodiment 1 of this invention. It is a figure for demonstrating the structure of the U-phase unit 2U. FIG. 3 is a functional block diagram illustrating a configuration example of a control circuit 10 illustrated in FIG. 2. It is a wave form diagram explaining operation | movement of main element Q1, Q4 and AC switch element Q2, Q3 at the time of normal. FIG. 3 is a circuit diagram showing an operation of a U-phase unit 2U shown in FIG. It is another circuit diagram which shows the operation | movement of the U-phase unit 2U shown in FIG. FIG. 4 is a diagram illustrating a configuration of a failure detection circuit 27 illustrated in FIG. 3. It is the wave form diagram which showed the result of having simulated the operation | movement of the power converter device 100 when AC switch element Q2 breaks openly in the state where load is 100%. It is the wave form diagram which showed the result of having simulated the operation | movement of the power converter device 100 when AC switch element Q2 breaks openly in the state where load is 20%. It is a figure for demonstrating the structure of the U-phase unit among the three units with which the power converter device by Embodiment 2 of this invention is provided. FIG. 11 is a functional block diagram illustrating a configuration example of a control circuit 10A illustrated in FIG. It is a block diagram of the failure detection circuit 27A shown in FIG. It is a figure for demonstrating the structure of the U-phase unit among the three units with which the power converter device by Embodiment 3 of this invention is provided. FIG. 14 is a functional block diagram illustrating a configuration example of a control circuit 10B illustrated in FIG. It is a block diagram of the failure detection circuit 27B shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing a configuration of a power conversion device according to Embodiment 1 of the present invention. Referring to FIG. 1, power conversion device 100 converts DC power from DC power supply 1 into a three-phase AC and applies it to load 16. The power conversion device 100 includes capacitors C1 and C2 and an inverter 2. Inverter 2 includes a U-phase unit 2U, a V-phase unit 2V, and a W-phase unit 2W corresponding to each phase of the three-phase AC.

  Capacitors C <b> 1 and C <b> 2 are connected in series between the positive electrode line 11 and the negative electrode line 12 of the DC power supply 1. The capacitor C1 is connected between a DC positive phase and a neutral phase, and the capacitor C2 is connected between a DC negative phase and a neutral phase. Each of U-phase unit 2U, V-phase unit 2V, and W-phase unit 2W is connected to positive electrode line 11 and negative electrode line, and further connected to a neutral phase (a connection point of capacitors C1 and C2). U-phase unit 2U, V-phase unit 2V, and W-phase unit 2W output AC voltages from lines 14U, 14V, and 14W, respectively. Load 16 is connected to U-phase unit 2U, V-phase unit 2V, and W-phase unit 2W by lines 14U, 14V, and 14W, and is connected to negative electrode line 12 by line 15.

  The configurations of the U-phase unit 2U, the V-phase unit 2V, and the W-phase unit 2W are common. Hereinafter, representatively, the configuration of U-phase unit 2U will be described in detail, and detailed description of the configurations of V-phase unit 2V and W-phase unit 2W will not be repeated.

  FIG. 2 is a diagram for explaining the configuration of the U-phase unit 2U. 2, U-phase unit 2U includes AC switch elements Q2 and Q3, main elements Q1 and Q4, diodes D1 to D4, current sensors 6 and 7, and voltage sensor 8. Power conversion device 100 further includes a control circuit 10 for controlling U-phase unit 2U (the same applies to V-phase unit 2V and W-phase unit 2W).

  The main elements Q1 and Q4 and the AC switch elements Q2 and Q3 are turned on / off according to the control signal S from the control circuit 10. These switch elements are realized by a semiconductor switch element such as an IGBT (Insulated Gate Bipolar Transistor).

  AC switch elements Q2 and Q3 have their collectors connected to each other. The emitter of AC switch element Q3 is connected to the neutral phase of DC (the connection point of capacitors C1 and C2). The emitter of AC switch element Q2 is connected to the connection point of switch elements Q1 and Q4 via line 13. Diodes D2 and D3 are connected in antiparallel to AC switch elements Q2 and Q3, respectively.

  The main elements Q1, Q4 are connected in series between the positive electrode line 11 and the negative electrode line 12. Diodes D1 and D4 are connected in antiparallel to main elements Q1 and Q4, respectively.

  The collector of the main element Q1 is connected to the positive electrode line 11. On the other hand, the emitter of the main element Q4 is connected to the negative electrode line 12. The emitter of the main element Q1 and the collector of the main element Q4 are connected to each other and to both the lines 13 and 14.

  The current sensor 6 detects a current idu (AC switch current) input / output to / from the AC switch element Q2 via the line 13. The value of the current idu detected by the current sensor 6 is sent to the control circuit 10.

  The line 13 and one end of the load 16 are connected by a line 14 (corresponding to the line 14U in FIG. 1). The other end of the load 16 is connected to the negative electrode line 12 by a line 15.

  Output voltage Vou from U-phase unit 2U is applied to load 16 via line 14. The current sensor 7 detects a current iau flowing through the line 14. The voltage sensor 8 detects the voltage Vou of the line 14. The output of the current sensor 7 and the output of the voltage sensor 8 are sent to the control circuit 10.

  Based on the output of the current sensor 7 and the output of the voltage sensor 8, the control circuit 10 generates a control signal S for turning on and off the AC switch elements Q2 and Q3 and the main elements Q1 and Q4. The switch elements (IGBT gates) are supplied.

  Furthermore, the control circuit 10 detects a failure (for example, an open failure) of at least one of the AC switch elements Q2 and Q3 based on the output of the current sensor 6. An open failure is a failure in which the switch element does not turn on (is kept off).

  When such a failure occurs, control circuit 10 turns off AC switch elements Q2, Q3 and main elements Q1, Q4. This can reduce the possibility that the main elements Q1 and Q4 will fail.

  FIG. 3 is a functional block diagram showing a configuration example of the control circuit 10 shown in FIG. 2 and 3, control circuit 10 includes a reference generation circuit 21, an output voltage control circuit 22, a zero-phase voltage control circuit 23, an adder 24, an output current control circuit 25, and a gate control. A circuit 26 and a failure detection circuit 27 are included.

  The reference generation circuit 21 generates a three-phase reference value Vr (a U-phase reference value, a V-phase reference value, and a W-phase reference value are collectively shown) that is an amplitude reference value of the three-phase AC voltage. The waveform of the reference value Vr is, for example, a sine wave. The reference value Vr generated by the reference generation circuit 21 is output to the output voltage control circuit 22.

  The output voltage control circuit 22 calculates a deviation between the reference value Vr and the output voltage Vo (the U phase voltage Vou, the V phase voltage and the W phase voltage are collectively shown) detected by the voltage sensor 8 of each phase, A current command value Ir * (a U-phase current command value, a V-phase current command value, and a W-phase current command value are collectively shown), which is a reference value of the output current, is calculated according to the deviation.

  The current command value Ir * calculated by the output voltage control circuit 22 is input to the adding unit 24. Further, the zero-phase current command value Irz * from the zero-phase voltage control circuit 23 is input to the adding unit 24. Adder 24 adds current command value Ir * and zero-phase current command value Irz *, and outputs the addition result to output current control circuit 25 as output current command value ia *.

  The output current control circuit 25 receives the output current command value ia * from the adder 24, receives the output voltage Vo detected by the voltage sensor 8, and receives the current ia detected by the current sensor 7. Based on these inputs, the output current control circuit 25 generates an output voltage command value Vo * (shows the U-phase voltage command value, the V-phase voltage command value, and the W-phase voltage command value together), and the generated output The voltage command value Vo * is output to the gate control circuit 26.

  Gate control circuit 26 generates a control signal S for controlling on / off of main elements Q1 and Q4 and AC switch elements Q2 and Q3 based on a comparison between a carrier wave (for example, a triangular wave) and output voltage command value Vo *. Then, the generated control signal S is output to the main elements Q1 and Q4 and the AC switch elements Q2 and Q3 of each unit.

  The failure detection circuit 27 uses at least one of the AC switch elements Q2 and Q3 in each unit based on the current id (the U-phase current idu, the V-phase current and the W-phase current are collectively shown) detected by the current sensor 6. Is detected, and a signal indicating the detection result is output to the gate control circuit 26. The gate control circuit 26 generates a control signal S for turning off the main elements Q1 and Q4 and the AC switch elements Q2 and Q3 according to the signal from the failure detection circuit 27.

  Next, the operation of the power conversion device shown in FIG. 1 will be described. In the following, the operation of any one of the three phase units will be described. The operation of the other two units is the same as the operation described below except that the phase of the output voltage is different by + 120 ° or -120 °. In this embodiment, each of the three units is operated as a three-level conversion circuit. That is, each unit controls the pulse voltage in three stages.

  FIG. 4 is a waveform diagram for explaining the operation of the main elements Q1 and Q4 and the AC switch elements Q2 and Q3 at the normal time. Referring to FIGS. 3 and 4, gate control circuit 26 compares the output voltage command value Vo * with the reference signals φ 1 and φ 2. On / off combinations of main elements Q1, Q4 and AC switch elements Q2, Q3 are determined based on the comparison result.

  During a period (t1, t3, t5, t7, t9, t11, t13) in which the level of the output voltage command value Vo * is between the levels of the reference signals φ1, φ2, the AC switch elements Q2, Q3 are turned on, and the main element Q1 and Q4 are turned off. During a period (t2, t4, t10, t12) in which the level of the output voltage command value Vo * is higher than the level of the reference signals φ1, φ2, the main element Q1 and the AC switch element Q2 are turned on, and the main element Q4 and the AC switch element Q3 is turned off. During the period (t6, t8) when the level of the output voltage command value Vo * is lower than the level of the reference signals φ1, φ2, the main element Q4 and the AC switch element Q3 are turned on, and the main element Q1 and the AC switch element Q2 are turned off. The

  FIGS. 5A to 5D show the on / off states and currents of the main elements Q1 and Q4 and the AC switch elements Q2 and Q3 in the period t4 to t6 in which the output voltage command value Vo * changes from the positive voltage to the negative voltage. It is a figure which shows a path | route. The “periods t4 to t6” correspond to the periods t4 to t6 shown in FIG.

  As shown in FIG. 5A, the main element Q1 and the AC switch element Q2 are turned on, and a positive voltage is output from the capacitor C1 to the line 14 via the main element Q1. In the period transitioning from the period t4 to t5, as shown in FIG. 5B, the main element Q1 is turned off and only the AC switch element Q2 is turned on.

  In the period t5, as shown in FIG. 5C, the AC switch elements Q2 and Q3 are turned on, and the neutral point voltage is output from the capacitors C1 and C2 to the line 14 via the AC switch elements Q2 and Q3. In the period transitioning from the period t5 to t6, as shown in FIG. 5D, the AC switch element Q2 is turned off and only the AC switch element Q3 is turned on. In the period t6, as shown in FIG. 5E, the main element Q4 and the AC switch element Q3 are turned on, and a negative voltage is output from the capacitor C2 to the line 14 via the main element Q4.

  6A to 6D show on / off states and currents of the main elements Q1 and Q4 and the AC switch elements Q2 and Q3 in the period t8 to t10 in which the output voltage command value Vo * changes from a negative voltage to a positive voltage. It is a figure which shows a path | route. The “periods t8 to t10” correspond to the periods t8 to t10 shown in FIG.

  As shown in FIG. 6A, in the period t8, the main element Q4 and the AC switch element Q3 are turned on, and a negative voltage is output from the capacitor C2 to the line 14 via the main element Q4. In the period transitioning from the period t8 to t9, as shown in FIG. 6B, the main element Q4 is turned off and only the AC switch element Q3 is turned on.

  In the period t9, as shown in FIG. 6C, the AC switch elements Q2 and Q3 are turned on, and the neutral point voltage is output from the capacitors C1 and C2 to the line 14 via the AC switch elements Q2 and Q3. In the period transitioning from the period t9 to t10, as shown in FIG. 6D, the AC switch element Q3 is turned off and only the AC switch element Q2 is turned on. In the period t10, as shown in FIG. 6E, the main element Q1 and the AC switch element Q2 are turned on, and a positive voltage is output from the capacitor C1 to the line 14 via the main element Q1.

  By operating each unit as a three-level circuit, the waveform of the output voltage can be made closer to a sine wave as compared to a two-level circuit. However, when a failure (specifically, open failure) occurs in one of the AC switch elements Q2 and Q3, the operation of the unit including the AC switch element in which the failure has occurred becomes a two-level operation.

  In this case, since the change width of the output voltage Vo due to on / off of the main elements Q1 and Q4 is increased, the surge voltage is increased. When this surge voltage exceeds the withstand voltage of main elements Q1, Q4, main elements Q1, Q4 may be damaged.

  In the first embodiment, currents input / output to / from AC switch element Q2 (current idu shown in FIG. 2 and current id shown in FIG. 3 are detected by current sensor 6. Based on the detected current, AC When the failure of the switch elements Q2 and Q3 is detected, when the failure of the AC switch elements Q2 and Q3 is detected, the control circuit 10 stops the power converter, specifically, the switch elements (AC Switch element and main element) are turned off.

  FIG. 7 is a diagram showing a configuration of failure detection circuit 27 shown in FIG. Referring to FIG. 7, failure detection circuit 27 includes an integration circuit 31, a limit value generation circuit 32, comparators 33 and 34, and an OR circuit 35.

  The integrating circuit 31 integrates the current id detected by the current sensor 6 of each unit. The limit value generation circuit 32 generates a positive limit value and a negative limit value of the integral value of the current id. The comparator 33 compares the integrated value of the current id with a positive limit value. The comparator 34 compares the integrated value of the current id with the negative limit value. The OR circuit 35 generates a logical sum of the output of the comparator 33 and the output of the comparator 34. The output of the OR circuit 35 is given to the gate control circuit 26.

  When AC switch elements Q2 and Q3 are normal, current sensor 6 detects current id in the positive direction during the switching period (for example, the period from t2 to t4 shown in FIG. 4) on main element Q1 and AC switch element Q3 side. . On the other hand, in the switching period (for example, the period from t6 to t8 shown in FIG. 4) on the main element Q4 and AC switching element Q2 side, the current sensor 6 detects the current id in the negative direction. When the AC switch elements Q2 and Q3 are normal, the integral value of the current id over one period is zero.

  In this case, since both the outputs of the comparators 33 and 34 are “0”, the output of the OR circuit 35 is “0” indicating that the AC switch elements Q2 and Q3 are normal. Therefore, the gate control circuit 26 generates a control signal for turning on / off the main elements Q1, Q4 and the AC switch elements Q2, Q3.

  On the other hand, when the AC switch element Q2 has an open failure, a positive current id does not occur during the switching period on the main element Q1 and AC switch element Q3 side. Therefore, the integral value of one cycle of the current id is a negative value. While continuing the operation of the power conversion device 100, the integrated value of the current id increases in the negative direction and falls below the negative limit value. At this time, the comparator 34 outputs “1” indicating a failure of the AC switch element Q2. The OR circuit 35 outputs “1” in response to the output “1” of the comparator 34.

  Conversely, when the AC switch element Q3 has an open failure, no negative current id occurs in the switching period on the main element Q4 and AC switch element Q2 side. Therefore, the integral value of one cycle of the current id becomes a positive value. As the operation of the power conversion device 100 continues, the integral value of the current id increases in the positive direction and exceeds the positive limit value. At this time, the comparator 33 outputs “1” indicating a failure of the AC switch element Q3. The OR circuit 35 outputs “1” in response to the output “1” of the comparator 33.

  The positive limit value is set to, for example, twice the integral value of the current id during a period in which the current id is positive (that is, a half cycle). Similarly, the negative limit value is set to, for example, twice the integral value of the current id during a period in which the current id is negative (that is, a half cycle). The setting of the limit value is not limited to this.

  The output “1” of the OR circuit 35 indicates a failure of the AC switch element Q2 or Q3. In this case, the gate control circuit 26 generates a control signal for turning off the main elements Q1, Q4 and the AC switch elements Q2, Q3. That is, the comparators 33 and 34 are circuits for generating signals for turning off the main elements Q1 and Q4 and the AC switch elements Q2 and Q3.

  8 and 9 are waveform diagrams showing the results of simulating the operation of the power conversion device 100 when the AC switch element Q2 breaks open. FIG. 8 is a waveform diagram illustrating the operation of the power conversion device 100 when the load is 100%, and FIG. 9 is a waveform diagram illustrating the operation of the power conversion device 100 when the load is 20%. is there. 8 and 9, the direction of the current is positive when current flows from the collector to the emitter of the switch element, and negative when current flows through the diode connected in reverse parallel to the switch element. .

  After AC switch element Q2 breaks open, no current flows through AC switch element Q2. For this reason, only the current in the negative direction, that is, the current flowing through the diode D2 and the AC switch element Q3, is generated as the current id of the AC switch element. For this reason, the integral value of the current id increases in the negative direction. Conversely, when the AC switch element Q3 breaks open, only the current in the positive direction, that is, the current flowing through the diode D3 and the AC switch element Q2 is generated as the current id of the AC switch element. In this case, the integrated value of the current id increases in the positive direction. Therefore, the failure detection circuit 27 shown in FIG. 7 can detect the failure of the AC switch element Q2 or Q3.

  As described above, according to the first embodiment, failure detection circuit 27 compares the integral value of current id flowing through AC switch elements Q2 and Q3 with the upper limit value. As a result, a failure of the AC switch element Q2 or Q3 can be detected.

  Further, according to the first embodiment, when the failure detection circuit 27 detects an open failure of the AC switch element Q2 or Q3 in a certain phase, the gate control circuit 26 generates a signal for stopping the power conversion device. To do. Thereby, it can prevent that a failure expands.

[Embodiment 2]
FIG. 10 is a diagram for describing the configuration of the U-phase unit among the three units included in the power conversion device according to Embodiment 2 of the present invention. The remaining two units have the same configuration as the U-phase unit shown in FIG.

  2 and 10, the power conversion apparatus according to the second embodiment is different from the first embodiment in that the current sensor 6 of each unit is omitted. Furthermore, the power conversion device according to the second embodiment is different from the first embodiment in that a control circuit 10A is provided instead of the control circuit 10. Since the structure of the other part of the power converter device which concerns on Embodiment 2 is the same as the structure of the corresponding part of the power converter device which concerns on Embodiment 1, subsequent description is not repeated.

  FIG. 11 is a functional block diagram showing a configuration example of the control circuit 10A shown in FIG. Referring to FIGS. 3 and 11, control circuit 10 </ b> A is different from control circuit 10 in that it includes failure detection circuit 27 </ b> A instead of failure detection circuit 27. Since the configuration of other parts of control circuit 10A is similar to the configuration of the corresponding part of control circuit 10, the following description will not be repeated.

  Referring to FIGS. 8 and 9 again, when the AC switching element Q2 is broken open, distortion occurs in the d-axis component and the q-axis component of the output voltage Vo (broken lines in FIGS. 8 and 9). Part surrounded by). In the second embodiment, failure detection circuit 27A detects an open failure of AC switch element Q2 or Q3 based on the distortion rates of the d-axis component and q-axis component of output voltage Vo. For both the d-axis component and the q-axis component, the distortion rate is obtained from the ratio of the output voltage to the voltage command value. In order to calculate the distortion rate, the failure detection circuit 27A receives the output voltage command value Vo * from the output current control circuit 25.

  FIG. 12 is a configuration diagram of the failure detection circuit 27A shown in FIG. Referring to FIG. 12, failure detection circuit 27A includes a distortion rate calculation unit 41, a limit value generation circuit 42, comparators 43 and 44, an OR circuit 45, an RS flip-flop 46, and a timer 47. .

  The distortion rate calculation unit 41 receives the voltage Vo detected by the voltage sensor 8 of each phase and generates a d-axis component and a q-axis component.

  The distortion rate calculation unit 41 receives the output voltage command value Vo * from the output current control circuit 25 and generates a d-axis component and a q-axis component of the output voltage command value Vo *.

  Furthermore, the distortion rate calculation unit 41 calculates the ratio of the actual output voltage to the command value for each of the d-axis component and the q-axis component, and calculates the calculated ratio from the ratio (= 1) when there is no distortion rate. Subtract. Thereby, the distortion rate of each of the d-axis component and the q-axis component is calculated. The distortion rate of the d-axis component is given to the comparator 43, and the distortion rate of the q-axis component is given to the comparator 44.

  The limit value generation circuit 42 generates limit values for the distortion rate of the d-axis component and the distortion rate of the q-axis component. In this embodiment, the limit value of the distortion rate of the d-axis component and the limit value of the distortion rate of the q-axis component are common. The limit value is not particularly limited, but is 5%, for example. The limit value may be different between the d-axis component and the q-axis component.

  The comparator 43 compares the distortion rate of the d-axis component with the limit value. The comparator 44 compares the distortion rate of the q-axis component with the limit value. When the distortion rate of the d-axis component exceeds the limit value, the comparator 43 outputs “1”. When the distortion rate of the q-axis component exceeds the limit value, the comparator 44 outputs “1”. Each of the comparators 43 and 44 outputs “0” when the distortion rate of the corresponding component is below the limit value.

  The OR circuit 45 generates a logical sum of the output of the comparator 43 and the output of the comparator 44. The output of the OR circuit 45 is input to the S terminal of the RS flip-flop 46.

  When at least one of the output of the comparator 43 and the output of the comparator 44 is “1”, the output of the OR circuit 45 is “1”. As a result, the output of the RS flip-flop 46 (output from the Q terminal) becomes “1”. The output of the RS flip-flop 46 is sent to the gate control circuit 26 and also sent to the timer 47.

  The timer 47 is activated when the output of the RS flip-flop 46 becomes “1”, and outputs “1” after a predetermined time (for example, 1 second). After outputting “1”, the output of the timer 47 returns to “0”. The output of the timer 47 is input to the R terminal of the RS flip-flop 46. When the output of the timer 47 becomes “1”, the output of the RS flip-flop 46 is reset and returns to “0”.

  That is, when at least one of the output of the comparator 43 and the output of the comparator 44 is “1”, the output of the RS flip-flop 46 is kept at “1” for a predetermined time set by the timer 47, It is then reset. When both the output of the comparator 43 and the output of the comparator 44 are “0”, the output of the RS flip-flop 46 is kept at “0”.

  When AC switch elements Q2 and Q3 are normal, the d-axis component and the q-axis component of the output voltage are constant values. However, when the AC switch element Q2 or Q3 fails to open, the failed AC switch element cannot be turned on during the period in which it should be turned on. For this reason, distortion occurs in the d-axis component and the q-axis component of the output voltage. When the distortion rate exceeds the limit value, the failure detection circuit 27A detects an open failure of the AC switch element Q2 or Q3. The comparators 43 and 44, the OR circuit 45, the RS flip-flop 46, and the timer 47 are at least when the distortion rate of the d-axis component exceeds the upper limit value and when the distortion rate of the q-axis component exceeds the upper limit value. In one case, a signal generation circuit that generates a signal for turning off the main elements Q1 and Q4 and the AC switch elements Q2 and Q3 is configured.

  According to the second embodiment, the same effect as in the first embodiment can be obtained. According to the second embodiment, voltage sensor 8 is used not only to control main elements Q1 and Q4 and AC switch elements Q2 and Q3, but also to detect an open failure of AC switch element Q2 or Q3. Therefore, according to the second embodiment, it is possible to detect an open failure of the AC switch element Q2 or Q3 while eliminating the need for a current sensor for detecting the current flowing through the AC switch elements Q2 and Q3.

  Furthermore, according to the second embodiment, an AC switch element open failure is detected based on the distortion rate of the d-axis component and the q-axis component of the output voltage. When a three-phase AC voltage is used as it is as an output voltage, it may be difficult to detect distortion because the three-phase AC voltage changes with time. On the other hand, when the AC switch element is normal, the d-axis component and the q-axis component are constant values. Therefore, according to the second embodiment, the distortion of the output voltage can be easily detected by detecting the distortion rate of the d-axis component or the q-axis component.

[Embodiment 3]
In the third embodiment, the open failure of the AC switch element Q2 or Q3 is detected by combining the first and second embodiments.

  FIG. 13 is a diagram for explaining a configuration of a U-phase unit among three units included in the power conversion device according to Embodiment 3 of the present invention. The configuration of the remaining two units is the same as the configuration of the U-phase unit shown in FIG. With reference to FIG. 2 and FIG. 13, in the power conversion device according to the third embodiment, the configuration of each unit is the same as that of the first embodiment. However, the power conversion device according to the third embodiment is different from the power conversion device according to the first embodiment in that a control circuit 10B is provided instead of the control circuit 10. In addition, since the structure of the other part of the power converter device which concerns on Embodiment 3 is the same as the structure of the corresponding part of the power converter device which concerns on Embodiment 1, subsequent description is not repeated.

  FIG. 14 is a functional block diagram showing a configuration example of the control circuit 10B shown in FIG. Referring to FIGS. 3 and 14, control circuit 10 </ b> B differs from control circuit 10 in that it includes failure detection circuit 27 </ b> B instead of failure detection circuit 27. Since the configuration of other parts of control circuit 10B is the same as the configuration of the corresponding part of control circuit 10, the following description will not be repeated.

  FIG. 15 is a configuration diagram of failure detection circuit 27B shown in FIG. Referring to FIG. 15, failure detection circuit 27 </ b> B includes failure detection circuit 27, failure detection circuit 27 </ b> A, and OR circuit 51. The failure detection circuit 27 has the configuration shown in FIG. The failure detection circuit 27A has the configuration shown in FIG. The OR circuit 51 generates a logical sum of the output of the failure detection circuit 27 and the output of the failure detection circuit 27A. The output of the OR circuit 51 is given to the gate control circuit 26.

  According to the configuration shown in FIG. 15, the detection of the AC switch element failure according to the first embodiment and the detection of the AC switch element failure according to the second embodiment are combined. Therefore, a failure of the AC switch element can be detected more reliably.

  In each of the above embodiments, the configuration for converting power from DC power to three-phase AC has been described. However, the present invention can also be applied to a configuration for converting power from three-phase AC to DC power. is there. For example, the present invention can be applied to a configuration in which power conversion is performed between DC power and single-phase AC by setting the number of units to two.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  1 DC power supply, 2 inverter, 2U U phase unit, 2V V phase unit, 2W W phase unit, 6, 7 current sensor, 8 voltage sensor, 10, 10A, 10B control circuit, 11 positive line, 12 negative line, 13, 14, 14U, 14V, 14W, 15 lines, 16 loads, 21 reference generation circuit, 22 output voltage control circuit, 23 zero phase voltage control circuit, 24 adder, 25 output current control circuit, 26 gate control circuit, 27, 27A , 27B Fault detection circuit, 31 integration circuit, 32, 42 limit value generation circuit, 33, 34, 43, 44 comparator, 35, 45, 51 OR circuit, 41 distortion rate calculation unit, 46 RS flip-flop, 47 timer, 100 Power converter, C1, C2 capacitors, D1-D4 diodes, Q1, Q4 main elements.

Claims (3)

A power converter,
A first capacitor connected between a DC positive phase and a neutral phase;
A second capacitor connected between the DC negative phase and the neutral phase;
First and second switch elements connected in series between the positive phase and the negative phase of the direct current;
First and second diodes connected in antiparallel to the first and second switch elements, respectively;
A third switch element having one end connected to a connection point of the first and second switch elements;
A fourth switch element having one end connected to the neutral phase and the other end connected to the other end of the third switch element;
Third and fourth diodes connected in antiparallel to the third and fourth switch elements, respectively;
A control unit for controlling the first to fourth switch elements so that the first and second switch elements operate as a three-level conversion circuit;
A current sensor for detecting a current input to and output from one end of the third switch element;
A failure detection circuit for detecting that at least one of the third and fourth switch elements has an open failure ;
The failure detection circuit is
An integrating circuit for integrating the current value detected by the current sensor;
When the integrated value of the current value from the integrating circuit is compared with a predetermined positive limit value of the integrated value, and the integrated value exceeds the predetermined positive limit value, the first to first A first comparison circuit that outputs a failure detection signal for turning off the four switch elements;
When the integrated value of the current value from the integrating circuit is compared with a predetermined negative limit value of the integrated value, and the integrated value falls below the predetermined negative limit value, the first to first A second comparison circuit that outputs the failure detection signal for turning off the switching element of 4;
The said control part is a power converter device which stops the said power converter device according to the said failure detection signal being output from the said 1st or 2nd comparison circuit . A power conversion device,
A first capacitor connected between a DC positive phase and a neutral phase;
A second capacitor connected between the DC negative phase and the neutral phase;
First and second switch elements connected in series between the positive phase and the negative phase of the direct current;
First and second diodes connected in antiparallel to the first and second switch elements, respectively;
A third switch element having one end connected to a connection point of the first and second switch elements;
A fourth switch element having one end connected to the neutral phase and the other end connected to the other end of the third switch element;
Third and fourth diodes connected in antiparallel to the third and fourth switch elements, respectively;
A voltage sensor for detecting a voltage of the connection point of the first and second switching elements,
A controller that controls the first to fourth switch elements based on a voltage value detected by the voltage sensor so that the first and second switch elements operate as a three-level conversion circuit ;
A first failure detection circuit for detecting that at least one of the third and fourth switch elements has failed,
The first failure detection circuit includes:
Generating a d-axis component and a q-axis component of the voltage value detected by the voltage sensor, and using the reference value corresponding to each of the d-axis component and the q-axis component, the d-axis component and the q-axis component; A distortion rate calculation unit for calculating each distortion rate of
The first to fourth switch elements are turned off when the distortion rate of the d-axis component exceeds an upper limit value and / or when the distortion rate of the q-axis component exceeds an upper limit value. look including a signal generation circuit for outputting a failure detection signal for,
The said control part is a power converter device which stops the said power converter device according to the said failure detection signal being output from the said 1st failure detection circuit . Furthermore, a current sensor for detecting a current input to and output from one end of the third switch element;
A second failure detection circuit for detecting that at least one of the third and fourth switch elements has failed ,
The second failure detection circuit includes:
An integrating circuit for integrating the current value detected by the current sensor;
When the integrated value of the current value from the integrating circuit is compared with a predetermined upper limit value of the integrated value, and the integrated value exceeds the predetermined upper limit value, the first to fourth switch elements A comparator circuit for outputting the failure detection signal for turning off
The said control part stops the said power converter device according to the said failure detection signal being output from at least any one of the said 1st and 2nd failure detection circuit. Power conversion device.