JP2000278958A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the full voltage of power source voltage from being applied to a second switching element or a third switching element. SOLUTION: A power converter, in which from a first switching element 19a to a fourth switching element 20a are connected in order between the positive potential and the negative potential of a DC power source, and which outputs AC-phase voltage having three levels of potential from the junction between a second switching element 34a and a third switching element 35a, and detects the abnormality of each switching element 19a, 34a, 35a, and 20a and breaks it, is equipped with a delay circuit 43 which outputs a break signal so that the break of the second switching element 34a and the third switching element 35a may be behind the break of the first switching element 19a and the fourth switching element 20a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device such as an inverter or a converter for outputting a three-level voltage.

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a configuration diagram illustrating a main circuit of a three-phase inverter that is a power conversion device applied to a railway electric vehicle described in Japanese Patent Application Laid-Open Publication No. HEI 10-152139. In FIG. 4, 1 is a train line to which a DC voltage is applied from a DC power supply (not shown), 2 is a DC reactor,
Reference numerals 3 and 4 denote clamp capacitors, which create intermediate potential points from the DC voltage of the train line 1. Switching unit 5 for each phase
Reference numeral 7 denotes switching elements 5a to 5 that enable self-protection.
d, 6a to 6d, and 7a to 7d are connected in series. The first to fourth switching elements 5a to 5a of the switching units 5 to 7 are used.
By controlling the gate signals of d, 6a to 6d and 7a to 7d,
Two adjacent ones are turned on sequentially. Thereby, the high-potential point voltage at point P, the neutral point voltage at point O, and N
The three-level voltage of the low potential point voltage at the point is selectively output from each output terminal 5e, 6e, 7e, and three-phase AC power is supplied to the induction motor 8 of the load. Generally, each of the switching elements 5a to 5d, 6a to 6d, and 7a to 7d is integrated with a gate driver with a protection function as a main circuit element.

FIG. 5 shows, for example, a second switching element 5.
FIG. 3 is a configuration diagram showing a main circuit element incorporating b. The other switching elements 5a, 5c, 5d, 6a to 6d,
The main circuit elements having the built-in circuits 7a to 7d are similarly configured. In FIG. 5, the normal operation is that the gate control signal 9 is A
The signal is amplified by the amplifier 11 via the ND element 10 and on-off control of the second switching element 5b is performed. When the control voltage detection circuit 12, the current detection circuit 13, and the temperature detection circuit 14 determine that the set values 12a, 13a, and 14a are abnormal, the cutoff signal 15a is output to the AND element 10 via the OR circuit 15. Is input to the active low input terminal. Therefore, the gate control signal 9 is cut off, and the second switching element 5b is cut off by the self-protection function. Further, the cutoff signal 5a is transmitted to the other switching elements 5a, 5a in the same switching unit 5.
The signal is also transmitted to each main circuit element in which c and 5d are built. For example, when the first switching element 5a and the second switching element 5b are operating in the “ON” state, the gate control signal 9 of the first switching element 5a is cut off and the first switching element 5a is cut off. Is done.

[0004]

Since the conventional power converter is constructed as described above, for example, in the switching unit 5, the first switching element 5a and the second switching element 5b are in the "ON" state. When the current is output from the output terminal 5e through the first switching element 5a through the second switching element 5b,
When the control voltage detection circuit 12 of the main circuit element in which the second switching element 5b is built detects a decrease in the control voltage and outputs the cutoff signal 15a, each of the switching elements 5a,
5b is shut off. In this case, since the interruption of the second switching element 5b in which the failure has been detected by the self-protection is generally quickened, the first switching element 5 in the “ON” state is generally used.
Since the entire DC voltage of the clamp capacitors 3 and 4 is applied to the second switching element 5b through a, there is a problem that the withstand voltage of the second switching element 5b must be increased.

When the third switching element 5c and the fourth switching element 5d are in the "on" state, the third switching element 5c
Similarly, when the switching element 5c is cut off by self-protection, the entire voltage is applied to the third switching element 5c. The present invention has been made to solve the above problems, and when the second switching element or the third switching element is cut off, the entire DC power supply voltage is reduced to the second switching element. Another object of the present invention is to provide a power conversion device capable of preventing application to a third switching element.

[0006]

A power converter according to the present invention connects a first clamp capacitor and a second clamp capacitor between a positive potential and a negative potential of a DC power supply, and further includes a first A switching element to a fourth switching element are sequentially connected between a positive potential and a negative potential of the DC power supply, and an AC phase voltage having a three-level potential is connected to a connection portion between the second switching element and the third switching element. In the power conversion device configured to detect the abnormality of each switching element and perform the interruption of each switching element, the interruption of the second switching element and the third switching element is performed by the first switching element and the third switching element. 4 is provided with a delay circuit that outputs a cutoff signal so as to be later than the cutoff of the switching element. The cutoff signal is output when overheating of each switching element is detected. The cutoff signal is output when it is detected that the control voltage of each switching element has become equal to or less than a predetermined value. The cutoff signal is output when it is detected that a current equal to or more than a predetermined value has flowed through each switching element. Further, the cutoff signals of the first switching element and the fourth switching element are output at a lower current than the cutoff signals of the second switching element and the third switching element are output.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a configuration diagram showing the first embodiment, showing one phase of a three-phase inverter. In FIG. 1, 16 and 17 are first series-connected
Are connected between a positive potential and a negative potential of a DC power supply (not shown). In addition, each clamp capacitor 16, 17
Creates a high-potential at P, a neutral at O, and a low-potential at N. Reference numeral 18 denotes a control power supply, which supplies a control voltage to each of main circuit elements 19, 20, 34, and 35 described later. Reference numeral 19 denotes a first main circuit element connected to the positive potential side of a DC power supply (not shown), and a first switching element 1
9a is built in. Reference numeral 20 denotes a fourth main circuit element, which incorporates a fourth switching element 20a connected to the negative potential side of a DC power supply (not shown). The main circuit elements 19 and 20 are configured as shown in FIG.

In FIG. 2, reference numeral 21 denotes a blocking diode connected to the control power supply 18. A capacitor 22 stabilizes the control voltage supplied from the control power supply 18. Reference numeral 23 denotes control voltage setting means for setting a lower limit value of the control voltage supplied from the control power supply 18.
Reference numeral 24 denotes a control voltage detection circuit, which outputs a voltage drop detection signal 24a when the control voltage supplied from the control power supply 18 falls below the set value of the control voltage setting means 23. Reference numeral 25 denotes a temperature sensor that detects the temperatures of the switching elements 19a and 20a. 26 is an element temperature setting means for setting a set value of an upper limit temperature for protecting the switching elements 19a and 20a from overheating. Reference numeral 27 denotes a temperature detection circuit which outputs an overheat detection signal 27a when the temperature of the switching elements 19a, 20a exceeds a value set by the element temperature setting means 26. Reference numeral 28 denotes a current sensor for detecting the current of the switching elements 19a and 20a. Reference numeral 29 denotes current value setting means for setting the set value of the upper limit current of the switching elements 19a and 20a.
Reference numeral 30 denotes an overcurrent detection circuit, which is a switching element 19a, 2
When the current of 0a exceeds the value set by the current value setting means 29, an overcurrent detection signal 30a is output.

Reference numeral 31 denotes an OR circuit.
a, when at least one of the overheat detection signal 27a and the overcurrent detection signal 30a is input, a cutoff signal 31a is output. An AND circuit 32 outputs a gate signal 32a and has an active low input terminal 32b.
When a is not input to the input terminal 32b, the input gate signals 49a and 55a (described later) are input to the gate signal 32a.
Output as The input terminal 32 of the AND circuit 32
When the cutoff signal 31a is inputted to the gate signal b, the gate signal 32a
Cut off. An amplifier 33 amplifies the gate signal 32a and drives the switching elements 19a and 20a. 34
Is a second main circuit element, and the first switching element 19a
And a second switching element 34a connected in series. A third main circuit element 35 has a built-in third switching element 35a connected in series between the second switching element 34a and the fourth switching element 20a. The main circuit elements 34 and 35 are configured as shown in FIG.

In FIG. 3, reference numerals 21 to 24 are the same as those in FIG. A temperature sensor 36 detects the temperatures of the switching elements 34a and 35a. An element temperature setting means 37 sets a set value of an upper limit temperature for protecting the switching elements 34a and 35a from overheating. Reference numeral 38 denotes a temperature detection circuit, which detects an overheat detection signal 38 when the temperature of the switching elements 34a, 35a exceeds the set value of the element temperature setting means 37.
a is output. 39 is a switching element 34a, 35a
This is a current sensor that detects the current of the current sensor. Numeral 40 denotes current value setting means for setting the set value of the upper limit current of each of the switching elements 34a and 35a. Each current value setting means 2
The setting values of 9, 40 are set to the same value.

Reference numeral 41 denotes an overcurrent detection circuit, which outputs an overcurrent detection signal 41a when the current of each of the switching elements 34a and 35a exceeds the value set by the current value setting means 40. Reference numeral 42 denotes an OR circuit, which includes a voltage drop detection signal 24a and an overheat detection signal 3
When at least one of the input signal 8a and the overcurrent detection signal 41a is input, a cutoff signal 42a is output. Reference numeral 43 denotes a delay circuit to which the cutoff signal 42a is input, and outputs a cutoff signal 43a a predetermined time after the cutoff signal 42a is input.
An AND circuit 44 outputs a gate signal 44a and has an active low input terminal 44b. When the cutoff signal 43a is not input to the input terminal 44b, the AND circuit 44 outputs the input gate signals 51a and 53a to be described later as the gate signal 44a. I do. When the cutoff signal 43a is input to the input terminal 44b of the AND circuit 44, the gate signal 44a is cut off. An amplifier 45 drives the switching elements 34a and 35a by amplifying the gate signal 44a.

In FIG. 1, reference numerals 46 and 47 denote coupling diodes connected in series. The cathode of the coupling diode 46 is connected between the first main circuit element 19 and the second main circuit element 34. The anode is connected between the third main circuit element 35 and the fourth main circuit element 20. Further, a connection point between both coupling diodes 46 and 47 is connected to a connection point between both clamp capacitors 16 and 17. An output terminal 48 is provided between the two main circuit elements 34 and 35. Reference numeral 49 denotes an AND circuit which outputs a gate signal 49a and has active-low input terminals 49b, 49c, and 49d. A control signal 50 for performing "on" control of the first switching element 19a and a second input terminal 49b are provided to the input terminal 49b.
Signal 42a from the main circuit element 34 and the input terminal 4
9c, a cutoff signal 42a from the third main circuit element 35,
The cutoff signal 31a from the fourth main circuit element 20 is input to the input terminal 49d. Normally, the control signal 50
Is output as a gate signal 49a through the AND circuit 49. The main circuit element 34 is connected to the input terminal 49b.
Signal 42a from the main circuit element 3 to the input terminal 49c.
When any one of the cutoff signal 42a from 5 and the cutoff signal 31a from the main circuit element 20 is input to the input terminal 49d, the AND circuit 49 stops outputting the gate signal 49a.

An AN 51 outputs a gate signal 51a and has active-low input terminals 51b, 51c and 51d.
In the D circuit, a control signal 52 for performing "on" control of the second switching element 34a, a cutoff signal 31a from the first main circuit element 19 at an input terminal 51b, and a third main circuit element at an input terminal 51c. And a cutoff signal 31a from the fourth main circuit element 20 to the input terminal 49d.
Is entered. Normally, the control signal 52 is set to AN
It is output as a gate signal 51a through the D circuit 51. Then, the first main circuit element 19 is connected to the input terminal 51b.
When any one of the shutoff signal 31a from the third main circuit element 35 and the shutoff signal 42a from the third main circuit element 35 to the input terminal 51c and the shutoff signal 31a from the fourth main circuit element 20 to the input terminal 51d are input to the AND circuit, The gate signal 51a is no longer output from 51.

An AN 53 outputs a gate signal 53a and has active-low input terminals 53b, 53c and 53d.
In the D circuit, a control signal 54 for performing "on" control of the third switching element 35a, a cutoff signal 31a from the first main circuit element 19 at an input terminal 53b, and a second main circuit element at an input terminal 53c. And a cutoff signal 31a from the fourth main circuit element 20 to the input terminal 53d.
Is entered. Normally, the control signal 54 is set to AN
It is output as a gate signal 53a through the D circuit 53. Then, the first main circuit element 19 is connected to the input terminal 53b.
When any one of the shutoff signal 31a from the second main circuit element 34 is input to the input terminal 53c, the shutoff signal 42a from the second main circuit element 34 and the failure detection signal 31a from the fourth main circuit element 20 are input to the input terminal 53d, AND Gate signal 53 from circuit 53
a is no longer output.

Reference numeral 55 denotes an AN which outputs a gate signal 55a and has active-low input terminals 55b, 55c and 55d.
In the D circuit, a control signal 56 for performing "on" control of the fourth switching element 20a, a cutoff signal 31a from the first main circuit element 19 at an input terminal 55b, and a second main circuit element at an input terminal 55c. 34 and a cut-off signal 42a from the third main circuit element 35 to the input terminal 55d.
Is entered. Normally, the control signal 56 is set to AN
It is output as a gate signal 55a through the D circuit 55. Then, the first main circuit element 19 is connected to the input terminal 55b.
When any one of the shutoff signal 31a from the second main circuit element 34 is input to the input terminal 55c, and the shutoff signal 31a from the third main circuit element 20 is input to the input terminal 55d, the AND circuit The gate signal 55a is no longer output from 55.

Next, the operation will be described. In FIGS. 1 to 3, it is assumed that a neutral point potential O point is virtually grounded. When the adjacent switching elements 19a and 34a are controlled by the control signals 50 and 52 to be "ON" and the other switching elements 35a and 20a are "OFF", the DC voltage of the DC power supply (not shown) is changed to Ed. Then, the output voltage of the output terminal 48 becomes Ed / 2. Next, the adjacent switching elements 34a and 35a are controlled to be "ON" by the control signals 52 and 54, and the other switching elements 19a and 35a are turned on.
When a and 20a are "off", the output voltage of the output terminal 48 becomes zero potential. Further, when the adjacent switching elements 35a and 20a are controlled by the control signals 54 and 56 to be "ON" and the other switching elements 19a and 34a are "OFF", the output voltage of the output terminal 48 is -Ed / 2
Becomes Thus, the three-level voltage is applied to the output terminal 4
8 is selectively output. Here, when the first switching element 19a and the second switching element 34a are "ON" and the third switching element 35a and the fourth switching element 20a are "OFF" and in the operating state,
When the temperature sensor 25 of the first main circuit element 19 detects overheating of the first switching element 19a, the temperature detection circuit 2
7 outputs an overheat detection signal 27a. The overheat detection signal 27a is output via the OR circuit 31 as a cutoff signal 31a. Then, since the cutoff signal 31a is input to the active low input terminal 32b of the AND circuit 32, the gate signal 32a of the first main circuit element 19 is cut off and the first switching element 19a is turned off.

On the other hand, the cutoff signal 31a is input to the input terminal 51b of the AND circuit 51.
Since the cutoff of the gate signal 51a output from the D circuit 51 is delayed, the gate signal 44 of the second main circuit element 34 is
a is later than the interruption of the gate signal 32a of the first main circuit element 19. Therefore, the second switching element 3
4a is turned off later than the first switching element 19a. Therefore, the entire voltage of the DC power supply (not shown) is not applied to the second switching element 34a. Next, when the first switching element 19a and the second switching element 34a are "ON" and the third switching element 35a and the fourth switching element 20a are "OFF" and in the operating state, the second main element is turned on. When the temperature sensor 36 of the circuit element 34 detects overheating of the second switching element 34a, the overheating detection signal 38a
Is output. The overheat detection signal 38a is output via the OR circuit 42 as a cutoff signal 42a. Then, since the cutoff signal 42a is input to the input terminal 49b of the AND circuit 49, the first switching element 19 in the “ON” operation
The control signal 50a is cut off and the gate signal 49a is not output. Therefore, the first switching element 19
a is “off”.

On the other hand, in the second main circuit element 34, the cutoff signal 42a is delayed by the delay circuit 43, and the cutoff signal 43a is turned off after the first switching element 19a is turned off.
Is set to be input to the input terminal 44b of the AND circuit 44, so that the second switching element 34a located inside the first switching element 19a with respect to the DC power supply (not shown) performs the first switching. Becomes "off" later than the element 19. As described above, while the first switching element 19a and the second switching element 34a are operating in the “ON” state, the second switching element 34a
Is detected, the second switching element 34a
Since the first switching element 19a is turned "off" earlier, it is possible to prevent the entire DC voltage from being applied to the second switching element 34a.

When the third switching element 35a and the fourth switching element 20a are "ON", the first switching element 19a and the second switching element 34
When “a” is “off” and in the operating state, the temperature sensor 36 of the third main circuit element 35 outputs the third switching element 35a.
When the overheat is detected, the overheat detection signal 38a is output from the temperature detection circuit 38. When the overheat detection signal 38a is output, similarly to the case where the first switching element 19a and the second switching element 34a are operating, the DC power supply (not shown) is located inside the fourth switching element 20a. A certain third switching element 35a is turned off later than the fourth switching element 20a. Therefore,
Even when the third switching element 35a is turned off when the abnormality of the third switching element 35a is detected, it is possible to prevent application of the entire DC voltage.

In the first embodiment, the temperature sensor 36
Has been described above, but when the control voltage detection circuit 24 detects an abnormality in the control voltage or when the overcurrent detection circuit 41 detects an overcurrent,
2a is a cutoff signal 43 after a predetermined time through the delay circuit 43.
a, the second switching element 34a or the third switching element 35a is similarly connected to the first switching element 19a or the fourth switching element 20a.
Becomes "off" later than a. Embodiment 1
In the control voltage, the switching elements 19a,
Although the description has been given of the detection of overheating and overcurrent of the heaters 20a, 34a, and 35a, similar effects can be expected by performing other abnormality detection. In the first embodiment, the current value setting means 29 of each of the main circuit elements 19 and 20 and the current value setting means 40 of each of the main circuit elements 34 and 35 are set to the same value. The cutoff signals of the element 19a and the fourth switching element 20a may be output at a lower current than the current at which the cutoff signals of the second switching element 34a and the third switching element 35a are output. That is, the set value of the current value setting means 29 is set to a value lower than the set value of the current value setting means 40. Thereby, each switching element 19
a, 20a is “ON”, when overcurrent flows during operation,
Since the overcurrent detection circuit 30 of the first main circuit element 19 detects the overcurrent before the overcurrent detection circuit 41 of the second main circuit element 34, the first switching element 19a is cut off first. Further, when an overcurrent flows during the operation when each of the switching elements 34a and 35a is “ON”, the overcurrent detection circuit 30 of the fourth main circuit element 20 is turned on by the third main circuit element 35.
Since the overcurrent is detected before the overcurrent detection circuit 41 of
The fourth switching element 20a is cut off first. Thereby, it is possible to prevent the full DC voltage of the DC power supply from being applied to the second switching element 34a and the third switching element 35a. Furthermore, although one phase of the three-phase inverter has been described in the first embodiment, the same effect can be expected when applied to a chopper control device, a single-phase inverter, a converter, and the like.

[0021]

According to the present invention, the delay for outputting the cutoff signal such that the cutoff of the second switching element and the third switching element is later than the cutoff of the first switching element and the fourth switching element. By providing the circuit, when an abnormality is detected in the second switching element while the first switching element and the second switching element are “ON” and operating, the second switching element performs the first switching. Since it is turned off later than the element, the second
Can be prevented from being applied to all the switching elements. Therefore, the first switching element and the second switching element have the same withstand voltage, and can share the DC voltage evenly. Similarly, if an abnormality is detected in the third switching element during operation when the third switching element and the fourth switching element are “ON”, the third switching element is delayed with respect to the fourth switching element. Since it is “off”, it is possible to prevent the full DC voltage of the DC power supply from being applied to the third switching element. Therefore, the third switching element and the fourth switching element can have the same withstand voltage, and can share the DC voltage evenly.

Also, the cutoff signal is output when overheating of each switching element is detected,
Each switching element can be prevented from being damaged by overheating. Further, since the cutoff signal is output when it is detected that the control voltage of each switching element has become equal to or less than the predetermined value, the control of each switching element can be stabilized. In addition, since the cutoff signal is output when it is detected that a current equal to or more than a predetermined value has flowed through each switching element, each switching element can be prevented from being destroyed by an overcurrent. Further, the cutoff signals of the first switching element and the fourth switching element are output at a lower current than the current at which the cutoff signals of the second switching element and the third switching element are output. When the overcurrent flows, the first switching element and the fourth switching element are cut off before the second switching element and the third switching element, so that the second switching element and the third switching element are turned off. It is possible to prevent application of the full DC voltage of the DC power supply.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a main part of FIG. 1;

FIG. 3 is a configuration diagram showing a main part of FIG. 1;

FIG. 4 is a configuration diagram showing a conventional power converter.

FIG. 5 is a configuration diagram showing a main part of FIG. 4;

[Explanation of symbols]

16 first clamp capacitor, 17 second clamp capacitor, 19a first switching element, 20
a fourth switching element, 34a second switching element, 35a third switching element, 43 delay circuit.

Claims (5)

[Claims] 1. A first clamp capacitor and a second clamp capacitor are connected between a positive potential and a negative potential of a DC power supply, and a first switching element to a fourth switching element are connected to the DC power supply. An AC phase voltage having a three-level potential is sequentially output between a positive potential and a negative potential, and is output from a connection between the second switching element and the third switching element. In the power conversion device, the switching elements are detected and the switching elements are cut off, the cutoff of the second switching element and the third switching element is performed by the first switching element.
And a delay circuit that outputs a cutoff signal so as to be later than the cutoff of the fourth switching element. 2. The power conversion device according to claim 1, wherein the cutoff signal is output when overheating of each switching element is detected. 3. The power converter according to claim 1, wherein the cutoff signal is output when detecting that the control voltage of each switching element has become equal to or lower than a predetermined value. 4. The electric power according to claim 1, wherein the cutoff signal is output when it is detected that a current equal to or more than a predetermined value flows through each switching element. Conversion device. 5. The shut-off signal of the first switching element and the fourth switching element is output at a lower current than the cut-off signal of the second switching element and the third switching element. The power converter according to claim 4, wherein