JP5775446B2 - Overcurrent protection device and power conversion device - Google Patents

Description

  The present invention relates to an overcurrent protection device for a multilevel inverter circuit and a power conversion device including the overcurrent protection device and the multilevel inverter circuit.

  In a power conversion device that converts alternating current power into direct current power by switching the semiconductor element and a power conversion device that converts direct current power into alternating current power (see, for example, Patent Document 1), an insulated gate bipolar transistor ( Hereinafter, IGBT (Insulated Gate Bipolar Transistor) is used. When an excessive current flows through the semiconductor element, the semiconductor element is destroyed. Therefore, in order to protect each semiconductor element from the overcurrent, the power device is provided with an overcurrent protection device for protecting each semiconductor element. There are many.

  FIG. 8 is a block diagram showing a configuration of a power conversion device according to the prior art, and FIG. 9 is a circuit diagram showing a configuration of the overcurrent protection circuit 22B of FIG. 10A is a timing chart showing the carrier waves Sc1 and Sc2, the signal wave Sr, and the drive signal Sd1 generated by the drive signal generation circuit 1B of FIG. 8, and FIG. FIG. 9 is a timing chart showing carrier waves Sc1 and Sc2, a signal wave Sr, and a drive signal Sd2 generated by the drive signal generation circuit 1B of FIG.

  In FIG. 8, the power conversion device according to the prior art includes a drive signal generation circuit 1B, drive circuits 11, 12, 13, and 14, overcurrent protection circuits 21B, 22B, 23B, and 24B, and a three-level inverter circuit 2. It is configured with. In FIG. 8, only the structure for one phase is shown. 8, the three-level inverter circuit 2 includes DC power supplies P1 and P2, transistors Q1, Q2, Q3, and Q4, which are IGBTs, freewheeling diodes D1, D2, D3, and D4, and clamp diodes D5 and D6, respectively. And snubber capacitors CP1 and CP2. Further, in FIG. 9, the overcurrent protection circuit 22B includes a voltage detection circuit 31, a filter circuit 32 including a resistor 33 and a capacitor 34, a comparator 35, and a voltage source 36. The other overcurrent protection circuits 21B, 23B, and 24B are configured in the same manner as the overcurrent protection circuit 22B, and operate in the same manner as the overcurrent protection circuit 22B.

  In FIG. 8, DC power supplies P1 and P2 are connected in series with each other and generate predetermined DC voltages E, respectively. Transistors Q1-Q4 are connected in series between the positive electrode of DC power supply P1 and the negative electrode of DC power supply P2. The freewheeling diodes D1, D2, D3, and D4 are connected in antiparallel to the transistors Q1, Q2, Q3, and Q4, respectively. The anode of clamp diode D5 is connected to the connection point between DC power supplies P1 and P2, while the cathode is connected to the connection point between transistors Q1 and Q2. Further, the cathode of the clamp diode D6 is connected to the connection point between the DC power supplies P1 and P2, while the anode is connected to the connection point between the transistors Q3 and Q4. Snubber capacitor CP1 is connected between the anode of clamp diode D5 and the collector of transistor Q1, and snubber capacitor CP2 is connected between the cathode of clamp diode D6 and the emitter of transistor Q5.

  In FIG. 8, the drive signal generation circuit 1B generates a signal wave Sr and two carrier waves Sc1 and Sc2 (see FIGS. 10A and 10B). Here, the signal wave Sr is a sine wave having a predetermined fundamental frequency and having a zero level as a reference level. The carrier wave Sc1 has a predetermined positive DC bias (+0.5 in the example of FIG. 10A) with reference to the zero level, and has a predetermined carrier frequency (PWM (Pulse Width Modulation: Pulse width modulation). The carrier frequency is set to be higher than the fundamental frequency. On the other hand, the carrier wave Sc2 is a triangular wave having a predetermined negative DC bias (−0.5 in the example of FIG. 10B) with the zero level as a reference and having the above-described carrier frequency. The carrier waves Sc1 and Sc2 have substantially the same phase.

  In FIG. 8, the drive signal generation circuit 1B compares the carrier wave Sc1 with the signal wave Sr, and the transistors Q1 and Q3 are complementarily turned on and off at each timing when the carrier wave Sc1 and the signal wave Sr intersect. A drive signal Sd1 (see FIG. 10A) for driving the transistor Q1 and a drive signal Sd3 for driving the transistor Q3 are generated. Further, the drive signal generation circuit 1B compares the carrier wave Sc2 with the signal wave Sr, and the transistors Q2 and Q4 are complementarily turned on and off at each timing when the carrier wave Sc2 and the signal wave Sr intersect. A drive signal Sd2 (see FIG. 10B) for driving and a drive signal Sd4 for driving the transistor Q4 are generated. In order to prevent a vertical short circuit, after the transistor Q1 is turned off, a dead time having a predetermined period length is provided to turn on the transistor Q3. Similarly, after the transistor Q2 is turned off, a dead time having a predetermined period length is provided to turn on the transistor Q4. The drive signals Sd1 to Sd4 are output to the drive circuits 11 to 14, respectively.

  Further, in FIG. 8, the drive circuits 11 to 14 generate drive voltages V11 to V14 for driving the transistors Q1 to Q4 based on the input drive signals Sd1 to Sd4, respectively. Applied between the gate and emitter. As described above, since the drive signals Sd1 to Sd4 are generated, the transistor Q2 is always turned on in the half cycle period in which the signal wave Sr exceeds the zero level (hereinafter referred to as a positive half cycle period). Q4 is always off, and transistors Q1 and Q3 are complementarily turned on and off at the carrier frequency. In addition, in a half cycle period in which the signal wave Sr is less than zero level (hereinafter referred to as a negative half cycle period), the transistor Q3 is always turned on, the transistor Q1 is always turned off, and the transistors Q2 and Q4 have a carrier frequency. Complementary on / off. As a result, an output voltage Vout having three voltage levels E, 0, and −E is output from the connection point between the diodes D2 and D3.

  In the overcurrent protection circuit 22B of FIG. 9, the voltage detection circuit 31 detects the collector-emitter voltage Vce2 of the transistor Q2, and outputs the Vce detection voltage V31 corresponding to the detected voltage Vce2 to the filter circuit 32. The filter circuit 32 is a low-pass filter circuit having a time constant τ determined by the product of the resistance value of the resistor 33 and the capacitance value of the capacitor 34, and performs low-pass filtering on the Vce detection voltage V31, The filtered voltage V32 after filtering is output to the non-inverting input terminal of the comparator 35. The voltage source 36 generates a predetermined overcurrent detection voltage Vr corresponding to a predetermined overcurrent threshold of the collector current I2 flowing through the transistor Q2, and outputs it to the inverting input terminal of the comparator 35. The comparator 35 compares the filtered voltage V32 with the overcurrent detection voltage Vr. When the filtered voltage V32 is larger than the overcurrent detection voltage Vr, the collector current Ic2 exceeding the overcurrent threshold value is applied to the transistor Q2. A high-level overcurrent detection signal S22B indicating that has flowed is generated. On the other hand, when the filtered voltage V32 is equal to or lower than the overcurrent detection voltage Vr, a low level overcurrent detection signal S22B is generated. The overcurrent detection signal S22B is output to the drive signal generation circuit 1 and the drive circuit 12. In the overcurrent protection circuit 22B, the voltage detection circuit 31 and the filter circuit 32 are controlled so as to operate only during the ON period of the transistor Q2.

  In FIG. 8, each of the overcurrent protection circuits 21B, 23B, and 24B detects whether or not a collector current exceeding the overcurrent threshold value is flowing in the transistors Q1, Q3, and Q4, similarly to the overcurrent protection circuit 22B. The overcurrent detection signals S21B, S23B, and S24B indicating the detection result are output to the drive circuits 11, 13, and 14 and the drive signal generation circuit 1B. The drive circuits 11, 12, 13, and 14 are responsive to high-level overcurrent detection signals S21B, S22B, S23B, and S24B, respectively, to drive voltages V11, V12, and V4 for turning off the transistors Q1, Q2, Q3, and Q4. V13 and V14 are generated and applied between the gates and emitters of the transistors Q1, Q2, Q3, and Q4. In addition, when the overcurrent flows through at least one of the transistors Q1 to Q4 based on the overcurrent detection signals S21B, S22B, S23B, and S24B, the drive signal generation circuit 1B causes all the transistors Q1 to Q4 to pass through. Drive signals Sd1 to Sd4 are generated so as to be turned off. In response, all transistors Q1-Q4 are turned off and protected from overcurrent.

  FIG. 11 is a timing chart showing the operation of the power conversion device of FIG. 8 during normal operation. In FIG. 11, when the voltage level of the drive signal Sd2 of the transistor Q2 changes from the low level to the high level at the timing t1, the transistor Q2 is turned on in response to this, and the collector-emitter voltage Vce2 of the transistor Q2 is reduced. A collector current Ic2 flows out to Q2. Further, the voltage detection circuit 31 and the filter circuit 32 start to operate. Further, the post-filtering voltage V32 from the filter circuit 32 gradually increases with a time constant τ. During this time, even if the collector current Ic2 exceeds the predetermined overcurrent threshold value, the filtered voltage V32 does not exceed the overcurrent detection voltage Vr, so the voltage level of the overcurrent detection signal S22B remains low. It is. When the collector current Ic2 (overcurrent) exceeding the overcurrent threshold flows through the transistor Q2, and the filtered voltage V32 exceeds the overcurrent detection voltage Vr at the timing t3 after the timing t2 when the time constant τ has elapsed. A high level overcurrent detection signal S22B is generated. In response to this, the drive circuit 12 generates the drive signal Sd2 to turn off the transistor Q2, and the drive signal generation circuit 1B generates the drive signals Sd1 to Sd4 to turn off all the transistors Q1 to Q4. Note that the period length Ta (τ <Ta) from when the transistor Q2 is turned on until the high-level post-filtering voltage V32 is generated is equal to the short-circuit withstand capability of the transistor Q2 (short-circuit current flows out of the transistor Q2). Until the transistor Q2 is destroyed.) Is set to be as follows.

Japanese Patent Laid-Open No. 2006-271042

  FIG. 12 is a timing chart showing the operation of the power conversion device of FIG. 8 when the overcurrent protection circuit 22B of FIG. 8 is affected by the switching of the transistor Q3. In FIG. 12, when the voltage level of the drive signal Sd2 of the transistor Q2 changes from the low level to the high level at the timing t4, the transistor Q2 is turned on in response thereto. Then, the collector-emitter voltage Vce2 of the transistor Q2 decreases, and the collector current Ic2 flows out to the transistor Q2. Further, the voltage detection circuit 31 and the filter circuit 32 start to operate. Further, the post-filtering voltage V32 from the filter circuit 32 gradually increases with a time constant τ. In the case of FIG. 12, since the collector current Ic2 of the transistor Q2 does not exceed the overcurrent threshold, the filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22B does not exceed the overcurrent detection voltage Vr. The voltage level of the overcurrent detection signal S22B remains low.

  By the way, as shown in FIG. 10B, the transistor Q2 is always turned on in the positive half cycle period described above, and the transistor Q3 is turned on and off in this positive half cycle period. In FIG. 12, when the transistor Q3 is turned on at the timing t5 within the positive half cycle period, the collector-emitter voltage Vce2 of the transistor Q2 varies due to the influence of the parasitic inductance and parasitic capacitance of the three-level inverter circuit 2. For this reason, the filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22B gradually increases although the collector current Ic2 (overcurrent) exceeding the overcurrent threshold does not flow through the transistor Q2. . When the fluctuation of the collector-emitter voltage Vce2 continues for a certain period, the filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22B exceeds the overcurrent detection voltage Vr, and the comparator 35 of the overcurrent protection circuit 22B. Generates a high-level overcurrent detection signal S22B. In response to this, all the transistors Q1 to Q4 are turned off.

  As described above, the overcurrent protection circuit 22B according to the prior art detects the collector-emitter voltage Vce2 of the transistor Q2, and compares the detected voltage with the overcurrent detection voltage Vr after filtering. Therefore, if the time constant τ of the filter circuit 32 is not set sufficiently large, when the transistor Q2 is turned on for a half period of the fundamental frequency and the other transistors are turned on and the collector-emitter voltage Vce2 varies, The overcurrent of the transistor Q2 is erroneously detected.

  The object of the present invention is to solve the above problems and to prevent an overcurrent protection device capable of preventing erroneous detection of overcurrent of each semiconductor element of the multilevel inverter circuit, and an electric power including the overcurrent protection device and the multilevel inverter circuit It is to provide a conversion device.

The overcurrent protection device according to the first invention is:
A first, a second, a third and a fourth semiconductor element connected in series with each other between a positive potential and a negative potential of two DC power supplies connected in series with each other;
First to fourth freewheeling diodes connected in antiparallel to the first to fourth semiconductor elements, respectively;
A first clamp diode connected from a connection point of the two DC power sources to a connection point of the first and second semiconductor elements;
In an overcurrent protection device for a multi-level inverter circuit comprising a second clamp diode connected from a connection point of the third and fourth semiconductor elements to a connection point of the two DC power supplies,
A signal wave having a predetermined reference level and a predetermined basic period is converted into one of first and second carrier waves each having a predetermined positive DC bias and a predetermined negative bias with respect to the reference level. Compared with the wave, based on the comparison result, first and third drive signals for driving on and off the first and third semiconductor elements are generated, and the first and third semiconductor elements are respectively generated. For outputting and comparing the signal wave with the other carrier wave of the first and second carrier waves and driving the second and fourth semiconductor elements on and off based on the comparison result, respectively. A drive signal generation circuit that generates second and fourth drive signals and outputs the second and fourth drive signals to the second and fourth semiconductor elements, respectively;
Provided corresponding to each of the semiconductor elements, the voltage across the semiconductor elements is detected, low-pass filtering is performed on the voltage across the semiconductor elements, and the filtered voltage is set to a predetermined overcurrent detection voltage. Four overcurrent protection circuits for generating an overcurrent detection signal indicating that an overcurrent has passed through each of the semiconductor elements and outputting the detected signal to the drive signal generation circuit to protect the semiconductor elements. Prepared,
The drive signal generation circuit is provided corresponding to a semiconductor element that is always turned on in the period from the detected timing to a half period of the basic period from the detected timing when the signal wave reaches the reference level. The overcurrent protection circuit is controlled so as to substantially stop the operation.

The overcurrent protection device according to the second invention is:
A first, a second, a third and a fourth semiconductor element connected in series with each other between a positive potential and a negative potential of two DC power supplies connected in series with each other;
First to fourth freewheeling diodes connected in antiparallel to the first to fourth semiconductor elements, respectively;
A first clamp diode connected from a connection point of the two DC power sources to a connection point of the first and second semiconductor elements;
In an overcurrent protection device for a multi-level inverter circuit comprising a second clamp diode connected from a connection point of the third and fourth semiconductor elements to a connection point of the two DC power supplies,
A signal wave having a predetermined reference level and a predetermined basic period is converted into one of first and second carrier waves each having a predetermined positive DC bias and a predetermined negative bias with respect to the reference level. Compared with the wave, based on the comparison result, first and third drive signals for driving on and off the first and third semiconductor elements are generated, and the first and third semiconductor elements are respectively generated. For outputting and comparing the signal wave with the other carrier wave of the first and second carrier waves and driving the second and fourth semiconductor elements on and off based on the comparison result, respectively. A drive signal generation circuit that generates second and fourth drive signals and outputs the second and fourth drive signals to the second and fourth semiconductor elements, respectively;
Provided corresponding to each of the semiconductor elements, the voltage across the semiconductor elements is detected, low-pass filtering is performed on the voltage across the semiconductor elements, and the filtered voltage is set to a predetermined overcurrent detection voltage. Four overcurrent protection circuits for generating an overcurrent detection signal indicating that an overcurrent has passed through each of the semiconductor elements and outputting the detected signal to the drive signal generation circuit to protect the semiconductor elements. Prepared,
Of the four overcurrent protection circuits, each overcurrent protection circuit provided in each of the second and third semiconductor elements is turned on after the semiconductor element provided in the overcurrent protection circuit is turned on. A threshold time set to be greater than the short-circuit withstand capability of the semiconductor element and smaller than the period from when the semiconductor element is turned on until the other one of the second and third semiconductor elements is turned on. And a timer circuit for substantially stopping the operation of the overcurrent protection circuit.

A power conversion device according to a third invention is:
The multi-level inverter circuit;
The overcurrent protection device according to the first or second invention is provided.

  According to the overcurrent protection device and the power conversion device including the overcurrent protection device according to the first aspect of the invention, the drive signal generation circuit detects the timing at which the signal wave is at the reference level, and starts from the detected timing. Since the operation of the overcurrent protection circuit provided corresponding to the semiconductor element that is always turned on in the period is controlled to be substantially stopped over a half period of the cycle, each semiconductor element of the multilevel inverter circuit is controlled. It is possible to prevent erroneous detection of overcurrent.

  According to the overcurrent protection device and the power conversion device including the overcurrent protection device according to the second invention, each overcurrent protection circuit provided in each of the second and third semiconductor elements includes the overcurrent protection circuit. After the semiconductor element provided in the current protection circuit is turned on, until the other semiconductor element of the second and third semiconductor elements is turned on after the semiconductor element is turned on, which is greater than the short-circuit tolerance of the semiconductor element. When a threshold time set to be smaller than the period of time elapses, a timer circuit that substantially stops the operation of the overcurrent protection circuit is provided, so that the overcurrent of each semiconductor element of the multilevel inverter circuit is reduced. False detection can be prevented.

It is a block diagram which shows the structure of the power converter device which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the overcurrent protection circuit 22 of FIG. (A) is a timing chart showing carrier waves Sc1 and Sc2, a signal wave Sr, and a drive signal Sd2 generated by the drive signal generation circuit 1 of FIG. 1, and (b) is a drive signal of FIG. 2 is a timing chart showing an overcurrent protection circuit control signal Sa2 generated by the generation circuit 1, and (c) is a timing chart showing an overcurrent protection circuit control signal Sa3 generated by the drive signal generation circuit 1 of FIG. is there. It is a timing chart which shows operation | movement of the power converter device of FIG. It is a block diagram which shows the structure of the power converter device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a configuration of an overcurrent protection circuit 22A of FIG. It is a timing chart which shows operation | movement of the power converter device of FIG. It is a block diagram which shows the structure of the power converter device which concerns on a prior art. It is a circuit diagram which shows the structure of the overcurrent protection circuit 22B of FIG. (A) is a timing chart showing carrier waves Sc1 and Sc2, a signal wave Sr, and a drive signal Sd1 generated by the drive signal generation circuit 1B of FIG. 8, and (b) is a drive signal of FIG. 6 is a timing chart showing carrier waves Sc1 and Sc2, a signal wave Sr, and a drive signal Sd2 generated by the generation circuit 1B. It is a timing chart which shows the operation | movement at the time of normal operation | movement of the power converter device of FIG. FIG. 9 is a timing chart showing an operation of the power conversion device of FIG. 8 when the overcurrent protection circuit 22B of FIG. 8 is affected by the switching of the transistor Q3.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In each of the following embodiments and the background art described above, the same components are denoted by the same reference numerals, and the description thereof is not repeated.

First embodiment.
FIG. 1 is a block diagram showing the configuration of the power conversion device according to the first embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of the overcurrent protection circuit 22 of FIG. 3A is a timing chart showing the carrier waves Sc1 and Sc2, the signal wave Sr, and the drive signal Sd2 generated by the drive signal generation circuit 1 of FIG. 1, and FIG. FIG. 2 is a timing chart showing an overcurrent protection circuit control signal Sa2 generated by the drive signal generation circuit 1 of FIG. 1, and (c) is an overcurrent protection circuit control signal generated by the drive signal generation circuit 1 of FIG. 1. It is a timing chart which shows Sa3.

  1, the power conversion device according to the present embodiment includes a drive signal generation circuit 1, drive circuits 11, 12, 13, and 14, overcurrent protection circuits 21B, 22, 23, and 24B, and a three-level inverter circuit 2. And is configured. In FIG. 1, only the structure for one phase is shown. In FIG. 1, the power conversion device according to the present embodiment replaces the drive signal generation circuit 1 </ b> B and the overcurrent protection circuits 22 </ b> B and 23 </ b> B with a drive signal as compared with the power conversion device according to the related art (see FIG. 8). The difference is that the generation circuit 1 and the overcurrent protection circuits 22 and 23 are provided. In FIG. 1, the drive signal generation circuit 1 and the overcurrent protection circuits 21B, 22, 23, and 24B constitute an overcurrent protection device for the three-level inverter circuit 2. Hereinafter, only differences from the power converter according to the prior art will be described.

  In FIG. 2, the overcurrent protection circuit 22 includes a voltage detection circuit 31, a filter circuit 32 including a resistor 33 and a capacitor 34, a comparator 35, voltage sources 36 and 37, and a switch SW. . In FIG. 2, the voltage detection circuit 31 detects the collector-emitter voltage Vce2 of the transistor Q2, and outputs a Vce detection voltage V31 corresponding to the detected voltage Vce2 to the filter circuit 32. The filter circuit 32 is a low-pass filter circuit having a time constant τ determined by the product of the resistance value of the resistor 33 and the capacitance value of the capacitor 34, and performs low-pass filtering on the Vce detection voltage V31, The post-filtering voltage V32 after filtering is output to the contact a of the switch SW. The voltage source 36 generates a predetermined overcurrent detection voltage Vr corresponding to a predetermined overcurrent threshold of the collector current I2 flowing through the transistor Q2, and outputs it to the inverting input terminal of the comparator 35. Further, the voltage source 37 generates a predetermined voltage Va lower than the overcurrent detection voltage Vr and outputs it to the contact b of the switch SW.

  In FIG. 2, the switch SW is switched to the contact a side in response to a low level overcurrent protection circuit control signal Sa2 (details will be described later) from the drive signal generation circuit 1, while the high level overcurrent protection is performed. In response to the circuit control signal Sa2, the contact b is switched. In response to the overcurrent protection circuit control signal Sa2, the switch SW selectively outputs one of the filtered voltage V32 and the voltage Va to the non-inverting input terminal of the comparator 35 via the control terminal c. The comparator 35 compares the voltage output from the control terminal c of the switch SW with the overcurrent detection voltage Vr. When the voltage output from the switch SW is greater than the overcurrent detection voltage Vr, the comparator 35 supplies an overcurrent to the transistor Q2. A high level overcurrent detection signal S22 indicating that collector current Ic2 exceeding the threshold value flows is generated. On the other hand, when the control terminal c is equal to or lower than the overcurrent detection voltage Vr, the low level overcurrent detection signal S22 is generated. The overcurrent detection signal S22 is output to the drive signal generation circuit 1 and the drive circuit 12. In the overcurrent protection circuit 22, the voltage detection circuit 31 and the filter circuit 32 are controlled so as to operate only during the ON period of the transistor Q2. When the transistor Q2 is turned on, the switch SW is switched to the contact a side.

  In FIG. 1, an overcurrent protection circuit 23 is configured in the same manner as the overcurrent protection circuit 22, detects whether or not a collector current exceeding an overcurrent threshold value is flowing through the transistor Q3, and indicates the detection result. A detection signal S23 is generated and output to the drive circuit 13 and the drive signal generation circuit 1. The drive circuits 12 and 13 generate drive voltages V12 and V13 for turning off the transistors Q2 and Q3 in response to the high level overcurrent detection signals S22 and S23, respectively, so that each gate-emitter of the transistors Q2 and Q3. Apply between.

  In FIG. 1, the drive signal generation circuit 1 generates a signal wave Sr and two carrier waves Sc1 and Sc2 as in the drive signal generation circuit 1B of FIG. 8 (FIG. 3 (a), FIG. 10 (a). ) And FIG. 10 (b)). Specifically, the signal wave Sr is a sine wave having a predetermined fundamental frequency and having a zero level as a reference level. Hereinafter, the period corresponding to the fundamental frequency is referred to as the fundamental period. Further, the carrier wave Sc1 is a triangular wave having a predetermined positive DC bias (+0.5 in the example of FIG. 3A) with a zero level as a reference and having a predetermined carrier frequency. The carrier frequency is set to be higher than the fundamental frequency. On the other hand, the carrier wave Sc2 is a triangular wave having a predetermined negative DC bias (−0.5 in the example of FIG. 3A) with the zero level as a reference and having the above-described carrier frequency. The carrier waves Sc1 and Sc2 have substantially the same phase.

  In FIG. 1, the drive signal generation circuit 1 compares the carrier wave Sc1 with the signal wave Sr, and the transistors Q1 and Q3 are complementarily turned on and off at each timing at which the carrier wave Sc1 and the signal wave Sr intersect. A drive signal Sd1 for driving the transistor Q1 and a drive signal Sd3 for driving the transistor Q3 are generated. Furthermore, the drive signal generation circuit 1 compares the carrier wave Sc2 with the signal wave Sr, and the transistors Q2 and Q4 are complementarily turned on and off at each timing when the carrier wave Sc2 and the signal wave Sr intersect. A drive signal Sd2 for driving and a drive signal Sd4 for driving the transistor Q4 are generated. In order to prevent a vertical short circuit, after the transistor Q1 is turned off, a dead time having a predetermined period length is provided to turn on the transistor Q3. Similarly, after the transistor Q2 is turned off, a dead time having a predetermined period length is provided to turn on the transistor Q4. The drive signals Sd1 to Sd4 are output to the drive circuits 11 to 14, respectively. The drive circuits 11 to 14 generate drive voltages V11 to V14 for driving the transistors Q1 to Q4 based on the input drive signals Sd1 to Sd4, respectively, and are applied between the gates and emitters of the transistors Q1 to Q4. To do.

  Therefore, in the positive half cycle period in which the signal wave Sr exceeds the zero level, the transistor Q2 is always turned on, the transistor Q4 is always turned off, and the transistors Q1 and Q3 are complementarily turned on and off at the carrier frequency. In the negative half-cycle period in which the signal wave Sr is less than zero level, the transistor Q3 is always turned on, the transistor Q1 is always turned off, and the transistors Q2 and Q4 are complementarily turned on and off at the carrier frequency. As a result, an output voltage Vout having three voltage levels E, 0, and −E is output from the connection point between the diodes D2 and D3.

  Further, in FIG. 1, the drive signal generation circuit 1 is configured so that, when an overcurrent flows through at least one of the transistors Q1 to Q4 based on the overcurrent detection signals S21B, S22, S23, and S24B, all transistors Drive signals Sd1 to Sd4 are generated so as to turn off Q1 to Q4. In response, all transistors Q1-Q4 are turned off and protected from overcurrent.

  Further, in FIG. 1, the drive signal generation circuit 1 detects the timing at which the signal wave Sr intersects the zero level that is the reference level of the two carrier waves Sc1 and Sc2, and when the level of the signal wave Sr is higher than the zero level Generates a high level overcurrent protection circuit control signal Sa2 and outputs it to the switch SW of the overcurrent protection circuit 22, and also generates a low level overcurrent protection circuit control signal Sa3 to switch the overcurrent protection circuit 23. Output to SW. On the other hand, when the level of the signal wave Sr is lower than the zero level, the low-level overcurrent protection circuit control signal Sa2 is generated and output to the switch SW of the overcurrent protection circuit 22, and the high-level overcurrent protection circuit control is performed. A signal Sa3 is generated and output to the switch SW of the overcurrent protection circuit 23.

  When the timing at which the signal wave Sc intersects the zero level and the peak timing of the carrier wave Sc2 coincide, the timing at which the transistor Q2 is turned on coincides with the timing at which the high-level overcurrent protection circuit control signal Sa2 is output. Therefore, the overcurrent protection circuit 22 cannot detect the overcurrent. Similarly, when the timing at which the signal wave Sc crosses the zero level coincides with the valley timing of the carrier wave Sc1, the timing at which the transistor Q3 is turned on coincides with the timing at which the high-level overcurrent protection circuit control signal Sa3 is output. Therefore, the overcurrent protection circuit 23 cannot detect the overcurrent. For this reason, the signal wave Sr and the carrier waves Sc1 and Sc2 are generated so that the timing at which the signal wave Sr crosses the zero line does not match the timing of the peak of the carrier wave Sc2 and the timing of the valley of the carrier wave Sc1. It is necessary to design a circuit for this purpose.

  FIG. 4 is a timing chart showing the operation of the power conversion device of FIG. In FIG. 4, at timing t11, the drive signal generation circuit 1 generates a high level drive signal Sd2 and a low level overcurrent protection circuit control signal Sa2. In response to the high level drive signal Sd2, the transistor Q2 is turned on, the collector-emitter voltage Vce2 of the transistor Q2 is lowered, and the collector current Ic2 flows out to the transistor Q2. Further, the voltage detection circuit 31 and the filter circuit 32 of the overcurrent protection circuit 22 start operation, and the switch SW is switched to the contact a side. Therefore, after the timing t11, the filtered voltage V32 from the filter circuit 32 is output to the comparator 35 of the overcurrent protection circuit 22 via the control terminal c of the overcurrent protection circuit 22. The filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22 gradually increases with a time constant τ. In the case of FIG. 4, since the collector current Ic2 of the transistor Q2 does not exceed the overcurrent threshold, the filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22 does not exceed the overcurrent detection voltage Vr. The voltage level of the overcurrent detection signal S22 remains low.

  At timing t12, when the drive signal generation circuit 1 detects that the level of the signal wave Sr is higher than the zero level, the drive signal generation circuit 1 generates a high level overcurrent protection circuit control signal Sa2 and switches the switch SW of the overcurrent protection circuit 22. Output to. In response to this, the switch SW of the overcurrent protection circuit 22 is switched to the contact b side, and the overcurrent protection circuit 22 substantially stops its operation and generates a low level overcurrent detection signal S22. Further, when a dead time having a predetermined period length elapses from timing t12, the driving signal generation circuit 1 generates a high-level driving signal Sd3 at timing t13. In response to this, the transistor Q3 is turned on.

  The transistor Q2 is always on in the positive half-cycle period after the timing t12. When the transistor Q3 is turned on at the timing t13 in the positive half-cycle period, due to the parasitic inductance and parasitic capacitance of the three-level inverter circuit 2, The collector-emitter voltage Vce2 of the transistor Q2 varies. However, since the operation of the overcurrent protection circuit 22 is substantially stopped, the overcurrent is not erroneously detected even if the collector-emitter voltage Vce2 of the transistor Q2 varies as the transistor Q3 is turned on.

  As described above, according to the drive signal generation circuit 1 and the overcurrent protection circuit 22 according to the present embodiment, the transistor Q2 can be protected from the overcurrent that occurs due to the switching of the transistor Q2. Further, the drive signal generation circuit 1 detects the timing at which the signal wave Sr becomes the reference level, and the overcurrent provided in the transistor Q2 that is always turned on during the period from the detected timing to the half of the basic period. Control is performed so that the operation of the protection circuit 22 is substantially stopped. As a result, the operation of the overcurrent protection circuit 22 is substantially stopped during the positive half-cycle period in which the transistor Q2 is always on, so that the collector of the transistor Q2 is caused by the switching of the other transistors Q1 and Q3. Even if the emitter-to-emitter voltage Vce2 varies, the overcurrent is not erroneously detected. The overcurrent protection circuit 22 cannot detect overcurrent caused by switching of the transistors Q1 and Q3 other than the transistor Q2 during the positive half cycle period, but the overcurrent is detected by the overcurrent protection circuits 21B and 23 of the transistors Q1 and Q3. Therefore, the transistor Q2 can be protected from overcurrent.

  Further, according to the drive signal generation circuit 1 and the overcurrent protection circuit 23 according to the present embodiment, the transistor Q3 can be protected from the overcurrent that is caused by the switching of the transistor Q3. Further, the drive signal generation circuit 1 detects the timing at which the signal wave Sr becomes the reference level, and the overcurrent provided in the transistor Q3 that is always turned on during the period from the detected timing to the half of the basic period. Control is performed so that the operation of the protection circuit 23 is substantially stopped. This substantially stops the operation of the overcurrent protection circuit 23 in the negative half-cycle period in which the transistor Q3 is always on, so that the collector of the transistor Q3 is caused by the switching of the other transistors Q2 and Q4. Even if the emitter-to-emitter voltage Vce3 varies, the overcurrent is not erroneously detected. The overcurrent protection circuit 23 cannot detect overcurrent caused by switching of the transistors Q2 and Q4 other than the transistor Q3 in the negative half-cycle period, but the overcurrent is detected by the overcurrent protection circuits 22 and 24B of the transistors Q2 and Q4. Therefore, the transistor Q3 can be protected from overcurrent.

  Therefore, according to the present embodiment, it is possible to prevent erroneous detection of overcurrent by the overcurrent protection circuit of the transistor that is always turned on over the half cycle period of the basic cycle. Further, in the overcurrent protection circuit 22B according to the related art, it is necessary to set the time constant τ of the filter circuit 32 sufficiently large. However, according to the overcurrent protection circuit 22 according to the present embodiment, the filter circuit 32 includes The time constant τ can be set to an arbitrary value less than or equal to the short-circuit tolerance of the transistor Q2.

Second embodiment.
FIG. 5 is a block diagram showing the configuration of the power conversion device according to the second embodiment of the present invention, and FIG. 6 is a circuit diagram showing the configuration of the overcurrent protection circuit 22A of FIG. 5, the power converter according to the present embodiment includes a drive signal generation circuit 1A, drive circuits 11, 12, 13, and 14, overcurrent protection circuits 21B, 22A, 23A, and 24B, and a three-level inverter circuit 2. And is configured. In FIG. 5, only the configuration for one phase is shown. The power conversion device according to the present embodiment generates a drive signal instead of the drive signal generation circuit 1 and the overcurrent protection circuits 21 and 24, as compared to the power conversion device according to the first embodiment (see FIG. 1). The difference is that a circuit 1A and overcurrent protection circuits 21A and 24A are provided. The drive signal generation circuit 1A and the overcurrent protection circuits 21B, 22A, 23A, and 24B constitute an overcurrent protection device for the three-level inverter circuit 2. Only differences from the power conversion apparatus according to the first embodiment will be described below.

  In FIG. 6, the overcurrent protection circuit 22A includes a voltage detection circuit 31, a filter circuit 32 including a resistor 33 and a capacitor 34, a comparator 35, voltage sources 36 and 37, a timer circuit 40, and a switch SW. It is prepared for. The overcurrent protection circuit 23A is configured similarly to the overcurrent protection circuit 22A.

  In FIG. 5, the drive signal generation circuit 1A generates a signal wave Sr and two carrier waves Sc1 and Sc2 as in the drive signal generation circuit 1B of FIG. 8 (FIGS. 10A and 10B). ), And drive signals Sd1 to Sd4 are generated using the signal wave Sr and the carrier waves Sc1 and Sc2. Furthermore, similarly to the drive signal generation circuit 1B, the drive signal generation circuit 1A outputs the drive signals Sd1 to Sd4 to the drive circuits 11 to 14, respectively. Further, the drive signal generation circuit 1A outputs the drive signal Sd2 to the timer circuit 40 (see FIG. 6) of the overcurrent protection circuit 22A, and outputs the drive signal Sd3 to the timer circuit 40 of the overcurrent protection circuit 23A.

  6, the overcurrent protection circuit 22A is different from the overcurrent protection circuit 22 of FIG. 2 in that a timer circuit 40 is further provided. In FIG. 6, the timer circuit 40 starts operation at the rising timing of the drive signal Sd2, is reset, generates a low-level overcurrent protection circuit control signal S40, and outputs it to the switch SW. Then, the timer circuit 40 generates a high-level overcurrent protection circuit control signal S40 when a predetermined threshold time T1 has elapsed from the start of operation, and outputs it to the switch SW. Here, the threshold time T1 is set to be larger than the short-circuit tolerance T of the transistor Q2 and smaller than a predetermined period T23 from when the transistor Q2 is turned on until the transistor Q3 is turned on next. Note that the short-circuit tolerances of the transistors Q1 to Q4 are substantially equal to each other.

  In FIG. 6, the switch SW is switched to the contact a side in response to the low level overcurrent protection circuit control signal S40 from the timer circuit 40, while the contact b in response to the high level overcurrent protection circuit control signal S40. Switched to the side. In response to the overcurrent protection circuit control signal S40, the switch SW selectively outputs one of the filtered voltage V32 and the voltage Va to the non-inverting input terminal of the comparator 35 via the control terminal c. The comparator 35 compares the voltage output from the control terminal c of the switch SW with the overcurrent detection voltage Vr. When the voltage output from the switch SW is greater than the overcurrent detection voltage Vr, the comparator 35 supplies an overcurrent to the transistor Q2. A high level overcurrent detection signal S22A indicating that collector current Ic2 exceeding the threshold value has flowed is generated. On the other hand, when the control terminal c is equal to or lower than the overcurrent detection voltage Vr, the low level overcurrent detection signal S22A is generated. The overcurrent detection signal S22A is output to the drive signal generation circuit 1A and the drive circuit 12. In the overcurrent protection circuit 22A, the voltage detection circuit 31 and the filter circuit 32 are controlled so as to operate only during the ON period of the transistor Q2.

  In FIG. 5, an overcurrent protection circuit 23A is configured in the same manner as the overcurrent protection circuit 22A, detects whether or not a collector current exceeding an overcurrent threshold value flows through the transistor Q3, and indicates the detection result. The detection signal S23A is generated and output to the drive circuit 13 and the drive signal generation circuit 1A. In the overcurrent protection circuit 23A, the timer circuit 40 starts operation and is reset at the rising timing of the drive signal Sd3, generates a low-level overcurrent protection circuit control signal S40, and outputs it to the switch SW. Then, the timer circuit 40 of the overcurrent protection circuit 23A generates a high-level overcurrent protection circuit control signal S40 when a predetermined threshold time T2 has elapsed from the start of operation, and outputs it to the switch SW. Here, the threshold time T2 is set to be larger than the short-circuit withstand capability of the transistor Q3 and smaller than a predetermined period from when the transistor Q3 is turned on until the transistor Q2 is turned on next time. Note that, as described above, the short-circuit tolerances of the transistors Q1 to Q4 are substantially equal to each other, and therefore the first and second threshold times T1 and T2 are set to be substantially the same. The drive circuits 12 and 13 generate drive voltages V12 and V13 for turning off the transistors Q2 and Q3 in response to the high-level overcurrent detection signals S22A and S23A, respectively, and generate gates and emitters of the transistors Q2 and Q3. Apply between.

  In FIG. 5, the drive signal generation circuit 1 </ b> A is configured so that all the transistors are turned on when at least one of the transistors Q <b> 1 to Q <b> 4 flows based on the overcurrent detection signals S <b> 21 </ b> B, S <b> 22 </ b> A, S <b> 23 </ b> A, S24B. Drive signals Sd1 to Sd4 are generated so as to turn off Q1 to Q4. In response, all transistors Q1-Q4 are turned off and protected from overcurrent.

  FIG. 7 is a timing chart showing the operation of the power conversion apparatus of FIG. In FIG. 7, at timing t21, the drive signal generation circuit 1A generates a high level drive signal Sd2 and a low level overcurrent protection circuit control signal Sa2. In response to the high level drive signal Sd2, the transistor Q2 is turned on, the collector-emitter voltage Vce2 of the transistor Q2 is lowered, and the collector current Ic2 flows out to the transistor Q2. Further, the voltage detection circuit 31, the filter circuit 32, and the timer circuit 40 of the overcurrent protection circuit 22A start operation, and the switch SW is switched to the contact a side. For this reason, after timing t21, the filtered voltage V32 from the filter circuit 32 is output to the comparator 35 of the overcurrent protection circuit 22A via the control terminal c of the overcurrent protection circuit 22A. The filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22A gradually increases with a time constant τ. In the case of FIG. 7, since the collector current Ic2 of the transistor Q2 does not exceed the overcurrent threshold, the filtered voltage V32 from the filter circuit 32 of the overcurrent protection circuit 22A does not exceed the overcurrent detection voltage Vr. The voltage level of the overcurrent detection signal S22A remains low.

  When the threshold time T1 elapses from the timing t21, at the timing t22, the timer circuit 40 of the overcurrent protection circuit 22A generates a high-level overcurrent protection circuit control signal S40 to the switch SW of the overcurrent protection circuit 22A. Output. In response to this, the switch SW of the overcurrent protection circuit 22A is switched to the contact b side, and the overcurrent protection circuit 22A substantially stops its operation and generates a low level overcurrent detection signal S22A. Further, when a dead time having a predetermined period length elapses from timing t22, the driving signal generation circuit 1A generates a high-level driving signal Sd3 at timing t23. In response to this, the transistor Q3 is turned on.

  The transistor Q2 is always turned on in the positive half cycle period after the timing t22, and when the transistor Q3 is turned on at the timing t23 in the positive half cycle period, due to the parasitic inductance and parasitic capacitance of the three-level inverter circuit 2, The collector-emitter voltage Vce2 of the transistor Q2 varies. However, since the overcurrent protection circuit 22A substantially stops operating, even if the collector-emitter voltage Vce2 of the transistor Q2 varies as the transistor Q3 is turned on, the overcurrent is not erroneously detected.

  As described above, according to the drive signal generation circuit 1A and the overcurrent protection circuit 22A according to the present embodiment, the transistor Q2 can be protected from the overcurrent generated due to the switching of the transistor Q2. Further, since the operation of the overcurrent protection circuit 22A is substantially stopped in the positive half cycle period in which the transistor Q2 is always on, the collector-emitter of the transistor Q2 is caused by the switching of the other transistors Q1 and Q3. Even if the inter-voltage Vce2 varies, the overcurrent is not erroneously detected. The overcurrent protection circuit 22A cannot detect overcurrent caused by switching of the transistors Q1 and Q3 other than the transistor Q2 during the positive half-cycle period, but the overcurrent is detected by the overcurrent protection circuits 21B and 23A of the transistors Q1 and Q3. Therefore, the transistor Q2 can be protected from overcurrent.

  In addition, according to the drive signal generation circuit 1A and the overcurrent protection circuit 23A according to the present embodiment, the transistor Q3 can be protected from an overcurrent generated due to switching of the transistor Q3. Further, since the operation of the overcurrent protection circuit 23A is substantially stopped during the negative half cycle period in which the transistor Q3 is always on, the collector-emitter of the transistor Q3 is caused by the switching of the other transistors Q2 and Q4. Even if the inter-voltage Vce3 varies, the overcurrent is not erroneously detected. The overcurrent protection circuit 23A cannot detect overcurrent caused by switching of the transistors Q2 and Q4 other than the transistor Q3 in the negative half-cycle period. However, the overcurrent protection circuit 22A, 24B of the transistors Q2 and Q4 detects the overcurrent. Therefore, the transistor Q3 can be protected from overcurrent.

  Therefore, according to the present embodiment, it is possible to prevent erroneous detection of overcurrent by the overcurrent protection circuit of the transistor that is always turned on over the half cycle period of the basic cycle. Further, in the overcurrent protection circuit 22B according to the related art, it is necessary to set the time constant τ of the filter circuit 32 sufficiently large. However, according to the overcurrent protection circuit 22A according to the present embodiment, the filter circuit 32 includes The time constant τ can be set to an arbitrary value equal to or less than the short-circuit tolerance T of the transistor Q2.

  In each of the above embodiments, the overcurrent protection circuit provided corresponding to each of the transistors Q1 to Q4 is configured as an overcurrent protection circuit 21B, 22, 22A, 23, 23A, 24B. It is not limited to this. Each of the overcurrent protection circuits 21B, 22, 22A, 23, 23A, and 24B detects a voltage across each transistor, performs low-pass filtering on the voltage across each transistor, and the post-filtering voltage is a predetermined overvoltage. When the current detection voltage is exceeded, an overcurrent detection signal indicating that an overcurrent has flowed through the transistor may be generated and output to the drive signal generation circuit 1 or 1A to protect the transistors Q1 to Q4.

  Further, the overcurrent protection circuits 22 and 23 may be substantially stopped in response to the overcurrent protection circuit control signals Sa2 and Sa3 from the drive signal generation circuit 1, respectively. Furthermore, the overcurrent protection circuit 22A includes a timer circuit that substantially stops the operation of the overcurrent protection circuit 22A when a predetermined first threshold time T1 has elapsed since the transistor Q2 was turned on. The overcurrent protection circuit 23A may be a timer circuit that substantially stops the operation of the overcurrent protection circuit 23A when a predetermined second threshold time T2 has elapsed after the transistor Q3 is turned on. You should prepare. Here, the first threshold time T1 is set so as to be larger than the short-circuit withstand capability of the transistor Q2 and smaller than the period from when the transistor Q2 is turned on to when the transistor Q3 is turned on next. The threshold time T2 is set to be larger than the short-circuit withstand capability of the transistor Q3 and smaller than the period from when the transistor Q3 is turned on to when the transistor Q2 is turned on next time. In general, the first and second threshold times T1 and T2 are set to be substantially the same.

  Moreover, although the power converter device which concerns on each said embodiment was provided with the 3 level inverter circuit 2, this invention is not restricted to this, You may provide the multilevel inverter circuit of 4 levels or more.

  As described above, according to the overcurrent protection device according to the first invention and the power conversion device including the overcurrent protection device, the drive signal generation circuit detects the timing at which the signal wave becomes the reference level, The multi-level inverter is controlled so as to substantially stop the operation of the overcurrent protection circuit provided corresponding to the semiconductor element that is always turned on during the half period of the basic period from the detected timing. It is possible to prevent erroneous detection of overcurrent of each semiconductor element of the circuit.

  According to the overcurrent protection device and the power conversion device including the overcurrent protection device according to the second invention, each overcurrent protection circuit provided in each of the second and third semiconductor elements includes the overcurrent protection circuit. After the semiconductor element provided in the current protection circuit is turned on, until the other semiconductor element of the second and third semiconductor elements is turned on after the semiconductor element is turned on, which is greater than the short-circuit tolerance of the semiconductor element. When a threshold time set to be smaller than the period of time elapses, a timer circuit that substantially stops the operation of the overcurrent protection circuit is provided, so that the overcurrent of each semiconductor element of the multilevel inverter circuit is reduced. False detection can be prevented.

1, 1A, 1B... Drive signal generation circuit,
2 ... 3-level inverter circuit,
11-14 ... Driving circuit,
21B, 22, 22A, 22B, 23, 23A, 23B, 24B ... overcurrent protection circuit,
31 ... Voltage detection circuit,
32. Filter circuit,
35 ... Comparator,
40. Timer circuit,
SW: Switch.

Claims (3)

A first, a second, a third and a fourth semiconductor element connected in series with each other between a positive potential and a negative potential of two DC power supplies connected in series with each other;
First to fourth freewheeling diodes connected in antiparallel to the first to fourth semiconductor elements, respectively;
A first clamp diode connected from a connection point of the two DC power sources to a connection point of the first and second semiconductor elements;
In an overcurrent protection device for a multi-level inverter circuit comprising a second clamp diode connected from a connection point of the third and fourth semiconductor elements to a connection point of the two DC power supplies,
A signal wave having a predetermined reference level and a predetermined basic period is converted into one of first and second carrier waves each having a predetermined positive DC bias and a predetermined negative bias with respect to the reference level. Compared with the wave, based on the comparison result, first and third drive signals for driving on and off the first and third semiconductor elements are generated, and the first and third semiconductor elements are respectively generated. For outputting and comparing the signal wave with the other carrier wave of the first and second carrier waves and driving the second and fourth semiconductor elements on and off based on the comparison result, respectively. A drive signal generation circuit that generates second and fourth drive signals and outputs the second and fourth drive signals to the second and fourth semiconductor elements, respectively;
Provided corresponding to each of the semiconductor elements, the voltage across the semiconductor elements is detected, low-pass filtering is performed on the voltage across the semiconductor elements, and the filtered voltage is set to a predetermined overcurrent detection voltage. Four overcurrent protection circuits for generating an overcurrent detection signal indicating that an overcurrent has passed through each of the semiconductor elements and outputting the detected signal to the drive signal generation circuit to protect the semiconductor elements. Prepared,
The drive signal generation circuit is provided corresponding to a semiconductor element that is always turned on in the period from the detected timing to a half period of the basic period from the detected timing when the signal wave reaches the reference level. An overcurrent protection device that controls the operation of the overcurrent protection circuit to substantially stop. A first, a second, a third and a fourth semiconductor element connected in series with each other between a positive potential and a negative potential of two DC power supplies connected in series with each other;
First to fourth freewheeling diodes connected in antiparallel to the first to fourth semiconductor elements, respectively;
A first clamp diode connected from a connection point of the two DC power sources to a connection point of the first and second semiconductor elements;
In an overcurrent protection device for a multi-level inverter circuit comprising a second clamp diode connected from a connection point of the third and fourth semiconductor elements to a connection point of the two DC power supplies,
A signal wave having a predetermined reference level and a predetermined basic period is converted into one of first and second carrier waves each having a predetermined positive DC bias and a predetermined negative bias with respect to the reference level. Compared with the wave, based on the comparison result, first and third drive signals for driving on and off the first and third semiconductor elements are generated, and the first and third semiconductor elements are respectively generated. For outputting and comparing the signal wave with the other carrier wave of the first and second carrier waves and driving the second and fourth semiconductor elements on and off based on the comparison result, respectively. A drive signal generation circuit that generates second and fourth drive signals and outputs the second and fourth drive signals to the second and fourth semiconductor elements, respectively;
Provided corresponding to each of the semiconductor elements, the voltage across the semiconductor elements is detected, low-pass filtering is performed on the voltage across the semiconductor elements, and the filtered voltage is set to a predetermined overcurrent detection voltage. Four overcurrent protection circuits for generating an overcurrent detection signal indicating that an overcurrent has passed through each of the semiconductor elements and outputting the detected signal to the drive signal generation circuit to protect the semiconductor elements. Prepared,
Of the four overcurrent protection circuits, each overcurrent protection circuit provided in each of the second and third semiconductor elements is turned on after the semiconductor element provided in the overcurrent protection circuit is turned on. A threshold time set to be greater than the short-circuit withstand capability of the semiconductor element and smaller than the period from when the semiconductor element is turned on until the other one of the second and third semiconductor elements is turned on. And a timer circuit for substantially stopping the operation of the overcurrent protection circuit. The multi-level inverter circuit;
A power conversion device comprising the overcurrent protection device according to claim 1.

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