JP5736826B2 - Image data processing apparatus, recording apparatus, and image data processing method - Google Patents

Description

  The present invention relates to an image data processing apparatus, a recording apparatus, and an image data processing method for generating second image data obtained by vertically and horizontally converting the first image data.

  For example, Patent Documents 1 and 2 disclose a recording apparatus (printer) including a print head that ejects ink. In the printer, print image data (first image data) is subjected to a plurality of processes to generate head image data (second image data), and the print head is driven based on the head image data. The print image data has pixels arranged in the horizontal direction (row direction), whereas the head image data sent to the print head needs to be arranged so that the pixels are arranged in the vertical direction. This is because, for example, in a serial printer, a nozzle row in which a plurality of nozzles are arranged in a direction orthogonal to the scanning direction of the print head is formed, and each time the print head moves by one pixel in the scanning direction, This is because it is necessary to eject ink one by one. For this reason, in the print image data, the arrangement order of the pixels along the scanning direction (lateral direction) of the print head is aligned with the arrangement order of the pixels in the nozzle row direction (vertical direction) in accordance with the ink ejection order of the print head. Head image data is generated by performing vertical / horizontal conversion (rotation processing). For example, in Patent Documents 1 and 2, print image data is transferred from a main memory such as a RAM to a vertical / horizontal conversion device (rotation unit) for each processing unit, and in the vertical / horizontal conversion device, the arrangement order of pixels in the line direction (horizontal direction) is printed. Vertical / horizontal conversion is performed in the order of the pixels in the raster direction (vertical direction) corresponding to the nozzle arrangement of the head, and the processing unit data after vertical / horizontal conversion is sequentially transferred to the main memory, so that the vertical / horizontal conversion of the print image data is performed. Is called. The data transfer at this time employs burst transfer that can transfer data in units of processing continuously and can perform high-speed processing.

  In Patent Documents 1 and 2, for example, A × A pixels of the first image data (original image data) are transferred to SRAM (memory) and then rotated. The A × A pixels to be rotated at this time are the consecutive pixels belonging to the same row of the first image data in the order of the pixels arranged in the horizontal direction, and the order of the pixels arranged in the vertical direction is the first image data. Are continuous pixels belonging to the same column. For this reason, vertical / horizontal conversion can be performed only by continuously rotating the A × A pixel.

  When the data size (raster size) in the row direction of the first image data is not an integral multiple of a burst size (for example, a data size for N pixels) that is a transfer unit of burst transfer, it is less than the burst size (transfer size). Extra pixels are created. FIG. 20 shows an example in which extra pixels less than the burst size can be formed in this way.

  FIG. 20A shows print image data before rotation processing, and FIG. 20B shows head image data after rotation processing. In FIG. 20A, the pixels constituting the print image data are arranged in a matrix of N rows × M columns. Normally, the image data at the time of the rotation process has a number of pixels of about several hundred rows × several 1000 columns, but FIG. 20 shows an example of image data having 6 rows × 10 columns of pixels for the sake of simplicity. Here, the symbol “NM” of the pixel indicates the pixel data of the Nth row and the Mth column. Further, the column direction (vertical direction in FIG. 20A) corresponds to the nozzle column direction in which the nozzles constituting the nozzle column of the print head are arranged, and the row direction (left and right direction in FIG. 20) corresponds to the scan direction of the print head. To do.

  In the rotation processing, print image data stored in the main memory 100 (DRAM) is burst-transferred to the rotation unit in the order indicated by bold numbers in the figure, for example, in each square area (square block) of 4 × 4 pixels. . Then, the rotation unit performs rotation processing (vertical / horizontal conversion) on the transferred data, burst-transfers the rotated data to the main memory 100, and stores the data at the positions indicated by bold numerals in FIG. As a result, the head image data subjected to vertical / horizontal conversion is generated in the main memory 100.

  By the way, in the burst transfer method, when transferring data of a square block (4 × 4 pixels) in a rotation processing unit surrounded by a thick line frame in FIG. 20A, the burst size (4 pixels (16 bits × 16 in FIG. 20)) is transferred. 4)) Transfer the data four times while switching the rows. Then, the square blocks are read in the order of the bold numbers “1”, “2”,... “6” shown in FIG.

JP 2004-122594 A JP 2008-221769 A

  By the way, as shown in FIG. 20A, the data of the bold numbers “3” and “6” are the remainder data whose pixel data is less than 4 pixels of the burst size in the row direction, and the bold numbers “4”. ”,“ 5 ”,“ 6 ”data is the column remainder data in which the pixel data is less than the number of transfers“ 4 ”(4 pixels) in the column direction. For this reason, dummy data indicated by hatching in FIG. In this case, there is a method of changing the method of specifying burst transfer only when the number of pixels is less than 4 pixels and avoiding the addition of dummy data, but this is not preferable because the memory access of the CPU becomes frequent and the transfer rate is slowed down.

  For this reason, if high-speed transfer is to be performed by the burst transfer method, it is necessary to store dummy data. In this case, since dummy data is added to the print image data and dummy data is also added to the head image data, a main memory 100 having a large data storage area (storage capacity) is prepared, and other data in the main memory 100 is provided. There were problems such as the data storage area being compressed. For this reason, there has been a demand for reducing dummy data as much as possible.

  The present invention has been made in view of the above problems, and one of its purposes is an image data processing apparatus and a recording apparatus that can reduce the storage area used in the storage means without significantly reducing the vertical / horizontal conversion processing speed. And providing an image data processing method.

  In order to achieve one of the above objects, one aspect of the present invention is an image data processing apparatus for generating second image data by longitudinally and laterally converting first image data, wherein the first image data is stored. First storage means, a memory, second storage means for storing second image data, and first data of transfer size including at least one pixel of interest arranged in the same column from the first image data First transfer means for transferring the first data to the memory, writing means for storing the transferred first data in the memory, and selecting and reading at least one pixel of interest from the first data in the memory A second transfer means for transferring second data having a transfer size including the pixel of interest read from the memory to the second storage means; a second transfer means for transferring the second image data to the second storage means; When the pixel group of the second data is written so as to be in the pixel arrangement order, and the pixel group includes unnecessary pixels other than the target pixel, the target pixel is overwritten with the unnecessary pixel, and the unnecessary pixel is transferred to the target pixel. The gist of the present invention is that it comprises a writing adjustment means for prohibiting overwriting.

According to one embodiment of the present invention, the first data having a transfer size including at least one pixel of interest arranged in the same column is transferred from the first image data by the first transfer unit. The transferred first data is written (stored) in the memory by the writing means. The reading means selects and reads at least one target pixel from the first data in the memory. The second data having the transfer size including the target pixel read from the memory is transferred by the second transfer unit. The transferred second data (pixel group) is written by the writing adjusting means so as to be in the pixel arrangement order of the second image data. At this time, when the second data includes unnecessary pixels other than the target pixel, the write adjustment unit overwrites the target pixel with the unnecessary pixel and prohibits the unnecessary pixel from being overwritten on the target pixel. Therefore, the vertical / horizontal conversion from the first image data to the second image data can be performed without adding dummy data so that the raster size is a natural number multiple of the transfer size. Therefore, it is possible to suppress the use storage area in the storage means without significantly reducing the vertical / horizontal conversion processing speed.
In order to achieve one of the above objects, one aspect of the present invention is an image data processing apparatus for generating second image data by longitudinally and laterally converting first image data, wherein the first image data is stored. First storage means, a memory, second storage means for storing second image data, and a transfer size in which a plurality of pixels arranged in a line including at least one pixel of interest are selected from the first image data The first data is transferred from the first storage means by the transfer size by sequentially changing the pixel of interest and stored in the memory, and from the group of the first data stored in the memory Second data having a transfer size in which a plurality of pixels including at least one pixel of interest are selected is transferred from the memory to the second storage unit in increments of the transfer size by sequentially changing the pixels of interest. Second transfer means for writing the pixel of interest in the data to a position in the second storage means arranged at a position that matches the pixel arrangement order of the second image data in the second storage means, and The transfer means includes: a correction means for correcting the arrangement order of the pixels of the second data that is the misalignment when the second data is a misalignment in which the arrangement order of the pixels is inappropriate; and the second data is the pixel of interest And a write adjustment unit that prohibits writing of the unnecessary pixel to the second storage unit when unnecessary pixels other than the above are included.

  In the image data processing apparatus according to one aspect of the present invention, the reading means is configured such that the transfer size is B bytes (B is a natural number), and an exponent when the B is expressed as a power of 2 is m (note that m Is a natural number), and it is preferable to read the pixel of interest from the transfer size data written in the memory, using the position of the lower m bits of the address of the pixel of interest as a read address.

  According to one embodiment of the present invention, the reading means reads the pixel of interest from the transfer size data written in the memory, using the position of the lower m bits of the address of the pixel of interest as the reading address. Therefore, the pixel of interest can be appropriately read from the transfer size data stored in the memory.

  In the image data processing apparatus according to one aspect of the present invention, a determination unit that determines whether or not the second data is a misalignment in which the pixel arrangement order is inappropriate, and a second that is determined to be the misalignment. It is preferable that correction means for correcting the arrangement order of the two data pixels is further provided.

  According to one embodiment of the present invention, when the determination unit determines that the second data is misaligned, the correction unit corrects the pixel arrangement order of the misaligned second data. Therefore, the corrected second data is written in the second storage unit, so that the pixels of the second data can be written at an appropriate position after the rotation process.

In the image data processing apparatus according to one aspect of the present invention, the correction unit generates a first flag that is attached to each pixel data and takes one of a mask valid value and a mask invalid value. Flag generating means; second flag generating means for generating a second flag which is attached to each pixel data and takes one of a mask valid value and a mask invalid value; and the pixels constituting the second data A shift processing means for shifting and changing the arrangement order of the pixels; and the second flag corresponding to an unnecessary pixel other than the target pixel is shifted while the first flag and the second flag are shifted in accordance with the shift of the pixel. And a third flag generating means for generating a third flag by performing an OR operation on the shifted first flag and second flag after changing to a mask valid value, wherein the second transfer means comprises: , The third flag is attached to each pixel data constituting the second data after transfer, and the data is transferred to the second storage means. The write adjustment means has the mask invalid for the third flag. It is preferable to provide mask processing means for writing the corresponding pixel data if the value is valid, and prohibiting the writing of the corresponding pixel data if the mask is valid .

According to one embodiment of the present invention, the third flag is allowed write of the corresponding pixel data if the value of the invalid mask, the writing of the corresponding pixel data is prohibited if the mask effective value. Therefore, the pixel of interest can be written to the second storage means, and overwriting of the pixel of interest by unnecessary pixels can be prohibited. Therefore, it is possible to write the target pixel that has been subjected to the rotation process without overwriting the target pixel that has been previously written in the second storage means.

  In the image data processing apparatus according to one aspect of the present invention, the first transfer unit is instructed to read out the first data by transfer size from the first image data stored in the first storage unit. The read address to be specified is preferably specified by masking the lower m bits of the read address of the pixel of interest in the first data.

  According to one embodiment of the present invention, since the lower m bits of the read address of the pixel of interest in the first data are masked to designate the read address, the first data is obtained from the appropriate read address of the first storage means. Can be read.

  In the image data processing apparatus according to one aspect of the present invention, the reading unit selects a pixel at a position indicated by lower m bits of the read address from the first data stored in the memory. It is preferable to read.

  According to one embodiment of the present invention, the reading means selects and reads out the pixel at the position indicated by the lower m bits of the read address from among the pixels belonging to the first data stored in the memory, thereby appropriately The second data from which the pixel is selected can be read out.

  In the image data processing apparatus according to one aspect of the present invention, the write address instructing the second transfer means to write the second data in the second storage means is the second data. Of these, it is preferable to specify by masking the lower m bits of the write address of the pixel of interest.

  According to one embodiment of the present invention, the lower m bits of the write address of the pixel of interest in the second data are masked to designate the write address, so that the second write means has an appropriate write address. Data can be written.

  A recording apparatus according to an aspect of the present invention is based on the image data processing apparatus according to the aspect of the invention described above and the second image data obtained by vertically and horizontally converting the first image data by the image data processing apparatus. And a recording means for performing the above.

  According to one embodiment of the present invention, when the first image data is vertically and horizontally converted to generate the second image data, use of each image data in the first storage means and the second storage means provided in the recording apparatus Vertical / horizontal conversion processing can be performed while keeping the storage area (used storage capacity) small.

One aspect of the present invention is an image data processing method for generating second image data by performing vertical / horizontal conversion on first image data, and includes at least one pixel of interest arranged in the same column from the first image data. A first transfer step of transferring first data of a transfer size to the memory; a writing step of storing the transferred first data in the memory; and at least one pixel of interest from the first data in the memory A read step for selecting and reading out, a second transfer step for transferring the second data of the transfer size including the pixel of interest read from the memory to the second storage means, and the second storage means to the second storage means When the pixel group of the second data is written so as to be in the pixel arrangement order of the two image data, and the pixel group includes unnecessary pixels other than the target pixel, the target image With Allow writing to unwanted pixels, is summarized as further comprising a, a write adjustment step of masking writing to the pixel of interest unnecessary pixels. According to the image data processing method of one embodiment of the present invention, it is possible to obtain the same effect as that of the image data processing apparatus.
One aspect of the present invention is an image data processing method for generating first image data by converting the first image data into vertical and horizontal directions, and includes at least one attention from the first image data stored in the first storage means. A first transfer step of storing first data of a transfer size in which a plurality of pixels arranged in a row including the pixels are selected, sequentially changing the pixel of interest from the first storage unit, transferring the transfer size by the transfer size, and storing the first data; Second data having a transfer size obtained by selecting a plurality of pixels including at least one pixel of interest from the group of the first data stored in the memory, and second data of the transfer size from the memory by changing the size of the second one by one. The pixel of interest in the second data is placed in a position that matches the pixel arrangement order of the second image data in the second storage means. A second transfer step of writing to the device, wherein the second transfer step is an array of pixels of the second data that is the misalignment when the second data is a misalignment in which the pixel arrangement order is inappropriate A correction step for correcting the order; and a writing adjustment step for prohibiting writing of the unnecessary pixel to the second storage means when the second data includes an unnecessary pixel other than the target pixel. And

1 is a perspective view of a multifunction machine according to an embodiment. FIG. 2 is a schematic bottom view of a print head. FIG. 2 is a block diagram illustrating an electrical configuration of the multifunction machine. The block diagram which shows the electrical structure which concerns on a vertical / horizontal conversion process. (A) The schematic diagram for demonstrating the storage state of print image data, respectively (b) The storage state of head image data. The figure which shows the data structure of print image data. (A) Storing state of print image data, (b) Schematic diagram explaining the writing process to SRAM. (A) Storing state of print image data, (b) Schematic diagram explaining the writing process to SRAM. (A)-(c) The figure explaining the data reading from SRAM. (A) Data reading process from SRAM, (b) Schematic diagram showing first to third read data. The schematic diagram explaining the data preservation | save to the main memory. (A)-(d) The schematic diagram explaining the write-in process of the 1st time of a misalignment process. (A)-(d) The schematic diagram explaining the write-in process of the 2nd time of misalignment process. The schematic diagram of the printing image data PD which shows the 5th-6th line. (A)-(c) The schematic diagram explaining the data read-out process from SRAM in the 5th-6th line. (A) Data reading process from SRAM, (b) Schematic diagram showing first to third read data. (A)-(c) The schematic diagram explaining the preservation | save of the 1st data to the main memory. (A)-(d) The schematic diagram explaining the write-in process of the 1st time of a misalignment process. (A)-(d) The schematic diagram explaining the write-in process of the 2nd time of misalignment process. (A), (b) The schematic diagram explaining the vertical / horizontal conversion process from the printing image data to head image data in a prior art.

  Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS. As illustrated in FIG. 1, a multifunction machine 11 that is an example of a recording apparatus includes a main body 12 and a cover 13. The lower part of the main body 12 is a printer unit 14, and the upper part is a scanner unit 15. The printer unit 14 employs, for example, an ink jet recording method. An operation panel portion 17 is provided on the upper front portion of the main body 12. A paper discharge unit 18 for discharging the printed paper P is provided at the lower front side of the main body 12. A card slot 20 into which the memory card 19 can be inserted and removed is provided at the upper right position in FIG.

  As shown in FIG. 1, the operation panel unit 17 is provided with a display unit 21 (for example, a liquid crystal display) at the center in the width direction. Further, the operation panel unit 17 is provided with a power button 22, a mode selection button 23, a start button 24 for starting printing / scanning, a stop button 25 for stopping an operation being executed, and the like. By operating the mode selection button 23, one of five modes including “memory card”, “copy”, “scan”, and the like can be selected, and printing of a photo or the like based on image data read from the memory card 19 can be performed. Copy printing, document scanning, etc. can be performed.

  FIG. 3 is a block diagram showing an electrical configuration of the multifunction machine 11. The multifunction machine 11 includes a control device 30 that controls the overall control. The control device 30 drives and controls the printer unit 14 and the scanner unit 15. The control device 30 drives and controls a carriage motor 27 that constitutes the printer unit 14, a conveyance motor 28 that constitutes a conveyance unit, and a print head 29 (fluid ejection head) that is an example of a recording unit. Printing on P (medium) is performed.

  The control device 30 includes a CPU 31 (central processing unit), an ASIC 32 (Application Specific IC), a ROM 33, a memory controller 34, a main memory 35 including a DRAM (Dynamic Random Access Memory), and a motor drive circuit 36. As DRAM, SDRAM (Synchronous DRAM), DDR SDRAM (Double-Data-Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, etc. are used. Etc. can be used.

  The ROM 33 stores programs, setting data necessary for various controls, and the like. The CPU 31 drives and controls the carriage motor 27 and the carry motor 28 by executing a program (for example, a firmware program) read from the ROM 33 and giving commands and command values to the motor drive circuit 36. Thereby, the conveyance control of the paper in the printer unit 14 and the carriage control for moving the carriage (not shown) including the print head 29 in the main scanning direction are performed.

  The multifunction machine 11 also includes a communication interface (hereinafter referred to as “communication I / F 37”). For example, the communication I / F 37 receives print data transferred from a host device (such as a personal computer) (not shown). The bus 38 connected to the communication I / F 37 is connected with a CPU 31, an ASIC 32, a ROM 33, a memory controller 34, a main memory 35, and a motor drive circuit 36 constituting the control device 30, as well as a scanner input circuit 41, a memory The card input / output circuit 42 and the operation panel unit 17 are connected.

  The scanner unit 15 optically reads a document, and performs A / D conversion on a read signal (analog signal) from the line sensor 15a and outputs it as multi-gradation RGB image data (line data). D conversion circuit 15b. The scanner input circuit 41 performs inter-line correction processing and resolution conversion processing on the RGB image data input from the scanner unit 15 under the control of the CPU 31. The RGB image data subjected to these processes is input to the ASIC 32, and is compressed into JPEG image data by a compression circuit (not shown). The memory card input / output circuit 42 reads, for example, JPEG image data from the memory card 19 inserted in the slot 20.

  A part of the storage area of the main memory 35 is used as a buffer for storing image data, and includes a reception buffer 35a, a first storage unit 35b (intermediate buffer), and a second storage unit 35c (print buffer). The reception buffer 35a stores print data received from the host device, JPEG image data via the scanner unit 15 and the memory card input / output circuit 42, and the like.

  The ASIC 32 performs image processing corresponding to the image data type on the image data (print data, JPEG image data, etc.) stored in the reception buffer 35a, so that the JPEG decompression circuit 43, the image processing circuit 44, and the like shown in FIG. A vertical / horizontal conversion device 45 and a head control unit 46 are incorporated.

  The JPEG decompression circuit 43 decompresses (decompresses) the JPEG image data read from the reception buffer 35a and develops it into RGB image data, and stores the decompressed RGB image data in the first storage unit 35b.

  The image processing circuit 44 performs known image processing including resolution conversion processing, color conversion processing, halftone processing, and the like on the RGB image data read from the first storage unit 35b. Here, the resolution conversion processing is processing for converting the resolution of the RGB image data from the display resolution to the printing resolution. The color conversion process is a process of converting RGB image data from RGB color system to CMYK image data of CMYK color system with reference to a color conversion table (not shown). The halftone process is a process of converting a gradation value (for example, 256 gradations) of pixels of CMYK image data into a gradation value for printing (for example, 2 gradations or 4 gradations). The first storage unit 35b includes three storage areas for storing the image data after completion of each of these image processes, and the final print image data (CMYK image data) after completion of all these image processes is the first storage area. It is stored in the storage area of the last stage of the storage unit 35b.

  The vertical / horizontal conversion device 45 performs vertical / horizontal conversion processing on the print image data read from the first storage unit 35b. Vertical / horizontal conversion processing is a vertical direction (raster direction) in which the order of pixels of print image data is adjusted from the horizontal order (line direction) for display to the nozzle arrangement of the print head 29 (that is, the ink ejection order). ) In the order of arrangement. The head image data after the vertical / horizontal conversion processing is stored in the second storage unit 35c (image buffer).

  The head control unit 46 converts the head image data stored in the second storage unit 35 c into head control data that can be printed by the print head 29 (ejecting control). The head control data is transferred from the head control unit 46 to the print head 29, for example, for one pass (one scan of the print head). The print head 29 includes a head drive circuit (not shown), and the head drive circuit performs ink ejection control based on the head control data.

  FIG. 2 shows the bottom surface (nozzle opening surface) of the print head. As shown in FIG. 2, the nozzle opening surface 29A of the print head 29 has a total of 180 nozzles # 1 to # 180 arranged at a constant nozzle pitch in the sub-scanning direction (vertical direction in FIG. 2). Four columns (four columns) are formed. In this example, each nozzle row includes 180 nozzles 29K, 29C, 29M, and 29Y, and is used to eject ink droplets of black (K), cyan (C), magenta (M), and yellow (Y). Is done.

  The print head 29 includes the same number of ejection drive elements 48 corresponding to the nozzles # 1 to # 180 shown in FIG. 2 as the nozzles (however, in FIG. ing). The ejection drive element 48 is composed of, for example, a piezoelectric vibration element or an electrostatic drive element. The print head 29 performs drive control of the ejection drive element 48 based on the head control data transferred from the head control unit 46 by a head drive circuit (not shown), and performs ejection control from the nozzles. Of course, the ejection driving element 48 may be a heater that heats the ink in the nozzle passage, or may be configured to eject ink droplets from the nozzles by utilizing expansion of bubbles generated by boiling in the ink heated by the heater.

  The print head 29 shown in FIG. 2 is fixed to a lower portion of a carriage (not shown) provided in the printer unit 14 so as to be movable in the main scanning direction (left and right direction in FIG. 2). By driving the carriage motor 27, the print head 29 is moved in the main scanning direction together with the carriage, and printing is performed on the paper P by ejecting ink droplets from the nozzles at intervals of one dot during the movement.

  FIG. 4 is a detailed configuration diagram of a portion related to the rotation process. As shown in FIG. 4, the vertical / horizontal conversion device 45 includes a rotation unit 50 connected to the bus 38 and an SRAM 80 connected to the rotation unit 50. The main memory 35 includes the first storage unit 35b and the second storage unit 35c described above (however, the reception buffer 35a is omitted in FIG. 4). As shown in FIG. 4, the print image data PD before the rotation process by the rotation unit 50 is stored in the first storage unit 35b, and the head image data HD after the rotation process by the rotation unit 50 is stored in the second storage unit 35c. It is to be stored. The print image data PD in the first storage unit 35b is the print image data PD shown in FIG. 6 generated by the image processing circuit 44 in the upper stage of the vertical / horizontal conversion device 45 performing predetermined image processing, in the state shown in FIG. Are stored in the first storage unit 35b.

  FIG. 6 shows the data structure of the print image data PD. The print image data PD shown in FIG. 6 is generated by performing predetermined image processing by the upper image processing circuit 44 of the vertical / horizontal conversion device 45. The number of lines of print image data PD for one pass is 180 lines, which is the same as the number of nozzles per nozzle row (180 in this example), but in order to simplify the explanation, 6 lines of 6 nozzles are used. This will be explained with an example. The number of pixels per line in the print image data for one scan (one pass) of the print head 29 is M. M corresponds to the maximum number of ink dots (maximum number of dots) printed on the paper in the paper width direction, and depends on the paper size, print range, and print resolution, for example, thousands to tens of thousands. When the burst size B is 4 pixels (8 bytes in this example), M is assumed to be divisible by the burst size B (8 bytes (4 pixels) in this example). To do. Here, if the remainder is an example, the effective operation of the vertical / horizontal conversion device 45 can be described. Therefore, in order to simplify the description, the number of pixels per line of the print image data PD is set to the burst size B. It is assumed that there are 2 pixels (4 bytes) and 10 pixels (20 bytes) remaining by dividing by the number of pixels “4” (8 bytes). That is, the print image data PD will be described using an example of N rows × M columns = 6 rows × 10 columns. In this case, the data size per line of the print image data PD, that is, the raster size is set to “R”. In this example, which is an example of 10 pixels per line, the raster size R is 20 bytes.

  In the rotation unit 50 of the present embodiment, the raster size R (length in the row direction) of data is a natural number times the burst size B in the storage area of the print image data PD before rotation and the head image data HD after rotation in the rotation process. Even in the case where they do not coincide with each other, a rotation process having an align function is realized by hardware in order to eliminate the need for dummy data.

  FIG. 5A shows a storage state of the print image data PD stored in the main memory 35 (first storage unit 35b), and FIG. 5B shows a rotation process (vertical / horizontal conversion) on the print image data PD. The storage state of the head image data HD generated in the main memory 35 (second storage unit 35c) is shown. In FIG. 5A, the pixels constituting the print image data are arranged in a matrix of N rows × M columns. The print image data PD is data for one pass used for printing when the print head 29 moves once (one pass) in the main scanning direction for printing. Therefore, the print image data PD at the time of the rotation process is formed in the main scanning direction when the print head 29 performs main scanning with the same number of rows N as the number of nozzles for one nozzle row (180 in this example). The number of columns M is the same as the maximum number of ink dots. For this reason, the print image data PD usually has a number of pixels of about several hundred rows × several thousand columns. However, in order to simplify the explanation, as shown in FIG. An example of Here, the symbol “NM” of the pixel indicates the pixel data of the Nth row and the Mth column. In the following description, a data unit for one pixel may be referred to as a “cell”. Since the print head 29 of this example has four nozzle rows so that four colors can be printed with one color per nozzle row, the rotation processing for converting the print image data PD into the head image data HD is performed for each ink color. To be done. For example, the same number of rotation units 50 as the number of colors may be provided for parallel processing, or a single rotation unit 50 may sequentially rotate the print image data PD for a plurality of colors.

  In this example, the burst size B (byte), which is the data size for one burst transfer, is 8 bytes corresponding to 4 pixels. In the first storage unit 35b, in consideration of the burst size B, the size (Byte) in the row direction is set to C · B (Byte) (where C is a natural number) which is a natural number multiple of the burst size. In FIG. 5, a region surrounded by a broken line is data of a burst size B (for four pixels) that is burst transferred at a time. Burst size data is transferred J times in one burst transfer. By continuously transferring the data for each burst size B (for the A pixel in the row direction) N times, data with A × A pixel data as one unit is transferred.

  As shown in FIG. 5A, the first burst data (pixel data “1-1”, “1-2”, “1-”) of the print image data PD stored in the main memory 35 (first storage unit 35b). 3 ”“ 1-4 ”) when the head image data after the rotation processing is stored in the main memory 35 (second storage unit 35c), the pixel data may be stored at different positions. I understand. Thus, in order to store the pixel data at different positions, memory access becomes frequent and efficiency is lowered. Therefore, in the present embodiment, a vertical / horizontal conversion device 45 (rotation processing device) made of hardware capable of efficient rotation processing without frequent memory access is used for each pixel data stored in discrete positions. .

  The rotation unit 50 shown in FIG. 4 designates the read address AR1, the burst size B, and the transfer count J for the memory controller 34. The memory controller 34 continuously transfers data (for A pixels) of each burst size B from the designated read address AR1 A times (when J = A). Thereby, the rotation unit 50 reads the A × A square block from the first storage unit 35b. This is continuously performed and A × A square blocks are read out.

  Further, the rotation unit 50 designates the write address AW1, the burst size B, and the transfer count J to the memory controller 34. The memory controller 34 continuously transfers data of burst size B (for A pixels) A times from the designated write address AW1. Thereby, the rotation unit 50 writes the A × A square block in the second storage unit 35c. Then, this is continuously performed and A × A square blocks are read out.

  In this embodiment, the burst size B is 32 bytes, and the memory controller 34 performs a 32-byte burst. However, in order to simplify the description, as described above, an example of performing an 8-byte burst with a burst size B of 8 bytes will be described. Of course, the burst size can be set as appropriate. For example, a 16-byte burst, a 24-byte burst, a 64-byte burst, or the like can be adopted. Further, the burst transfer count J may be set as appropriate.

Hereinafter, detailed configurations of the rotation unit 50, the memory controller 34, the SRAM 80, and the like will be described with reference to FIG.
4 includes a first address controller 51, an input interface (hereinafter referred to as “input I / F 52”), and an input buffer 53 as an input system. In the present embodiment, the first address controller 51 and the input I / F 52 constitute an example of a first transfer unit.

  The first address controller 51 generates a read address AR0 of the pixel of interest to be read from the print image data PD stored in the first storage unit 32b of the main memory 35. Then, the first address controller 51 sends the generated read address AR0 to the input I / F 52.

  The input I / F 52 includes an address generation unit 60 that generates a read address AR1 based on the read address AR0 from the first address controller 51. Then, the input I / F 52 requests the memory controller 34 to perform a burst read for designating the read address AR1 and reading data by burst transfer. Further, the input I / F 52 sends the read address AR 0 to the pointer controller 54.

  The memory controller 34 includes a read transfer unit 81 (burst read processing unit) having a function of performing burst read. When the read transfer unit 81 receives a burst read request from the input I / F 52, the read transfer unit 81 sequentially reads the data D1 corresponding to the burst size B from the read address AR1, and burst-transfers the data to the input I / F 52. In this example, the burst size B is a data size for four pixels. Four burst addresses are continuously transferred by designating four read addresses AR1 by one burst read request. In other words, the read transfer unit 81 reads four times from the read address AR1 specified by the burst read request by the burst size B (4 pixels), and performs burst transfer to the input I / F 52 of the rotation unit 50.

  When the input I / F 52 receives the data D1 that has been burst transferred, the input I / F 52 stores the data D1 in the input buffer 53 together with the corresponding read address AR0 used to read the data D1.

  The pointer controller 54 constitutes data D2 from the first pointer generator 61 that generates a write pointer WP that indicates the write position (write start address) of the data D1 to the SRAM 80, and the data D1 written to the SRAM 80. And a second pointer generation unit 62 that generates a read pointer RP indicating the readout position of four pixels. The write pointer WP is a pointer that indicates the write start position of the data D1 in the row direction of the SRAM 80. The read pointer RP is a pointer that points to a cell to be read in the data D1. The first pointer generator 61 shifts the write pointer WP to the next writing start position every time data D1 is written to the SRAM 80. In this example, an example in which the row direction size of the SRAM 80 is 2 · B bytes will be described. When the size is 2 · B bytes, the write pointer WP switches between two write positions in order.

  Further, the second pointer generator 62 generates a read pointer RP indicating a cell to be read out of each data D1 in the SRAM 80 from the read address AR0. The second pointer generator 62 obtains the lower 3 bits of the read address AR0 corresponding to each data D1 as the position of the read pointer RP for each row.

  The SRAM controller 55 sequentially reads the data D1 stored in the input buffer 53 and writes the data D1 in the SRAM 80, and the reading unit 64 reads out the cell indicated by the read pointer RP from the data D1 stored in the SRAM 80. Is provided.

  In addition, the SRAM controller 55 includes a first flag generation unit 65 that generates a first flag F1 for masking a cell indicated by the read pointer RP in the data D1 when the cell does not belong to the print image data PD. Prepare. Since the start address (head address) and the data size of the print image data PD are known, the first flag generation unit 65 can identify an indefinite cell that does not belong to the print image data PD from the read address AR0. Then, when the cell pointed to by the read pointer RP is a pixel of the print image data PD, the first flag generation unit 65 sets “0” to the effect that the cell is not masked as the first flag F1, and prints the cell. If the cell is an indefinite cell that is not a pixel of the image data PD, “1” is set to mask the indefinite cell as the first flag F1. Since there is one read pointer RP for each data D1, the first flag F1 corresponding to L read pointers RP is set to F1K (where K is 0, 1, 2,... L−1; where L is A natural number of 2 or more)). Here, L is the number of lines of the data D1. In this example in which the data D1 is four lines, F1 (0), F1 (1), F1 (2, F1 (3) are set as the first flag F1 in the four cells indicated by the four read pointers RP, respectively. The SRAM controller 55 includes L cells (four cells in this example) read by the reading unit 64 and the first flag F1 (K) (where K is 0, 1, 2,... L−1). Are associated with each other and output to the output buffer 56.

  The rotation unit 50 includes an output buffer 56, a second address controller 57, and an output interface (hereinafter referred to as “output I / F 58”) as an output system. In the present embodiment, the second address controller 57 and the output I / F 58 constitute an example of a writing unit.

  The second address controller 57 generates the write address AW0 of the cell to be stored as part of the head image data HD in the second storage unit 35c of the main memory 35. That is, the write address AW0 for writing the L cells read from the SRAM 80 to the second storage unit 35c of the main memory 35 is generated.

  Further, the second address controller 57 includes a determination unit 66 that determines whether or not a misalignment is made based on the write address AW0. Here, the misalignment means that the writing position is not continuous with the previous writing position and it is necessary to write with a space between them, and if it is written as it is, it is written at a position that should be vacated. The second address controller 57 determines that it is not misaligned if the lower 3 bits of the write address AW0 are “000” (binary number), and sets a value other than “000”, that is, any one of the lower 3 bits. If “1” exists, it is determined as misalignment.

  The second address controller 57 includes a second flag generation unit 67 that generates a second flag F2. The second flag generation unit 67 generates the second flag F2 for use in misalignment processing for rearranging the cells in an appropriate arrangement order when the arrangement order of the cells (pixels) read from the SRAM 80 is inappropriate. . The second flag F2 is also a mask flag similar to the first flag F1, and takes a flag value of “0” not masking and “1” masking. The second flag generation unit 67 generates a second flag F2 having a value “0”. The second address controller 57 sends the write address AW0, the second flag F2, and the misalignment determination result to the output I / F 58. The determination unit 66 may be provided in the output I / F 58 to determine whether or not the determination unit 66 in the output I / F 58 is a miss line based on the write address AW0 from the second address controller 57. .

  The output I / F 58 includes an address generation unit 68 that generates a write address AW1 based on the write address AW0, a shift processing unit 69 that shifts cells to change the cell arrangement order for misalignment processing, and a first A third flag generation unit 70 that generates a third flag F3 using the flag F1 and the second flag F2 is provided.

  The shift processing unit 69 performs shift processing for shifting the cells together with the flags F1 and F2 in order to change the cell arrangement order for misalignment processing. The third flag generation unit 70 changes the second flag F2 corresponding to the pixel other than the target pixel shifted by the shift process from “0” to “1”, the first flag F1 and the changed second flag The third flag F3 is generated by performing a logical sum operation (OR operation) for calculating a logical sum with the flag F2. Here, the third flag F3 is a mask flag similar to the first flag F1 and the second flag F2, and takes a flag value of “0” for not masking and “1” for masking.

  The output I / F 58 requests the memory controller 34 to perform a burst write in which the write address AW1 is designated and the data D2 is written by burst transfer. At this time, a burst write request is made for the data D2 with the third flag F3.

  When the memory controller 34 shown in FIG. 4 receives the burst write request, the memory controller 34 burst-transfers the data D2, and writes the data D2 to the designated write address AW1 in the second storage unit 35c of the main memory 35. Is provided. The write transfer unit 82 allows writing (overwriting) for pixel data for which the third flag F3 attached to the data D2 is “0”, and masks pixel data for which the third flag F3 is “1”. A mask processing unit 82A that prohibits the writing (overwriting) is provided.

Next, a rotation process performed by the rotation unit 50 using the SRAM 80 will be described.
If the raster size R is set as an offset amount offset, in the present example in which the value is 20 bytes, the offset is “0x14” in hexadecimal.

  Here, in the example shown in FIG. 5A, the row direction size of the first storage unit 35b is set to C · B (Byte), which is a natural number multiple of the burst size B, and one print image. When the raster size R of the data PD is divided by the burst size B, it is a value that can form a surplus pixel. In this case, N (N = 6 in this example) pixel data “1-1”, “2-1”, “3-1”, and “6-1” in the first column of the print image data PD shown in FIG. In the state stored in the first storage unit 35b of the main memory 35, it is shifted backward by 2 (4 bytes) every time one line is advanced. Therefore, the pixels “1-1”, “2-1”, “3-1”... “6-1” belonging to the same column have the same position in the four pixels in each data D1 to which the burst size B is transferred. Don't be. Therefore, as in the prior art, vertical / horizontal conversion cannot be performed by simply rotating a 4 × 4 square block including four consecutive pixels belonging to the same column with an SRAM. The rotation unit 50 of this example uses the overwriting prohibition function in units of pixels (cells) of the memory controller 34, and does not add dummy data to the print image data PD as in the prior art, and also converts the vertical and horizontal directions. The print image data PD is converted into the head image data HD while avoiding frequent memory accesses that cause a reduction in processing efficiency. Note that the number of remaining pixels that does not satisfy the burst size B may be a value other than two. Of course, the vertical / horizontal conversion device 45 of this example can also perform vertical / horizontal conversion on the print image data PD with the remaining number of pixels of “0”.

  The SRAM 80 prepares for 16 bytes × 8 lines × 2 planes in consideration of the burst size B and the burst transfer count J. If generalized, the storage size that can store the number of lines that is a natural number Q times the burst size B in the row direction and that is a natural number S times the natural number S of the burst transfer times J is set as one, and two are prepared.

  The first address controller 51 obtains the read address AR0 as follows. As shown in FIG. 6, the storage position of the first pixel of the print image data PD, that is, the pixel data of the first row (one line) and first column (one raster) is set as the start address ADst (first address). Further, a value (offset amount) by which a line (row) is offset to the next line is set as “offset”. This offset amount offset is equal to the raster size R. These pieces of information are set in the first address controller 51 by the CPU 31. The first address controller 51 calculates the leading address AD0 of the nth line in the print image data PD by the following formula.

AR0 = ADst + offset * (n−1) (1)
Here, the start address ADst is a leading address where the print image data PD is stored in the first storage unit 35b, and is an arbitrary address. In this example, the start address ADst is set to “0x0000” in order to simplify the description.

  The first address controller 51 generates the read address AR0 based on the above equation (1). This read address AR0 is the pixel data of the first column of the print image data PD in the main memory 35, that is, “1-1” “2-1” “3-1” “4-1” “5-1” “ This is an address indicating the position of “6-1”. The pixel data “1-1”, “2-1”, “3-1”, “4-1”, “5-1”, and “6-1” in the first column are vertically and horizontally converted so as to be arranged in the row direction. In order to select the pixel data at the head of these lines, the first address controller 51 generates a read address AR0. That is, the first address controller 51 obtains the address at which the line head pixel data is located as the read address AR0 so that the data D1 of the burst size B (for four pixels) including the line head pixel is selected as the transfer target. .

  The read address AR0 generated by the first address controller 51 is merely the address of the pixel at the beginning of the line (pixel in the first column), and this is not necessarily the data D1 (FIG. 5A) in which the line head pixel is necessarily burst transferred. Since it is not the first pixel of the data surrounded by the broken line frame, it does not necessarily match the first address of the data D1. The first address controller 51 sends the generated read address AR0 to the input I / F 52.

  The input I / F 52 calculates the read address AR1 by masking the lower 3 bits of the read address AR0 received from the first address controller 51. The read address AR1 indicates the head address of the data D1 of the burst size B surrounded by a broken line in the print image data PD in FIG. That is, the read address AR1 is generated by masking the lower m bits of the read address AR0 using the index m when the burst size B is expressed by 2 to the power of m. Here, the value obtained by masking the lower 3 bits of the read address AR0 indicates the head address of the burst size data D1 (dashed area in FIG. 5A) to which the pixel data belongs, and the lower 3 bits indicate the data D1. This indicates how many bytes the target pixel is located from the head address when the head address of is the reference (0). Then, the input I / F 52 designates the read address AR1 to the memory controller 34 and makes a burst read request for requesting burst transfer of data D1 from the main memory 35. Further, the input I / F 52 passes the read address AR 0 received from the first address controller 51 to the pointer controller 54.

  When the read transfer unit 81 of the memory controller 34 receives a burst read request together with the read address AR1 from the input I / F 52, it reads the data D1 for the burst size B from the read address AR1 of the main memory 35 and bursts it to the input I / F 52. Forward. The input I / F 52 stores the input data D1 transferred from the memory controller 34 in the input buffer 53 together with the read address AR0.

  On the other hand, in the pointer controller 54, the first pointer generator 61 generates a write pointer WP, and the second pointer generator 62 generates a read pointer RP. The write pointer WP is a pointer that indicates a write position (write address) of the data D1 to the SRAM 80. The first pointer generator 61 shifts the write pointer WP to the next writing position advanced by the burst size B (4 pixels) every time a 4 × 4 pixel square block (data D1 for 4 lines) is written. Let On the other hand, the read pointer RP is a pointer that indicates the relative position (number of bytes from the start address) of the pixel data to be read out from the data D1 stored in the SRAM 80 with reference to the start address. The second pointer generator 62 uses the lower m bits (lower 3 bits in this example) of the read address AR0 as the value of the read pointer RP.

Next, the operation of the vertical / horizontal conversion device 45 will be described with reference to the drawings.
First, referring to FIG. 7 and FIG. 8, burst read (burst transfer) of data D1 in burst size B and burst read data D1 from print image data PD stored in the first storage unit 35b of the main memory 35 are used. A process of writing to the SRAM 80 will be described.

  Print image data PD is stored in the first storage unit 35b of the main memory 35 in the state shown in FIG. The CPU 31 gives the start address ADst and the offset amount offset (= raster size R) to the vertical / horizontal conversion device 45. The first address controller 51 uses the start address ADst and the offset amount offset (= R) to calculate the read address AR0 = ADst + offset * (n−1) (n is a line number) based on the equation (1). Ask.

  In FIG. 7A, the pixel data “1-1” and “2-” for the first four lines among the pixels belonging to the first column of the print image data PD (six shaded pixels in FIG. 7). For the read addresses AR0 of “1”, “3-1”, and “4-1”, ADst (0x0000), ADst + offset (0x0014), ADst + offset * 2 (0x0028), and ADst + offset * 3 (0x003C) are obtained, respectively. The input I / F 52 instructs the memory controller 34 with the read address AR1 obtained by masking the lower 3 bits of the read address AR0. That is, the read address AR1 is designated to the memory controller 34 as “0x0000”, “0x0010”, “0x0028”, “0x0038” (hexadecimal number). As a result, four data D1 corresponding to the burst size B surrounded by the broken line frame in FIG. 7A is burst read from the designated read address AR1 to the rotation unit 50 in order.

  Before and after this, the pointer controller 54 obtains the initial value of the write pointer WP of the SRAM 80 and obtains the lower 3 bits as the initial value of the read pointer RP of the SRAM 80 based on the read address AR0. Send to. In FIG. 7B, the respective data D1 are arranged in order from the upper row at the position indicated by the write pointer WP indicated by the downward bold arrow (in the order of row addresses “+0000”, “+0010”, “+0020”, “+0030”). Write to. In FIG. 7B, the slanted thick arrow is the position of the lead pointer RP. The four read pointers RP indicated by the lower 3 bits of the four read addresses AR0 are the positions of the pixels “1-1”, “2-1”, “3-1”, and “4-1” in the first column in each data D1. Pointing. That is, RP1 = 0x0, RP2 = 0x4, RP3 = 0x0, and RP4 = 0x4 are set as the read pointer RP in order from the upper row in each data D1.

  Further, the SRAM controller 55 adds a first flag F1 to each data D1 for each pixel constituting the data D1. If the cell is pixel data belonging to the valid line of the print image data PD, the first flag F1 is assigned “0” indicating that it is not masked. If the cell does not belong to the valid line, the first flag F1 is masked “ 1 "is attached. In the example of FIG. 7B, since all the four data D1 have four pixels, each data D1 has a first flag F1 (0 = 0) for each pixel constituting the data D1 in order from the upper row. 0, F1 (1 = 0, F1 (2 = 0, F1 (3 = 0). That is, the data D1 of the row address “+0000” has a first flag F1 (0 = 0 added to each pixel). The first flag F 1 (1 = 0 is assigned to each pixel in the data D1 at the row address “+0010”, and the first flag F1 (2 = 2 = to each pixel in the data D1 at the row address “+0020”. In addition, the first flag F1 (3 = 0 is assigned to each pixel in the data D1 of the row address “+0030”, and the SRAM 80 has the write pointer WP in the first burst read. A square block of 4 × 4 pixels shown in Fig. 7 (b) is stored at the position indicated by the write pointer W. P shifts from the writing position “+0” indicated by the bold arrow in FIG. 7B to the writing position “+8” indicated by the two-dot chain line arrow in FIG.

  Next, the second burst read is performed. In FIG. 8A, the read address AR0 is calculated by adding “8” for the burst size B to the read address AR0 of the pixel that is the target of the first burst read of the print image data PD. That is, ADst + 8 (0x0008), ADst + offset + 8 (0x001C), ADst + offset * 2 + 8 (0x0030), and ADst + offset * 3 + 8 (0x0044) are obtained, respectively. The input I / F 52 instructs the memory controller 34 to read address AR1 in which the lower 3 bits of the read address AR0 are masked. In other words, the read address AR1 is instructed to the memory controller 34 as “0x0008”, “0x0018”, “0x0030”, “0x0040” (hexadecimal number). As a result, four data D1 corresponding to the burst size B surrounded by a broken line frame in FIG. 8A is burst read from the designated read address AR1 to the rotation unit 50 in order.

  Then, each data D1 burst-read for the second time is written in order from the upper row at the write position “+8” (row addresses “+0000” “+0010”), as indicated by the dashed frame in FIG. 8B. In the order of “+0020” and “+0030”).

  Further, the SRAM controller 55 adds a first flag F1 to each data D1 for each pixel constituting the data D1. In the example of FIG. 8B, since all the four data D1 have four pixels, each data D1 has a first flag F1 (1) for each pixel constituting the data D1 in order from the upper row. = 0, F1 (2) = 0, F1 (3) = 0, and F1 (4) = 0. That is, the first flag F1 (1) = 0 is assigned to each pixel in the data D1 at the row address “+0000”, and the first flag F1 (2) is assigned to each pixel in the data D1 at the row address “+0010”. = 0, the data D1 at the row address “+0020” is assigned a first flag F1 (3) = 0 to each pixel, and the data D1 at the row address “+0030” is assigned a first value to each pixel. Flag F1 (4) = 0 is attached. Thus, by the second burst read, the square block of 4 × 4 pixels shown in FIG. 8B is stored in the SRAM 80 at the position indicated by the write pointer WP. When the writing of each data D1 to the SRAM 80 is completed, the write pointer WP moves from the writing position “+8” indicated by the bold arrow in FIG. 8B to the writing position “+0” indicated by the two-dot chain line arrow in FIG. Shift to.

  Note that when the first to fourth lines of the print image data PD are read, the number of lines to be read is a multiple of 4, so the first flag F1 remains reset (= 0). However, when the fifth line and the sixth line, which will be described later, are read, the number of lines to be read is not a multiple of 4, and the odd line becomes dummy data, and the first flag F1 is set (= 1). In other words, if the number of lines to be read is not a multiple of J (J = 4 in this example), which is the number of burst transfers performed in one burst read request, the odd lines other than the lines to be transferred are dummy data. The first flag F1 for masking the dummy data cell is set to a valid value “1”.

  Next, a process in which the reading unit 64 of the SRAM controller 55 reads data from the SRAM 80 will be described with reference to FIG. As shown in FIG. 9A, the reading unit 64 reads the pixel data pointed to by the read pointers RP <b> 1 to RP <b> 4 and transfers it to the output buffer 56. That is, in the first reading shown in FIG. 9A, the pixel data “1-1”, “2-1”, “3-1”, and “4-1” are read and transferred to the output buffer 56. After reading out the pixel data, the read pointer RP is counted up. As a result, the read pointer RP advances by one to the position shown in FIG.

  In the second reading shown in FIG. 9B, the pixel data indicated by the read pointers RP 1 to RP 4 is read and transferred to the output buffer 56. That is, pixel data “1-2”, “2-2”, “3-2”, and “4-2” are read and transferred to the output buffer 56. After reading out the pixel data, the read pointer RP is counted up. As a result, the read pointer RP advances by one to the position shown in FIG. As shown in FIG. 9C, when the read pointer RP of any line catches up with the write pointer WP, reading is temporarily stopped. Thereafter, when data is loaded from the main memory 35 and the write pointer WP advances, the reading of the pixel data by the reading unit 64 is resumed.

  As shown in FIG. 10A, when the data D1 transferred from the main memory 35 is written in the write position indicated by the write pointer WP at that time in the SRAM 80, the write pointer WP advances. When the write pointer WP advances, reading of pixel data from the SRAM 80 is resumed. Then, as illustrated in FIG. 10A, the reading unit 64 reads the pixel data pointed to by the read pointers RP <b> 1 to RP <b> 4 and transfers it to the output buffer 56. That is, pixel data “1-3”, “2-3”, “3-3”, and “4-3” are read and transferred to the output buffer 56. In this way, while advancing the read pointer RP of each line, the process of reading the pixel data pointed to by the read pointer RP is repeated until all the pixel data for four lines are processed.

  For example, as shown in FIG. 10B, pixel data “1-1”, “2-1”, “3-1”, and “4-1” are read out by the first reading by the reading process up to FIG. The pixel data “1-2”, “2-2”, “3-2”, and “4-2” are read out in the second reading, and the pixel data “1-3” and “4-2” are read out in the third reading. 2-3, 3-3, and 4-3 are read out. The first flag F1 (0) to F1 (3) is added to each pixel data for each read data. Since the first line to the fourth line, the first flags F1 (0) to F1 (3) at this time have a value “0” indicating that they are not masked.

  The read data D2 for every four pixels by the SRAM controller 55 is stored in the output buffer 56 together with the first flags F1 (0) to F1 (3) corresponding to each pixel. The output I / F 58 inputs the read data D2 from the output buffer 56 together with the first flags F1 (0) to F1 (3).

  The second address controller 57 generates a write address AW0 when writing the data D2 to the second storage unit 35c of the main memory 35. The second address controller 57 is given a start address ADst (first address) and an offset amount OFS when writing data D2 from the CPU 31 to the second storage unit 35c. The second address controller 57 calculates the next write address AW0 by setting the first write address AW0 as the start address ADst and adding the offset amount OFS to the current write address AW0 in the second and subsequent times. Here, the offset amount OFS is given by the number of processing lines × 2. In this example, since the number of nozzles is “6”, the number of processing lines is “6”, and “0x000C” twice that is the offset amount OFS (= 0x000C).

  In the second address controller 57, the determination unit 66 determines whether the misalignment is made based on the write address AW0. The determination unit 66 determines that there is no misalignment when all the lower m bits of the write address AW0 are “0”, and determines that there is a misalignment when “1” exists in any of the lower m bits. For example, in the case of the first read data D2 (= pixel data of “1-1”, “2-1”, “3-1”, “4-1”) in FIG. 10B, the write address AW0 = 0x0000 and its lower order Since the 3 bits are “000”, the determination unit 66 determines that there is no misalignment. The second address controller 57 sends the write address AW0, the second flag F2, and the misalignment determination result to the output I / F 58.

  The address generation unit 68 of the output I / F 58 masks the lower 3 bits of the write address AW0 to generate the write address AW1. At this time, since the write address AW0 = 0x0000, the write address AW1 = 0x0000 is obtained. Then, in the output I / F 58, the third flag generation unit 70 causes the first flags F1 (0) to F1 (3) (= “0000”) and the second flags F2 (0) to F2 (3) (= “ 0000 ") is performed to generate the third flags F3 (0) to F3 (3) (=" 0000 "). At this time, since the misalignment result is not a misalignment, the shift processing by the shift processing unit 69 is not performed.

  The output I / F 58 requests the memory controller 34 to write the data D2 with the third flags F3 (0) to F3 (3) by designating the write address AW1. As a result, as shown in FIG. 11, the first read data D2 (= pixel data of “1-1”, “2-1”, “3-1”, “4-1”) is started in the second storage unit 35c. It is written at address ADst. When misalignment does not occur in this way, the data D2 is burst-transferred in the pixel reading order from the SRAM 80 and written to the write address AW1 of the second storage unit 35c.

  The process for writing the second and subsequent read data D2 is performed as follows. The second address controller 57 obtains the next write address AW0 by adding the offset amount OFS to the current read address AR0. Therefore, when writing the read data D2 for the second time, the read address AR0 = ADst + OFS = “0x000C” is obtained. Further, the determination unit 66 determines that the write address AW0 (= “0x000C”) is “100” (binary number) and “1” exists in any of the bits, so that it is misaligned. In case of misalignment, burst write processing is performed in two steps.

  First, when it is determined as misalignment, the second flag generation unit 67 prevents the pixel data other than the pixel data to be written to the next write address AW1 of the second storage unit 35c from being overwritten at this time. ) To F2 (3). At this time, the second flags F2 (0) to F2 (3) are generated in the no-mask state (value “0”). The second address controller 57 sends the write address AW0, the second flags F2 (0) to F2 (3), and the misalignment determination result to the output I / F 58.

  Hereinafter, the misalignment process will be described with reference to FIGS. In the misalignment process, burst write process (write process) is performed in two steps. First, the first writing process of the misalignment process will be described with reference to FIG.

  As shown in FIG. 12A, the output I / F 58 receives the second read data D2 with the first flags F1 (0) to F1 (3) input from the output buffer 56 from the second address controller 57. The second flags F2 (0) to F2 (3) are attached. The current write address AW0 is “0x000C”. The address generator 68 masks the lower 3 bits of the write address AW0 = 0x000C to generate the write address AW1 = 0x0008.

  In the output I / F 58, when the misalignment determination result is a misalignment, the shift processing unit 69 performs a shift process. The shift processing unit 69 performs a shift process for shifting the four pixel data constituting the data D2 using the lower m bits of the write address AW0 as a shift value. As shown in FIG. 12B, shift processing is performed using the lower 3 bits of the write address AW0 as a shift value. Since the write address AW0 is “0x000C” and the lower 3 bits thereof are “100” (= 4 bytes), the shift processing unit 69, as shown in FIG. Is shifted rightward in FIG. 12B by the amount of 4 bytes (2 pixels) (the rear side in the order of reading pixel data from the SRAM 80). At this time, the pixel data “3-2” and “4-2” shifted out to the right are shifted in from the left. As a result of the shift processing, the pixel data “1-2”, “2-2”, “3-2”, and “4-2” are converted into pixel data “3-2” and “4-2” as shown in FIG. It will be in the order of “1-2” and “2-2”. Along with the pixel data shift process, the third flag generation unit 70 also performs the shift process on the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3). The first flags F1 (0) to F1 (3) are all “0” even after the shift. On the other hand, the second flags F2 (0) to F2 (3) are shifted in with the shifted second flags F2 (2) and F2 (3) as “1” (mask) (FIG. 12C). reference). When the second flag F2 is shifted in, the third flag generation unit 70 performs a process of changing from “0” (without mask) to “1” (with mask).

  Further, the third flag generation unit 70 performs a logical OR operation (OR operation) between the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3) after the shift process. As a result of this logical sum operation, as shown in FIG. 12C, third flags F3 (0) to F3 (3) (= “1100”) are generated. Then, the output I / F 58 designates the write address AW1 (= 0x0008) to the memory controller 34 and performs burst write of the data D2 after the shift with the third flags F3 (0) to F3 (3). Request. When receiving the burst write request, the write transfer unit 82 of the memory controller 34 causes the mask processing unit 82A to perform mask processing when writing the shifted data D2 to the write address AW1. The mask processing unit 82A masks the pixel data “3-2” and “4-2” whose third flag F3 is “1”, and the pixel data “1-2” whose third flag F3 is “0”. Do not mask “2-2”. For this reason, as shown in FIG. 12D, the pixel data “3-2” and “4-2” are not overwritten in the write address AW1 of the second storage unit 35c (in FIG. dqm ”) and pixel data“ 1-2 ”and“ 2-2 ”are overwritten. As a result, the pixel data “1-2” and “2-2” are written in the correct positions 2 pixels apart from the pixel data “4-1” (that is, pixels “5-1” and “6-1”). It is.

  Next, the second writing process of the misalignment process will be described with reference to FIG. The second address controller 57 adds the burst size B (= “0x0008”) to the write address AW0 = 0x000C for the first misalignment process to generate the second write address AW0 = 0x0014 for the misalignment process. The address generation unit 68 masks the lower 3 bits “100” (binary number) of the current write address AW0 = 0x0014 to generate the write address AW1 = 0x0010.

  In the second misalignment process, as shown in FIG. 13A, the second read data D2 after the shift and the first flags F1 (0) to F1 (3) after the shift are used, and the second flag F2 is used. (0) to F2 (3) bit-invert the second flag F2 (0) to F2 (3) for the first misalignment process to “0011”. Then, the third flag generation unit 70 performs a logical sum operation (OR operation) of the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3). As a result of this logical sum operation, as shown in FIG. 13B, third flags F3 (0) to F3 (3) (= “0011”) are generated. Then, the output I / F 58 designates the write address AW1 (= 0x0010) to the memory controller 34 and requests burst write of the data D2 with the third flags F3 (0) to F3 (3). . When receiving the burst write request, the write transfer unit 82 of the memory controller 34 causes the mask processing unit 82A to perform mask processing when writing the data D2 to the write address AW1. The mask processing unit 82A does not mask the pixel data “3-2” and “4-2” in which the third flag F3 is “0”, and the pixel data “1-2” in which the third flag F3 is “1”. Mask “2-2”. For this reason, as shown in FIG. 13C, the pixel data “3-2” and “4-2” are overwritten in the write address AW1 of the second storage unit 35c, and the pixel data “1-2” “2” -2 "is not overwritten (shown as" dqm "in FIG. 13C).

  Then, the same processing is repeated for the third and subsequent read data D2. When the writing process of the data D2 of the first line to the fourth line is finished, the pixel data in the data D2 is converted into the second storage unit 35c of the main memory 35 as shown in FIG. If written in the appropriate location.

  Next, processing when the number of remaining lines is not a multiple of 4, that is, in the example shown in FIG. 14, when the number of remaining lines is two lines from the fifth line to the sixth line surrounded by a broken line frame will be described. First, a process of reading data D1 from the first storage unit 35b of the main memory 35 (burst read) and a process of reading image data from the SRAM 80 will be described.

  In the first storage unit 35b shown in FIG. 15A, each data D1 surrounded by a broken line frame including the target pixels “5-1” and “6-1” is read. At this time, the first address controller 51 obtains the read address AR0 = ADst + offset * 4 (= 0x0050) and AR0 = ADst + offset * 5 (= 0x0064). The address generation unit 60 of the input I / F 52 calculates the read addresses AR1 = 0x0050 and 0x0060 by masking the lower 3 bits of the read address AR0. The input I / F 52 requests the memory controller 34 to perform a burst read by designating the read address AR1. The read transfer unit 81 of the memory controller 34 sequentially reads the data D1 from the designated read address AR1 of the first storage unit 35b of the main memory 35, and burst-transfers it to the rotation unit 50. The input I / F 52 stores the data D1 burst-transferred from the memory controller 34 in the input buffer 53.

  Then, the first pointer generator 61 of the pointer controller 54 generates a write pointer WP that points to the write position of the data D1 to the SRAM 80. The writing unit 63 of the SRAM controller 55 writes the data D1 at the writing position indicated by the write pointer WP.

  The second pointer generator 62 of the pointer controller 54 generates the lower 3 bits of the read address AR0 as the initial value of the read pointer RP of the SRAM 80. However, the initial value of the read pointer RP is set to “0x0” at a location where no pixel data exists in the first storage unit 35b. Therefore, the initial values of the read pointer RP are calculated as RP1 = 0x0, RP2 = 0x4, RP3 = 0x0, RP4 = 0x0. Then, the SRAM controller 55 reads data D1 for the burst size B (4 pixels) from the reading position indicated by the read pointer RP.

  The first flag generator 65 of the SRAM controller 55 attaches the first flag F1 to each data D1 for each pixel constituting the data D1. If the cell is pixel data belonging to the valid line of the print image data PD, the first flag F1 is assigned “0” indicating that it is not masked. If the cell does not belong to the valid line, the first flag F1 is masked “ 1 "is attached. In the example of FIG. 15B, the first two data D1 of the four data D1 all have four pixels, but the lower two data are indefinite in which no pixel data exists in each cell, so each data D1 , In order from the upper row, the first flag F1 (0 = 0, F1 (1 = 0, F1 (2 = 1, F1 (3 = 1) is assigned to each pixel constituting each. The first flag F1 (0 = 0 is assigned to each pixel in the data D1 at the row address “+0000”, and the first flag F1 (1 = 0 is assigned to each pixel in the data D1 at the row address “+0010”. Then, the first flag F1 (2 = 1 is assigned to each cell in the data D1 at the row address “+0020”, and the first flag F1 (3 = 3 = to each cell in the data D1 at the row address “+0030”. 1 is attached.

  In this way, for the 5th to 6th lines where the remaining number of lines is not a multiple of 4, similarly to the 1st to 4th lines, the data D1 is written to the SRAM 80 and the data D2 is read. Since only the effective line is executed, the data for the pre-processing remains indefinite in the SRAM 80 for the ineffective line. In addition, the first flag F1 of the invalid line is “1” (mask valid).

  Then, in the first reading from the SRAM 80, the pixel data pointed to by the read pointer RP shown in FIG. In this first reading, as shown in FIG. 15C, pixel data (cell) “5-1”, “6-1”, “indefinite”, and “indefinite” are read out. At this time, the first flags F1 (0) to F1 (3) are assigned “0011” to each cell.

  When the writing of each data D1 to the SRAM 80 is completed, the write pointer WP is shifted, and the data D1 is written at the next writing position pointed to by the write pointer WP. As a result, data D1 is written in the SRAM 80 in the state shown in FIG. The SRAM controller 55 reads the data indicated by the read pointer RP while the read pointer RP is advanced (while counting up) in parallel with the writing process of the data D1 by the writing unit 63 to the write position indicated by the write pointer WP. Data D2 is read by the reading unit 64 that reads pixel data from the position.

  As a result of the reading process of the data D2, as shown in FIG. 16B, the cells “5-1”, “6-1”, “undefined”, and “undefined” are read by the first reading, 1 flag F1 (0) = 0, F1 (1) = 0, F1 (2) = 1, F1 (3) = 1 is added. In the second reading, cells “5-2”, “6-2”, “undefined”, and “undefined” are read, and the first flags F1 (0) = 0, F1 (1) = 0, F1 are read in the respective cells. (2) = 1 and F1 (3) = 1 are added. Furthermore, the cells “5-3”, “6-3”, “indeterminate”, and “indeterminate” are read out in the third reading, and the first flag F1 (0) = 0, F1 (1) = 0, F1 is read in each cell. (2) = 1 and F1 (3) = 1 are added. Each read data D2 is transferred to the output buffer 56 in the read order. The output I / F 58 sequentially reads the data D2 with the first flags F1 (0) to F1 (3) from the output buffer 56. The output I / F 58 receives the write address AW0 and the second flags F2 (0) to F2 (3) from the second address controller 57.

  Next, storing (writing) the read data D2 of the fifth to sixth lines in the second storage unit 35c of the main memory 35 will be described with reference to FIGS. First, the process of writing the first read data D2 of the 5th to 6th lines to the second storage unit 35c will be described with reference to FIG. The write address AW0 is calculated by AW0 = ADst + ((current line number ÷ 4) × 8). As shown in FIG. 17A, in the case of the first read data D2, since the write address AW0 = ADst + 8 = 0x0008, the lower 3 bits are “000” (binary number), and it is determined not to be misaligned. . Therefore, the second flag F2 (0) to F2 (3) is assigned with the value “0” (no mask) to each cell of the first read data D2. Since it is not a misalignment, no shift processing is performed. The third flag generation unit 70 performs a logical sum operation (OR operation) of the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3) to obtain the third flag F3 ( 0) to F3 (3) are obtained. Then, the third flag F3 (0) = 0, F3 (1) = 0, F3 (2) = 1, F3 (3) = 1 is assigned to each cell of the data D2.

  Then, burst write is requested by designating the write address AW1 = 0x0008 masking the lower 3 bits of the read address AR0. As a result, the data D2 is written to the write address AW1 by the memory controller 34 as shown by the broken line frame in FIG. At this time, since the cells corresponding to the third flags F3 (2) = 1 and F3 (3) = 1 are masked, the pixel data “1-2” and “2-2” remain without being overwritten.

  Next, the second address controller 57 calculates the next write address AW0 by adding the offset amount OFS to the current write address AW0. The next write address AW0 is obtained as AW0 = 0x0008 + OFS (= 0x0C) = 0x0014.

  As shown in FIG. 18, when the second read data D2 is written, since the current write address AW0 = 0x0014, the lower 3 bits are “1 00” (binary number), and it is determined to be misaligned. In the case of misalignment processing, burst write processing (write processing) is performed in two steps.

  First, in the first misalignment process, the second flag generation unit 67 generates the second flags F2 (0) to F2 (3) in order to prevent overwriting of pixel data other than the pixel data to be written to the current write address AW1. To do. At this time, the second flags F2 (0) to F2 (3) are generated in the no-mask state (value “0”). The write address AW0 and the second flags F2 (0) to F2 (3) are sent from the second address controller 57 to the output I / F 58.

  As shown in FIG. 18A, the output I / F 58 receives the second read data D2 with the first flags F1 (0) to F1 (3) input from the output buffer 56 from the second address controller 57. The second flags F2 (0) to F2 (3) are attached. The current write address AW0 is “0x0014”. The address generation unit 68 masks the lower 3 bits of the write address AW0 = 0x0014 to generate the write address AW1 = 0x0010.

  In the output I / F 58, when it is determined that the line is misaligned, the shift processing unit 69 performs a shift process. That is, as shown in FIG. 18B, the shift processing unit 69 performs shift processing for shifting the four pixel data constituting the data D2 using the lower 3 bits of the write address AW0 as a shift value. Since the write address AW0 is “0x0014”, the lower 3 bits are “100” (= 4 bytes). Therefore, the shift processing unit 69 shifts the four pixel data constituting the data D2 by 4 bytes (2 pixels) as shown in FIG. At this time, the cells “indefinite” and “indefinite” shifted out to the right in the figure are shifted in from the left. As a result of the shift processing, the pixel data “5-2”, “6-2”, “indefinite”, and “indefinite” are converted into pixel data “indefinite”, “indefinite”, “5-2”, “6- 2 ”in order. As the pixel data is shifted, the third flag generator 70 also shifts the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3). The first flags F1 (0) to F1 (3) are F1 (0) = 1, F1 (1) = 1, F1 (2) = 0, and F1 (3) = 0 after the shift. On the other hand, in the second flags F2 (0) to F2 (3), the shifted-in second flags F2 (2) and F2 (3) become “1” (mask valid) (see FIG. 18B). .

  Further, the third flag generation unit 70 performs a logical sum operation (OR operation) between the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3). As a result of this logical sum operation, third flags F3 (0) to F3 (3) (= “1100”) are generated. Then, the output I / F 58 designates the write address AW1 (= 0x0010) to the memory controller 34 and performs burst write of the data D2 after the shift with the third flags F3 (0) to F3 (3). Request. When receiving the burst write request, the write transfer unit 82 of the memory controller 34 writes the shifted data D2 to the write address AW1 (= 0x0010) as shown in FIG. At this time, the mask processing unit 82A masks the cells “indefinite” and “indefinite” with the third flags F3 (0) = 1 and F3 (1) = 1, so that the pixel data “3-2” “4-2” "Remains without being overwritten.

  Next, the second writing process of the misalignment process will be described with reference to FIG. The second address controller 57 adds the burst size B (= “0x0008”) to the first write address AW0 = 0x0014 in the misalignment process to generate the second write address AW0 = 0x001C in the misalignment process. The address generation unit 68 masks the lower 3 bits “100” (binary number) of the current write address AW0 = 0x001C to generate the write address AW1 = 0x0018.

  In the second misalignment process, as shown in FIG. 19A, the data D2 after the shift of the second read data and the same first flags F1 (0) to F1 (3) as the first time are used. Two flags F2 (0) to F2 (3) bit-invert the second flags F2 (0) to F2 (3) for the first misalignment process to “0011”. Then, the third flag generation unit 70 performs a logical sum operation (OR operation) of the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3). As a result of this OR operation, as shown in FIG. 19B, the third flags F3 (0) = 1, F3 (1) = 1, F3 (2) = 1, and F3 (3) = 1 are generated. The Then, the output I / F 58 designates the write address AW1 (= 0x0018) to the memory controller 34 and requests burst write of the data D2 with the third flags F3 (0) to F3 (3). . When receiving the burst write request, the write transfer unit 82 of the memory controller 34 causes the mask processing unit 82A to perform mask writing when writing the data D2 to the write address AW1. The mask processing unit 82A masks the cells “indefinite”, “indefinite”, “5-2”, and “6-2” in which the third flag F3 is “1”. For this reason, the pixel data “1-3”, “2-3”, “3-3”, and “4-3” indicated by the broken line frame in FIG.

  Then, by repeating the same process for the third and subsequent read data D2, the rotation process is advanced while performing the alignment process by burst transfer. By the writing process of the data D2 on the fifth to sixth lines, the pixel data indicated by hatching in FIG. 19D is written in the second storage unit 35c of the main memory 35. Thus, the head image data HD obtained by vertically and horizontally converting the print image data PD stored in the first storage unit 35b is stored in the second storage unit 35c.

As described above in detail, according to the present embodiment, the following effects can be obtained.
(1) The data D2 is read by selecting pixel data pointed to by the read pointer RP from the data D1 written in the SRAM 80. As a result, burst transfer can be performed efficiently without adding dummy data, even with print image data PD having extra pixels. Therefore, the used capacity of the first storage unit 35b necessary for storing the print image data PD and the used capacity of the second storage unit 35c required for storing the head image data HD can be reduced. Therefore, the used capacity of the main memory 35 can be saved, and the storage area that can be used for storing other data can be increased. At this time, the memory access at the time of burst transfer does not become frequent, so that the processing speed of the vertical / horizontal conversion processing does not need to be reduced so much.

  (2) When the exponent when the burst size B (byte) is expressed as a power of 2 is m (where m is a natural number), the lower m bits (lower 3 bits in this example) of the read address AR0 of the pixel of interest The read address AR1 is generated by masking. Therefore, it is possible to burst transfer appropriate data D1 from the first storage unit 35b to the rotation unit 50 by designating an appropriate read address AR1.

  (3) Since the lower m bits (lower 3 bits in this example) of the read address AR0 are set as the initial value of the read pointer RP, appropriate pixel data is selected from the data D1 stored in the SRAM 80, and the appropriate data D2 Can be read out.

  (4) Since the determination unit 66 determines whether or not the misalignment processing is performed, it is possible to write the appropriate data D2 to the second storage unit 35c separately for the case where the misalignment is not performed and the case where the misalignment is performed. it can.

  (5) Since the write address AW1 is obtained by masking the lower m bits (lower 3 bits in this example) of the write address AW0, the data D2 can be written to an appropriate write position in the second storage unit 35c.

(6) The first flags F1 (0) to F1 (3) are generated, and if the cells constituting the data D2 are pixels belonging to the valid line of the print image data PD, “0” (mask invalid) is added. If the cell is not a valid line and is indefinite, "1" (mask valid) is added. Therefore, if a burst write request for directly writing the data D2 that is not misaligned is made, the data D2 can be written at an appropriate writing position in the second storage unit 35c.
(7) At the time of misalignment processing, it is possible to avoid overwriting necessary pixel data by an inappropriate cell by performing writing processing of data D2 in two steps.

  (8) In the misalignment process when the determination unit 66 determines that the line is misaligned, the pixels (cells) constituting the data D2 are shifted using the lower m bits (lower 3 bits) of the write address AW0 as a shift value. Can be changed to data D2 existing at an appropriate position. For example, when it is necessary to provide a space for securing the writing position of another pixel, the data D2 is stored in the second storage unit 35c by shifting the pixels in the data D2 by the shift process and changing the arrangement order. When writing, it is possible to write a pixel with a writing position of another pixel.

  (9) In the misalignment process, the third flag generation unit 70 sets the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3) along with the cell shift process. The second flag F2 shifted and shifted in is changed to “1”. Therefore, the third flag generation unit 70 performs an OR operation (OR operation) on the first flags F1 (0) to F1 (3) and the second flags F2 (0) to F2 (3), so that The third flags F3 (0) to F3 (3) can be generated.

  (10) Since burst write of the data D2 is requested with the third flags F3 (0) to F3 (3), the necessary pixel data previously written in the second storage unit 35c is overwritten by unnecessary cells. It can be avoided.

  (11) In the second misalignment process, the data D2 after the first shift is used, the first flag F1 is set to the same value as the first, and the second flag F2 is bit-inverted from the first value. The third flag F3 is generated by performing an OR operation on the first flag F1 and the second flag F2. Therefore, in the second burst write process, the pixel masked at the first write position can be written at the second write position.

  (12) Since the vertical / horizontal conversion device 45 is provided in the multi-function device 11 having the printer unit 14 in which the print head 29 ejects ink droplets onto the paper conveyed by the driving of the transport motor 28 to form an image, The storage area of the main memory 35 can be effectively used while suppressing a reduction in burst transfer rate.

In addition, the said embodiment can also be changed into the following forms.
The transfer unit (processing unit) is not limited to 4 × 4 pixels, and may be units of 8 × 8 pixels, 16 × 16 pixels, 32 × 32 pixels, and 64 × 64 pixels, for example. The transfer unit is not limited to a square block of A × A pixels, but may be a rectangular block of A × D pixels (A ≠ D). That is, an appropriate transfer unit can be set as long as vertical / horizontal conversion processing (rotation processing) is possible.

  The transfer method of the first and second transfer means is not limited to the burst transfer method. Other transfer methods used in direct memory access transfer (DMA transfer) can also be adopted. For example, a cycle steal transfer method or a demand transfer method may be employed. Further, different transfer methods may be adopted for the first transfer means and the second transfer means.

-The address generation method may be changed as appropriate. In short, as long as the method can generate the target address, the address may be generated by an operation using another arithmetic expression.
The print image data PD and the head image data HD are not limited to being stored in the same main memory 35 (for example, DRAM), but may be stored in different DRAMs.

  The rotation unit 50 is not limited to a hardware configuration, and may include a software portion as a part thereof and may be configured by cooperation of hardware and software. Furthermore, although the processing speed is somewhat reduced, it may be configured by software.

  In the above-described embodiment, as an example of the recording apparatus, a multifunction machine including the ink jet printer unit 14 is employed. However, a fluid ejecting apparatus that ejects or discharges fluid other than ink is employed. May be. Further, the present invention can be used for various liquid ejecting apparatuses including a liquid ejecting head that ejects a minute amount of liquid droplets. In this case, the droplet refers to the state of the liquid ejected from the liquid ejecting apparatus, and includes liquid droplets having a granular shape, a tear shape, and a thread shape. The liquid here may be any material that can be ejected by the liquid ejecting apparatus. For example, it may be in a state in which the substance is in a liquid phase, such as a liquid with high or low viscosity, sol, gel water, other inorganic solvents, organic solvents, solutions, liquid resins, liquid metals (metal melts ) And liquids as one state of the substance, as well as those obtained by dissolving, dispersing or mixing particles of a functional material made of solid materials such as pigments and metal particles in a solvent. Further, representative examples of the liquid include ink and liquid crystal as described in the above embodiment. Here, the ink includes general water-based inks and oil-based inks, and various liquid compositions such as gel inks and hot-melt inks. As a specific example of the liquid ejecting apparatus, for example, a liquid containing a material such as an electrode material or a coloring material used for manufacturing a liquid crystal display, an EL (electroluminescence) display, a surface emitting display, a color filter, or the like in a dispersed or dissolved state. A liquid ejecting apparatus for ejecting can be given. Further, it may be a liquid ejecting apparatus that ejects a bio-organic matter used for biochip manufacture, a liquid ejecting apparatus that ejects a liquid as a sample that is used as a precision pipette, a printing apparatus, a microdispenser, or the like. In addition, transparent resin liquids such as UV curable resin to form liquid injection devices that pinpoint lubricant oil onto precision machines such as watches and cameras, and micro hemispherical lenses (optical lenses) used in optical communication elements. A liquid ejecting apparatus that ejects a liquid onto the substrate or a liquid ejecting apparatus that ejects an etching solution such as an acid or an alkali to etch the substrate may be employed. The present invention can be applied to any one of these liquid ejecting apparatuses. Further, the fluid may be a granular material such as toner. In addition, the fluid referred to in this specification does not include a fluid consisting only of a gas.

  A multi-function device is used as an example of a recording device, but the recording device may be a printer that does not have a scanner function. The recording device is not limited to the ink jet recording method, and may be a wire impact recording device, a thermal transfer recording device, an electrophotographic recording device, or the like. Further, these recording apparatuses may adopt a monochrome recording apparatus.

  -The image data processing apparatus is not limited to application to a printer. The present invention can be widely applied to information processing apparatuses that perform vertical / horizontal conversion processing (rotation processing) of image data. An image data processing device may be employed in, for example, a scanner device, a digital camera, a projector, a digital photo frame, or the like as long as the image data is subjected to vertical / horizontal conversion processing (rotation processing).

  DESCRIPTION OF SYMBOLS 11 ... The multifunctional machine which is an example of a recording device, 14 ... Printer part, 28 ... The conveyance motor which is an example of a conveyance means, 29 ... The print head as a fluid ejection head which is an example of a recording means, 34 ... Memory controller, 35 ... Main memory as an example of storage means, 35b: a first storage unit as an example of the first storage means, 35c: a second storage unit as an example of the second storage means, 45 ... vertical / horizontal conversion device, 50 ... rotation unit, 51... First address controller constituting an example of first transfer means, 52... Input I / F constituting an example of first transfer means, 54... Pointer controller, 55... SRAM controller, 57. 58 ... Output I / F constituting an example of the second transfer means and an example of the write adjusting means, 60 ... Address generating unit 61... First pointer generating unit, 62... Second pointer generating unit, 63... Writing unit as an example of writing means, 64... Reading unit as an example of reading means, 65. A certain first flag generation unit, 66 ... a determination unit that is an example of a determination unit, 67 ... a second flag generation unit that is an example of a second flag generation unit, 68 ... an address generation unit, 69 ... a write adjustment unit and a correction unit And a shift processing unit that is an example of a shift processing unit, 70... A third flag generation unit that is an example of a third flag generation unit and 80. SRAM, 81..., A read transfer unit as an example of a first transfer unit, 82... A write transfer unit as an example of a second transfer unit, 82 A... Processing means Example mask processing unit, PD... Print image data as an example of first image data, HD... Head image data as an example of second image data, D1... Data as an example of first data, D2. Data as an example of data, B ... Burst size as an example of transfer size, R ... Raster size, AR0 ... Read address, AR1 ... Read address, AW0 ... Write address, AW1 ... Write address, F1 ... First flag, F2 ... second flag, F3 ... third flag, m ... index, P ... paper as an example of a recording medium.

Claims (8)

An image data processing device for generating first image data by converting the first image data into vertical and horizontal directions,
First storage means for storing first image data;
Memory,
Second storage means for storing second image data;
Transferring said first data transfer size selected a plurality of pixels arranged in a row including at least one target pixel first image data or, et al., By the transfer size from the sequentially changed by the first storing means the pixel of interest a first rolling feed means that stores in the memory and,
The transfer second data size that selects a plurality of pixels including at least one of said target pixel from the group of pre-Symbol first data stored in said memory, said transfer size from the memory sequentially changing the target pixel Are transferred to the second storage means one by one , and the pixel of interest in the second data is arranged at a position in the second storage means arranged at a position that matches the pixel arrangement order of the second image data in the second storage means. includes a second rolling feed means for writing, a,
Said second transfer means, when the second data is an unsuitable misalignment is the arrangement order of the pixels, and correcting means for correcting the order of arrangement of the pixels of the second data is the misalignment, before Symbol second If the data contains unwanted pixels other than the target pixel, the image data processing apparatus being characterized in that and a write adjustment means for inhibiting writing to said second storage means of the required pixel. Said second transfer hand stage, the transfer size B bytes (where B is a natural number), the index when expressed the B to a power of 2 m (where m is a natural number) when a, before Symbol target pixel 2. The image data processing apparatus according to claim 1, wherein the pixel of interest is read out from the memory using the position of the lower m bits of the address as a read address. The correction means includes
First flag generation means for generating a first flag that is attached to each pixel data and takes one of a mask valid value and a mask invalid value;
Second flag generating means for generating a second flag that is attached to each pixel data and takes one of a mask valid value and a mask invalid value;
Shift processing means for shifting the pixels constituting the second data to change the arrangement order of the pixels;
The first flag and the second flag are shifted with the shift of the pixel, and the second flag corresponding to an unnecessary pixel other than the target pixel is changed to a mask effective value, and then the first flag after the shift is performed. And a third flag generating means for generating a third flag by performing an OR operation on the second flag and
The second rolling feed means is configured to transfer the second data in the second storage means prior SL with a third flag for each pixel,
The write adjustment means, said third flag is provided with a masking means for inhibiting the writing of picture element corresponding if the corresponding write picture element, mask valid value if the value of the invalid mask The image data processing apparatus according to claim 1, wherein the image data processing apparatus is an image data processing apparatus. Read address to instruct to read the pre-Symbol first data from said first storing hand stage with respect to the first rolling feed means masks the lower m bits of the read address of the pixel of interest of the first data image data processing apparatus according to any one of claims 1 to 3, wherein the specifying Te. Said second transfer hand stage of the group of the first data stored in said memory, and characterized in that by selecting the position of the pixel indicated by the lower m bits of the read address reading the second data The image data processing apparatus according to claim 4 . Write address for indicating the second data to the second rolling feed means to be written into said second storage means, masks the lower m bits of the write address of the pixel of interest among the second data image data processing apparatus according to any one of claims 1 to 5, wherein the specifying Te. The image data processing device according to any one of claims 1 to 6 ,
Recording means for performing recording based on the second image data obtained by vertically and horizontally converting the first image data by the image data processing device;
A recording apparatus comprising: An image data processing method for generating first image data by subjecting first image data to vertical and horizontal conversion,
The by the first data transfer size selected a plurality of pixels arranged in a row including one target pixel even without least first image data or et stored in the first storing means, sequentially changing the target pixel 1 a first transfer step of storing in memory and transferred from the storage means by the transfer size,
The transfer second data size that selects a plurality of pixels including at least one of said target pixel from the group of pre-Symbol first data stored in said memory, said transfer size from the memory sequentially changing the target pixel Are transferred to the second storage means one by one, and the pixel of interest in the second data is written at a position in the second storage means arranged at a position that matches the pixel arrangement order of the second image data in the second storage means. a step feeding second rolling includes a
The second transfer step includes
When the second data is a misalignment in which the pixel arrangement order is inappropriate, a correction step of correcting the pixel arrangement order of the second data that is the misalignment;
If the previous SL second data includes unnecessary pixels other than the target pixel, and the second write to that write adjustment step prohibits to the storage means of the unnecessary pixel,
An image data processing method comprising:

Images