JP2011182106A - Image data processor, recorder, and image data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image data processor, a recorder and an image data processing method, capable of reducing a used storage area of image data in a storage without reducing transfer rate when the image data is transferred for every processing unit so much. <P>SOLUTION: Print image data PD is stored in a DRAM. The print image data PD is stored so that line remainder data Dr less than four pixels of transfer unit is settled in an array range (burst raster size BR) of full data Df whose 4×4 pixel area (thick line frame area in a drawing) of the transfer unit is filled with pixels following the tail of the line remainder data Dc in the line direction (horizontal direction in a drawing). This image data processor includes an address generation section which generates an address readable in the array order of the data when the data constituting the print image data PD is read for rotation processing. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image data processing apparatus, a recording apparatus, and an image data processing method for processing image data with data transfer in units of processing between a storage unit and a processing unit.

  For example, Patent Documents 1 and 2 disclose a recording apparatus (fluid ejecting apparatus) including a print head that ejects ink. For example, the image data read by the scanner unit is subjected to a plurality of processing such as binarization processing (halftone processing), color conversion processing from RGB color system to CMYK color system, interlace processing, vertical / horizontal conversion processing (rotation processing), etc. Processing is performed, and the print head is driven based on the head control data generated through these processing. At this time, in each processing, the image data before processing is transferred from the buffer to the processing unit for each processing unit, and the data of the processing unit processed by the processing unit is sequentially transferred to the buffer. For this data transfer, burst transfer capable of high-speed processing is employed (for example, Patent Documents 1 and 2).

  For example, in vertical / horizontal conversion processing (rotation processing), image data whose pixel arrangement order is in the line direction (horizontal direction) should be set as the pixel arrangement order in the raster direction (vertical direction) corresponding to the nozzle arrangement of the print head. Processing for switching the vertical direction and the horizontal direction of the image data is performed by the rotating unit. In this case, data in units of processing from the buffer is transferred in bursts to the rotation unit, and the data after vertical / horizontal conversion (rotation) is sequentially burst transferred from the rotation unit to the buffer.

  FIG. 10A shows image data (print image data) before the rotation process, and FIG. 10B shows image data (head image data) after the rotation process. In FIG. 10A, the pixels constituting the print image data before the rotation process are arranged in a matrix of N rows × M columns. Normally, the image data at the time of the rotation processing has a number of pixels of about several hundred rows × several hundred columns. However, in order to simplify the description in FIG. 10, an example of image data having six pixels × 10 columns will be described. Here, the symbol “NM” of the pixel indicates the pixel data of the Nth row and the Mth column.

  In the rotation process, print image data stored in the DRAM 100 is burst-transferred to the rotation unit in the order indicated by bold numbers in the figure, for example, in each square area (square block) data of 4 × 4 pixels. Then, the rotation unit performs rotation processing (vertical / horizontal conversion processing) on the transferred data, burst-transfers the rotated data to the DRAM 100, and stores the data at the positions indicated by bold numerals in FIG. 10B. Thus, the head image data subjected to vertical / horizontal conversion in the DRAM 100 is generated.

  By the way, in the burst transfer method, when transferring data of a square block (4 × 4 pixels) in a rotation processing unit surrounded by a thick line frame in FIG. 10, one row (4 pixels) having a burst size (16 bits × 4) is transferred. Transfer 4 times each. Then, the square blocks are read in the order of bold numbers “1”, “2”,... “6” shown in FIG.

JP 2004-122594 A JP 2008-221769 A

  Incidentally, as shown in FIG. 10, the data of the bold numbers “1” and “2” are full data in which the area of the bold frame is filled with 4 × 4 pixel data. However, the data of the bold numbers “3” and “6” is the remainder data whose pixel data is less than 4 pixels of the burst size in the row direction, and the bold numbers “4”, “5”, and “6”. The data is the column remainder data in which the pixel data is less than the number of transfers “4” (4 pixels) in the column direction. For this reason, dummy data indicated by hatching in FIG. 10A is prepared as the surplus data, and the burst data can be burst-transferred with the surplus data secured. In this case, there is a method of avoiding dummy data transfer by changing the burst transfer designation method only when the number of pixels is less than four pixels. However, the designation method becomes complicated, and the transfer rate is rather slow.

  For this reason, when performing high-speed transfer by the burst transfer method, it is necessary to store dummy data, and an extra storage area for dummy data is required. Therefore, a DRAM 100 having a large data storage area (storage capacity) is prepared. Or the storage area of other data in the DRAM 100 is compressed. For this reason, there has been a demand for reducing dummy data as much as possible. Further, the head image data is generated by storing the data after the rotation processing in the DRAM 100 at the positions indicated by the bold numerals in FIG. 10B, but as shown in FIG. Therefore, an extra storage area of the DRAM 100 is required for the dummy data, and the above-described problem occurs in the same manner.

  The present invention has been made in view of the above problems, and one of its purposes is to reduce the use storage area of image data in the storage means without significantly reducing the transfer speed when transferring image data for each processing unit. An object of the present invention is to provide an image data processing device, a recording device, and an image data processing method that can be suppressed.

  In order to solve the above-mentioned problems, the present invention (first invention) is an image data processing apparatus for processing image data, a storage means for storing the image data, and a process for processing the image data And transfer means for transferring the image data from the storage means to the processing means for each processing unit, wherein the processing means sequentially processes the data transferred from the storage means for each processing unit. In the storage means, the image data is stored in a matrix arrangement of X rows and Y columns in which X × Y full data, one of which is filled in the processing unit, and in the row direction If there is a remainder data less than the processing unit, the remainder data will fit within the full data Y column array width following the end of the data arranged within the full data Y column array width. The transfer unit is configured to transfer the data from the storage unit to the processing unit in the original order before the alignment in the image data.

  According to the present invention, the image data before processing is stored in the storage means so that the margin data fits within the full data Y column array width following the end of the data within the full data Y column array width. Therefore, it is possible to reduce the use storage area of the image data before processing in the storage means. Therefore, it is possible to suppress the use storage area of the image data in the storage means without reducing the transfer speed when transferring the image data for each processing unit.

  The present invention (second invention) is an image data processing device for processing image data, and processing means for reading the image data in units of processing and processing the data, and processing the processed image data Storage means for storing, and transfer means for sequentially transferring the processed unit data subjected to the processing from the processing means to the storage means and storing the processed image data in the storage means, The transfer means arranges the processed image data in a matrix of Y rows × X columns, with Y × X full data, one of which is filled in the processing unit, with respect to the storage means. In addition, when there is line remainder data that is less than the processing unit in the row direction, the line remainder data is added to the end of the data arranged within the full data X column arrangement width, and the full data X column arrangement To fit within the width The gist is to align and store.

  According to the present invention, the processed image data is stored in the storage means so that the margin data fits within the full data X column array width following the end of the data within the full data X column array width. Therefore, the use storage area of the processed image data in the storage means can be reduced. Therefore, it is possible to suppress the use storage area of the image data in the storage means without reducing the transfer speed when transferring the image data for each processing unit.

  The present invention is an image data processing apparatus for processing image data, a storage means for storing image data before processing, a processing means for processing image data, and the image data before processing. The processing unit transfers data from the processing unit to the processing unit, and the processing unit sequentially processes the data transferred by the processing unit to generate the processed data from the processing unit. Transfer means for causing the storage means to store the image data subjected to the processing by sequentially transferring to the means, wherein the image data is stored in the processing unit X × When Y full data is stored in a matrix arrangement of X rows × Y columns, and there is remaining data that is less than the processing unit in the row direction, the remaining data is The arrangement is such that the data arranged in the full data Y column array width is aligned and stored so as to fit within the full data Y column array width, and the transfer means is configured to perform the processing from the storage means. The data is transferred to the means in the original order before the alignment in the image data, and the data of the processing unit subjected to the processing is sequentially transferred from the processing means to the storage means and processed to the storage means Transfer means for storing the image data, and the transfer means stores the processed image data in the storage means with Y × X full data, one of which is filled in the processing unit. When there is a remainder data, the remainder data is arranged after the end of the data arranged within the full data X column arrangement width. Data X column array The gist is to arrange and store so as to fit within the width.

  According to this invention, since both configurations of the first invention and the second invention are provided, the use storage area of the image data before processing in the storage means can be reduced, and the image data after processing can be reduced. The storage area used can be reduced. Therefore, it is possible to suppress the use storage area of the image data in the storage means without reducing the transfer speed when transferring the image data for each processing unit.

  In the image data processing apparatus of the present invention, the processing means is a rotation processing means for performing a rotation process on the image data, and the transfer means includes K × K pixels having the same number of pixels in the row direction and the column direction. However, the gist is to burst transfer the data of the square block of K ≧ 2). According to the present invention, the data transfer of the square block (K × K pixels) can be performed by burst transfer. Therefore, the storage means uses the data storage area while performing the rotation process performed for each data of K × K pixels at high speed. Can be reduced.

  In the image data processing apparatus of the present invention, the transfer unit generates a read address when reading and transferring data from the storage unit, or generates a write address when writing the transferred data to the storage unit. The gist of the present invention is that it further comprises an address generation means.

According to this invention, the transfer means can transfer the data constituting the image data in the original arrangement order by designating the address generated by the address generation means and instructing the transfer.
In the image data processing apparatus of the present invention, the address generation means includes a determination means for determining whether or not the data to be transferred is a remainder data, and a first address when the data is other than the remainder data. The gist is to generate an address according to the generation arithmetic expression, and to generate an address according to the second address generation arithmetic expression when the data is margin data.

  According to the present invention, the address generating means generates an address according to the first or second address generation arithmetic expression corresponding to each depending on whether or not the data to be transferred is margin data. The image data can be transferred in the original arrangement order by designating the transfer by designating the address generated by the address generation means.

  The present invention includes the image data processing apparatus according to the invention, a conveying unit that conveys a medium, and a recording unit that forms an image on a medium conveyed by the conveying unit, and the recording unit performs processing by the processing unit. The gist is that it is controlled based on the applied image data.

According to the recording apparatus of the present invention, it is possible to obtain the same effects as the invention according to the image data processing apparatus.
The present invention is an image data processing method for processing image data, wherein in the storage means, X × Y full data, one of which is filled with the processing unit, is X rows × Y columns. And when there is less than the remaining data in the processing unit in the row direction, the remaining data is continued from the end of the data arranged within the full data Y column arrangement width. A transfer step of aligning and storing the data so as to be within the full data Y column array width, and transferring the image data from the storage means to the processing means for each piece of processing unit; and the processing means includes the storage A processing step for sequentially processing the data transferred from the means in units of the processing units. In the transferring step, the data is transferred from the storage means in the original order before the alignment. Transfer to the processing means. According to the present invention, it is possible to obtain the same effects as those of the image processing apparatus according to the first invention.

  The present invention is an image data processing method for processing image data, the processing step of reading the image data in units of processing and processing the data by the processing means, and the processing subjected to the processing A transfer step in which the transfer means sequentially transfers the unit image data from the processing means to the storage means to store the processed image data in the storage means. In the transfer step, the transfer means includes 1 When Y × X full data, each of which is filled with the processing unit, is arranged in a matrix of Y rows × X columns, and there is remaining data that is less than the processing unit in the row direction, The gist is that the remaining data is aligned and stored so as to fit within the full data X column arrangement width following the end of the data arranged within the full data X column arrangement width. According to the present invention, it is possible to obtain the same effect as the image processing apparatus according to the second invention.

1 is a perspective view of a multifunction machine according to an embodiment. FIG. 2 is a schematic bottom view of a print head. FIG. 2 is a block diagram illustrating an electrical configuration of the multifunction machine. The block diagram which shows the electrical structure which concerns on a vertical / horizontal conversion process. (A) Print image data storage structure, (b) Schematic diagram for explaining the head image data storage structure. (A) Print image data storage structure, (b) Schematic diagram showing the head image data storage structure. The schematic diagram explaining the address generation method of a source side. The schematic diagram explaining the address generation method on the destination side. The schematic diagram explaining the rotation process in SRAM. (A) (b) The schematic diagram which shows the data storage structure at the time of the rotation process in a prior art.

  Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS. FIG. 1 is a perspective view of a multifunction machine 11 which is a printing apparatus having a scanner function. A multifunction machine 11 as a fluid ejecting apparatus as an example of a recording unit includes a main body 12 and a cover 13. The lower part of the main body 12 is a printer unit 14, and the upper part is a scanner unit 15. The printer unit 14 employs, for example, an ink jet recording method. An operation panel 17 is provided on the upper front portion of the main body 12. A paper discharge unit 18 for discharging the printed paper P is provided at the lower front side of the main body 12. A card slot 20 into which the memory card 19 can be inserted and removed is provided at the upper right position in FIG.

  As shown in FIG. 1, the operation panel 17 is provided with a display unit 21 (for example, a liquid crystal display) at the center in the width direction. The operation panel 17 is also provided with a power button 22, a mode selection button 23, a start button 24 for starting printing / scanning, a stop button 25 for stopping an operation being executed, and the like. By operating the mode selection button 23, one of five modes including “memory card”, “copy”, “scan”, and the like can be selected, and printing of a photo or the like based on image data read from the memory card 19 can be performed. Copy printing, document scanning, etc. can be performed.

  FIG. 3 is a block diagram showing an electrical configuration of the multifunction machine 11. The multifunction machine 11 includes a control device 30 that controls the overall control. The control device 30 drives and controls the printer unit 14 and the scanner unit 15. The control device 30 drives and controls a carriage motor 27 that constitutes the printer unit 14, a conveyance motor 28 that constitutes a conveyance unit, and a print head 29 that constitutes a fluid ejection head that is an example of a recording unit. Printing on paper P (medium) is performed.

  The control device 30 includes a CPU 31 (central processing unit), an ASIC 32 (Application Specific IC), a ROM 33, a memory controller 34, a DRAM 35 (Dynamic Random Access Memory), and a motor drive circuit 36. As the DRAM 35, SDRAM (Synchronous DRAM), DDR SDRAM (Double-Data-Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, etc. are used. Etc. can be used.

  The ROM 33 stores programs, setting data necessary for various controls, and the like. The CPU 31 drives and controls the carriage motor 27 and the carry motor 28 by executing a program (for example, a firmware program) read from the ROM 33 and giving commands and command values to the motor drive circuit 36. Thereby, the conveyance control of the paper in the printer unit 14 and the carriage control for moving the carriage (not shown) including the print head 29 in the main scanning direction are performed.

  The multifunction machine 11 also includes a communication interface (hereinafter referred to as “communication I / F 37”). For example, the communication I / F 37 receives print data transferred from a host device (such as a personal computer) (not shown). A CPU 31, ASIC 32, ROM 33, memory controller 34, DRAM 35 and motor drive circuit 36 constituting the control device 30 are connected to the bus 38 connected to the communication I / F 37, and a scanner input circuit 41 and a memory card are inserted. The output circuit 42 and the operation panel 17 are connected.

  The scanner unit 15 optically reads a document, and performs A / D conversion on a read signal (analog signal) from the line sensor 15a and outputs it as multi-gradation RGB image data (line data). D conversion circuit 15b. The scanner input circuit 41 performs inter-line correction processing and resolution conversion processing on the RGB image data input from the scanner unit 15 under the control of the CPU 31. The RGB image data subjected to these processes is input to the ASIC 32, and is compressed into JPEG image data by a compression circuit (not shown). The memory card input / output circuit 42 reads, for example, JPEG image data from the memory card 19 inserted in the slot 20.

  A part of the storage area of the DRAM 35 is used as a buffer for storing image data, and includes an input buffer 35a, an intermediate buffer 35b, and an output buffer 35c. The input buffer 35a stores print data received from the host device, JPEG image data via the scanner unit 15 and the memory card input / output circuit 42, and the like.

  The ASIC 32 performs image processing corresponding to the image data type on the image data (print data, JPEG image data, etc.) stored in the input buffer 35a, so that the JPEG decompression circuit 43, the image processing circuit 44, and the like shown in FIG. A vertical / horizontal conversion circuit 45 and a head control unit 46 are incorporated.

  The JPEG decompression circuit 43 decompresses (decompresses) the JPEG image data read from the input buffer 35a and develops it into RGB image data, and stores the decompressed RGB image data in the intermediate buffer 35b.

  The image processing circuit 44 performs known image processing including resolution conversion processing, color conversion processing, halftone processing, and the like on the RGB image data read from the intermediate buffer 35b. Here, the resolution conversion processing is processing for converting the resolution of the RGB image data from the display resolution to the printing resolution. The color conversion process is a process of converting RGB image data from RGB color system to CMYK image data of CMYK color system with reference to a color conversion table (not shown). The halftone process is a process of converting a gradation value (for example, 256 gradations) of pixels of CMYK image data into a gradation value for printing (for example, 2 gradations or 4 gradations). The intermediate buffer 35b includes three storage areas for storing the image data after completion of each of these image processes, and the final print image data (CMYK image data) after completion of all these image processes is stored in the intermediate buffer 35b. Stored in the final storage area.

  The vertical / horizontal conversion circuit 45 performs vertical / horizontal conversion processing on the print image data read from the intermediate buffer 35b. Vertical / horizontal conversion processing is a vertical direction (raster direction) in which the order of pixels of print image data is adjusted from the horizontal order (line direction) for display to the nozzle arrangement of the print head 29 (that is, the ink ejection order). ) In the order of arrangement. The head image data after the vertical / horizontal conversion processing is stored in the output buffer 35c (image buffer).

  The head control unit 46 converts the head image data stored in the output buffer 35 c into head control data that can be printed by the print head 29 (ejection control). The head control data is transferred from the head control unit 46 to the print head 29, for example, for one pass (one scan of the print head). The print head 29 includes a head drive circuit (not shown), and the head drive circuit performs ink ejection control based on the head control data.

  FIG. 2 shows the bottom surface (nozzle opening surface) of the print head. As shown in FIG. 2, the nozzle opening surface 29A of the print head 29 has a total of 180 nozzles # 1 to # 180 arranged at a constant nozzle pitch in the sub-scanning direction (vertical direction in FIG. 2). Four columns (four columns) are formed. In this example, each nozzle row includes 180 nozzles 29K, 29C, 29M, and 29Y, and is used to eject ink droplets of black (K), cyan (C), magenta (M), and yellow (Y). Is done.

  The print head 29 includes the same number of ejection drive elements 48 corresponding to the nozzles # 1 to # 180 shown in FIG. 2 as the nozzles (however, in FIG. ing). The ejection drive element 48 is composed of, for example, a piezoelectric vibration element or an electrostatic drive element. The print head 29 performs drive control of the ejection drive element 48 based on the head control data transferred from the head control unit 46 by a head drive circuit (not shown), and performs ejection control from the nozzles. Of course, the ejection driving element 48 may be a heater that heats the ink in the nozzle passage, or may be configured to eject ink droplets from the nozzles by utilizing expansion of bubbles generated by boiling in the ink heated by the heater.

  The print head 29 shown in FIG. 2 is fixed to a lower portion of a carriage (not shown) provided in the printer unit 14 so as to be movable in the main scanning direction (left and right direction in FIG. 2). By driving the carriage motor 27, the print head 29 is moved in the main scanning direction together with the carriage, and printing is performed on the paper P by ejecting ink droplets from the nozzles at intervals of one dot during the movement.

  FIG. 4 is a detailed configuration diagram of a portion related to the rotation process. As shown in FIG. 4, the vertical / horizontal conversion circuit 45 includes a rotation unit 50 connected to the bus 38 and an SRAM 70 connected to the rotation unit 50. The DRAM 35 includes the above-described intermediate buffer 35b and output buffer 35c (however, the input buffer 35a is omitted in FIG. 4). As shown in FIG. 4, the intermediate buffer 35b stores print image data PD before rotation processing by the rotation unit 50, and the output buffer 35c stores head image data HD after rotation processing by the rotation unit 50. It has become.

  The rotation unit 50 illustrated in FIG. 4 includes a DMA controller 51 as an example of a transfer unit and a rotation processing unit 52 as an example of a rotation unit. The DMA controller 51 controls the data transfer performed with the DRAM 35 by designating an address to the memory controller 34 and making a read (read) or write (write) request. Specifically, the DMA controller 51 designates the read address ADread from the DRAM 35 to the memory controller 34, and rotates the print image data PD from the DRAM 35 (more specifically, the intermediate buffer 35b) by data of a set size (processing unit). 50 has a first transfer function. In addition, the rotation processing unit 52 stores, in the SRAM 70, data that has been transferred to the rotation unit 50 among the print image data PD in the DRAM 35 by a set size (processing unit), and rotates the data stored in the SRAM 70 (vertically and horizontally). Conversion processing). Further, the DMA controller 51 designates the write address ADwrite to the DRAM 35 to the memory controller 34, and transfers the rotated data from the SRAM 70 to the DRAM 35 (specifically, the output buffer 35c) by a set size (processing unit). A second transfer function is provided.

  As shown in FIG. 4, the DMA controller 51 has a configuration register 53, a sequencer 54, a first counter 55, a second counter 56, a third counter as a configuration for realizing the first transfer function and the second transfer function. 57, a fourth counter 58, a first address generator 59, a second address generator 60, and a transfer instruction unit 61.

  The first address generator 59 generates a read address ADread when transferring the data before the rotation process from the DRAM 35 to the rotation unit 50. The second address generator 60 generates a write address ADwrite when transferring the rotated data from the SRAM 70 to the DRAM 35.

  Setting information regarding the print image data PD and the head image data HD is set in the setting register 53 by the CPU 31. The various setting information in the setting register 53 is used when the address generators 59 and 60 generate addresses. In the setting register 53, as setting information for burst transfer, a burst size BS (16 bits × 4 in this example) which is a data size per burst transfer and a transfer count T (4 times in this example) are stored. Are set by the CPU 31.

  The sequencer 54 manages the counting process of each counter 55-58. Each of the counters 55 to 58 counts which row / column of pixels in the print image data PD is the target pixel in the rotation processing target data. Each address generation unit 59, 60 generates each address ADread, ADwrite using the setting information of the setting register 53 and the count value of each counter 55-58. The first address generation unit 59 includes a determination unit 59a and a calculation unit 59b that are used to generate the read address ADread, and the second address generation unit 60 includes a determination unit 60a and a calculation unit 60b that are used to generate the write address ADwrite. In the present embodiment, a determination unit is configured by the determination units 59a and 60a.

  The transfer instruction unit 61 has a function of instructing data transfer between the rotation unit 50 and the DRAM 35. The transfer instruction unit 61 transfers the data from the DRAM 35 to the rotation unit 50 by designating the read address ADread generated by the first address generation unit 59 to the memory controller 34 and making a read request. Further, the transfer instruction unit 61 transfers the data from the rotation unit 50 to the DRAM 35 by designating the write address ADwrite generated by the second address generation unit 60 to the memory controller 34 and making a write request.

  On the other hand, the rotation processing unit 52 illustrated in FIG. 4 includes a rotation control unit 62 and a data register 63. The data transferred from the DRAM 35 to the rotation unit 50 is temporarily stored in the data register 63. When the rotation processing unit 52 accumulates data in units of rotation processing in the data register 63, the rotation processing unit 52 stores the data in the SRAM 70. The rotation control unit 62 reads the data from the SRAM 70 again, performs rotation processing (vertical / horizontal conversion processing), and writes the data in the SRAM 70 again, thereby rotating the data by 90 degrees. The SRAM 70 includes two storage areas for the rotation process, and the rotation control unit 62 advances the rotation process at high speed by alternately using the two storage areas.

  As shown in FIG. 4, print image data PD is stored in the intermediate buffer 35b in the DRAM 35 in a data storage structure in which data is arranged in the order indicated by bold numerals in the figure. This is because a DMA controller (transfer means) (not shown) in the image processing circuit 44 stores each data subjected to burst transfer in the intermediate buffer 35b of the DRAM 35 in the arrangement shown in FIG.

  The DMA controller 51 makes a read or write request to the memory controller 34 by designating the read address ADread and the data size (burst size BS). When the memory controller 34 receives a read request from the DMA controller 51, the memory controller 34 sequentially reads data of a specified data size from a specified read address ADread in the DRAM 35. The read data is transferred to the rotation unit 50 that is the read request source. In addition, when the memory controller 34 receives a write request from the DMA controller 51, the memory controller 34 sequentially writes the data transferred in burst from the rotation unit 50 to the designated write address ADwrite in the DRAM 35.

  FIG. 5 shows a data storage structure in the DRAM. FIG. 5A shows print image data before rotation processing, and FIG. 5B shows head image data after rotation processing. In order to simplify the description in FIG. 5, as in FIG. 10, image data having a pixel array of 6 rows × 10 columns is taken as an example.

  In FIG. 5A, the symbol “NM” of the pixel indicates the pixel data of the Mth column of the Nth row in the print image data PD, as in FIG. In FIG. 5A, the range of the thick line frame is one unit of the rotation process. In this one unit (processing unit), a square block of K × K pixels is set so that the number of pixels in the row and column is the same before and after the rotation processing. In the present embodiment, a square block of 4 × 4 pixels is set as an example. In this example, as shown in FIG. 5A, one pixel (one unit) is B bytes (B = 16 bits in this example). The burst size BS for one burst transfer is 4 · B bytes for 4 pixel data. When transferring data of a square block (processing unit) surrounded by a thick line frame in FIG. 5, first, pixel data of 4 pixels (4 · B bytes) in the first row is burst transferred, followed by the second row and the third row. In the fourth and fourth rows, pixel data of 4 pixels (4 · B bytes) is sequentially transferred in bursts. In principle, burst transfer of “4 times” is performed for transfer in units of processing.

  In this embodiment, the data of the blocks of bold numbers “1” and “2” surrounded by a thick frame in FIG. 5A is a square block of 4 × 4 pixels, which is one transfer unit (processing unit). The full data Df is filled with pixel data. Also, in FIG. 5A, the data of the blocks of bold numbers “3” and “6” enclosed in a broken line frame on the right side is the remainder data that is less than 4 pixels of the burst size BS in the row direction. Further, in FIG. 5A, the data of the blocks of bold numbers “4” and “5” surrounded by the thick line frame is the column remainder data Dc which is less than 4 pixels corresponding to the transfer count “4 times” in the column direction. .

  Here, in FIG. 5A, the size of the print image data PD in the row direction (lateral direction in FIG. 5A) is “raster size R”, and the print image data PD in the column direction (FIG. 5A). The size in the (vertical direction) is defined as “line size L”. Further, the size of the range where the full data Df exists in the row direction is defined as “burst raster size BR”, and the size of the range where the full data Df exists in the column direction is defined as “burst line size BL”. Each size R, L, BR, BL is a value corresponding to the number of pixels.

  In this embodiment, the remainder data “3” and “6” surrounded by the broken line frame in FIG. 5A are stored in the DRAM 35 at the positions indicated by the arrows in FIG. That is, the row remainder data Dr of “3” and “6” is arranged after the end of the column remainder data Dc (pixel 6-8 in FIG. 5A), and the arrangement width of the full data Df (that is, the burst raster size BR). ) Are arranged so as to be within. That is, in the print image data PD, X · Y full data Df is arranged in a matrix of X rows and Y columns, and X row remainder data Dr is continued from the end of Y column remainder data Dc. Thus, the data is stored in the DRAM 35 in a state of being arranged so as to be within the Y column arrangement width (the arrangement width for the Y column) of the full data Df.

  On the other hand, as shown in FIG. 5B, in the head image data HD after the rotation processing, the data in the areas of the bold numbers “1” and “2” surrounded by the thick line frame are transferred in one transfer unit (process). A square block of 4 × 4 pixels, which is a unit, is full data Df filled with pixel data. In FIG. 5B, the data in the area of the bold numeral “3” surrounded by the thick frame is the column remainder data Dc that is less than 4 pixels corresponding to the transfer count “4 times” in the column direction. In addition, the data in the area of the bold numerals “4”, “5”, and “6” surrounded by the broken line frame on the right side in FIG. 5B is the remaining data that is less than 4 pixels of the burst size BS in the row direction. It has become. Note that the head image data HD shown in FIG. 5B is obtained by vertically and horizontally converting the print image data PD, so that the size in the row direction and the size in the column direction are reversed. That is, in the head image data HD, the size in the row direction (horizontal direction in FIG. 5B) is “line size L”, and the size in the column direction (vertical direction in FIG. 5B) is “raster size R”. " In the head image data HD, the size of the range where the full data Df exists in the row direction is “burst line size BL”, and the size of the range where the full data Df exists in the column direction is “burst raster size BR”.

  In this embodiment, the remainder data “4”, “5”, and “6” surrounded by the broken line frame in FIG. 5B are arranged in the DRAM 35 at the positions indicated by the arrows in FIG. That is, the row remainder data Dr of “4”, “5”, and “6” is the full data Df following the end of the column remainder data Dc of “3” (pixel 4-10 in FIG. 5B). They are arranged so as to be within the arrangement width (that is, burst line size BL). That is, in the head image data HD, Y · X full data Df is arranged in a matrix of Y rows and X columns, and Y row remainder data Dr is continued from the end of X column remainder data Dc. Thus, the data is stored in the DRAM 35 in such a state that the full data Df is arranged within the X column arrangement width (X column arrangement width).

  FIG. 6 shows a data storage structure of the print image data PD stored in the DRAM 35 in such a data arrangement and the head image data HD stored in the DRAM 35 after the rotation process. Since the print image data PD is stored in the DRAM 35 in an aligned state as shown in FIG. 6A, a large number (36 in the example of FIG. 10A) exists in the prior art of FIG. The number of dummy data is reduced. Further, the head image data HD after the rotation processing is stored in the DRAM 35 in an aligned state as shown in FIG. 6B, so that a large number (examples of FIG. 10B) are obtained in the prior art shown in FIG. 36) the number of existing dummy data can be reduced.

  Here, even if the print image data PD has the data storage structure shown in FIG. 6A, burst transfer is performed in the order of data “1” “2” “3” “4” “5” “6”. A first address generator 59 (see FIG. 4) is prepared so that a possible read address can be designated. Further, a second address generation unit 60 (see FIG. 4) is prepared so that the write address that can store the head image data HD after the rotation processing in the DRAM 35 with the data storage structure shown in FIG. .

  Next, an address generation method by the address generation units 59 and 60 will be described. The setting information set in the setting register 53 by the CPU 31 includes a raster size R, a line size L, a burst raster size BR, and a burst line size BL shown in FIG. These sizes R, L, BR, and BL are set separately for print image data PD and head image data HD. Further, the CPU 31 sets the base address Base Address of the print image data PD and the base address Base Address of the head image data HD in the setting register 53. Further, the CPU 31 sets the burst size BS (4 · B bytes in this example) and the transfer count T (4 times in this example) in the setting register 53 as burst transfer conditions.

  The first counter 55 counts, as the data position RP, the number of pixels (that is, which column) in the row direction (line direction) (the horizontal direction in FIG. 5A) from the base address Base Address. The data position RP counts 0, 1, 2, ..., BR, BR + 1, ..., R (where R≥BR).

  The second counter 56 counts, as the data position LP, the pixel position (that is, which row) in the column direction (raster direction) (vertical direction in FIG. 5A) from the base address Base Address. The second counter 56 adds “1” each time the data position RP reaches the raster size R (RP = R) after the first counter 55 finishes counting the raster size R corresponding to the number of pixels in one row. Is done. The data position LP counts 0, 1, 2,..., BL, BL + 1, ..., L (where L ≧ BL). Therefore, when the data position LP of the second counter 56 reaches the line size L (LP = L) and the data position RP of the first counter 55 reaches the raster size R (RP = R), the sequencer 54 prints the print image. It is determined that the rotation process (that is, the address generation process) has been completed for all the pixels of the data.

  The third counter 57 counts the number (number of columns) of the target pixel in the row direction (line direction) in the 4 × 4 pixel square block. The fourth counter 58 counts what number (that is, what row) the target pixel is in the column direction (raster direction) in the 4 × 4 pixel square block. When the third counter 57 counts “1”, “2”, “3”, “4” and finishes counting the four pixels in the first row in the square block, it is reset to the initial value “1”. The fourth counter 58 adds “1” to “2” indicating the second row. Next, when the third counter 57 finishes counting four pixels in the second row, the fourth counter 58 becomes “3”, and when the third counter 57 finishes counting four pixels in the third row, the fourth counter 58 becomes “4”, and finally the third counter 57 counts four pixels in the fourth row.

  The first counter 55 is the first column pixel in the next column block of the same row only after the third and fourth counters 57 and 58 have counted all the pixels in the square block of the first row and first column. The value is advanced to the data position RP (in this example, “5”). Further, the second counter 56 finishes counting the pixels in the last column block of the first row in FIG. 5A, and the third and fourth counters 57 and 58 finish counting the pixels of all the blocks of the first row. When the counting is completed, the value is advanced to the data position LP (in this example, “5”) indicating the pixel in the first row in the first column block of the next row. That is, the data position RP of the first counter 55 repeats “1, 2, 3, 4” four times in the first column block of each row and “5, 6, 7, 8” in the next column block of the same row. Is repeated four times, and “4 · (Y−1) + 1,4 · (Y−1) + 2,4 · (Y−1) +3” is obtained in the block of the same row and the Yth column (the last column of the full data Df). Repeat “4 • Y” four times. Then, “BR + 1, BR + 2,..., BR + r (= R)” is performed four times in the block of the (Y + 1) th column (the column of the remainder data in FIG. 5A and the bold numeral “3” in FIG. 5A). repeat. Here, r is the number of pixels in the row direction of the remainder data (r = R−BR), and 0 ≦ r <K (= 4).

  On the other hand, the second counter 56 counts “1, 2, 3, 4” once in each block from the first column to the (Y + 1) th column in the first row block, In the block, “5, 6, 7, 8” is counted once, and “4 · (X−1) + 1,4 · (X−) in the block of each column of the Xth row (the last row of the full data Df). 1) +2, 4 · (X−1) + 3,4 × X ”are counted once. Then, “BL + 1, BL + 2,..., BL + c (= L)” is counted once in each column block of the last (X + 1) th row (row of column remainder data Dc). However, c is the number of pixels in the column direction of the column remainder data (c = L−BL), and 0 ≦ c <K (= 4).

  Then, when the data position LP = L and the data position RP = R, the sequencer 54 determines that the transfer of all pixel data of the print image data PD has been completed. The block in the (Y + 1) th column indicates a block to which the remainder data Dr belongs, and the block in the (X + 1) th row indicates a block to which the column remainder data Dr belongs. Therefore, when there is no line remainder data Dr, the last column is the Yth column, and when there is no column remainder data Dc, the last row is the Xth column.

  Hereinafter, the address generation method will be described with reference to FIGS. FIG. 7 is an explanatory diagram of a source-side address generation method by the first address generator 59, and FIG. 8 is an explanatory diagram of a destination-side address generation method by the second address generator 60. First, a source-side address generation method by the first address generation unit 59 will be described with reference to FIG.

  Read when data position RP is less than burst raster size BR (RP ≦ BR) and within full data, and when data position RP exceeds burst raster size BR (RP> BR) and is within the remainder data Use different formulas for address generation.

When RP ≦ BR, the read address ADread of the pixel M−N of M rows and N columns of the print image data PD in the DRAM 35 is given by the following equation.
ADread = Base Address + (M−1) × BR × B + (N−1) × B (1)
Further, when RP> BR, the read address ADread of the pixel M-N of M rows and N columns of the print image data PD in the DRAM 35 is given by the following equation.
ADread = Base Address + (BR × L) + (M−1) × (R−BR) × B + (N−BR−1) × B (2)
The determination unit 59a of the first address generation unit 59 illustrated in FIG. 4 determines whether the data position RP is RP ≦ BR or RP> BR. The calculation unit 59b of the first address generation unit 59 is configured to set the set value Base Address of the setting register 53 based on one of the above formulas (1) and (2) according to the determination result of the determination unit 59a. The read address ADread is calculated using BR, L, B and the count values RP (= N) and LP (= M) of the first and second counters 55 and 56. However, the base address Base Address at this time is that of the print image data PD. Note that the numerical values M and N when the position of the pixel data to be transferred is represented by M rows and N columns in the print image data PD are given M (= LP) as the count value of the second counter 56, and the first counter N (= RP) is given as a count value of 55.

  The arithmetic unit 59b uses N and M of the data positions RP (= N) and LP (= M) counted by the first and second counters 55 and 56 when the third counter 57 is “1”. Thus, the read address ADread is calculated. Here, the time when the third counter 57 is “1” is the time when it indicates the position of the first pixel in the data for four pixels (burst size BS) to be subjected to one burst transfer. , M can be used to calculate the read address ADread for each burst transfer performed four times for each block. The expression (1) corresponds to the first address generation calculation expression, and the expression (2) corresponds to the second address generation calculation expression.

  The DMA controller (not shown) in the image processing circuit 44 includes an address generator (not shown) having the same configuration as that of the first address generator 59. This address generation unit (not shown) uses the formula (1) or (2) according to the determination result of the determination unit by the built-in determination unit and calculation unit in the same manner as the first address generation unit 59. To calculate the write address. Then, by sequentially writing each burst data burst-transferred to the calculated write address in the DRAM 35, the print image data PD is stored in the data storage structure shown in FIG.

Next, a destination-side address generation method by the second address generation unit 60 will be described with reference to FIG.
Write when data position LP is less than burst line size BL (LP ≦ BL) and within full data, and when data position LP exceeds burst line size BL (RP> BR) and within remainder data Use different formulas for address generation.

When LP ≦ BL, the write address ADwrite to the DRAM 35 of the pixel data DM-N of M rows and N columns of the head image data HD is given by the following equation.
ADwrite = Base Address + (N−1) × BL × B + (M−1) × B (3)
When LP> BL, a write address ADwrite to the DRAM 35 of the pixel data DM-N of M rows and N columns of the head image data HD is given by the following equation.
ADwrite = Base Address + (BR × R) + (N−1) × (L−BL) × B + (M−BL−1) × B (4)
The determination unit 60a of the second address generation unit 60 illustrated in FIG. 4 determines whether the data position LP is LP ≦ BL or LP> BL. The calculation unit 60b of the second address generation unit 60 is based on one of the above formulas (3) and (4) according to the determination result of the determination unit 60a, and the set value Base Address, The write address ADwrite is calculated using BL, R, B and the count values RP (= M), LP (= N) of the first and second counters 55, 56. However, the base address Base Address at this time is that of the head image data HD. The numerical values M and N when the position of the pixel data to be transferred is represented by M rows and N columns in the head image data HD are given M (= RP) as the count value of the first counter 55, and the second counter N (= LP) is given as a count value of 56.

  The arithmetic unit 60b uses N and M of the data positions RP (= N) and LP (= M) counted by the first and second counters 55 and 56 when the fourth counter 58 is “1”. The write address ADwrite is calculated. Here, the time when the fourth counter 58 is “1” means that the position of the first pixel in the data of four pixels (burst size BS) to be subjected to one burst transfer is indicated. , M can be used to calculate the write address ADwrite for each burst transfer performed four times for each block. The expression (3) corresponds to the first address generation arithmetic expression, and the expression (4) corresponds to the second address generation arithmetic expression.

  Next, the vertical / horizontal conversion process (rotation process) in the rotation unit 50 will be described. In the following description, if the block data Df, Dr, and Dc are not particularly distinguished, they may be simply referred to as data D. The rotation unit 50 performs rotation processing on the transferred data while transferring the print image data PD stored in the DRAM 35 (specifically, the first buffer 35a) to the rotation unit 50 by 4 × 4 pixel data. The data after the rotation processing is sequentially transferred and written to the DRAM 35 (specifically, the second buffer 35b).

  At this time, the transfer instruction unit 61 of the rotation unit 50 makes a read request to the memory controller 34 by specifying the read address ADread generated by the first address generation unit 59. As a result, the square block data D of 4 × 4 pixels constituting the print image data PD is transferred by four burst transfers of each burst size BS (4 pixel data). Then, the print image data PD stored in the DRAM 35 as shown in FIG. 6A is read in the order of the block data D indicated by bold numbers in FIG. Is done. The rotation unit 50 performs rotation processing (vertical / horizontal conversion processing) on the data D transferred for each block of 4 × 4 pixels.

  FIG. 9 is a schematic diagram for explaining data rotation processing by the rotation unit. In FIG. 9, the left side shows data before rotation, and the right side shows data after rotation. Further, in FIG. 9, each data is shown in order of transfer from the top. Note that the numbers in <> shown at the upper left of the left data correspond to the thick numbers attached to the blocks indicated by the thick line frames in FIG. 6.

The rotation processing of the data is performed by the rotation processing unit 52 shown in FIG. Data D before rotation is temporarily stored in the data register 63 and then stored in the SRAM 70.
At this time, the rotation control unit 62 sequentially stores the four pixel data (hereinafter also referred to as “burst data”) transferred in four burst sizes BS in the first to fourth rows of the SRAM 70. The rotation control unit 62 performs the rotation process while reading the data D from the SRAM 70 and writes the rotated data in the SRAM 70 again. This rotation processing is performed, for example, by writing pixel data read in the row direction in the column direction. As a result of this rotation processing, the pre-rotation data D shown on the left side in FIG. 9 is vertically and horizontally converted as data D shown on the right side in FIG.

  Here, the full data Df of the bold numbers “1” and “2” in FIG. 6A is obtained from the read address ADread calculated based on the arithmetic expression of the above expression (1) using M and N at that time. The burst data sequentially read and transferred four times are sequentially stored in the first to fourth rows of the SRAM 70 on the left side of FIG. 9, thereby being stored as shown on the left side of FIG. Then, the rotation processing is sequentially performed on the full data Df of <1> and <2> on the left side of FIG. 9, and the rotated data Df shown on the right side of FIG. 9 is generated.

  Next, the row remainder data Dr indicated by the bold numeral “3” shown by shading in FIG. 6 is stored in the full data array width (burst raster size BR) following the end of the column remainder data Dc. At this time, the first address generation unit 59 uses the M and N at the time of the pixel 1-9 in FIG. 7 and the burst data including the pixel 1-9 in FIG. A read address ADread is calculated. As a result, burst data for four pixels starting from pixel 1-9 in the block of bold numeral “3” in FIG. 6A is stored in the first row of the SRAM 70 on the left side of FIG. Next, the first address generation unit 59 reads out burst data including the pixel 2-9 in FIG. 6A based on the equation (2) using M and N at the pixel 2-9 in FIG. The address ADread is calculated. As a result, burst data for four pixels starting from pixel 2-9 in the block of bold number “3” in FIG. 6A is stored in the second row of the SRAM 70 on the left side of FIG. Similarly, burst data for four pixels starting from pixel 3-9 in the block of bold numeral “3” in FIG. 6A is stored in the third row of the SRAM 70 on the left side of FIG. Burst data for four pixels starting from pixel 4-9 in the block of bold number “3” in FIG. 6A is stored in the fourth row of the SRAM 70 on the left side of FIG. Therefore, in the blank area in <3> on the left side of FIG. 9, unnecessary data for the rear two pixels in the burst data is actually stored. Then, the rotation processing is performed on the <3> margin data Dr, and the rotated data Dc shown on the right side of FIG. 9 is generated.

  Similarly, the column remainder data <4> and <5> are also stored in the SRAM 70 in the arrangement shown on the left side of FIG. Unnecessary data that has actually been burst transferred together is stored in at least a part of the blank areas in <4> and <5> on the left side of FIG. Then, the column remainder data Dc of <4> and <5> is subjected to the rotation process, and the rotated data Dr shown on the right side of FIG. 9 is generated.

  Next, the surplus data Dr indicated by the bold numeral “6” shown by hatching in FIG. 6 is stored in the full data array width (burst raster size BR). At this time, the first address generation unit 59 uses the M and N of the pixel 5-9 in FIG. 7 and the burst data including the pixel 5-9 in FIG. A read address ADread is calculated. As a result, burst data for four pixels starting from pixel 5-9 in the block of bold number “6” in FIG. 6A is stored in the first row of the SRAM 70 on the left side of FIG. Next, the first address generator 59 reads out burst data including the pixel 6-9 in FIG. 6A based on the equation (2) using M and N at the time of the pixel 6-9 in FIG. The address ADread is calculated. As a result, burst data for four pixels starting from pixel 6-9 in the block of bold number “6” in FIG. 6A is stored in the second row of the SRAM 70 on the left side of FIG. At this time, the count processing of all the pixels of the print image data PD is completed, and the data positions RP and LP become RP = R and LP = L, so the transfer of the print image data PD is finished. In part of the blank area in <6> on the left side of FIG. 9, unnecessary data for the rear two pixels in the burst data is actually stored. Then, rotation processing is performed on the <6> margin data Dr, and the rotated data Dr shown on the right side of FIG. 9 is generated.

  In this way, the data D sequentially transferred is subjected to rotation processing one by one, and the write data ADwrite generated by the second address generation unit 60 is designated for the rotated data and a write request is sent to the memory controller 34. As a result, the data is sequentially transferred to the DRAM 35. As a result, the rotated data D is stored in an array indicated by bold numerals in FIG.

  Here, when the rotated data D is transferred from the SRAM 70 to the DRAM 35, the blocks of bold numbers “4”, “5”, “6” surrounded by a broken line frame in FIG. In the buffer 35c), the margin data Dr is obtained (see the blocks <4> to <6> on the right side of FIG. 9). Further, the block of bold number “3” surrounded by a thick frame in FIG. 8 becomes the column remainder data Dc in the write destination DRAM 35 (output buffer 35c) (see the block <3> on the right side of FIG. 9).

  Here, the full data Df of <1> and <2> after the rotation shown on the right side of FIG. 9 uses the write address ADwrite calculated based on the arithmetic expression of the above expression (3) using M and N at that time. Designated burst data is read out and transferred to the DRAM 35 to be sequentially stored in blocks of bold numbers “1” and “2” shown in FIG.

  Next, <3> column remainder data Dc indicated by shading on the right side of FIG. 9 designates the write address ADwrite calculated based on the equation (3) using M and N at that time. Each burst data is read out and transferred to the DRAM 35, and stored in the block of bold numerals “3” shown in FIG. At this time, the unnecessary data transferred together is stored in the area below the block of the bold numeral “3” (bold numeral “4”).

  Next, the remainder data Dr of <4> and <5> shown on the right side of FIG. 9 designates the write address ADwrite calculated based on the equation (4) using M and N at that time. As a result, the burst data is read out and transferred to the DRAM 35, and stored in the blocks of bold numbers "4" and "5" shown in FIG. At this time, the block <4> in FIG. 6B is overwritten with the unnecessary data written during the transfer of “3”.

  At this time, burst data for four pixels starting from the pixel 5-1 in the block of the bold numeral “4” in FIG. 6B is stored first, and then 4 starting from the pixel 5-2. The burst data for the pixels is stored, and the pixels 5-2 and 6-2 are overwritten with the unnecessary data. Similarly, the burst data for the four pixels starting with the pixel 5-3 and the pixel 5-4 starting at the same time. Burst data for 4 pixels is sequentially stored. Similarly, the block indicated by the bold numeral “5” in FIG. 6B is written four times for each four pixels. Therefore, unnecessary data (dummy data) for two pixels per row is generated on the right side of the blocks “4” and “5” in FIG.

  Then, the <6> margin data Dr shown on the right side of FIG. 9 is read in burst data by designating the write address ADwrite calculated based on the equation (4) using M and N at that time. By being outputted and transferred to the DRAM 35, it is stored in the block of the bold numeral “6” shown in FIG. At this time, four pixels are written twice. Therefore, unnecessary data (dummy data) for two pixels is generated on the right side of the block “6” in FIG. 6B (a total of 10 dummy data). Of course, the block “6” may be configured to unify the transfer conditions and transfer four pixels (burst data) four times, and in this case, six pixels (6 · B bytes) below the block “6”. ) Dummy data is generated (a total of 16 dummy data).

  In this way, the head image data HD is stored so that the surplus data in the area indicated by the broken line in FIG. 8 fits within the full data array width (burst line size BL) as shown in FIG.

As described above in detail, in the present embodiment, the following effects can be obtained.
(1) When storing the print image data PD in the DRAM 35, the line remainder data Dr that is less than 4 × 4 pixels as the transfer unit in the row direction (line direction) is replaced with the end of the column remainder data Dc (within the full data array width). The data is stored so as to fit within the full data array width (burst raster size BR) following the end of the data. Therefore, dummy data to be stored for efficient burst transfer can be suppressed, and the used capacity of the DRAM 35 necessary for storing the print image data PD can be reduced. Therefore, the used capacity of the DRAM 35 can be saved, and the storage area usable for storing other data can be increased. Accordingly, the transfer storage speed when burst transfer of the print image data PD from the DRAM 35 to the rotation unit 50 in units of processing units (square area of 4 × 4 pixels) is not reduced so much, and the use storage area of the print image data PD in the DRAM 35 is reduced. be able to.

  (2) When the head image data HD is stored in the DRAM 35, the row remainder data Dr that is less than 4 × 4 pixels as the transfer unit in the row direction (raster direction) is replaced with the end of the column remainder data Dc (within the full data array width). The data is stored so as to fit within the full data array width (burst line size BL) following the end of the data. Therefore, it is possible to suppress dummy data to be stored in order to efficiently perform burst transfer. As a result, the used capacity of the DRAM 35 necessary for storing the head image data HD can be reduced. Therefore, the used capacity of the DRAM 35 can be saved, and the storage area usable for storing other data can be increased. Therefore, the use storage area of the head image data HD in the DRAM 35 is not reduced so much as the transfer speed at the time of burst transfer of the data D after the rotation process from the rotation unit 50 to the DRAM 35 in units of processing (square area of 4 × 4 pixels). It can be kept low.

  (3) Even if the data storage structure shown in FIG. 6A is adopted, the first address generator 59 transfers the data D constituting the print image data PD from the DRAM 35 in the original arrangement order (the arrangement order of the images themselves). A readable address ADread is generated. Therefore, the data D constituting the print image data PD can be transferred from the DRAM 35 to the rotation unit 50 in an appropriate order.

  (4) Since the write address ADwrite generated by the second address generation unit 60 is specified when transferring the data D after the rotation processing to the DRAM 35, the remainder data Dr is set within the full data array width as shown in FIG. The head image data HD can be stored with the aligned data storage structure shown in FIG.

  (5) The first address generation unit 59 sets an arithmetic expression for generating the read address ADread to be used according to the determination result of determining whether the data position RP is equal to or less than BR (RP ≦ BR) (1 ) And (2). Therefore, even if the print image data PD is stored in the data storage structure shown in FIG. 6A, an appropriate read address ADread can be generated.

  (6) The second address generation unit 60 sets an arithmetic expression for generating the address ADwrite to be used according to the determination result of determining whether the data position LP is equal to or less than BL (LP ≦ BL) (3) Switch between equation and equation (4). Therefore, it is possible to generate an appropriate write address ADwrite and store the head image data HD with the data storage structure shown in FIG.

  (7) Since the data storage structure of the print image data PD can be made compact and the data storage structure of the head image data HD after the rotation process can be made compact, the storage area used in the DRAM 35 before and after the rotation process is considerably reduced. it can.

  (8) Since the print image data PD is stored in the DRAM 35 in a data array in which the margin data Dr is within the full data array range (burst raster size BR), burst transfer of data from the DRAM 35 to the rotation unit 50 is performed at high speed. be able to. Accordingly, it is possible to effectively reduce the use storage area of the print image data PD in the DRAM 35 without reducing the burst transfer rate as much as possible.

  (9) When the processed data is transferred to the DRAM 35, the blocks “1”, “2”, “3”, “4”, “5”, “6” in the original order of the image of the image data itself. Since the data is sequentially transferred and stored in the DRAM 35, unnecessary data written at the time of transferring the previous block can be overwritten by the subsequent block transferred later.

  (10) Since the head image data HD is stored in the DRAM 35 in a data array in which the extra data Dr falls within the full data array range (burst line size BL), the burst of the data D after the rotation processing from the rotation unit 50 to the DRAM 35 Transfer can be performed at high speed. Therefore, it is possible to effectively reduce the use storage area of the head image data HD in the DRAM 35 without reducing the burst transfer rate as much as possible.

  (11) Since the image processing apparatus is provided in the multi-function device 11 having the printer unit 14 in which the print head 29 ejects ink droplets onto the paper conveyed by driving the conveyance motor 28 to form an image, the data in the multi-function device 11 The storage area of the DRAM 35 can be effectively used while suppressing a reduction in transfer speed.

In addition, the said embodiment can also be changed into the following forms.
-A processing means is not limited to a rotation means, You may perform another process. The processing means may perform image processing, for example. Examples of the image processing include resolution conversion processing, color conversion processing, halftone processing, interlace processing (microweave processing), and the like. In addition, the processing may be compression processing or decompression processing. In short, the type of processing is not particularly limited as long as the image data is transferred to the processing unit for each set size and the processing unit sequentially processes the transferred data for each set size.

  The transfer unit (processing unit) is not limited to 4 × 4 pixels, and may be a unit of 8 × 8 pixels, 16 × 16 pixels, or 64 × 64 pixels, for example. The transfer unit is not limited to a square block of K × K pixels, but may be a rectangular block of K × J pixels (K ≠ J). That is, an appropriate transfer unit can be set in accordance with the processing unit in the processing circuit (processing means).

  -Two counters may be used for address generation. For example, the third and fourth counters 57 and 58 are eliminated, and the address is calculated using the count values of the first and second counters 55 and 56. In this case, when the count value RP of the first counter 55 is “1”, “5”, “9”,... (RP = 4 · (Y−1) +1), RP (= M) at that time , LP (= N) is used to calculate the read address ADread. When the count value LP of the second counter 56 is “1”, “5”, “9”,... (LP = 4 · (X−1) +1), RP (= M), A configuration in which the write address ADwrite is calculated using LP (= N) may be employed.

  The DMA controller 51, which is an example of a transfer unit, may be provided as an independent circuit outside the rotation unit 50. Further, the transfer method of the transfer means is not limited to the burst transfer method. Other transfer methods can also be adopted.

  In the above-described embodiment, the data storage structure of the present invention is used for storing both the print image data PD and the head image data HD. However, the data storage of the present invention is stored in only one of the two. A structure may be adopted. For example, the data read by designating the read address ADread calculated using the equation (1) or (2) from the print image data PD stored in the DRAM with the data storage structure shown in FIG. After the rotation process, the storage may be performed as shown in FIG. In this case, the use storage area of the intermediate buffer 35b in the DRAM 35 can be suppressed. Further, for example, the data read from the print image data stored in the DRAM with the data storage structure shown in FIG. 10A is designated by the write address ADwrite calculated using the equation (3) or (4). A configuration of storing as shown in FIG. In this case, the use storage area of the output buffer 35c in the DRAM 35 can be suppressed.

  The address generation method (determination content of the determination unit, calculation content of the arithmetic unit, etc.) may be changed as appropriate. In short, as long as the method can generate the target address, the address may be generated by an operation using another arithmetic expression.

The print image data PD and the head image data HD are not limited to being stored in the same DRAM, and may be stored in different DRAMs.
The rotation unit 50 is not limited to a hardware configuration, and may include a software portion as a part thereof and may be configured by cooperation of hardware and software. Furthermore, although the processing speed is somewhat reduced, it may be configured by software.

  In each of the above embodiments, the ink jet printer unit 14 is employed, but a fluid ejecting apparatus that ejects or ejects fluid other than ink may be employed. Further, the present invention can be used for various liquid ejecting apparatuses including a liquid ejecting head that ejects a minute amount of liquid droplets. In this case, the droplet refers to the state of the liquid ejected from the liquid ejecting apparatus, and includes liquid droplets having a granular shape, a tear shape, and a thread shape. The liquid here may be any material that can be ejected by the liquid ejecting apparatus. For example, it may be in a state in which the substance is in a liquid phase, such as a liquid with high or low viscosity, sol, gel water, other inorganic solvents, organic solvents, solutions, liquid resins, liquid metals (metal melts ) And liquids as one state of the substance, as well as those obtained by dissolving, dispersing or mixing particles of a functional material made of solid materials such as pigments and metal particles in a solvent. Further, representative examples of the liquid include ink and liquid crystal as described in the above embodiment. Here, the ink includes general water-based inks and oil-based inks, and various liquid compositions such as gel inks and hot-melt inks. As a specific example of the liquid ejecting apparatus, for example, a liquid containing a material such as an electrode material or a coloring material used for manufacturing a liquid crystal display, an EL (electroluminescence) display, a surface emitting display, a color filter, or the like in a dispersed or dissolved state. A liquid ejecting apparatus for ejecting can be given. Further, it may be a liquid ejecting apparatus that ejects a bio-organic matter used for biochip manufacture, a liquid ejecting apparatus that ejects a liquid as a sample that is used as a precision pipette, a printing apparatus, a microdispenser, or the like. In addition, transparent resin liquids such as UV curable resin to form liquid injection devices that pinpoint lubricant oil onto precision machines such as watches and cameras, and micro hemispherical lenses (optical lenses) used in optical communication elements. A liquid ejecting apparatus that ejects a liquid onto the substrate or a liquid ejecting apparatus that ejects an etching solution such as an acid or an alkali to etch the substrate may be employed. The present invention can be applied to any one of these liquid ejecting apparatuses. Further, the fluid may be a granular material such as toner. In addition, the fluid referred to in this specification does not include a fluid consisting only of a gas.

  In each of the above embodiments, the color ink jet printer unit 14 having a scanner function is employed, but a recording device such as a wire impact recording device, a thermal transfer recording device, or an electrophotographic recording device is employed. May be. Further, these recording apparatuses may adopt a monochrome recording apparatus. Further, these recording apparatuses may employ recording apparatuses that do not have a scanner function.

In addition, the technical idea grasped | ascertained from the said embodiment and modification is described below.
(A) The transfer means has a configuration in which the row direction size of the data of the processing unit is a burst size, and the data of the processing unit is burst transferred by the burst size, and the margin data is the image data The image data processing apparatus according to any one of claims 1 to 6, wherein the data is less than the burst size in a row direction when divided in units of processing units. The image data processing method according to claim 8 or 9, wherein the margin data has a configuration similar to that of (b).

DESCRIPTION OF SYMBOLS 11 ... Multifunction machine as a fluid ejecting apparatus which is an example of a recording apparatus, 14 ... Printer part, 28 ... Conveyance motor which is an example of a conveying means, 29 ... Print head as a fluid ejecting head which is an example of a recording means, 35 ... DRAM as an example of storage means, 35b... Intermediate buffer as an example of storage means for storing image data before processing, 35c... Output buffer as an example of storage means for storing image data before processing, DESCRIPTION OF SYMBOLS 50 ... Rotation unit, 51 ... DMA controller as an example of transfer means, 52 ... Rotation processing part as an example of processing means and rotation processing means, 53 ... Setting register, 54 ... Sequencer, 55 ... First counter, 56 ... First 2 counter, 57... Third counter, 58... 4th counter, 59. 59a ... a determination unit as a determination unit, 59b ... a calculation unit, 60 ... a second address generation unit as an example of an address generation unit, 60a ... a determination unit as a determination unit, 60b ... a calculation unit, 61 ... transfer Instructing unit 70... SRAM, PD... Print image data as an example of image data before processing, HD... Head image data as an example of image data after processing, Df... Full data as processing unit data, Dr. This is an example of line remainder data as processing unit data, Dc: column remainder data as processing unit data, BS: burst size, ADread: read address as address, ADwrite: write address as address, P: medium. Paper.

Claims (9)

An image data processing device for processing image data,
Storage means for storing the image data;
Processing means for processing the image data;
And transfer means for transferring the image data from the storage means to the processing means in units of processing units,
The processing means is configured to sequentially process the data transferred from the storage means for each processing unit.
In the storage means, X × Y full data, one of which is filled in the processing unit, is stored in a matrix arrangement of X rows × Y columns, and the processing unit is filled in the row direction. If there is no remaining data, the remaining data is aligned and stored so as to fit within the full data Y column array width following the end of the data arranged within the full data Y column array width. The configuration
The image data processing apparatus, wherein the transfer means transfers the data from the storage means to the processing means in the original order of the image data before the alignment. An image data processing device for processing image data,
Processing means for reading the image data in units of processing and processing the data;
Storage means for storing the processed image data;
Transfer means for sequentially transferring the data of the processing unit subjected to the processing from the processing means to the storage means, and storing the processed image data in the storage means;
The transfer means arranges the processed image data in a matrix of Y rows × X columns, with Y × X full data, one of which is filled in the processing unit, with respect to the storage means. In addition, when there is line remainder data that is less than the processing unit in the row direction, the line remainder data is added to the end of the data arranged within the full data X column arrangement width, and the full data X column arrangement An image data processing apparatus, wherein the image data processing apparatus is arranged and stored so as to be within a width. An image data processing device for processing image data,
Storage means for storing image data before processing;
Processing means for processing the image data;
The post-processing image data generated by transferring the pre-processing image data from the storage unit to the processing unit for each processing unit, and the processing unit sequentially processing the data transferred for each processing unit. Transfer means for storing the processed image data in the storage means by sequentially transferring the data from the processing means to the storage means,
In the storage means, X × Y full data, one of which is filled in the processing unit, is stored in a matrix arrangement of X rows × Y columns, and the processing unit is filled in the row direction. If there is no remaining data, the remaining data is aligned and stored so as to fit within the full data Y column array width following the end of the data arranged within the full data Y column array width. The configuration
The transfer means transfers the data from the storage means to the processing means in the original order before the alignment in the image data,
Transfer means for sequentially transferring the data of the processing unit subjected to the processing from the processing means to the storage means, and storing the processed image data in the storage means;
The transfer means arranges the processed image data in a matrix of Y rows × X columns, with Y × X full data, one of which is filled in the processing unit, with respect to the storage means. At the same time, when there is the margin data, the margin data is aligned so that it fits within the full data X column arrangement width following the end of the data arranged within the full data X column arrangement width. An image data processing apparatus characterized by being stored. The processing means is rotation processing means for performing rotation processing on image data,
4. The transfer unit according to claim 1, wherein the transfer unit burst-transfers the data of a square block having K × K pixels (where K ≧ 2) having the same number of pixels in the row direction and the column direction. 5. The image data processing apparatus as described in any one of them.   The transfer means further comprises an address generation means for generating a read address for reading and transferring data from the storage means, or for generating a write address for writing data transferred to the storage means. The image data processing apparatus according to claim 1, wherein the image data processing apparatus is an image data processing apparatus. The address generating means determines whether or not the data to be transferred is margin data; and
The address is generated according to the first address generation arithmetic expression when the data is other than the remainder data, and the address is generated according to the second address generation arithmetic expression when the data is the remainder data. The image data processing apparatus according to claim 5. The image data processing device according to any one of claims 1 to 6,
Conveying means for conveying the medium;
Recording means for forming an image on a medium conveyed by the conveying means,
The recording apparatus according to claim 1, wherein the recording unit is controlled based on image data processed by the processing unit. An image data processing method for processing image data,
In the storage means, the image data is stored in a matrix arrangement of X rows and Y columns in which X × Y full data, one of which is filled in a processing unit, and rows less than the processing unit in the row direction. If there is surplus data, the line surplus data is aligned and stored so as to fit within the full data Y column array width following the end of the data arranged within the full data Y column array width. ,
A transfer step of transferring the image data from the storage means to the processing means for each piece of processing unit data;
The processing means includes processing steps for sequentially processing the data transferred from the storage means for each processing unit;
In the transfer step, the data is transferred from the storage means to the processing means in the original order before the alignment. An image data processing method for processing image data,
A processing step of reading the image data in units of processing units and processing means processing the data;
A transfer step of causing the storage unit to store the processed image data by sequentially transferring the processing unit data subjected to the processing from the processing unit to the storage unit;
In the transfer step, the transfer means arranges Y × X full data, one of which is filled in the processing unit, in a matrix of Y rows × X columns and fills the processing unit in the row direction. If there is no line remainder data, the line remainder data is aligned and stored so as to fit within the full data X column arrangement width following the end of the data arranged within the full data X column arrangement width. And a method of processing image data.

Images