JP5736261B2 - 遅延クロック信号生成回路およびパルス生成回路 - Google Patents
遅延クロック信号生成回路およびパルス生成回路 Download PDFInfo
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- JP5736261B2 JP5736261B2 JP2011154406A JP2011154406A JP5736261B2 JP 5736261 B2 JP5736261 B2 JP 5736261B2 JP 2011154406 A JP2011154406 A JP 2011154406A JP 2011154406 A JP2011154406 A JP 2011154406A JP 5736261 B2 JP5736261 B2 JP 5736261B2
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 title claims description 35
- 230000003111 delayed effect Effects 0.000 claims description 16
- 230000000630 rising effect Effects 0.000 claims description 9
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 29
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 29
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 16
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 6
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 4
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 4
- 230000001934 delay Effects 0.000 description 4
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011154406A JP5736261B2 (ja) | 2011-07-13 | 2011-07-13 | 遅延クロック信号生成回路およびパルス生成回路 |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011154406A JP5736261B2 (ja) | 2011-07-13 | 2011-07-13 | 遅延クロック信号生成回路およびパルス生成回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013021576A JP2013021576A (ja) | 2013-01-31 |
| JP2013021576A5 JP2013021576A5 (enrdf_load_stackoverflow) | 2014-09-11 |
| JP5736261B2 true JP5736261B2 (ja) | 2015-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2011154406A Expired - Fee Related JP5736261B2 (ja) | 2011-07-13 | 2011-07-13 | 遅延クロック信号生成回路およびパルス生成回路 |
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| JP (1) | JP5736261B2 (enrdf_load_stackoverflow) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6456790B2 (ja) * | 2015-07-29 | 2019-01-23 | 新電元工業株式会社 | 半導体試験装置及び半導体試験方法 |
| CN116155246B (zh) * | 2022-12-12 | 2024-12-27 | 天津兆讯电子技术有限公司 | 一种高精度延迟时钟生成电路及芯片 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2573787B2 (ja) * | 1993-05-18 | 1997-01-22 | 株式会社メガチップス | パルス幅変調回路 |
| JP2000236241A (ja) * | 1999-02-16 | 2000-08-29 | Kawasaki Steel Corp | 半導体集積回路 |
| JP2008021194A (ja) * | 2006-07-14 | 2008-01-31 | Kawasaki Microelectronics Kk | クロック変調回路 |
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- 2011-07-13 JP JP2011154406A patent/JP5736261B2/ja not_active Expired - Fee Related
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| Publication number | Publication date |
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| JP2013021576A (ja) | 2013-01-31 |
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