JP5719041B2 - 論理アドレス変換 - Google Patents
論理アドレス変換 Download PDFInfo
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- JP5719041B2 JP5719041B2 JP2013557761A JP2013557761A JP5719041B2 JP 5719041 B2 JP5719041 B2 JP 5719041B2 JP 2013557761 A JP2013557761 A JP 2013557761A JP 2013557761 A JP2013557761 A JP 2013557761A JP 5719041 B2 JP5719041 B2 JP 5719041B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
- G06F12/1466—Key-lock mechanism
- G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
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- G—PHYSICS
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- G06F2212/72—Details relating to flash memory management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Human Computer Interaction (AREA)
- Storage Device Security (AREA)
- Read Only Memory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
- Executing Machine-Instructions (AREA)
Description
Claims (14)
- 論理アドレス(LA)変換のための方法であって、
LAと関連付けられたコマンドを受信することであって、前記LAは特定のLA範囲内にある、ことと、
オフセットを用いて前記LAをメモリ中の物理的位置へと変換することであって、前記オフセットが、前記特定のLA範囲および前記特定のLA範囲以外のLA範囲と関連付けられたデータを含む書き込み動作の際にスキップされる幾つかの物理的位置に対応し、前記書き込み動作は、前記特定のLA範囲と関連付けられたデータと前記特定のLA範囲以外の前記LA範囲と関連付けられたデータとがそれぞれ異なるページ上にあるように、前記幾つかの物理的位置をスキップさせる、ことと、
を含む、方法。 - 第1の暗号鍵が、前記特定のLA範囲以外の前記LA範囲と関連付けられたデータへ付加され、かつ、第2の暗号鍵が、前記特定のLA範囲と関連付けられたデータへ付加される、請求項1に記載の方法。
- 前記方法は、鍵範囲テーブル中に前記オフセットを配置することを含む、請求項1に記載の方法。
- 前記変換することは、前記物理的位置をメモリ中に配置する前に、前記オフセットを前記LAへ付加することを含む、請求項1に記載の方法。
- 前記LAを前記物理的位置へ変換することは、前記オフセットによって示された幾つかの物理的セクターをスキップすることを含む、請求項4に記載の方法。
- 前記オフセットによって示された前記幾つかの物理的セクターをスキップすることは、前記特定のLA範囲以外の前記LA範囲および前記特定のLA範囲に先行するLA範囲と関連付けられたデータを含む前記書き込み動作中にスキップされる物理的セクターの累積合計をスキップすることを含む、請求項5に記載の方法。
- 前記変換することは、物理的セクターへ変換することを含む、請求項1〜6のうちいずれか1項に記載の方法。
- 前記変換することは、オフセットを用いて前記LAを物理的位置へ変換することを含み、前記オフセットは、前記特定のLA範囲に先行するLA範囲と関連付けられたデータを含む前記書き込み動作中にスキップされる幾つかの物理的位置に対応する、請求項1〜6のうちいずれか1項に記載の方法。
- 異なる暗号鍵が、前記LA範囲のそれぞれに付与される、請求項8に記載の方法。
- 前記特定のLA範囲が、第2の暗号鍵と関連付けられる、請求項1から6のいずれか1項に記載の方法。
- 前記特定のLA範囲以外の前記LA範囲が、第1の暗号鍵と関連付けられる、請求項1から6のいずれか1項に記載の方法。
- メモリシステムであって、
不揮発性メモリと、
前記不揮発性メモリに接続されたコントローラであって、前記コントローラは、
論理アドレス(LA)の特定のグループに暗号鍵を付与することと、
LAの前記特定のグループ内にある前記LAと、LAの前記特定のグループおよび前記特定のグループ以外のLAの幾つかの他のグループと関連付けられたデータを含む書き込み動作中にスキップされる幾つかの物理的位置とに基づいて、コマンドと関連付けられたLAを変換することであって、前記書き込み動作は、LAの前記特定のグループと関連付けられたデータとLAの前記特定のグループ以外の前記幾つかの他のグループと関連付けられたデータとがそれぞれ異なるページ上にあるように、前記幾つかの物理的位置をスキップさせる、ことと、
を行うよう構成される、コントローラと、
を含む、メモリシステム。 - 前記コントローラは鍵範囲テーブルをさらに含み、前記鍵範囲テーブルは、それぞれがオフセットを有する幾つかのエントリーを含み、前記オフセットは、それぞれのエントリーと関連付けられたLAのグループ以外のLAと関連付けられたデータを書き込む際にスキップされる物理的セクターの数を示す、請求項12に記載のメモリシステム。
- 前記鍵範囲テーブルの前記幾つかのエントリーのそれぞれと関連付けられた前記オフセットは、前記鍵範囲テーブルの各先行するエントリーからのオフセットを累積することによって決定される、請求項13に記載のメモリシステム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/041,402 US8732431B2 (en) | 2011-03-06 | 2011-03-06 | Logical address translation |
US13/041,402 | 2011-03-06 | ||
PCT/US2012/027265 WO2012121968A2 (en) | 2011-03-06 | 2012-03-01 | Logical address translation |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2015055721A Division JP6181689B2 (ja) | 2011-03-06 | 2015-03-19 | 論理アドレス変換 |
Publications (2)
Publication Number | Publication Date |
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JP2014507738A JP2014507738A (ja) | 2014-03-27 |
JP5719041B2 true JP5719041B2 (ja) | 2015-05-13 |
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Family Applications (2)
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JP2013557761A Active JP5719041B2 (ja) | 2011-03-06 | 2012-03-01 | 論理アドレス変換 |
JP2015055721A Active JP6181689B2 (ja) | 2011-03-06 | 2015-03-19 | 論理アドレス変換 |
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JP2015055721A Active JP6181689B2 (ja) | 2011-03-06 | 2015-03-19 | 論理アドレス変換 |
Country Status (7)
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---|---|
US (2) | US8732431B2 (ja) |
EP (1) | EP2684132B1 (ja) |
JP (2) | JP5719041B2 (ja) |
KR (1) | KR101554084B1 (ja) |
CN (1) | CN103502958B (ja) |
TW (1) | TWI459200B (ja) |
WO (1) | WO2012121968A2 (ja) |
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2011
- 2011-03-06 US US13/041,402 patent/US8732431B2/en active Active
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2012
- 2012-03-01 WO PCT/US2012/027265 patent/WO2012121968A2/en unknown
- 2012-03-01 CN CN201280012166.4A patent/CN103502958B/zh active Active
- 2012-03-01 EP EP12754482.3A patent/EP2684132B1/en active Active
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JP2015164044A (ja) | 2015-09-10 |
TW201250470A (en) | 2012-12-16 |
CN103502958A (zh) | 2014-01-08 |
TWI459200B (zh) | 2014-11-01 |
US20140317374A1 (en) | 2014-10-23 |
WO2012121968A3 (en) | 2012-11-22 |
WO2012121968A2 (en) | 2012-09-13 |
EP2684132B1 (en) | 2019-04-24 |
KR101554084B1 (ko) | 2015-09-17 |
US9164701B2 (en) | 2015-10-20 |
US20120226887A1 (en) | 2012-09-06 |
JP2014507738A (ja) | 2014-03-27 |
JP6181689B2 (ja) | 2017-08-16 |
US8732431B2 (en) | 2014-05-20 |
KR20130120541A (ko) | 2013-11-04 |
EP2684132A4 (en) | 2014-12-10 |
EP2684132A2 (en) | 2014-01-15 |
CN103502958B (zh) | 2016-08-17 |
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