JP5716372B2 - Nonvolatile latch circuit and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a nonvolatile latch circuit having a resistance change element and a semiconductor integrated circuit having a nonvolatile latch circuit.

  Recently, a nonvolatile latch circuit using a resistance change element such as a magnetic tunnel junction (MTJ) element has been proposed (see, for example, Patent Document 1-2 and Non-Patent Document 1). In this type of nonvolatile latch circuit, a pair of resistance change elements set to different resistance values are arranged between a power supply terminal and a power supply line of the latch circuit. For example, when the logic held in the latch circuit is written into the variable resistance element, currents in opposite directions flow through the pair of variable resistance elements according to the logic held in the latch circuit. When the logic held in the variable resistance element is read out to the latch circuit, different currents depending on the resistance value of the variable resistance element are supplied to the complementary nodes set in the intermediate state in the latch circuit.

JP 2008-85770 A Japanese translation of PCT publication No. 2002-511631

W. Zhao, et al., Integration of Spin-RAM technology in FPGA circuits, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) 2006, PP799-802

  When the variable resistance element is disposed between the power supply terminal of the latch circuit and the power supply line, a current flows through the variable resistance element each time the logic of the latch circuit is rewritten. As a result, the magnetization characteristics of the resistance change element may be degraded, and electrical characteristics such as a read margin may be degraded.

In one embodiment of the present invention, a nonvolatile latch circuit includes a latch circuit including complementary first and second storage nodes, a current flowing from one end to the other end, and a current flowing from the other end to the one end. A first variable resistance element having a variable resistance value; a current flowing from one end to the other end; a second variable resistance element having a resistance value varying by flowing a current from the other end to the one end; and a switch circuit connecting the second resistance-variable element in the latch circuit, switch circuit, during normal operation of the logic is written to the latch circuit from the outside, blocking the connection between the first and second variable resistance element and a latch circuit In the store operation of writing the logic held in the latch circuit to the first and second resistance change elements, one end of the first resistance change element and the other end of the second resistance change element are connected to the first storage node, 1 Connecting one end of the other end and a second resistance element of the anti-change element to the second storage node.

  By interrupting the connection between the first and second variable resistance elements and the latch circuit during normal operation, current can be prevented from flowing through the variable resistance element when the logic of the latch circuit is rewritten from the outside. And it can prevent that the magnetization characteristic of a 2nd resistance change element deteriorates. As a result, it is possible to prevent a decrease in electrical characteristics such as a read margin.

2 illustrates an example of a nonvolatile latch circuit according to an embodiment. The example of the non-volatile latch circuit in another embodiment is shown. 3 shows an example of the element structure of the magnetic tunnel junction element MTJ1 and switches SW1 and SW3 shown in FIG. 3 shows an example of a store operation of the nonvolatile latch circuit shown in FIG. 3 shows an example of a restore operation of the nonvolatile latch circuit shown in FIG. 3 shows an example of normal operation of the nonvolatile latch circuit shown in FIG. 3 shows an example of the operation of the semiconductor integrated circuit having the nonvolatile latch circuit shown in FIG. The example of the non-volatile latch circuit in another embodiment is shown. 9 shows an example of a restore operation of the nonvolatile latch circuit shown in FIG. The example of the non-volatile latch circuit in another embodiment is shown. 11 shows an example of normal operation of the nonvolatile latch circuit shown in FIG. The example of the non-volatile latch circuit in another embodiment is shown. The example of the non-volatile latch circuit in another embodiment is shown. 14 shows an example of a store operation of the nonvolatile latch circuit shown in FIG. 14 shows an example of a restore operation of the nonvolatile latch circuit shown in FIG. The example of the electrical property of the resistance change element formed in the non-volatile latch circuit in another embodiment is shown. An example of a semiconductor integrated circuit on which the above-described nonvolatile latch circuit is mounted is shown. 3 shows another example of a semiconductor integrated circuit on which the above-described nonvolatile latch circuit is mounted. 3 shows another example of a semiconductor integrated circuit on which the above-described nonvolatile latch circuit is mounted. An example of the switch matrix shown in FIG. 19 is shown. An example of the logic block shown in FIG. 19 is shown.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals as the signal names are used for signal lines through which signals or voltages are transmitted. “/” Added to the heads of signal names and signal line names indicates negative logic.

  FIG. 1 shows an example of a nonvolatile latch circuit NVLT according to an embodiment. The nonvolatile latch circuit NVLT includes a latch circuit LT, a switch circuit SW, and magnetic tunnel junction elements MTJ1 and MTJ2. The latch circuit LT is connected to a power supply line VDD that is an example of a high level voltage line and a ground line VSS that is an example of a low level voltage line, and operates by receiving the power supply voltage VDD and the ground voltage VSS. For example, the power supply voltage VDD is 1.2V.

  The latch circuit LT has a pair of inverters IV1 and IV2 which are arranged in parallel and in opposite directions between the complementary storage nodes ND1 and ND2, and one input and the other output are connected to each other. For example, the inverters IV1 and IV2 are CMOS inverters. Storage node ND1 is connected to an input terminal DT that receives input data, and storage node ND2 is connected to an output terminal / DT that outputs output data. For example, when the storage node ND1 is logic 0, the latch circuit LT is defined as storing logic 0, and when the storage node ND1 is logic 1, the latch circuit LT is defined as storing logic 1.

  The magnetic tunnel junction elements MTJ1 and MTJ2 are connected to the storage nodes ND1 and ND2 or the ground line VSS of the latch circuit LT via the switch circuit SW. Each of the magnetic tunnel junction elements MTJ1 and MTJ2 has two ferromagnetic layers (a fixed layer and a free layer) stacked via a tunnel insulating film. The free layer is disposed on the front end side of the arrow, and the fixed layer is disposed on the rear end side of the arrow. For example, the magnetic tunnel junction elements MTJ1 and MTJ2 are elements formed in a magnetic random access memory (MRAM). The structure of the magnetic tunnel junction elements MTJ1 and MTJ2 will be described with reference to FIG.

  The electric resistances of the magnetic tunnel junction elements MTJ1 and MTJ2 are low when the magnetization directions of the fixed layer and the free layer are parallel (parallel state), and high when the magnetization directions of the fixed layer and the free layer are antiparallel (anti-parallel state). ). For example, logic 0 is defined when each magnetic tunnel junction element MTJ1, MTJ2 is in a parallel state, and logic 1 is defined when each magnetic tunnel junction element MTJ1, MTJ2 is in an antiparallel state.

  The magnetic tunnel junction elements MTJ1 and MTJ2 are in a low resistance state (parallel state) having a low resistance value by flowing a current from the free layer to the fixed layer, and a high resistance value by flowing a current from the fixed layer to the free layer. It becomes a resistance state (anti-parallel state). That is, the magnetic tunnel junction elements MTJ1 and MTJ2 are a kind of variable resistance element in which the resistance value changes when a current flows from one end to the other end and a current flows from the other end to the one end.

  The switch circuit SW includes switches SW1, SW2, SW3, SW4, SW5, and SW6. The switch SW1 connects one end (for example, the fixed layer side) of the magnetic tunnel junction element MTJ1 to the storage node ND1. The switch SW2 connects the other end (for example, the free layer side) of the magnetic tunnel junction element MTJ2 to the storage node ND1. The switch SW3 connects the other end (for example, the free layer side) of the magnetic tunnel junction element MTJ1 to the storage node ND2. The switch SW4 connects one end (for example, the fixed layer side) of the magnetic tunnel junction element MTJ2 to the storage node ND2. The switch SW5 connects the other end of the magnetic tunnel junction element MTJ1 to the ground line VSS. The switch SW6 connects the other end of the magnetic tunnel junction element MTJ2 to the ground line VSS.

  During a normal operation in which logic is written to the latch circuit LT from the outside of the nonvolatile latch circuit NVLT, the switch circuit SW turns off the switches SW1 to SW6 and cuts off the connection between the magnetic tunnel junction elements MTJ1 and MTJ2 and the latch circuit LT. . As a result, during normal operation, the current flowing through the storage nodes ND1 and ND2 along with the rewriting of the logic of the latch circuit LT does not flow through the magnetic tunnel junction elements MTJ1 and MTJ2. As a result, it is possible to prevent the magnetization characteristics of the magnetic tunnel junction elements MTJ1 and MTJ2 from deteriorating during normal operation, and to prevent deterioration of electrical characteristics such as a read margin due to the deterioration.

  During a store operation in which the logic held in the latch circuit LT is written to the magnetic tunnel junction elements MTJ1 and MTJ2, the switch circuit SW turns on the switches SW1 to SW4 and turns off the switches SW5 and SW6. As a result, one end of the magnetic tunnel junction element MTJ1 and the other end of the magnetic tunnel junction element MTJ2 are connected to the storage node ND1. The other end of the magnetic tunnel junction element MTJ1 and one end of the magnetic tunnel junction element MTJ2 are connected to the storage node ND2.

  For example, when the latch circuit LT stores logic 1 (ND1 = "1", ND2 = "0"), in the magnetic tunnel junction element MTJ1, a current flows from the fixed layer toward the free layer, and the magnetic tunnel junction In the element MTJ2, a current flows from the free layer toward the fixed layer. Thereby, the magnetic tunnel junction elements MTJ1 and MTJ2 are set to a high resistance state and a low resistance state, respectively. On the contrary, when the latch circuit LT stores logic 0 (ND1 = "0", ND2 = "1"), the magnetic tunnel junction elements MTJ1 and MTJ2 are in the low resistance state and the high resistance state, respectively. Is set.

  In the store operation, the magnetic tunnel junction elements MTJ1 and MTJ2 are connected in parallel between the storage nodes ND1 and ND2. For this reason, the write voltage (VDD in this example) can be made lower than when the magnetic tunnel junction element pairs are connected in series. In other words, the store operation can be executed using the normal power supply voltage VDD (that is, without using a booster circuit or the like).

  During a restore operation for returning the logic held in the magnetic tunnel junction elements MTJ1 and MTJ2 to the latch circuit LT, the switch circuit SW turns on the switches SW5 and SW6, and the other end of the magnetic tunnel junction element MTJ1 and the magnetic tunnel junction element MTJ2 Is connected to the ground line VSS. The switch circuit SW turns on the switches SW1 and SW4, connects one end of the magnetic tunnel junction element MTJ1 to the storage node ND1, and connects one end of the magnetic tunnel junction element MTJ2 to the storage node ND2. The switches SW2 and SW3 are turned off.

  Thereby, the storage node ND1 is connected to the ground line VSS via the magnetic tunnel junction element MTJ1, and the storage node ND2 is connected to the ground line VSS via the magnetic tunnel junction element MTJ2. In this state, when the power supply voltage VDD is supplied to the latch circuit LT, the voltages of the storage nodes ND1 and ND2 gradually increase.

  For example, when the magnetic tunnel junction element MTJ1 is in a high resistance state and the magnetic tunnel junction element MTJ2 is in a low resistance state, the storage node ND2 has more charge discharged to the ground line VSS than the storage node ND1. For this reason, the voltage of the storage node ND1 is higher than the voltage of the storage node ND2. In this state, when the power supply voltage VDD rises to a voltage at which the inverters IV1 and IV2 of the latch circuit LT normally operate (for example, half of VDD), the latch circuit LT has a relatively high storage node ND1. The voltage and the voltage of the relatively low storage node ND2 are latched, and a logic 0 data signal / DT is output. That is, a restore operation is executed.

  At this time, a current flows from the high-level storage node ND1 to the ground line VSS via the magnetic tunnel junction element MTJ1. However, since the direction of this current is the same as the direction of the current required to bring the magnetic tunnel junction element MTJ1 into a high resistance state, the resistance state of the magnetic tunnel junction element MTJ1 does not change. Since the storage node ND2 drops to the ground voltage VSS with a half of the power supply voltage VDD as the maximum voltage, the current flowing through the magnetic tunnel junction element MTJ2 is smaller than the current flowing during the store operation. For this reason, the magnetic tunnel junction element MTJ2 is not switched from the low resistance state to the high resistance state by a current that temporarily flows from the fixed layer side to the free layer side of the magnetic tunnel junction element MTJ2.

  In the restore operation when the magnetic tunnel junction element MTJ1 is in the low resistance state and the magnetic tunnel junction element MTJ2 is in the high resistance state, the voltage of the storage node ND1 is lower than the voltage of the storage node ND2, contrary to the above. The latch circuit LT latches a relatively low voltage of the storage node ND1 and a relatively high voltage of the storage node ND2, and outputs a logic 1 data signal / DT.

  The restore operation is executed by temporarily turning on a short switch (nMOS transistor N3 or pMOS transistor P3) that short-circuits the inverters IV1 and IV2 of the latch circuit LT as shown in FIG. 2 or FIG. May be.

  As described above, in this embodiment, when the logic of the latch circuit LT is rewritten by external data, it is possible to prevent a current from flowing through the magnetic tunnel junction elements MTJ1 and MTJ2. Therefore, it is possible to prevent the amount of magnetization written in the magnetic tunnel junction elements MTJ1 and MTJ2 from changing, and to prevent the characteristics of the tunnel insulating film and the free layer from deteriorating. Since the deterioration of the magnetization characteristics can be prevented, it is possible to prevent the deterioration of the electrical characteristics such as the read margin.

  Since the magnetic tunnel junction elements MTJ1 and MTJ2 are not connected to the current path of the latch circuit LT during normal operation, the latch circuit LT can be operated at high speed. During the store operation, the magnetic tunnel junction elements MTJ1 and MTJ2 are connected in parallel between the storage nodes ND1 and ND2, so that the write voltage can be lowered. As a result, the store operation can be reliably executed using the normal power supply voltage VDD supplied to the latch circuit LT.

  By supplying the power supply voltage VDD to the latch circuit LT with the magnetic tunnel junction elements MTJ1 and MTJ2 connected to the latch circuit LT, the restore operation can be executed without changing the resistance state of the magnetic tunnel junction elements MTJ1 and MTJ2. . The number of transistors required for the nonvolatile latch circuit NVLT can be reduced as compared with the conventional case, and the circuit area of the nonvolatile latch circuit NVLT can be reduced.

  FIG. 2 shows an example of a nonvolatile latch circuit NVLT in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the latch circuit LT has a pair of CMOS inverters IV1 and IV2 in which one input and the other output are connected to each other, and an nMOS transistor N3 that connects the CMOS inverters IV1 and IV2 to each other. . The gate of the nMOS transistor N3 receives a restore signal RS that is activated to a high level during a restore operation.

  The CMOS inverter IV1 is formed by a pMOS transistor P1 and an nMOS transistor N1 arranged between the power supply line VDD and the ground line VSS. The CMOS inverter IV2 is formed by a pMOS transistor P2 and an nMOS transistor N2 arranged between the power supply line VDD and the ground line VSS. The input of the CMOS inverter IV1 and the output of the CMOS inverter IV2 are connected to the input terminal DT. The output of the CMOS inverter IV1 and the input of the CMOS inverter IV2 are connected to the output terminal / DT. The driving capability of the pMOS transistor P1 and the nMOS transistor N1 is smaller than the driving capability of the output circuit (driver) that supplies the input data DT to the nonvolatile latch circuit NVLT. Thereby, the logic held in the latch circuit LT can be easily inverted according to the input data DT.

  The switches SW1-SW4 of the switch circuit SW have a CMOS transfer gate in which the sources and drains of the nMOS transistor and the pMOS transistor are connected to each other. The switch SW1 is turned on when the OR signal OR is at a high level and the OR signal / OR is at a low level, and connects one end (fixed layer side) of the magnetic tunnel junction element MTJ1 to the storage node ND1.

  The OR signal OR is activated to a high level when either the store signal ST or the restore signal RS is activated to a high level. The OR signal / OR is activated to a low level when either the store signal ST or the restore signal RS is activated to a high level. Store signal ST is activated to a high level during a store operation. The OR circuit OR1 generates OR signals OR and / OR based on the store signal ST and the restore signal RS. Inverter IV3 inverts the logic of store signal ST to generate store signal / ST. The activation level of the store signal / ST is low level.

  The switch SW2 is turned on when the store signals ST, / ST are activated, and connects the other end (free layer side) of the magnetic tunnel junction element MTJ2 to the storage node ND1. The switch SW3 is turned on when the store signals ST and / ST are activated, and connects the other end (free layer side) of the magnetic tunnel junction element MTJ1 to the storage node ND2. The switch SW4 is turned on when the OR signals OR and / OR are activated, and connects one end (the fixed layer side) of the magnetic tunnel junction element MTJ2 to the storage node ND2.

  The switches SW5 and SW6 have nMOS transistors. The nMOS transistor of the switch SW5 has a drain connected to the other end of the magnetic tunnel junction element MTJ1, a source connected to the ground line VSS, and a gate connected to the restore signal line RS. The nMOS transistor of the switch SW6 has a drain connected to the other end of the magnetic tunnel junction element MTJ2, a source connected to the ground line VSS, and a gate connected to the restore signal line RS.

  For example, the store signal ST and the restore signal RS are generated outside the nonvolatile latch circuit NVLT. The OR circuit OR1 and the inverter IV3 may be formed outside the nonvolatile latch circuit NVLT. Further, when the plurality of nonvolatile latch circuits NVLT are formed in the semiconductor integrated circuit, the OR circuit OR1 and the inverter IV3 may be provided in common to the plurality of nonvolatile latch circuits NVLT.

  FIG. 3 shows an example of the element structure of the magnetic tunnel junction element MTJ1 and the switches SW1 and SW3 shown in FIG. The switches SW1 and SW3 are formed on the surface of the semiconductor substrate SUB, and the magnetic tunnel junction element MTJ1 is formed above the semiconductor substrate SUB. For example, the semiconductor substrate SUB is a p-type substrate. The p-type substrate is used as a substrate region (p-type well region PW) of the nMOS transistor. In the p-type well region PW, an n-type well region NW which is a substrate of a pMOS transistor is formed.

  Switch SW1 includes an nMOS transistor that receives an OR signal OR at its gate and a pMOS transistor that receives an OR signal / OR at its gate. One of the diffusion layer DR of the nMOS transistor and one of the diffusion layer DR of the pMOS transistor of the switch SW1 are connected to the storage node ND1 (DT). The other of the diffusion layer DR of the nMOS transistor and the other of the diffusion layer DR of the pMOS transistor of the switch SW1 is connected to the fixed layer PL of the magnetic tunnel junction element MTJ1. Although not particularly limited, the gate of the nMOS transistor and the gate of the pMOS transistor are formed using the polysilicon wiring layer POLY.

  Switch SW3 has an nMOS transistor that receives store signal ST at its gate and a pMOS transistor that receives store signal / ST at its gate. One of the diffusion layer DR of the nMOS transistor and one of the diffusion layer DR of the pMOS transistor of the switch SW3 are connected to the storage node ND2 (/ DT). The other of the diffusion layer DR of the nMOS transistor and the other of the diffusion layer DR of the pMOS transistor of the switch SW3 are connected to the free layer FL of the magnetic tunnel junction element MTJ1.

  For example, the magnetic tunnel junction element MTJ1 is formed by sequentially laminating a fixed layer PL, a tunnel insulating film TL, and a free layer FL between the second metal wiring layer M2 and the third metal wiring layer M3. The free layer FL of the magnetic tunnel junction element MTJ1 is connected to the switch SW5 via the third metal wiring layer M3. In FIG. 3, the wiring including the storage nodes ND1 and ND2 is formed in the first metal wiring layer M1, but may be formed in another metal wiring layer.

  The magnetic tunnel junction element MTJ1 shown in FIG. 3 is replaced with the magnetic tunnel junction element MTJ2, the switches SW1 and SW3 are replaced with the switches SW4 and SW2, and the storage nodes ND1 and ND2 are replaced. The structure is MTJ2 and switches SW2 and SW4. At this time, the free layer FL of the magnetic tunnel junction element MTJ2 is connected to the switches SW2 and SW6 via the third metal wiring layer M3.

  FIG. 4 shows an example of the store operation of the nonvolatile latch circuit NVLT shown in FIG. In the store operation, the store signal ST is set to logic 1, and the restore signal RS is set to logic 0. Thereby, the switches SW1 to SW4 shown in FIG. 2 are turned on, the switches SW5 and SW6 are turned off, and the nMOS transistor N3 of the latch circuit LT is turned off. FIG. 4 shows an equivalent state at this time.

  First, when the latch circuit LT holds logic 1 (ND1 = "1", ND2 = "0"), the pMOS transistor P2 and the nMOS transistor N1 are turned on, and the pMOS transistor P1 and the nMOS transistor N2 are turned off. As a result, current flows from the power supply line VDD to the ground line VSS via the magnetic tunnel junction elements MTJ1 and MTJ2, as indicated by the dashed arrows. When the amount of current flowing through each magnetic tunnel junction element MTJ1 and MTJ2 is IC, the power supply current is 2IC.

  The magnetic tunnel junction element MTJ1 is set to the high resistance state RH because a current flows from the fixed layer to the free layer. The magnetic tunnel junction element MTJ2 is set to the low resistance state RL because a current flows from the free layer to the fixed layer. That is, complementary logic held in the latch circuit LT is written to the magnetic tunnel junction elements MTJ1 and MTJ2.

  On the other hand, when the latch circuit LT holds logic 0 (ND1 = "0", ND2 = "1"), the pMOS transistor P1 and the nMOS transistor N2 are turned on, and the pMOS transistor P2 and the nMOS transistor N1 are turned off. As a result, current flows from the power supply line VDD to the ground line VSS via the magnetic tunnel junction elements MTJ1 and MTJ2, as indicated by the dashed arrows. When the amount of current flowing through each magnetic tunnel junction element MTJ1 and MTJ2 is IC, the power supply current is 2IC.

  The magnetic tunnel junction element MTJ1 is set to the low resistance state RL because a current flows from the free layer to the fixed layer. The magnetic tunnel junction element MTJ2 is set to the high resistance state RH because a current flows from the fixed layer to the free layer. That is, complementary logic held in the latch circuit LT is written to the magnetic tunnel junction elements MTJ1 and MTJ2.

  In the store operation, similarly to the nonvolatile latch circuit NVLT illustrated in FIG. 1, the magnetic tunnel junction elements MTJ1 and MTJ2 are connected in parallel between the power supply line VDD and the ground line VSS. Therefore, the store operation can be executed using the normal power supply voltage VDD as the write voltage.

  FIG. 5 shows an example of the restore operation of the nonvolatile latch circuit NVLT shown in FIG. In the restore operation, the store signal ST is set to logic 0. The restore signal RS is set to logic 1 and then set to logic 0. Thereby, the switches SW2 and SW3 shown in FIG. 2 are turned off, and the switches SW1, SW4, SW5 and SW6 and the nMOS transistor N3 of the latch circuit LT are temporarily turned on. FIG. 4 shows an equivalent state when the switches SW1, SW4, SW5, and SW6 are on. The restore operation of this embodiment is executed when the power supply voltage VDD is a normal voltage (1.2 V in this example). As a result, the restore operation can be executed reliably and stably.

  First, the nMOS transistor N3 is turned on by a logical 1 restore signal RS. The inputs and outputs of the pair of CMOS inverters of the latch circuit LT are connected to each other, and the voltages of the storage nodes ND1 and ND2 are approximately one half of the power supply voltage. Thus, the nMOS transistor N3 functions as a short switch that connects the storage nodes ND1 and ND2 to each other.

  When the magnetic tunnel junction element MTJ1 is set to the high resistance state RH and the magnetic tunnel junction element MTJ2 is set to the low resistance state RL, the current IC1 is supplied from the storage node ND1 through the magnetic tunnel junction element MTJ1 to the ground line VSS. Flowing into. Further, a current IC2 larger than the current IC1 flows from the storage node ND2 to the ground line VSS via the magnetic tunnel junction element MTJ2. As a result, the voltage VH of the storage node ND1 becomes higher than the voltage VL of the storage node ND2.

  Next, when the restore signal RS is changed to logic 0, SW1, SW4, SW5, SW6 and the nMOS transistor N3 are turned off. When the nMOS transistor N3 is turned off, the latch circuit LT starts a normal operation, and latches logic 1 according to the voltage levels of the storage nodes ND1 and ND2. That is, complementary logic is read from the magnetic tunnel junction elements MTJ1 and MTJ2, and written back to the latch circuit LT.

  On the other hand, when the magnetic tunnel junction element MTJ1 is set to the low resistance state RL and the magnetic tunnel junction element MTJ2 is set to the high resistance state RH, the current IC2 is grounded from the storage node ND1 via the magnetic tunnel junction element MTJ1. Flows on line VSS. Further, a current IC1 smaller than the current IC2 flows from the storage node ND2 to the ground line VSS through the magnetic tunnel junction element MTJ2. As a result, the voltage VL of the storage node ND1 becomes higher than the voltage VH of the storage node ND2.

  Thereafter, when the restore signal RS is changed to logic 0, the latch circuit LT starts normal operation as described above, and latches logic 0 according to the voltage levels of the storage nodes ND1 and ND2. That is, complementary logic is read from the magnetic tunnel junction elements MTJ1 and MTJ2, and written back to the latch circuit LT.

  FIG. 6 shows an example of normal operation of the nonvolatile latch circuit NVLT shown in FIG. In normal operation, store signal ST and restore signal RS are both set to logic zero. Thereby, the switches SW1 to SW6 shown in FIG. 2 are turned off, and the nMOS transistor N3 of the latch circuit LT is turned off. FIG. 4 shows an equivalent state at this time.

  Since the switches SW1-SW6 are turned off, both ends of the magnetic tunnel junction element MTJ1 and both ends of the magnetic tunnel junction element MTJ2 are set in a floating state. That is, the connection between the magnetic tunnel junction elements MTJ1 and MTJ2 and the latch circuit LT is cut off, and the magnetic tunnel junction elements MTJ1 and MTJ2 are disconnected from the latch circuit LT. In this state, the latch circuit LT latches the logic of the input data DT supplied from the outside of the nonvolatile latch circuit NVLT, inverts the latched logic, and outputs it as output data / DT.

  In normal operation, the current flowing through the storage nodes ND1 and ND2 due to the rewriting of the logic of the latch circuit LT does not flow through the magnetic tunnel junction elements MTJ1 and MTJ2. As a result, like the nonvolatile latch circuit NVLT shown in FIG. 1, it is possible to prevent the magnetization characteristics of the magnetic tunnel junction elements MTJ1 and MTJ2 from deteriorating during normal operation.

  FIG. 7 shows an example of the operation of the semiconductor integrated circuit having the nonvolatile latch circuit NVLT shown in FIG. For example, a semiconductor integrated circuit is a logic circuit including a latch circuit such as a flip-flop. The nonvolatile latch circuit NVLT shown in FIG. 2 is used as at least one of the latch circuits in the logic circuit. For example, the semiconductor integrated circuit includes a signal generation circuit that generates a store signal ST when power is turned on and generates a restore signal RS when power is turned off.

  The magnetic tunnel junction elements MTJ1 and MTJ2 of the nonvolatile latch circuit NVLT hold complementary logic before power-on. The resistance value RMTJ1 of the magnetic tunnel junction element MTJ1 and the resistance value RMTJ2 of the magnetic tunnel junction element MTJ2 are set to the MTJ2 high resistance state RH or the low resistance state RL (FIG. 7A). First, the power-on PON gradually increases the power supply voltage VDD supplied to the semiconductor integrated circuit (FIG. 7B). One and the other of the storage nodes ND1 and ND2 of the nonvolatile latch circuit NVLT change to logic 0 (= VDD) and logic 1 (= VSS) regardless of the logic held in the magnetic tunnel junction elements MTJ1 and MTJ2. (FIG. 7 (c)).

  The signal generation circuit temporarily activates the restore signal RS after the power supply voltage VDD rises to a predetermined value (for example, 1.2 V) (FIG. 7 (d)). While the restore signal RS is activated, the voltages of the storage nodes ND1 and ND2 are approximately half of the power supply voltage VDD (VDD / 2 = 0.6V). At this time, currents IMTJ1 and IMTJ2 flow in the magnetic tunnel junction elements MTJ1 and MTJ2, respectively.

  The voltages of the storage nodes ND1 and ND2 are set to almost half of the power supply voltage VDD while the restore signal RS is activated. As a result, the current values IMTJ1 and IMTJ2 flowing in the magnetic tunnel junction elements MTJ1 and MTJ2 can be made smaller than the write current values IP and IAP necessary for changing the resistance values of the magnetic tunnel junction elements MTJ1 and MTJ2 (FIG. 7). (E)). Specifically, the current IC2 flowing through the magnetic tunnel junction element MTJ1 (or MTJ2) in the low resistance state shown in FIG. 5 is smaller than the write current IP for setting the high resistance state. Therefore, it is possible to prevent the resistance values of the magnetic tunnel junction elements MTJ1 and MTJ2 from being changed by the currents IMTJ1 and IMTJ2 during the restore period RESTR.

  When the restore signal RS is deactivated, the complementary logic held in the magnetic tunnel junction elements MTJ1 and MTJ2 is supplied to the latch circuit LT according to the voltage difference between the storage nodes ND1 and ND2, as described in FIG. Read out. As a result, the voltages of the storage nodes ND1 and ND2 change to the power supply voltage VDD or the ground voltage VSS (FIG. 7 (f)). That is, a restore operation is executed.

  Thereafter, in the normal operation period OP, the semiconductor integrated circuit performs a normal operation as a system. The logic of the latch circuit LT of the nonvolatile latch circuit NVLT is rewritten during normal operation (FIG. 7 (g)). The store signal ST and the restore signal RS are inactivated to logic 0 during the normal operation period OP (FIG. 7 (h)). Therefore, as shown in FIG. 6, the magnetic tunnel junction elements MTJ1 and MTJ2 are disconnected from the latch circuit LT and are not affected by the operation of the latch circuit LT. In other words, the current accompanying the operation of the latch circuit LT does not flow through the magnetic tunnel junction elements MTJ1 and MTJ2. As a result, the resistance values of the magnetic tunnel junction elements MTJ1 and MTJ2 can be prevented from changing during the normal operation period OP, and the reliability of the semiconductor integrated circuit including the nonvolatile latch circuit NVLT and the nonvolatile latch circuit NVLT can be improved.

  After the normal operation is completed, the signal generation circuit activates the store signal ST in the store period STR (FIG. 7 (i)). As a result, the store operation is executed as described in FIG. That is, the magnetic tunnel junction elements MTJ1 and MTJ2 are connected in parallel and opposite to each other between the power supply terminal VDD and the ground terminal VSS of the latch circuit LT. Since the power supply voltage VDD is independently applied to each of the magnetic tunnel junction elements MTJ1 and MTJ2, the current value flowing through the magnetic tunnel junction elements MTJ1 and MTJ2 can be easily made larger than the write current values IP and IAP. Therefore, the complementary logic held in the latch circuit LT can be reliably written as the resistance values of the magnetic tunnel junction elements MTJ1 and MTJ2 by using the power supply voltage VDD supplied to the latch circuit LT.

  As described above, in this embodiment, the current values IMTJ1 and IMTJ2 at the time of the restore operation can be made smaller than the write current values IP and IAP by the single power supply voltage VDD, and the current values IMTJ1 and IMTJ2 at the time of the store operation It can be larger than IP and IAP. In the store operation, since the magnetic tunnel junction elements MTJ1 and MTJ2 are connected in parallel, the write voltage can be reduced as compared with the circuit configuration connected in series.

  After the store operation is completed, the power supply voltage VDD gradually decreases due to the power-off POFF (FIG. 7 (j)). Along with this, the logic held in the latch circuit LT is gradually lost (FIG. 7 (k)). However, the logic held in the latch circuit LT is held by the magnetic tunnel junction elements MTJ1 and MTJ2 even after power-off (FIG. 7 (l)).

  Thereafter, when the power supply voltage VDD rises again due to power-on PON, the semiconductor integrated circuit performs a restore operation, and reads the logic held in the magnetic tunnel junction elements MTJ1 and MTJ2 to the latch circuit LT (FIG. 7 (m )).

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by forming the nMOS transistor N3 in the switch circuit SW, the restore operation can be executed in a state where the power supply voltage VDD is supplied to the nonvolatile latch circuit NVLT. As a result, the restore operation can be executed reliably and stably.

  FIG. 8 shows an example of a nonvolatile latch circuit NVLT in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the switch circuit SW is different from the switch circuit SW shown in FIG. Further, an inverter IV4 for generating a restore signal / RS is newly formed. Other configurations of the nonvolatile latch circuit NVLT are the same as those in FIG. In FIG. 8, the positions of the magnetic tunnel junction elements MTJ1 and MTJ2 are opposite to those in FIG.

  The switch SW1 is turned on when the OR signal OR is at a high level and the OR signal / OR is at a low level, and connects one end (fixed layer side) of the magnetic tunnel junction element MTJ1 to the storage node ND1. The switch SW2 is turned on when the OR signal OR is at a high level and the OR signal / OR is at a low level, and connects the other end (free layer side) of the magnetic tunnel junction element MTJ2 to the storage node ND1. The switch SW3 is turned on when the store signals ST and / ST are activated, and connects the other end (free layer side) of the magnetic tunnel junction element MTJ1 to the storage node ND2. The switch SW4 is turned on when the store signals ST and / ST are activated, and connects one end (the fixed layer side) of the magnetic tunnel junction element MTJ2 to the storage node ND2.

  The nMOS transistor of the switch SW5 has an nMOS transistor having a drain connected to the other end of the magnetic tunnel junction element MTJ1, a source connected to the ground line VSS, and a gate connected to the restore signal line RS. The nMOS transistor of the switch SW6 has a pMOS transistor having a drain connected to one end of the magnetic tunnel junction element MTJ2, a source connected to the power supply line VDD, and a gate connected to the restore signal line / RS.

  For example, the store signal ST and the restore signal RS are generated outside the nonvolatile latch circuit NVLT. The OR circuit OR1 and the inverters IV3 and IV4 may be formed outside the nonvolatile latch circuit NVLT. Further, when the plurality of nonvolatile latch circuits NVLT are formed in the semiconductor integrated circuit, the OR circuit OR1 and the inverters IV3 and IV4 may be provided in common to the plurality of nonvolatile latch circuits NVLT.

  FIG. 9 shows an example of the restore operation of the nonvolatile latch circuit NVLT shown in FIG. Note that the store operation and the normal operation are performed in the same manner as in FIGS. The operation of the semiconductor integrated circuit having the nonvolatile latch circuit NVLT is executed in the same manner as in FIG.

  As in FIG. 5, in the restore operation, the store signal ST is set to logic 0, the restore signal RS is set to logic 1, and then set to logic 0. Thereby, the switches SW3 and SW4 shown in FIG. 8 are turned off, and the switches SW1, SW2, SW5 and SW6 and the nMOS transistor N3 of the latch circuit LT are temporarily turned on. FIG. 4 shows an equivalent state when the switches SW1, SW2, SW5, SW6 and the nMOS transistor N3 are on.

  Similarly to FIG. 5, when the nMOS transistor N3 is turned on, the storage nodes ND1 and ND2 are connected to each other, and the voltages of the storage nodes ND1 and ND2 tend to become approximately VDD / 2. On the other hand, while the restore signal RS is activated to logic 1, the magnetic tunnel junction elements MTJ2 and MTJ1 are connected in series between the power supply line VDD and the ground line VSS. An intermediate node connected to the free layer side of the magnetic tunnel junction element MTJ2 and the fixed layer side of the magnetic tunnel junction element MTJ1 generates a divided voltage according to the resistance values of the magnetic tunnel junction elements MTJ1 and MTJ2. As a result, the voltage of the storage storage node ND1 becomes a voltage higher than the voltage VDD / 2 or lower than the voltage VDD / 2 depending on the resistance division by the magnetic tunnel junction elements MTJ1 and MTJ2.

  For example, when the magnetic tunnel junction element MTJ1 is in the high resistance state RH and the magnetic tunnel junction element MTJ2 is in the low resistance state RL, the voltage of the storage node ND1 becomes higher than VDD / 2 (left side in FIG. 9). When the magnetic tunnel junction element MTJ1 is in the low resistance state RL and the magnetic tunnel junction element MTJ2 is in the high resistance state RH, the voltage of the storage node ND1 is lower than VDD / 2 (right side in FIG. 9). On the other hand, the voltage of the storage node ND2 is substantially the voltage VDD / 2 regardless of the resistance state of the magnetic tunnel junction elements MTJ1 and MTJ2. Note that the current flowing through the magnetic tunnel junction element MTJ1 or MTJ2 in the low resistance state needs to be smaller than the write current IAP shown in FIG. 7 in order to prevent the current from flowing into the high resistance state. Since the direction of the current flowing through the magnetic tunnel junction element MTJ1 or MTJ2 in the high resistance state is the same as the direction of the current necessary for setting the high resistance state, the current value is not limited.

  When restore signal RS is changed to logic 0, switches SW1-SW6 and nMOS transistor N3 of latch circuit LT are turned off. The magnetic tunnel junction elements MTJ1 and MTJ2 are disconnected from the power supply line VDD, the ground line VSS, and the storage node ND1. When the nMOS transistor N3 is turned off, the latch circuit LT starts normal operation, and latches the logic according to the voltage difference between the storage nodes ND1 and ND2. For example, when the magnetic tunnel junction element MTJ1 is in the high resistance state RH and the magnetic tunnel junction element MTJ2 is in the low resistance state RL, the voltage of the storage node ND1 is the power supply voltage VDD and the voltage of the storage node ND2 is the ground voltage VSS. . When the magnetic tunnel junction element MTJ1 is in the low resistance state RL and the magnetic tunnel junction element MTJ2 is in the high resistance state RH, the voltage of the storage node ND1 becomes the ground voltage VSS, and the voltage of the storage node ND2 becomes the power supply voltage VDD. That is, complementary logic is read from the magnetic tunnel junction elements MTJ1 and MTJ2, and returned to the latch circuit LT. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 10 shows an example of a nonvolatile latch circuit NVLT in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the latch circuit LT is different from the latch circuit LT shown in FIG. Other configurations of the nonvolatile latch circuit NVLT are the same as those in FIG.

  The latch circuit LT of this embodiment is a clock synchronous type, and is disposed between the switch SW7 disposed between the input terminal DT and the input of the inverter IV1, and between the output of the inverter IV2 and the input of the inverter IV1. And a switch SW8. For example, the switches SW7 and SW8 have CMOS transfer gates. The clocks CK and / CK are complementary signals.

  Switch SW7 is turned on when clock CK is logic 1 and clock / CK is logic 0, and transmits input data DT to the input of inverter IV1. Inverter IV1 inverts the logic of input data DT and outputs it as output data / DT to the output terminal / DT and the input of inverter IV2. At this time, since the switch SW8 is off, the latch operation is not performed.

  The switch SW8 is turned on when the clock CK is logic 0 and the clock / CK is logic 1, and connects the output of the inverter IV2 to the input of the inverter IV1. At this time, the input data DT is latched by the latch circuit LT. Since the switch SW7 is turned off when the switch SW8 is turned on, reception of new input data DT is prohibited.

  The store operation and the restore operation of the nonvolatile latch circuit NVLT shown in FIG. 10 are the same as those in FIGS. 4 and 6 except that the operation is performed when the clock CK is logic 0. The operation of the semiconductor integrated circuit having the nonvolatile latch circuit NVLT is executed in the same manner as in FIG. When the plurality of nonvolatile latch circuits NVLT are formed in the semiconductor integrated circuit, the clocks CK and / CK may be supplied in common to the plurality of nonvolatile latch circuits NVLT and are supplied for each nonvolatile latch circuit NVLT. May be. Further, the nonvolatile latch circuit NVLT may be formed by using the switch SW shown in FIG. 8 instead of the switch SW shown in FIG.

  For example, the store signal ST and the restore signal RS are generated outside the nonvolatile latch circuit NVLT. The OR circuit OR1 and the inverter IV3 may be formed outside the nonvolatile latch circuit NVLT. Further, when the plurality of nonvolatile latch circuits NVLT are formed in the semiconductor integrated circuit, the OR circuit OR1 and the inverter IV3 may be provided in common to the plurality of nonvolatile latch circuits NVLT.

  FIG. 11 shows an example of normal operation of the nonvolatile latch circuit NVLT shown in FIG. In this example, the clocks CK and / CK are periodically generated during the normal operation period OP. The clocks CK and / CK may be generated when a latch operation is necessary.

  First, in synchronization with the rising edge of the clock CK, the switch SW7 shown in FIG. 10 is turned on and the switch SW8 is turned off. The inverter IV1 receives the input data DT, inverts the logic (D1, D2, D3) of the received input data DT, and outputs the output data / DT (/ D1, / D2, / D3).

  Next, the switch SW7 shown in FIG. 10 is turned off and the switch SW8 is turned on in synchronization with the falling edge of the clock CK. When the switch SW8 is turned on, the output of the inverter IV2 is connected to the input of the inverter IV1, and the logic (D1, D2, D3) of the input data DT is latched. Since the switch SW7 is turned off while the clock CK is logic 0, a new change in the input data DT is not transmitted to the inverter IV1. After the normal operation period OP is completed, the clocks CK and / CK are stopped, and the store operation is executed in the store period STR as in FIG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, the nonvolatile latch circuit NVLT can be formed using the clock synchronous type latch circuit LT.

  FIG. 12 shows an example of a nonvolatile latch circuit NVLT in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The nonvolatile latch circuit NVLT of this embodiment is formed as a master / slave flip-flop. The operation of the semiconductor integrated circuit having the nonvolatile latch circuit NVLT shown in FIG. 12 is executed in the same manner as in FIG.

  The nonvolatile latch circuit NVLT includes a master latch circuit MLT, a slave latch circuit SLT, magnetic tunnel junction elements MTJ1 and MTJ2, and a switch circuit SW. For example, the switch circuit SW is the same as the switch circuit SW shown in FIGS. 2 and 10 and is connected to the storage nodes ND1 and ND2 of the slave latch circuit SLT. Note that the switch circuit SW shown in FIG. 8 or the switch circuit SW shown in FIG. 13 may be used as the switch circuit SW. The switch circuit SW may be connected to the master latch circuit MLT. Two switch circuits SW may be connected to the master latch circuit MLT and the slave latch circuit SLT, respectively.

  The master latch circuit MLT has a switch SW9 that transmits data obtained by inverting the logic of the input data IN to the input of the inverter IV1, and a switch SW10 that connects the output of the inverter IV2 to the input of the inverter IV1. For example, the switches SW9 and SW10 have CMOS transfer gates. The master latch circuit MLT outputs the input data IN as the input data DT when the clock CK is logic 1, and latches the logic of the input data IN and accepts new input data IN when the clock CK is logic 0. Is prohibited.

  The slave latch circuit SLT has a switch SW11 that transmits the logic of the input data DT to the input of the inverter IV1, and a switch SW12 that connects the output of the inverter IV2 to the input of the inverter IV1. For example, the switches SW11 and SW12 have a CMOS transfer gate. The slave latch circuit SLT inverts the logic of the input data DT when the clock CK is logic 0 and outputs it as output data / DT. When the clock CK is logic 1, the slave latch circuit SLT latches the logic of the input data DT. Accepting input data DT is prohibited. The slave latch circuit SLT is the same circuit as the latch circuit LT shown in FIG. 10 except that the logics of the clocks CK and / CK received by the switches SW11 and SW12 are reversed.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, the nonvolatile latch circuit NVLT can be formed using a master-slave flip-flop.

  FIG. 13 shows an example of a nonvolatile latch circuit NVLT in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the latch circuit LT includes a pMOS transistor P3 that connects the inverters IV1 and IV2. The switches SW5 and SW6 of the switch circuit SW have pMOS transistors, respectively. Further, an inverter IV4 for generating a restore signal / RS is newly formed.

  One end (free layer side) of the magnetic tunnel junction element MTJ1 is connected to the storage node ND1 via the switch SW1, and the other end (fixed layer side) of the magnetic tunnel junction element MTJ1 is connected to the storage node ND2 via the switch SW3. It is connected. One end (free layer side) of the magnetic tunnel junction element MTJ2 is connected to the storage node ND2 via the switch SW4, and the other end (fixed layer side) of the magnetic tunnel junction element MTJ1 is connected to the storage node ND1 via the switch SW2. It is connected. That is, the direction of the magnetic tunnel junction element MTJ1 is opposite to the direction of the magnetic tunnel junction element MTJ1 in FIG. The direction of the magnetic tunnel junction element MTJ2 is opposite to the direction of the magnetic tunnel junction element MTJ2 in FIG. Other configurations of the nonvolatile latch circuit NVLT are the same as those in FIG.

  The pMOS transistor P3 of the latch circuit LT has a source and a drain connected to the storage nodes ND1 and ND2, respectively, and a gate connected to the restore signal line / RS. Instead of the latch circuit LT shown in FIG. 13, the latch circuit LT shown in FIG. 2 having an nMOS transistor N3 that receives the restore signal RS at the gate may be formed.

  In the switch circuit SW, the pMOS transistor of the switch SW5 has a drain connected to the other end (fixed layer side) of the magnetic tunnel junction element MTJ1, a source connected to the power supply line VDD, and a gate connected to the restore signal line / RS. ing. The pMOS transistor of the switch SW6 has a drain connected to the other end of the magnetic tunnel junction element MTJ2, a source connected to the power supply line VDD, and a gate connected to the restore signal line / RS.

  For example, the store signal ST and the restore signal RS are generated outside the nonvolatile latch circuit NVLT. The OR circuit OR1 and the inverters IV3 and IV4 may be formed outside the nonvolatile latch circuit NVLT. Further, when the plurality of nonvolatile latch circuits NVLT are formed in the semiconductor integrated circuit, the OR circuit OR1 and the inverters IV3 and IV4 may be provided in common to the plurality of nonvolatile latch circuits NVLT.

  FIG. 14 shows an example of the store operation of the nonvolatile latch circuit NVLT shown in FIG. Detailed descriptions of the same operations as those in FIG. 4 are omitted. The logic of the store signal ST and the restore signal RS during the store operation is the same as in FIG. In this embodiment, the directions of the magnetic tunnel junction elements MTJ1 and MTJ2 are opposite to those in FIG. For this reason, when logic 1 is held in the latch circuit LT (ND1 = “1”, ND2 = “0”), the magnetic tunnel junction element MTJ1 is set to the low resistance state RL, and the magnetic tunnel junction element MTJ2 is high. Resistance state RH is set. When logic 0 is held in the latch circuit LT (ND1 = "0", ND2 = "1"), the magnetic tunnel junction element MTJ1 is set to the high resistance state RH, and the magnetic tunnel junction element MTJ2 is set to the low resistance state RL. Set to

  FIG. 15 shows an example of the restore operation of the nonvolatile latch circuit NVLT shown in FIG. Detailed descriptions of the same operations as those in FIG. 5 are omitted. The logic of the store signal ST and the restore signal RS during the restore operation is the same as in FIG. First, when the restore signal RS is set to logic 1, the restore signal / RS changes to logic 0. The pMOS transistor P3 is turned on in response to the logical 0 restore signal / RS, and the inputs and outputs of the pair of CMOS inverters of the latch circuit LT are connected to each other. As a result, the voltages of the storage nodes ND1 and ND2 become approximately VDD / 2.

  The switches SW5 and SW6 shown in FIG. 13 are turned on by a logical 0 restore signal / RS. When the restore signal RS is set to logic 1, the OR signal OR is set to logic 1 and SW1 and SW4 are turned on. Accordingly, the power supply line VDD and the storage node ND1 are connected via the switch SW5, the magnetic tunnel junction element MTJ1, and the switch SW1. Similarly, the power supply line VDD and the storage node ND2 are connected via the switch SW6, the magnetic tunnel junction element MTJ2, and the switch SW4. Then, currents IC1 or IC2 corresponding to the resistance values of the magnetic tunnel junction elements MTJ1 and MTJ2 are supplied to the storage nodes ND1 and ND2, respectively.

  The storage node ND1 (or ND2) connected to the magnetic tunnel junction element MTJ1 (or MTJ2) in the low resistance state RL becomes the voltage VH and is connected to the magnetic tunnel junction element MTJ2 (or MTJ1) in the high resistance state RH. The storage node ND2 (or ND1) becomes a voltage VL lower than the voltage VH. Thereafter, as in FIG. 5, the restore signal RS is changed to logic 0, and the latch circuit LT latches the logic according to the voltage levels of the storage nodes ND1 and ND2. The operation of the semiconductor integrated circuit having the nonvolatile latch circuit NVLT is executed in the same manner as in FIG. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 16 shows an example of electrical characteristics of the variable resistance element formed in the nonvolatile latch circuit NVLT in another embodiment. For example, the resistance change element having the characteristics shown in FIG. 16 is an element formed in a resistance change memory (ReRAM).

A pair of resistance change elements having the characteristics shown in FIG. 16 is arranged instead of the magnetic tunnel junction elements MTJ1 and MTJ2 shown in FIGS. 1, 2, 8, 10, and 13. Although not particularly limited, the resistance change element is formed by stacking an electrode formed of SrRuO ₃ , an SrZrO ₃ film, and an electrode formed of Au.

  In FIG. 16, the horizontal axis indicates a write voltage VWR that is a voltage difference applied to both ends of the variable resistance element. The vertical axis represents the write current IWR that is a current that flows in accordance with the voltage applied across the resistance change element. For example, when a write voltage VWR of 1.0 V or higher is applied to the variable resistance element in the low resistance state RL, the write current IWR initially flowing by about 40 μA decreases to 10 μA or lower as indicated by the solid line arrow. That is, the resistance state of the variable resistance element changes to the high resistance state RH by applying the write voltage VWR of 1.0V.

  Similarly, when a write voltage VWR of −1.0 V or less is applied to the variable resistance element in the high resistance state RH, the write current IWR that initially flows about −7 μA increases to about −40 μA, as indicated by the dashed arrow. To do. That is, the resistance state of the variable resistance element changes to the low resistance state RL by applying the write voltage VWR of −1.0V. Thereby, the store operation of the above-described embodiment can be realized. With a voltage difference smaller than 1.0 V, the resistance state of the resistance change element does not change. For this reason, the restore operation of the above-described embodiment can be realized.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, the nonvolatile latch circuit NVLT can be formed using a resistance change element formed in a resistance random access memory (ReRAM).

  FIG. 17 shows an example of a semiconductor integrated circuit SEM on which the above-described nonvolatile latch circuit NVLT is mounted. For example, the semiconductor integrated circuit SEM is formed by alternately arranging a column of nonvolatile latch circuits NVLT and a combinational circuit CL which is a kind of logic circuit. Each combinational circuit CL is formed by combining logic gates such as NAND gates, NOR gates, and inverters.

  The semiconductor integrated circuit SEM has a signal generation circuit SGEN that generates control signals such as the store signal ST and the restore signal RS shown in FIG. As shown in FIG. 7, the semiconductor integrated circuit SEM performs a restore operation at power-on when the supply of the power supply voltage VDD is started, and reads the logic from the variable resistance element of each nonvolatile latch circuit NVLT to the latch circuit LT. . Thereby, the state of the combinational circuit CL is restored to the state at the previous power-off. Then, the normal operation is executed after the restore operation.

  As shown in FIG. 7, the semiconductor integrated circuit SEM performs a store operation at the time of power-off when the supply of the power supply voltage VDD is stopped, and writes logic from the latch circuit LT of each nonvolatile latch circuit NVLT to the variable resistance element. . Thereby, the semiconductor integrated circuit SEM can maintain the state before the power is turned off, and can immediately continue the original operation when the power is turned on. In addition, since battery backup or the like is unnecessary, power consumption when the power is turned off can be reduced to zero.

  FIG. 18 shows another example of the semiconductor integrated circuit SEM on which the nonvolatile latch circuit NVLT described above is mounted. The same elements as those in FIG. 17 are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor integrated circuit SEM of this embodiment employs so-called power gating technology.

  The power supply line VDD is an internal power supply line, and is connected to the external power supply line EVDD via the power switch VDSW. The ground line VSS is an internal ground line, and is connected to the external ground line EVSS via the ground switch VSSW. The power switch VDSW has a pMOS transistor that receives a low power signal / LP at its gate. The ground switch VSSW has an nMOS transistor that receives a low power signal LP at its gate. The low power signals LP and / LP are set to logic 0 and logic 1, respectively, when the operation of the circuit block shown in FIG. 18 is stopped, and when the circuit block shown in FIG. Respectively.

  Although not particularly limited, the semiconductor integrated circuit SEM has a plurality of circuit blocks similar to those in FIG. When the operation of the circuit block is started, the low power signals LP and / LP corresponding to the circuit block are set to logic 1 and logic 0, respectively, and the power supply voltage VDD and the ground voltage VSS are supplied to the circuit block. . The signal generation circuit SGEN is formed for each circuit block, and activates the restore signal RS when the power supply voltage VDD rises to a predetermined value. The operation shown in FIG. 7 shows the operation of each circuit block.

  Thereby, the restore operation of each nonvolatile latch circuit NVLT is executed, and the logic is read from the variable resistance element of each nonvolatile latch circuit NVLT to the latch circuit LT. Further, similarly to FIG. 17, the store operation of each nonvolatile latch circuit NVLT is executed when each circuit block is powered off, and logic is written from the latch circuit LT of each nonvolatile latch circuit NVLT to the variable resistance element.

  By forming the above-described nonvolatile latch circuit NVLT in the semiconductor integrated circuit SEM that employs power gating technology, a store operation and a restore operation can be executed for each circuit block. As a result, the power consumption of the semiconductor integrated circuit SEM can be finely controlled, and the power consumption of the entire semiconductor integrated circuit SEM can be reduced. Furthermore, since the operation can be started immediately after power-on, the performance of the semiconductor integrated circuit SEM can be improved.

  FIG. 19 shows another example of the semiconductor integrated circuit SEM on which the nonvolatile latch circuit NVLT described above is mounted. The same elements as those in FIG. 17 are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor integrated circuit SEM of this embodiment is, for example, an FPGA (Field Programmable Gate Array). The semiconductor integrated circuit SEM has a plurality of logic blocks LBLK, a wiring channel WCH wired around the logic block LBLK, and a switch matrix SWM formed at the intersection of the wiring channels WCH.

  FIG. 20 shows an example of the switch matrix SWM shown in FIG. The switch matrix SWM has a plurality of switch groups SWG formed at the intersections of the respective wirings of the wiring matrix SWM.

  Each switch group SWG has six selection switches SSW1 to SSW6 and six nonvolatile latch circuits NVLT for controlling on / off of these selection switches SSW1 to SSW6. For example, each selection switch SSW1-6 has a CMOS transfer gate, and is turned on or off according to the logic of the output data / DT output from each nonvolatile latch circuit NVLT. Each nonvolatile latch circuit NVLT is one of the nonvolatile latch circuits NVLT described above, and operates according to the store signal ST and the restore signal RS shown in FIG.

  For example, when the selection switches SSW1 and SSW6 are turned on and the selection switches SSW2 to SSW5 are turned off, the wiring WL extending on the left side and the wiring WU extending on the upper side in FIG. 20 are connected to each other, and the wiring WD extending on the lower side and the right side Are connected to each other. Alternatively, when the selection switches SSW3 to SSW4 are turned on and the selection switches SSW1, SSW2, SSW5, and SSW6 are turned off, the wirings WL and WR are connected to each other, and the wirings WU and WD are connected to each other.

  FIG. 21 shows an example of the logical block LBLK shown in FIG. The logic block LBLK has a plurality of logic cells LCEL. Each logic cell LCEL has a lookup table LUT and a flip-flop FF.

  The lookup table LUT has an address decoder ADEC, eight nonvolatile latch circuits NVLT, eight AND circuits, and an OR circuit. The address decoder ADEC decodes the logic of the 3-bit addresses A2, A1, and A0 and outputs the decoding result to the AND circuit. Each nonvolatile latch circuit NVLT outputs the held logic as output data / DT to a corresponding AND circuit. The OR circuit sets the output signal OUT to logic 1 when any of the AND circuits outputs logic 1.

  The nonvolatile latch circuit NVLT outputs the logic 1 output data / DT when storing the logic 0, as described with reference to FIGS. For example, when the logic 0 is stored in the nonvolatile latch circuit NVLT corresponding to the addresses A2, A1, and A0 = “111” and the logic 1 is stored in the other nonvolatile latch circuit NVLT, the lookup table LUT is ANDed. Operates as a circuit. By storing logic 1 in the nonvolatile latch circuit NVLT corresponding to the addresses A2, A1, A0 = “000” and storing logic 0 in the other nonvolatile latch circuit NVLT, the lookup table LUT can be used as an OR circuit. Operate. The look-up table LUT may include an address decoder ADEC that receives a 4-bit address, 16 nonvolatile latch circuits NVLT, and 16 AND circuits.

  Each nonvolatile latch circuit NVLT operates in accordance with the store signal ST and the restore signal RS shown in FIG. For example, the input terminals (DT in FIG. 1 and the like) of the nonvolatile latch circuit NVLT shown in FIGS. 20 and 21 are connected to the output of the storage stage of the shift register formed in the semiconductor integrated circuit SEM, respectively.

  First, when logic is formed in the FPGA, data is latched in the latch circuit LT of the nonvolatile latch circuit NVLT via the shift register. This operation is the same as the operation in the normal operation period OP shown in FIG. However, the latch operation to the latch circuit LT may be performed once. After the data is latched by the latch circuit LT, the latched data is written to the resistance change elements (for example, magnetic tunnel junction elements MTJ1 and MTJ2) by the store signal ST. This operation is the same as the operation in the store period STR shown in FIG. Thereby, the logic of the FPGA is formed.

  Thereafter, each time the FPGA is powered on, a restore signal RS is generated, data held in the variable resistance element of the nonvolatile latch circuit NVLT is read out to the latch circuit LT, and the logic of the FPGA is generated. This operation is the same as the operation in the restore period RESTR shown in FIG. The FPGA implements at least a part of the functions of the system.

  In an FPGA formed using the nonvolatile latch circuit NVLT, it is not necessary to load data for forming logic from an EEPROM or the like every time the power is turned on. Therefore, the system operation can be executed immediately after power-on.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A latch circuit including complementary first and second storage nodes;
A first resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
A second resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
A switch circuit for connecting the first and second variable resistance elements to a latch circuit,
The non-volatile latch circuit, wherein the switch circuit cuts off the connection between the first and second variable resistance elements and the latch circuit during a normal operation in which logic is written to the latch circuit from the outside.
(Appendix 2)
The switch circuit connects one end of the first resistance change element and the other end of the second resistance change element during a store operation of writing the logic held in the latch circuit to the first and second resistance change elements. The nonvolatile latch circuit according to claim 1, wherein the nonvolatile memory circuit is connected to a first storage node, and the other end of the first variable resistance element and one end of the second variable resistance element are connected to the second storage node.
(Appendix 3)
In the restore operation for returning the logic held in the first and second variable resistance elements to the latch circuit, the switch circuit connects the other end of the first variable resistance element to one of a high level voltage line and a low level voltage line. One end of the first variable resistance element is connected to the first storage node, the other end of the second variable resistance element is connected to one of the high level voltage line and the low level voltage line, and The nonvolatile latch circuit according to appendix 1 or appendix 2, wherein one end of the two-resistance change element is connected to the second storage node.
(Appendix 4)
The switch circuit is
A first switch disposed between the first storage node and one end of the first variable resistance element;
A second switch disposed between the first storage node and the other end of the second variable resistance element;
A third switch disposed between the second storage node and the other end of the first variable resistance element;
A fourth switch disposed between the second storage node and one end of the second variable resistance element;
A fifth switch disposed between the other end of the first variable resistance element and one of the high-level voltage line and the low-level voltage line;
The supplementary note 2 or supplementary note 3, further comprising: a sixth switch disposed between the other end of the second variable resistance element and one of the high-level voltage line and the low-level voltage line. Nonvolatile latch circuit.
(Appendix 5)
The switch circuit connects one end of the first variable resistance element and the other end of the second variable resistance element during a restore operation for returning the logic held in the first and second variable resistance elements to the latch circuit. Connected to the first storage node, the other end of the first variable resistance element is connected to one of a high level voltage line and a low level voltage line, and one end of the second variable resistance element is connected to the high level voltage line and the low level voltage The nonvolatile latch circuit according to appendix 1 or appendix 2, wherein the nonvolatile latch circuit is connected to the other of the wires.
(Appendix 6)
The switch circuit is
A first switch disposed between the first storage node and one end of the first variable resistance element;
A second switch disposed between the first storage node and the other end of the second variable resistance element;
A third switch disposed between the second storage node and the other end of the first variable resistance element;
A fourth switch disposed between the second storage node and one end of the second variable resistance element;
A fifth switch disposed between the other end of the first variable resistance element and one of the high-level voltage line and the low-level voltage line;
The nonvolatile memory according to appendix 2 or appendix 5, further comprising: a sixth switch disposed between one end of the second variable resistance element and the other of the high level voltage line and the low level voltage line. Latch circuit.
(Appendix 7)
6. The nonvolatile latch circuit according to appendix 3 or appendix 5, further comprising a short switch that connects the first storage node and the second storage node to each other at the start of the restore operation.
(Appendix 8)
The nonvolatile latch circuit according to appendix 4 or appendix 6, wherein the first switch, the second switch, the third switch, and the fourth switch are CMOS transfer gates.
(Appendix 9)
The nonvolatile latch circuit according to any one of appendix 1 to appendix 8, wherein the first variable resistance element and the second variable resistance element are magnetic tunnel junction elements formed in a magnetic random access memory. .
(Appendix 10)
The nonvolatile latch circuit according to any one of appendix 1 to appendix 8, wherein the first variable resistance element and the second variable resistance element are variable resistance elements formed in a variable resistance memory.
(Appendix 11)
The nonvolatile latch circuit according to any one of appendices 1 to 10, and
A logic circuit connected to the output of the nonvolatile latch circuit;
And a signal generation circuit for generating a control signal for controlling the operation of the switch circuit.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  ADEC ... address decoder; CL ... combinational circuit; DR ... diffusion layer; DT ... input terminal; / DT ... output terminal; EVDD ... external power supply line; EVSS ... external ground line; FL ... free layer; IAP, IP ... write current value IV1, IV2 inverter, LBLK logic block, LCEL logic cell, LP, LP, low power signal, LT latch circuit, LUT look-up table, M1-M3 metal wiring layer, MLT master latch circuit MTJ1, MTJ2 ... magnetic tunnel junction element; ND1, ND2 ... storage node; NVLT ... nonvolatile latch circuit; NW ... n-type well region; OP ... normal operation period; OR, OR ... OR signal; Power off; POLY polysilicon wiring layer; PON power on; PW p-type well region; RES R: Store period; RH: High resistance state; RL: Low resistance state; RMTJ1, RMTJ2: Resistance value: RS, / RS: Restore signal; SEM: Semiconductor integrated circuit; SGEN: Signal generation circuit: SLT: Slave latch circuit; SSW1-SSW6 ... selection switch; ST, / ST ... store signal; SUB ... semiconductor substrate; SW ... switch circuit; SW1-SW6 ... switch; SWG ... switch group; SWM ... switch matrix; VDD ... power supply line; VSS VSS Ground line VSSW Ground switch WCH Wiring channel WD, WL, WR, WU Wiring

Claims (8)

A latch circuit including complementary first and second storage nodes;
A first resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
A second resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
A switch circuit for connecting the first and second variable resistance elements to a latch circuit,
The switch circuit cuts off the connection between the first and second resistance change elements and the latch circuit during a normal operation in which logic is written to the latch circuit from the outside, and the logic held in the latch circuit is During a store operation for writing to the first and second variable resistance elements, one end of the first variable resistance element and the other end of the second variable resistance element are connected to the first storage node, and the other one of the first variable resistance elements A nonvolatile latch circuit comprising: an end and one end of the second variable resistance element are connected to the second storage node . In the restore operation for returning the logic held in the first and second variable resistance elements to the latch circuit, the switch circuit connects the other end of the first variable resistance element to one of a high level voltage line and a low level voltage line. One end of the first variable resistance element is connected to the first storage node, the other end of the second variable resistance element is connected to one of the high level voltage line and the low level voltage line, and The nonvolatile latch circuit according to claim 1 , wherein one end of the two-resistance change element is connected to the second storage node. The switch circuit is
A first switch disposed between the first storage node and one end of the first variable resistance element;
A second switch disposed between the first storage node and the other end of the second variable resistance element;
A third switch disposed between the second storage node and the other end of the first variable resistance element;
A fourth switch disposed between the second storage node and one end of the second variable resistance element;
A fifth switch disposed between the other end of the first variable resistance element and one of the high-level voltage line and the low-level voltage line;
And the other end of said second variable resistance element, the claim 1 or claim 2, characterized in that it comprises a sixth switch arranged between one of the high voltage line and said low voltage line The non-volatile latch circuit as described. The switch circuit connects one end of the first variable resistance element and the other end of the second variable resistance element during a restore operation for returning the logic held in the first and second variable resistance elements to the latch circuit. Connected to the first storage node, the other end of the first variable resistance element is connected to one of a high level voltage line and a low level voltage line, and one end of the second variable resistance element is connected to the high level voltage line and the low level voltage The nonvolatile latch circuit according to claim 1 , wherein the nonvolatile latch circuit is connected to the other of the lines. The switch circuit is
A first switch disposed between the first storage node and one end of the first variable resistance element;
A second switch disposed between the first storage node and the other end of the second variable resistance element;
A third switch disposed between the second storage node and the other end of the first variable resistance element;
A fourth switch disposed between the second storage node and one end of the second variable resistance element;
A fifth switch disposed between the other end of the first variable resistance element and one of the high-level voltage line and the low-level voltage line;
One end of said second variable resistance element, the high level voltage line and said low voltage line other that it comprises a sixth switch arranged between the characterized claims 1 or claim 4, wherein the Non-volatile latch circuit.   A latch circuit including complementary first and second storage nodes;
  A first resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
  A second resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
  A switch circuit for connecting the first and second variable resistance elements to a latch circuit;
  With
  The switch circuit cuts off the connection between the first and second resistance change elements and the latch circuit during normal operation in which logic is written to the latch circuit from the outside, and is held by the first and second resistance change elements In a restore operation for returning the logic being returned to the latch circuit, the other end of the first resistance change element is connected to one of a high level voltage line and a low level voltage line, and one end of the first resistance change element is connected to the first resistance change element. Connecting to the storage node, connecting the other end of the second variable resistance element to one of the high-level voltage line and the low-level voltage line, connecting one end of the second variable resistance element to the second storage node,
  The switch circuit is
  A first switch disposed between the first storage node and one end of the first variable resistance element;
  A second switch disposed between the first storage node and the other end of the second variable resistance element;
  A third switch disposed between the second storage node and the other end of the first variable resistance element;
  A fourth switch disposed between the second storage node and one end of the second variable resistance element;
  A fifth switch disposed between the other end of the first variable resistance element and one of the high-level voltage line and the low-level voltage line;
  A sixth switch disposed between the other end of the second variable resistance element and one of the high-level voltage line and the low-level voltage line;
  Having
  A nonvolatile latch circuit characterized by the above.   A latch circuit including complementary first and second storage nodes;
  A first resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
  A second resistance change element in which a resistance value changes by flowing a current from one end to the other end, and a current flowing from the other end to the one end;
  A switch circuit for connecting the first and second variable resistance elements to a latch circuit;
  With
  The switch circuit cuts off the connection between the first and second resistance change elements and the latch circuit during normal operation in which logic is written to the latch circuit from the outside, and is held by the first and second resistance change elements At the time of a restoring operation for returning the logic that has been returned to the latch circuit, one end of the first resistance change element and the other end of the second resistance change element are connected to the first storage node, and the other ones of the first resistance change element An end is connected to one of the high level voltage line and the low level voltage line, and one end of the second variable resistance element is connected to the other of the high level voltage line and the low level voltage line,
  The switch circuit is
  A first switch disposed between the first storage node and one end of the first variable resistance element;
  A second switch disposed between the first storage node and the other end of the second variable resistance element;
  A third switch disposed between the second storage node and the other end of the first variable resistance element;
  A fourth switch disposed between the second storage node and one end of the second variable resistance element;
  A fifth switch disposed between the other end of the first variable resistance element and one of the high-level voltage line and the low-level voltage line;
  A sixth switch disposed between one end of the second variable resistance element and the other of the high-level voltage line and the low-level voltage line;
  Having
  A nonvolatile latch circuit characterized by the above. A nonvolatile latch circuit according to any one of claims 1 to 7 ,
A logic circuit connected to the output of the nonvolatile latch circuit;
And a signal generation circuit for generating a control signal for controlling the operation of the switch circuit.

Images