JP2011054239A - Thermally insulated charge memory circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent disconnection of wiring due to electromigration caused by microfabrication while keeping the potential of the source electrode of a pMOS transistor constant. <P>SOLUTION: While a word line WL is at a zero potential and switch elements S1 and S2 are ON and OFF, bit lines BL and NBL are boosted in voltage to a positive potential VDD. By turning off the switch element S1 and turning on the switch element S2, a ground line MCGL is boosted to the positive potential VDD through the switch element S2, by taking a time longer than the time constant of a flip flop circuit FF. The switch element S2 is turned off. The word line is boosted in voltage to the positive potential VDD. One of the bit lines BL and NBL which is on a side of writing data 0 into the flip flop circuit FF such as the bit line NBL is dropped in voltage to the zero potential, by taking a longer time than the time constant of the flip flop circuit FF. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an adiabatic charging memory circuit capable of preventing disconnection of wiring due to electromigration caused by miniaturization while keeping the potential of a source electrode of a pMOS transistor constant.

  Conventionally, an SRAM (Static Random Access Memory) circuit generally used, as shown in FIG. 16, uses two CMOS inverters composed of a pMOS transistor and an nMOS transistor (P1, P2, N1). N2), a flip-flop connecting the output terminal of each CMOS inverter to the other input terminal is used as a memory element. The output signal of each CMOS inverter is connected to the bit lines BL and NBL via nMOS transistors N3 and N4, and a total of six transistors are provided in one memory cell.

  In recent years, the miniaturization of memory elements has progressed, and the wiring current density has increased as the cross-sectional area of the wiring has decreased. As a result, there has been a problem that wiring disconnection due to electromigration or the like occurs.

  Therefore, a technique has been proposed in which the potential of the power supply line is stepped down for a time longer than the time constant of the flip-flop when data is written in the memory cell (see Patent Document 1).

  FIG. 17 is a circuit diagram of the adiabatic charging memory circuit disclosed in Patent Document 1. In FIG.

  In the memory cell, the source electrodes of the pMOS transistors P1 and P2 are made conductive by a memory cell power line (hereinafter referred to as MCPL (Memory Cell Power Line)). The power supply portion of the circuit includes a switch S1 ′ that opens and closes between the constant voltage power supply line V1 ′ set to the positive potential VDD and the MCPL, and a constant voltage power supply line V2 ′ set to the zero potential and the memory cell power supply line MCPL. It is the structure provided with switch S2 'which opens and closes between. The switch S1 'can be an nMOS transistor or a pMOS transistor itself, or can be realized by connecting an nMOS transistor and a pMOS transistor in parallel.

  Next, the operation when data is written to the memory cell will be described with reference to the timing chart of FIG. Here, nMOS transistors are used for the switches S1 'and S2', and a circuit configuration in which the switches are turned on when the gate potential of the nMOS transistor is the positive potential VDD is used.

  Note that the threshold voltage VT of the nMOS transistor used for the switches S1 ′ and S2 ′ is sufficiently small with respect to the magnitude of the positive potential VDD, and the voltage drop corresponding to the threshold voltage VT when the nMOS transistor is on is reduced. Ignore it.

  First, the switch S1 'is turned off from on and the switch S2' is turned on from off, whereby the MCPL is gradually lowered from the positive potential VDD to the zero potential (0) (t1 → t2). In order to gently step down the voltage, the switch S2 'is a transistor having a large resistance value.

  Next, the switch S2 'is turned off from on, and the MCPL is set to a high impedance state (t2).

  Subsequently, the word line WL is set to the positive potential VDD, the nMOS transistors N3 and N4 are turned on, and the input of signals from the bit lines BL and NBL is waited (t3).

  Next, the bit line NBL is set to zero potential, while the adiabatic charge signal A2 is input to the bit line BL, and the adiabatic charge signal A2 is gradually increased from zero potential to the positive potential VDD (t4 → t5). As a result, the current flowing through the bit line BL is input to the flip-flop circuit FF via the nMOS transistor N3, and the adiabatic charging memory circuit can be gently charged to write data. MCPL also boosts the voltage from zero potential to positive potential VDD.

  Thereafter, the switch S1 'is turned on (t5). In this way, the written data can be held by fixing MCPL to the positive potential VDD.

  According to this adiabatic charging memory, data is written after the MCPL is gently lowered from the positive potential VDD to the zero potential by operating the switches S1 ′ and S2 ′ using the constant voltage power supply lines V1 ′ and V2 ′. Therefore, the disconnection of the wiring inside the adiabatic charging memory due to electromigration can be prevented.

  However, this adiabatic charging memory must have a configuration in which switches S1 ′ and S2 ′ are arranged between MCPL and constant voltage power supply lines V1 ′ and V2 ′ in order to change the potential of the source electrode of the pMOS transistor. There was a restriction on the degree of freedom of circuit design.

JP 2007-226927 A

  The present invention has been made in view of the above, and an object thereof is to provide an adiabatic charging memory circuit capable of preventing disconnection of wiring due to electromigration due to miniaturization while keeping the potential of the source electrode of a pMOS transistor constant. There is to do.

  In order to solve the above problems, an adiabatic charging memory circuit according to a first aspect of the present invention includes a flip-flop circuit in which a CMOS inverter circuit including a pMOS transistor and an nMOS transistor connected in series is connected in a complementary manner, A transistor connected between an input terminal of one CMOS inverter circuit and a first bit line; a transistor connected between an input terminal of the other CMOS inverter circuit and a second bit line; and the flip-flop A first switch element that opens and closes between a ground line that connects a source electrode of each nMOS transistor in the circuit and a circuit node that exhibits zero potential; and a second switch element that has one end connected to the ground line. The source electrode of each pMOS transistor is kept at a positive potential, and each transistor is turned off. With the first switch element turned on and the second switch element turned off, the first and second bit lines are boosted to the positive potential, the first switch element is turned off, With the second switch element turned on, the ground line is boosted to the positive potential via the second switch element over a time longer than the time constant, and the second switch element In a state where the element is turned off and each transistor is turned on, data 0 is stored in the flip-flop circuit in the first and second bit lines over a time longer than the time constant. The bit line on the writing side is lowered from the positive potential to the zero potential.

  The adiabatic charging memory circuit according to the second aspect of the present invention includes a flip-flop circuit in which CMOS inverter circuits including a pMOS transistor and an nMOS transistor connected in series are complementarily connected, and an input terminal of the one CMOS inverter circuit , A transistor connected between the first bit line, a transistor connected between the input terminal of the other CMOS inverter circuit and the second bit line, and a source of each nMOS transistor in the flip-flop circuit A first switch element that opens and closes between a ground line that connects electrodes and a circuit node that exhibits zero potential; and a second switch element that is connected to one end of the ground line, and each pMOS The source electrode of the transistor is kept at a positive potential, each of the transistors is turned off, and the first switch With the child turned on and the second switch element turned off, the first and second bit lines are boosted to the first positive potential, the first switch element is turned off, and the first switch element is turned off. In a state in which the second switch element is turned on, the ground line is passed through the second switch element to a second positive potential lower than the first positive potential over a time longer than the time constant. In the state where the second switch element is turned off, the data 0 is stored in the flip-flop circuit in the first and second bit lines over a time longer than the time constant. Decreasing the bit line on the writing side to the second positive potential, and further lowering the bit line to zero potential over a time longer than the time constant in a state where each transistor is turned on. Features.

  According to the adiabatic charging memory circuit of the present invention, it is possible to prevent disconnection of wiring due to electromigration due to miniaturization while keeping the potential of the source electrode of the pMOS transistor constant.

It is a circuit diagram of the adiabatic charging memory circuit according to the first embodiment. It is a timing chart which shows operation | movement when writing data in the heat insulation charge memory circuit which concerns on 1st Embodiment. FIG. 3 is a circuit diagram of an AC power supply circuit using an inductor L and a capacitor C as a power supply circuit for reusing charges. FIG. 3 is a circuit diagram of a power supply circuit that generates a staircase voltage as a power supply circuit that reuses charges. FIG. 10 is a circuit diagram of another power supply circuit that generates a stepped voltage as a power supply circuit that reuses electric charges. It is a circuit diagram of an inverter with a large resistance value used as a method of not reusing electric charges. It is a circuit diagram which shows another example of the power supply circuit which generate | occur | produces a step-like voltage as a power supply circuit which reuses an electric charge. It is a timing chart which shows operation | movement when writing data in the heat insulation charge memory circuit which concerns on 2nd Embodiment. It is a figure which shows the vertical layout in SRAM. It is a figure which shows the horizontal layout in SRAM. It is a figure which shows the layout of a vertical 2x2 cell. It is a figure which shows the layout of horizontal type 2x2 cell. It is a figure which shows the circuit for preventing the influence of a glitch etc. It is a figure which shows another circuit for preventing the influence, such as a glitch. 15 is a timing chart of the circuits shown in FIGS. 13 and 14. It is a figure which shows the circuit structural example of the conventional SRAM. It is a figure which shows another circuit structural example of conventional SRAM. 18 is a timing chart of the circuit shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram of an adiabatic charging memory circuit according to the first embodiment.

  The adiabatic charging memory circuit indicates one of a plurality of adiabatic charging memory circuits arranged in a matrix, and is a so-called SRAM.

  In the adiabatic charging memory circuit, a CMOS inverter circuit IV1 including a pMOS transistor P1 and an nMOS transistor N1 connected in series, and a CMOS inverter circuit IV2 including a pMOS transistor P2 and an nMOS transistor N2 connected in series are complementarily connected. Flip-flop circuit FF, an nMOS transistor N3 connected between the input terminal of the CMOS inverter circuit IV1 (node ND1 connecting the gate electrodes of the pMOS transistor P1 and the nMOS transistor N1) and the first bit line BL, A transistor N4 connected between the input terminal of the CMOS inverter circuit IV2 (node ND2 connecting the gate electrodes of the pMOS transistor P2 and the nMOS transistor N2) and the second bit line NBL; The first switch element S1 that opens and closes between the ground line MCGL connecting the source electrodes of the nMOS transistors N1 and N2 and the constant voltage power supply line V1, and the first switch element S1 that opens and closes between the ground line MCGL and the constant voltage power supply line V2. 2 switch elements S2.

  The power supply line connecting the source electrodes of the pMOS transistors P1 and P2 is kept at the positive potential VDD. The CMOS inverter circuits IV1 and IV2 and the transistors N3 and N4 constitute a so-called memory cell. The constant voltage power supply lines V1 and V2 are circuit nodes that exhibit a zero potential and a positive potential VDD, respectively.

  Here, the switch elements S1 and S2 are nMOS transistors, respectively, and are turned on when the gate voltage becomes the positive potential VDD. The switch element may be a pMOS transistor.

  The transistors N3 and N4 are nMOS transistors, respectively, and are turned on when the gate voltage becomes the positive potential VDD. The transistor may be a pMOS transistor.

  The output of the CMOS inverter circuit IV1 (the drain electrodes of the pMOS transistor P1 and the nMOS transistor N1) is connected to the input of the CMOS inverter circuit IV2 (the gate electrodes of the pMOS transistor P2 and the nMOS transistor N2). Similarly, the CMOS inverter circuit The output of IV2 (drain electrodes of the pMOS transistor P2 and the nMOS transistor N2) is connected to the input (gate electrode of the pMOS transistor P1 and the nMOS transistor N1) of the CMOS inverter circuit IV1.

  An nMOS transistor N3 is connected between the gate electrodes of the pMOS transistor P1 and the nMOS transistor N1 and the bit line BL of the memory cell array, and the gate electrode of the nMOS transistor N3 is connected to the word line WL. Similarly, an nMOS transistor N4 is connected between the gate electrodes of the pMOS transistor P2 and the nMOS transistor N2 and the bit line NBL of the memory cell array, and the gate electrode of the nMOS transistor N4 is also connected to the word line WL.

  Next, the operation of the adiabatic charging memory circuit according to the first embodiment, particularly the operation during data writing will be described with reference to FIG. FIG. 2 is a timing chart showing an operation when data is written to the adiabatic charging memory circuit according to the first embodiment.

  First, the word line WL is set to zero potential, that is, the transistors N3 and N4 are turned off, and the bit lines BL and NBL are boosted to the positive potential VDD while the switch element S1 is on and the switch element S2 is off. .

  Next, the switch element S1 is turned off and the switch element S2 is turned on (t1). For example, by using an nMOS transistor having a relatively high on-resistance as the switch element S2, the ground line MCGL is boosted to the positive potential VDD over a time longer than the time constant of the flip-flop circuit FF (t2). Thereby, the data written in the flip-flop circuit FF is erased.

  When the ground line MCGL is boosted to the positive potential VDD, the switch element S2 is turned off (t2). As a result, the ground line MCGL enters a high impedance state.

  Next, the word line is set to the positive potential VDD. That is, the transistors N3 and N4 are turned on (t3).

  Next, of the bit lines BL and NBL, the bit line corresponding to the data 0 to be written to the flip-flop circuit FF, for example, the bit line NBL is set to zero potential over a time longer than the time constant of the flip-flop circuit FF. Step down (t3 → t4).

  At this time, a current flows from the positive potential VDD ground line MCGL to the bit line NBL, and the ground line MCGL gradually changes from the positive potential VDD to the zero potential (t3 → t4). Thus, the power supply side potential of the flip-flop circuit FF becomes the positive potential VDD and the ground side potential becomes zero potential. That is, the flip-flop circuit FF becomes the same as the state in which data is written by the conventional method. Specifically, a high voltage is written to the node ND1 and a low voltage is written to the node ND2.

  Next, the switch element S1 is turned on (t5), and the word line WL is set to zero potential. As a result, the ground line MCGL is kept at zero potential, and the transistors N3 and N4 are kept off, that is, the written data is held.

  Here, as described above, for example, when the bit line NBL is lowered to zero potential over a time longer than the time constant of the flip-flop circuit FF, it is also said that an adiabatic charging signal is applied to the bit line NBL.

  This adiabatic charging signal will be described. Adiabatic charging is a method in which charging is performed more slowly than the time constant of the circuit, and the term adiabatic is used to change the system very slowly in physics. Is used.

  In that sense, as described above, boosting the ground line MCGL to the positive potential VDD over a time longer than the time constant of the flip-flop circuit FF (t2) means that the ground line MCGL is connected to the ground line MCGL via the switch element S2. It is also said to give an adiabatic charge signal.

  In the above description, this is realized by setting the potential of the constant voltage power supply line V2 to the positive potential VDD (constant) and the nMOS transistor having a relatively large on-resistance as the switch element S2. The on-resistance is arbitrary, and this may be realized by raising the potential of the adiabatic charging signal applied to V2 from zero potential to positive potential VDD.

  Now, in order to boost the ground line MCGL to the positive potential VDD over a time longer than the time constant of the flip-flop circuit FF, the potential of the adiabatic charging signal is gently boosted, and the bit line NBL is A method for gradually lowering the potential of the adiabatic charging signal so as to step down to zero potential over a time longer than the time constant of the flip-flop circuit FF will be described.

  Specific circuits for gradually boosting and stepping down the potential of the adiabatic charging signal include an AC power supply circuit using an inductor and a capacitor that uses a method of reusing charges, and an N-stage stepped configuration using N-1 capacitors. A power supply circuit that generates a voltage can be used. The charge reuse is a method of reusing the charge by returning the charge charged to the load capacity from the power supply to the power supply again without throwing it back to the GND.

  FIG. 3 shows an example of an AC power supply circuit using an inductor L and a capacitor C, and FIG. 4 shows an example of a power supply circuit that generates four stepped voltages using three capacitors C1 to C3. In FIG. 4, a power supply circuit for generating a stepped voltage includes four constant voltage power supplies VDD, 3 / 4VDD, 2 / 4VDD, 1 / 4VDD, three capacitors C1 to C3, and eight nMOS transistors N5 to N12. This is a configuration provided. The three capacitors C1 to C3 are charged by voltages of 1/4 VDD, 2/4 VDD, and 3/4 VDD, respectively. The input signal Pre is applied to the gate electrodes of the three nMOS transistors N5 to N7, the input signals T1 to T4 are applied to the gate electrodes of the four nMOS transistors N8 to N11, and the input to the gate of one nMOS transistor N12. A signal CL is applied. Note that the power supplies of 1/4 VDD, 2/4 VDD, and 3/4 VDD are naturally charged to 1/4 VDD, 2/4 VDD, and 3/4 VDD, respectively, even in a circuit without them as shown in FIG. It becomes a stable state. First, the input signal Pre is set to High for a predetermined time, the nMOS transistors N5 to N7 are turned on, and the capacitors C1 to C3 are charged to voltages of 1 / 4VDD, 2 / 4VDD, and 3 / 4VDD, respectively. Next, each of the input signals T1 to T4 is set high for a predetermined time in the order of T1, T2, T3, T4, T3, T2, and T1, and the nMOS transistors N8 to N11 are turned on to charge the capacitors C1 to C3. The voltages 1 / 4VDD, 2 / 4VDD, and 3 / 4VDD are output as the output voltage Vout in a time-division manner. Finally, when the input signal T1 becomes Low, the input signal CL is set to High and the nMOS transistor N12 is turned on for a predetermined time. The output voltage Vout is set to the ground potential. By such timing control, the output voltage Vout of the power supply circuit that generates the staircase voltage has a waveform having four steps on the rising and falling edges. In these power supply circuits, an AC waveform (repetitive waveform) in which the output voltage is gradually increased and gradually decreased can be obtained.

  Further, as shown in FIG. 6, an inverter using a transistor having a large resistance value that can change the voltage in a time longer by about one digit than the time constant of the flip-flop circuit without reusing the charge. It is also possible to step up and down using Specifically, there are a method of increasing the gate length, a method of reducing the transistor width, and a method of reducing the ion implantation doping concentration of the source and drain. Alternatively, a method for increasing the threshold voltage of the transistor may be used.

  Further, the generation of the stepped waveform is not limited to the circuit of FIG. 4 using a capacitor, and the circuit of FIG. 7 may be used. This may be repeated by setting the input signal to High in the order of T0, T1, T2, T3, T4, T3, T2, T1, and T0.

  Therefore, according to the adiabatic charging memory circuit according to the first embodiment, the CMOS inverter circuit including the pMOS transistor and the nMOS transistor connected in series is complementarily connected, and the source electrode of each pMOS transistor is connected. A flip-flop circuit FF in which the power supply line is maintained at the positive potential VDD, a transistor N3 connected between the input terminal (ND1) of one CMOS inverter circuit IV1 and the first bit line BL, and the other CMOS inverter circuit A circuit node (V1) exhibiting zero potential with a transistor N4 connected between the input terminal (ND2) of IV2 and the second bit line NBL, and a ground line MCGL connecting the source electrodes of the nMOS transistors (N1, N2). ) Between the first switch element S1 and the ground line MCGL. Are connected to each other, the transistors N3 and N4 are turned off, the first switch element S1 is turned on, and the second switch element S2 is turned off. The bit lines BL and NBL are boosted to the positive potential VDD, the first switch element S1 is turned off, and the second switch element S2 is turned on, via the second switch element S2. Over a time longer than the time constant of the flip-flop circuit, the ground line MCGL is boosted to the positive potential VDD, the second switch element S2 is turned off, and the transistors N3 and N4 are turned on. The bit line on the side of writing data 0 to the flip-flop circuit FF in the first and second bit lines BL and NBL over a time longer than the time constant (in the above example, the bit line NB ) And since stepping down from the positive potential VDD to zero potential, it is possible to prevent with the potential of the source electrode of the pMOS transistor P1, P2 constant, disconnection of the wiring due to electromigration resulting from the miniaturization.

[Second Embodiment]
Next, an adiabatic charging memory circuit according to the second embodiment will be described. Since the circuit configuration of the adiabatic charging memory circuit is the same as that of the first embodiment, a duplicate description is omitted. However, the potential of the constant voltage power supply line V2 is lower than the positive potential VDD (here, a potential that is ½ of the positive potential VDD (hereinafter, “positive potential VDD / 2”)).

  The operation of the adiabatic charging memory circuit according to the second embodiment, particularly the operation during data writing will be described. FIG. 8 is a timing chart showing an operation when data is written to the adiabatic charging memory circuit according to the second embodiment.

  First, the word line WL is set to zero potential, that is, the transistors N3 and N4 are turned off, and the bit lines BL and NBL are boosted to the positive potential VDD while the switch element S1 is on and the switch element S2 is off. .

  Next, the switch element S1 is turned off and the switch element S2 is turned on (t1). For example, by using an nMOS transistor having a relatively large on-resistance as the switch element S2, the ground line MCGL is boosted to the positive potential VDD / 2 over a time longer than the time constant of the flip-flop circuit FF. Thereby, the data written in the flip-flop circuit FF is held.

  When the ground line MCGL is boosted to the positive potential VDD / 2, the switch element S2 is turned off (t2). As a result, the ground line MCGL enters a high impedance state.

  Next, the bit line corresponding to 0 which is the data to be written to the flip-flop circuit FF in the bit lines BL and NBL, for example, the bit line NBL is set to be positive over a time constant longer than the time constant of the flip-flop circuit FF. The voltage is lowered to the potential VDD / 2 (t3 → t4).

  Next, the word line is set to the positive potential VDD. That is, the transistors N3 and N4 are turned on (t4). Then, the same bit line (in the above example, bit line NBL) is stepped down to zero potential over a time longer than the time constant of the flip-flop circuit FF (t4 → t5).

  At this time, a current flows from the ground line MCGL at the positive potential VDD / 2 to the bit line NBL, and the ground line MCGL gradually becomes zero potential from the positive potential VDD / 2 (t4 → t5). Thus, the power supply side potential of the flip-flop circuit FF becomes the positive potential VDD and the ground side potential becomes zero potential. That is, the flip-flop circuit FF becomes the same as the state in which data is written by the conventional method. Specifically, a high voltage is written to the node ND1 and a low voltage is written to the node ND2.

  Next, the switch element S1 is turned on (t6), and the word line WL is set to zero potential. As a result, the ground line MCGL is kept at zero potential, and the transistors N3 and N4 are kept off, that is, the written data is held.

  Therefore, according to the adiabatic charging memory circuit according to the second embodiment, the CMOS inverter circuit including the pMOS transistor and the nMOS transistor connected in series is complementarily connected, and the source electrode of each pMOS transistor is connected. A flip-flop circuit FF in which the power supply line is maintained at the first positive potential VDD, a transistor N3 connected between the input terminal (ND1) of one CMOS inverter circuit IV1 and the first bit line BL, and the other A circuit exhibiting zero potential with a transistor N4 connected between the input terminal (ND2) of the CMOS inverter circuit IV2 and the second bit line NBL, and a ground line MCGL connecting the source electrodes of the respective nMOS transistors in the flip-flop circuit. A first switch element S1 for opening and closing between the node (V1) and a ground A second switch element S2 having one end connected to the line MCGL, the transistors N3 and N4 are turned off, the first switch element S1 is turned on, and the second switch element S2 is turned off. The first and second bit lines BL and NBL are boosted to the positive potential VDD, the first switch element S1 is turned off, and the second switch element S2 is turned on. Through the time constant, the ground line MCGL is boosted to the positive potential VDD / 2 over a time longer than the time constant of the flip-flop circuit, and the second switch element S2 is turned off. After a long time, the bit line (in the above example, the bit line NBL) on which data 0 is written to the flip-flop circuit FF in the first and second bit lines BL and NBL is set to the positive potential VDD. Since the voltage of the bit line (in the above example, the bit line NBL) is lowered to zero potential over a time longer than the time constant with the transistors N3 and N4 turned on. While making the potentials of the source electrodes of the pMOS transistors P1 and P2 constant, it is possible to prevent disconnection of wiring due to electromigration due to miniaturization. Further, since the ground line MCGL may be boosted to a positive potential lower than the positive potential VDD, data can be written quickly.

  Next, the layout of the adiabatic charging memory circuit (collectively, simply referred to as adiabatic charging memory circuit) according to each embodiment will be described.

  As the layout of the SRAM, a vertical type shown in FIG. 9 and a horizontal type shown in FIG. 10 are known.

  FIG. 11 is a diagram illustrating a layout of a vertical 2 × 2 cell. The word lines WL0 and WL1 corresponding to the word line WL in FIG. 1, the ground lines MCGL0 and MCGL1 corresponding to the ground line MCGL in FIG. 1 are arranged in the horizontal direction, and the bit lines BL0 and BL1 corresponding to the bit line BL in FIG. A layout in which wirings (not shown) set to the positive potential VDD are arranged in the vertical direction is possible.

  FIG. 12 is a diagram showing a layout of a horizontal 2 × 2 cell. Word lines WL0 and WL1 corresponding to the word line WL in FIG. 1 and wirings (not shown) set to the positive potential VDD are arranged in the horizontal direction, and the bit lines BL0 and BL1 corresponding to the bit line BL in FIG. A layout in which the ground lines MCGL0 and MCGL1 corresponding to the ground line MCGL in FIG. 1 are arranged in the vertical direction is possible. If the writing described in the first embodiment is performed with this layout, when the ground line becomes the positive potential VDD, the data in the memory cells of the word lines in the other rows not selected are erased. Therefore, writing according to the first embodiment cannot be performed with this layout. On the other hand, with this layout, even if the writing described in the second embodiment is performed, the ground line is boosted only to the positive potential VDD / 2, so that the data of the word lines of other unselected rows can be held. Therefore, writing according to the second embodiment can be performed with this layout. In the vertical layout, since the ground line is not shared between different words, writing according to any embodiment can be performed.

  In each embodiment, since both the bit lines BL and NBL are set to the positive potential VDD, data is not erroneously written to the memory cells of the unselected word.

  That is, when a decoder circuit (not shown) that controls a word line WL sets a certain word line WL to a positive potential VDD, other word lines WL are instantaneously set to a positive potential VDD due to the influence of a glitch or the like. There is. At this time, if the bit line BL is set to the positive potential VDD and the bit line NBL is set to the zero potential (or reverse), the opposite data may be erroneously written. In order to avoid this, a circuit is required in which the word line enable signal is raised after a sufficient time has elapsed and a stable signal without glitch is transmitted to the word line WL.

  FIG. 13 is a diagram showing this circuit. FIG. 14 is a diagram showing an equivalent circuit composed of a NAND gate and an inverter. FIG. 15 is a timing chart of the circuit.

  The signal PRE-WORD is a signal from the decoder circuit and has a glitch. The word line enable signal WORD-EN becomes the positive potential VDD at time t1. Immediately after this, the signal WORD becomes the positive potential VDD. Therefore, it is possible to prevent a glitch from occurring in the signal WORD. This signal WORD may be transmitted to the word line WL. However, a circuit as shown in FIGS. 13 and 14 is required.

  Therefore, in each embodiment of the present invention, both the bit lines BL and NBL are set to the positive potential VDD. Therefore, even if there is no circuit as shown in FIGS. There is an advantage that it is not written.

BL, NBL ... bit line FF ... flip-flop circuit IV1, IV2 ... CMOS inverter circuit MCGL ... ground line N1-N4 ... nMOS transistors P1, P2 ... pMOS transistors S1, S2 ... switch elements V1, V2 ... constant voltage power supply line WL ... Word line

Claims (2)

A flip-flop circuit in which CMOS inverter circuits including a pMOS transistor and an nMOS transistor connected in series are complementarily connected;
A transistor connected between the input end of the one CMOS inverter circuit and the first bit line;
A transistor connected between an input terminal of the other CMOS inverter circuit and a second bit line;
A first switch element that opens and closes between a ground line connecting a source electrode of each nMOS transistor in the flip-flop circuit and a circuit node exhibiting a zero potential;
A second switch element having one end connected to the ground line,
The first and second bit lines are maintained in a state where the source electrode of each pMOS transistor is maintained at a positive potential, each transistor is off, the first switch element is on, and the second switch element is off. Is increased to the positive potential,
With the first switch element changed to OFF and the second switch element changed to ON, the ground line is passed through the second switch element over a time longer than the time constant. Is increased to the positive potential,
In the state where the second switch element is turned off and the transistors are turned on, the flip-flops in the first and second bit lines are taken over a time longer than the time constant. An adiabatic charging memory circuit, wherein the bit line on the side where data 0 is written to the circuit is stepped down from the positive potential to the zero potential. A flip-flop circuit in which CMOS inverter circuits including a pMOS transistor and an nMOS transistor connected in series are complementarily connected;
A transistor connected between the input end of the one CMOS inverter circuit and the first bit line;
A transistor connected between an input terminal of the other CMOS inverter circuit and a second bit line;
A first switch element that opens and closes between a ground line that connects a source electrode of each nMOS transistor in the flip-flop circuit and a circuit node that exhibits zero potential;
A second switch element connected at one end to the ground line,
The first and second bit lines are maintained with the source electrode of each pMOS transistor kept at a positive potential, each transistor off, the first switch element on, and the second switch element off. Is increased to the first positive potential,
In a state where the first switch element is turned off and the second switch element is turned on, the first switch element is passed through the second switch element over a time longer than the time constant. Boosting the ground line to a second positive potential lower than the positive potential of
A bit on the side of writing data 0 to the flip-flop circuit in the first and second bit lines over a time longer than the time constant with the second switch element turned off. The heat insulation is characterized in that the line is stepped down to the second positive potential, and the bit line is stepped down to zero potential over a time longer than the time constant in a state where each transistor is turned on. Charging memory circuit.

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