JP4792093B2 - Switching box circuit, switching block circuit, and FPGA circuit - Google Patents

Description

  The present invention relates to a switching box circuit, a switching block circuit, and an FPGA circuit.

  In recent years, research and development of spin electronics devices using the spin degree of freedom of electrons has been actively conducted. Research and development based on the tunnel magnetoresistive effect (TMR) has been actively conducted and has been applied to reproducing heads of magnetic random access memories (MRAM) and hard disk drives (HDD). Further, a spin transistor in which a semiconductor and a magnetic material are combined is attracting attention.

  As a reconfigurable logic circuit based on the current semiconductor technology, there is an integrated circuit called FPGA (Field Programmable Gate Array). The FPGA stores information in the internal SRAM, and can control the logic and connection of the reconfigurable logic circuit according to the contents stored in the memory. Thus, since the logic can be changed by software, the circuit can be corrected after the hardware is manufactured. In recent years, it has been rapidly growing as a means for realizing complicated integrated circuits with a short delivery time and at a low cost.

  The switching box circuit is a circuit that stores connection methods of signal lines coming from four directions and determines connection and disconnection between signal lines and signal lines (see, for example, Non-Patent Document 1). The circuit having this switching box circuit can realize an arbitrary connection method by rewriting the memory.

Vaugun Betz et al., "Architecture and CAD for Deep-submicron FPGAs", Kluwer Academic Publishers, 3rd Edition, 2002, pp 63-103 and 207-220

  When this switching box circuit is manufactured by a semiconductor CMOS technology, an SRAM is conventionally used as a memory for storing information. For this reason, there exists a problem that the number of elements will increase. In addition, since a large amount of SRAM is used, power consumption due to leakage current increases even when no operation is performed. Therefore, the circuit is difficult to be highly integrated. In addition, since many pass transistors are used in the switching box circuit, the circuit scale becomes very large, which is one of the factors hindering high integration. Furthermore, since the SRAM is a volatile memory in which information is lost when the power is turned off, it is necessary to write the information stored in the external memory every time the power is turned on. For this reason, there is a problem that it takes time and effort when the power is turned on. In addition, it is necessary to secure an external memory for storing information when the power is turned off, and there is a problem that power consumption and volume are required for the external memory. For this reason, this is one of the factors that hinder high integration and low power consumption in the entire system.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a switching box circuit, a switching block circuit, and an FPGA circuit capable of high integration and low power consumption.

The switching box circuit according to the first aspect of the present invention includes first to nth (≧ 1) signal lines provided in the first to fourth directions, respectively, and the first to fourth directions, respectively. The i th (1 ≦ i ≦ n) input / output units in each direction are connected to the i th signal line in the corresponding direction. An nth input / output unit, first to second n connection terminals, and first to fourth directions, respectively, and each of the first to nth input / output units in each direction; In order to connect each of the 1st to 2nth connection terminals, one is provided between them, and 2n ² spin MOSFETs receiving a clock signal at their gates are provided.

  The switching block circuit according to the second aspect of the present invention includes first to mth (≧ 2) signal line groups each provided in the first to fourth directions, each including n signal lines. And the first to mth (≧ 2) switching box circuits of the first aspect, wherein the i th (1 ≦ i ≦ m) signal line group in the first to fourth directions is the i th It is connected to a switching box circuit.

  An FPGA circuit according to a third aspect of the present invention includes a switching block circuit according to the second aspect, a cluster logic block circuit including a lookup table, and a connection for connecting the switching block circuit and the cluster logic block circuit. And a block circuit.

  According to the present invention, high integration and low power consumption can be achieved.

The circuit diagram of the switching box circuit by a 1st embodiment. The circuit diagram which shows the example of a connection and a disconnection in the switching box circuit of 1st Embodiment. The circuit diagram which shows the input-output part in the switching box circuit of 1st Embodiment. The circuit diagram which shows the input part in the switching box circuit of 1st Embodiment. The circuit diagram which shows the output part in the switching box circuit of 1st Embodiment. The circuit diagram which shows the memory part in the switching box circuit of 1st Embodiment. The circuit diagram which shows the rewriting circuit in the switching box circuit of 1st Embodiment. The figure which shows the example of the current path in the case of performing rewriting in the switching box circuit of 1st Embodiment. The figure which shows one specific example of the switching block circuit comprised using the switching box circuit of 1st Embodiment. FIG. 10 is a diagram showing a specific example of an FPGA circuit configured using the switching block circuit shown in FIG. 9. The circuit diagram which shows the output part in the switching box circuit of 2nd Embodiment. The circuit diagram which shows the memory part in the switching box circuit of 2nd Embodiment. The circuit diagram of the switching box circuit by a 3rd embodiment. The figure which shows one specific example of the switching block circuit comprised using the switching box circuit of 3rd Embodiment. The figure which shows the relationship between the number n of signal lines in the case where a switching box circuit is comprised using spin MOSFET, and the case where a switching box circuit is comprised only by CMOS, and the number of elements. The figure which shows one specific example of the switching block circuit comprised using the switching box circuit of 4th Embodiment.

Embodiments of the present invention will be described below in detail with reference to the drawings. However, the drawings are schematic, and the size of each part, the height of each voltage and the length of each time, the size ratio between parts, the ratio between voltages, the time interval, etc. are actual. Is different. In addition, even among the drawings, even if the same parts are indicated, there are some parts that are shown in different sizes and ratios.

  In the signal voltage, a high voltage is set to H level and a low voltage is set to L level. The H level represents a voltage higher than half of the power supply voltage Vdd, and the L level represents a voltage lower than half of the power supply voltage Vdd.

(First embodiment)
A switching box circuit according to a first embodiment of the present invention is shown in FIG. Generally, a switching box circuit is a circuit that determines connection and disconnection in a region where signal lines from four directions meet. The switching box circuit 1 of this embodiment determines connection and disconnection of _four signal lines SL ₁ , SL ₂ , SL ₃ , SL ₄ , and includes two connection terminals 10 ₁ , 10 ₂ , There are four input / output units 12 _{1 to} 12 ₄ and eight n-type spin MOSFETs 14 _{1 to} 14 ₈ .

The four signal lines SL ₁ , SL ₂ , SL ₃ , SL ₄ are arranged one by one in four directions. In Figure 1, the signal line SL ₁ is upward, the signal line SL ₂ is leftward, the downward signal line SL _3, the right signal line SL ₄ is arranged. The input / output unit 12 _i is connected to each signal line SL _i (i = 1,... 4). One end of each of the two spin MOSFETs 14 _2i-1 and 14 _2i is connected to each input / output unit 12 _i (i = 1,... 4). Four spin _{MOSFET14 2i-1 (i = 1} , ··· 4) the other end of which is connected to the connection terminal 10 _1, the other end of the four spin _{MOSFET14 2i (i = 1, ···} 4) is It is connected to a connecting terminal 10 _2. Therefore, any one signal line can be connected to any other signal line through the input / output unit, the spin MOSFET, the connection terminal, the spin MOSFET, and the input / output unit. For example, the signal line SL ₁ is connected to the signal line SL ₂ through a route including the input / output unit 12 ₁ , the spin MOSFET 14 ₁ , the connection terminal 10 ₁ , the spin MOSFET 14 ₃ , and the input / output unit 12 ₂ . The signal line SL ₁ and the signal line SL ₂ are also connected through another path including the input / output unit 12 ₁ , the spin MOSFET 14 ₂ , the connection terminal 10 ₂ , the spin MOSFET 14 ₄ , and the input / output unit 12 ₂ . Thus, an arbitrary signal line is connected to another signal line through the connection terminal in the switching box circuit 1 of the present embodiment, and there are two connection paths. Each path has a configuration in which two spin MOSFETs are connected in series across a connection terminal.

Each of the spin MOSFETs 14 _{1 to} 14 ₈ has a configuration in which a ferromagnetic material is used for a source electrode and a drain electrode of a normal MOSFET, or a configuration in which a ferromagnetic material is added on the source electrode and the drain electrode of a normal MOSFET. It has a structure that combines a ferromagnet and a semiconductor. Depending on the direction of magnetization of the ferromagnetic material of the source electrode and the drain electrode or the direction of magnetization of the ferromagnetic material added on the source electrode and the drain electrode, the characteristics of the spin MOSFET, for example, the resistance value between the two ferromagnetic materials can be determined. Because of the difference, a non-volatile memory can be built in the logic. Thus, since the spin MOSFET has a memory function inside the element, a switching box circuit can be configured with a small area. Further, since the memory function is realized by using a ferromagnetic material, the memory is non-volatile, and it is not necessary to write to the memory of the switching box circuit every time the power is turned on. Further, since it has a nonvolatile memory inside, it is possible to cut off the power supply when it is not operating, and a switching box circuit with low power consumption can be constructed.

  The direction of magnetization of the ferromagnetic material on the source electrode and the drain electrode of the spin MOSFET, or the direction of magnetization of the ferromagnetic material on the source electrode and the drain electrode is either substantially parallel or substantially antiparallel. The resistance between the ferromagnets is either in a low resistance state or a high resistance state. Regarding the resistance value between the ferromagnetic materials of the source electrode and the drain electrode, a low resistance state is called a low resistance state, and a high resistance state is called a high resistance state. In each embodiment of the present invention, the signal lines are determined to be disconnected when the spin MOSFET is in the high resistance state, and the signal lines are determined to be conductive when the spin MOSFET is in the low resistance state.

  As described above, in this embodiment, signal lines are connected in all four directions. Two spin MOSFETs connected in series are provided between the signal lines. If both of the spin MOSFETs connected in series are in a low resistance state, it is determined as a connected state. In addition, if one or more of the two spin MOSFETs connected in series are in a high resistance state, it is determined that the wire is disconnected because current does not easily flow. In this embodiment, a common CLOCK signal (clock signal) is applied to the gates of the spin MOSFETs. That is, a CLOCK signal (clock signal) is simultaneously applied to the gates of the spin MOSFETs. In this embodiment, since each spin MOSFET is an n-type spin MOSFET, when the CLOCK signal (clock signal) is at an H level, the spin MOSFET conducts, operates the switching box circuit, and determines the output. Therefore, even if the spin MOSFET is in a conductive state, the signal line is determined to be disconnected when at least one spin MOSFET between the signal lines is in a high resistance state, and two spins connected in series When both MOSFETs are in the low resistance state, it is determined that the connection state is established.

Next, an example of the connection state of the switching box circuit 1 of the present embodiment is shown in FIG. In this example, it shows a case where the wires the signal line SL ₃ and to the right of the signal line SL ₄ below while connecting the signal line SL ₂ and the upper signal lines SL ₁ the left. The other route represents a disconnection. 2, the spin MOSFET 14 ₁ indicated by the dotted line, _{14 3,} 14 6, 14 ₈ denotes a low-resistance state, the spin MOSFET 14 _{2, 14 4,} 14 5, 14 ₇ indicated by a solid line shows a high resistance state. When all the spin MOSFETs in series between the signal lines are in a low resistance state, the signal lines are connected. When one of the two spin MOSFETs between the signal lines is in a high resistance state, the signal line is disconnected.

  Next, FIG. 3 shows a specific example of the input / output unit 12 of the switching box circuit 1 of the present embodiment. The input / output unit 12 of this specific example includes an input unit 12a, a memory unit 12b, and an output unit 12c. The memory unit 12b outputs a NOT-ENABLE signal complementary to the ENABLE signal and the ENABLE signal. The ENABLE signal and the NOT-ENABLE signal are output to the input unit 12a and the output unit 12c, and are connected so that only one of the input unit 12a and the output unit 12c becomes conductive.

Next, a specific example of the input unit 12a is shown in FIG. Input portion 12a of this embodiment includes a conventional p-type MOSFET 12a _1, a transfer gate consisting of a normal n-type MOSFET 12a _2. ENABLE signal to the gate of the p-type MOSFET 12a ₁ is input to the gate of the n-type MOSFET 12a ₂ NOT-ENABLE signal. Therefore, the input unit 12a becomes conductive when the ENABLE signal is L level and the NOT-ENABLE signal is H level, but becomes disconnected when ENABLE is H level and NOT-ENABLE is L level.

Next, a specific example of the output unit 12c is shown in FIG. The output portion 12c of this embodiment includes a p-type MOSFET12c _1, a sense amplifier 12c _2, includes a buffer 12c _3, a transfer gate composed of p-type MOSFET12c ₄ and n-type MOSFET12c _5, a. The p-type MOSFET 12c ₁ receives the ENABLE signal at the gate, the power supply voltage Vdd is applied to the source, and the drain is connected to the spin MOSFET. The sense amplifier 12c ₂ operates based on the NOT-ENABLE signal and detects an output from the spin MOSFET by comparing with the reference voltage. The buffer 12c ₃ stabilizes the output of the sense amplifier 12c ₂ and sends it to the transfer gate. A NOT-ENABLE signal and an ENABLE signal are applied to the gates of the p-type MOSFET 12c ₄ and the n-type MOSFET 12c ₅ of the transfer gate, respectively.

In the output unit 12c having such a configuration, when the NOT-ENABLE signal is at the L level and the ENABLE signal is at the H level, the voltage of the input unit 12a connected to the spin MOSFET in the low resistance state is supplied to the sense amplifier 12c ₂ , And the voltage is stabilized by the buffer and output to the signal line side through the transfer gate. The output unit 12c is disconnected when the NOT-ENABLE signal is at the H level and the ENABLE signal is at the L level. Note that the reference voltage shown in FIG. 5 is about Vdd / 2, and is determined so that the operation margin is the highest.

A specific example of the memory unit 12b is shown in FIG. The memory unit 12b of this specific example includes p-type MOSFETs 12b ₁ and 12b ₂ , an n-type spin MOSFET 12b ₃ , an n-type MOSFET 12b _4, and an inverter 12b ₅ . The p-type MOSFETs 12b ₁ and 12b ₂ , the n-type spin MOSFET 12b ₃ and the n-type MOSFET 12b ₄ are connected in series in this order. The source of the p-type MOSFET12b ₁ power supply voltage Vdd is applied, the source of the n-type MOSFET12b ₄ is grounded. Then, to the gate of the p-type MOSFET12b ₁ NOT-READ signal is applied to the gate of the n-type MOSFET12b ₄ READ signal is applied. Further, the gates of the p-type MOSFET 12b ₂ and the n-type spin MOSFET 12b ₃ are connected to a common 1/2 terminal, and an ENABLE signal is output from a connection node between the drain of the p-type MOSFET 12b _{2 and} the drain of the n-type spin MOSFET 12b _3. This ENABLE signal is output and inverted by the inverter 12b ₅ to obtain a NOT-ENABLE signal.

The 1/2 terminal connected to the gate of the spin MOSFET12b _3, half Vdd / 2 about the power supply voltage Vdd is applied. READ signal is H level, when NOT-READ signal is at the L level, power is supplied to the spin MOSFET12b _3, performs the transistor operation. At this time, if the spin MOSFET 12b ₃ is in the low resistance state, the ENABLE signal becomes L level, and if the spin MOSFET 12b ₃ is in the high resistance state, the ENABLE signal becomes H level.

On the other hand, READ signal is L level, when the NOT-READ signal is at H level, since the power supply to the spin MOSFET12b ₃ not supplied, the power consumption of the memory section 12b becomes extremely small. Even if no power is supplied, the spin MOSFET 12b ₃ is a non-volatile memory, so the memory content is retained.

Incidentally, the ENABLE signal lines since the electrically floating, without electric power is supplied to the spin MOSFET12b _3, the voltage of the ENABLE signal is held. Therefore, even when the READ signal is L level and the NOT-READ signal is H level, the output of the ENABLE signal is held.

  Next, when the resistance state of the spin MOSFET is rewritten, the direction of magnetization is reversed by passing a current equal to or greater than the reversal current due to the spin injection magnetization reversal. The reversal of the direction of magnetization is performed by changing the direction of the current flowing through the spin MOSFET. The rewriting of the resistance state of the spin MOSFET will be described with reference to FIG. FIG. 7 is a circuit diagram showing a specific example of the resistance state rewriting circuit of the spin MOSFET.

Two address lines 42 ₁ and 42 ₂ from the address section 40 are connected to the gates of four spin MOSFETs connected to the connection terminals 10 ₁ and 10 ₂ , respectively. That is, the address lines 42 _1, a connection terminal 10 ₁ four spin MOSFET 14 ₁ connected to, ₁₄ 3 _are connected to the 14 5, 14 ₇ of the gate address lines 42 ₂ is connected to the connecting terminal 10 ₂ Are connected to the gates of the _four spin MOSFETs 14 ₂ , 14 ₄ , 14 ₆ , 14 ₈ . Two current lines 52 ₁ and 52 ₂ from the driver / sinker unit 50 are connected to _two connection terminals 10 ₁ and 10 ₂ , respectively. Four current lines 62 ₁ , 62 ₂ , 62 ₃ , and 62 ₄ from the driver / sinker unit 60 are respectively connected to the terminals on the spin MOSFET side of the _four input / output units 12 ₁ , 12 ₂ , 12 ₃ , and 12 _4. Connected.

When writing is performed by spin injection magnetization reversal, the address unit 40 applies a voltage (address signal) to an address line connected to the spin MOSFET to be rewritten, thereby bringing the spin MOSFET to be rewritten into a conductive state. Rewriting is performed by flowing a rewriting current equal to or higher than a current value for reversing spin injection magnetization through a current line connected to the spin MOSFET to be rewritten. Here, a current is passed through only one spin MOSFET from the driver / sinker unit 50 to the driver / sinker unit 60 or from the driver / sinker unit 60 to the driver / sinker unit 50. A specific current path is shown in FIG. Figure 8 shows an example of a current path of the spin MOSFET, and the spin MOSFET 14 ₆ rewriting. 8, by selecting the address lines 42 _2, spin _{MOSFET14 2, 14 4, 14 6} , 14 8 becomes conductive, current flows to the driver / sinker portion 60 through the connection terminal 102 from the driver / sinker 50 it allows the rewriting current flows in the MOSFET 14 ₆ rewritten. With such a rewriting operation, the resistance state of an arbitrary spin MOSFET can be rewritten.

  In the switching box circuit 1 of the present embodiment, the total number of elements including the MOSFET and the spin MOSFET is 80. On the other hand, the number of elements of a conventional switching box circuit composed only of CMOS is 104. Therefore, the switching box circuit 1 of this embodiment using a spin MOSFET can be configured with 77% of the number of elements as compared with a conventional switching box circuit using a CMOS. Since the circuit area largely depends on the number of elements, the smaller the number of elements, the smaller the circuit area. The switching box circuit 1 of this embodiment using a spin MOSFET is a switching box circuit with a small area.

FIG. 9 shows a circuit diagram of a specific example of the switching block circuit 100 configured using the switching box circuit 1 of the present embodiment. In the switching block circuit 100 of this specific example, m signal lines are provided in each of the four directions. M signal lines SL _{11 to} SL _{1m on} the upper side, m signal lines SL _{21 to} SL _{2m on} the left side, m signal lines SL _{31 to} SL _{3m on} the lower side, _m signal lines on the right side signal lines _SL 41 _{to SL 4m} are provided. And the switching box circuit 1 of this embodiment is provided in the cross _| intersection area | region of four signal lines _SL1i , _SL2i , _SL3i , _SL4i (i = 1, ..., m). Since the switching block circuit 100 of this specific example uses a switching box circuit with a small area, it becomes a switching block circuit with a small area.

  A specific example of an FPGA (Field Programmable Gate Array) circuit 200 configured using the switching block circuit 100 is shown in FIG. The FPGA circuit 200 of this specific example includes a plurality of switching block (SB) circuits 100, a plurality of cluster logic block (CLB) circuits 120 that serve as logic circuits and include a look-up table, and the like. A plurality of connection box (CB) circuits 140 for connecting the logic block circuit 120 are provided. That is, in this specific example, each switching block circuit 100 is connected to one cluster logic lock circuit 120 via at least one connection box circuit 140. The FPGA circuit of this specific example is also a small area FPGA circuit.

  As described above, according to the present embodiment, it is possible to obtain a switching box circuit, a switching block circuit, and an FPGA circuit that can achieve high integration and low power consumption.

(Second Embodiment)
Next, a switching box circuit according to a second embodiment of the present invention will be described. In the switching box circuit of the first embodiment, the spin MOSFETs 14 _{1 to} 14 ₈ are n-type spin MOSFETs. The switching box circuit of this embodiment has a configuration in which the spin MOSFETs 14 _{1 to} 14 ₈ are p-type spin MOSFETs in the switching box circuit of the first embodiment.

For this reason, the configuration of the memory unit 12b and the output unit 12c of each input / output unit 12 _i (i = 1,..., 4) is different from the switching box circuit of the first embodiment.

A specific example of the output unit 12c according to the present embodiment is shown in FIG. The output portion 12c of this embodiment, in the output unit 12c shown in FIG. 5 has a configuration obtained by replacing the p-type MOSFET12c ₁ to n-type MOSFET12cA _1. The n-type MOSFET12cA ₁ has a drain connected to the spin MOSFET, the source is grounded, it receives the NOT-ENABLE signal to the gate.

FIG. 12 shows a specific example of the memory unit 12b according to this embodiment. Memory unit 12 of this embodiment is made a p-type MOSFET12b ₂ and n-type spin MOSFET12b ₃ of the memory unit 12b shown in FIG. 6, a structure obtained by replacing each of the p-type spin MOSFET12bA ₂ and n-type MOSFET12bA _3.

In the memory section 12b of this embodiment, READ signal is H level, when NOT-READ signal is at the L level, power is supplied to the spin MOSFET12bA _3, performs the transistor operation. At this time, if the spin MOSFET12bA ₃ is a low resistance state, ENABLE signal becomes H level, the spin MOSFET12bA ₃ is as long as the high-resistance state, ENABLE signal becomes L level.

In the present embodiment, except that the p-type spin MOSFET 14 ₁ to 14 ₈ at L-level of the CLOCK signal applied to the gate of the p-type spin MOSFET 14 ₁ to 14 ₈ (clock signal) is conducting, the first embodiment Operates in the same way as the form.

  Similarly to the first embodiment, the switching box circuit of this embodiment can be configured with 77% of the number of elements in the case of the conventional switching box circuit using CMOS, and the occupied circuit area can be reduced. And can be integrated. Also in the present embodiment, low power consumption can be achieved as in the first embodiment.

  Similarly to the first embodiment, a switching block circuit can be configured by using the switching box circuit of the present embodiment, and an FPGA circuit can be configured by using this switching block circuit. it can.

  As described above, according to the present embodiment, it is possible to obtain a switching box circuit, a switching block circuit, and an FPGA circuit that can achieve high integration and low power consumption.

(Third embodiment)
Next, a switching box circuit 1A according to a third embodiment of the present invention will be described with reference to FIG. The switching box circuit 1A of the first and second embodiments has one signal line arranged in each of the four directions, but the switching box circuit of this embodiment has two signal lines arranged in each of the four directions. It has been configured. That is, two signal lines SL ₁₁ and SL ₁₂ are arranged above, two signal lines SL ₂₁ and SL ₂₂ are arranged on the left side, and two signal lines SL ₃₁ and SL ₃₂ are arranged below. Are arranged, and two signal lines SL ₄₁ and SL ₄₂ are arranged on the right side. In the present embodiment, one input / output unit 12 _ij is provided corresponding to each signal line SL _ij (i, j = 1, 2). In the present embodiment, four connection terminals 10 ₁ to 10 ₄ and 32 n-type spin MOSFETs 14 _ijk (i = 1,..., 4, j = 1, 2, k = 1,. .., 4) are provided.

In the present embodiment, each input / output unit 12 _ij (i = 1,..., 4, j = 1, 2) is connected to the connection terminal 10 _k (k = 1,..., 4) with the spin MOSFET 14. connected via _ijk .

  In the present embodiment configured as described above, an arbitrary signal line in a certain direction is connected to an arbitrary signal line in the other direction through each connection terminal, and there are four connection paths. Each path has a configuration in which two spin MOSFETs are connected in series with a connection terminal interposed therebetween. Therefore, similarly to the switching box circuit of the first embodiment, the switching box circuit of this embodiment can be connected to any signal line in any direction.

  In the switching box circuit according to the present embodiment, the total number of elements including the MOSFET and the spin MOSFET is 176. In a conventional switching box circuit composed only of CMOS, the number is 416. For this reason, the switching box circuit of this embodiment can also be configured with 42% of the number of elements as compared with the conventional switching box circuit using CMOS, as in the first embodiment, and the occupied circuit area is also large. It can be made smaller and can be integrated. Also in the present embodiment, low power consumption can be achieved as in the first embodiment.

Similarly to the first embodiment, a switching block circuit can be configured by using the switching box circuit 1A of the present embodiment, and an FPGA circuit can be configured by using the switching block circuit. it can. A specific example of the switching block circuit configured using the switching box circuit 1A of the present embodiment is shown in FIG. In the switching block circuit of this specific example, 2m signal lines are arranged in each of four directions. Above 2m signal lines _{SL 1 i (i = 1,} ···, 2m) is disposed on the left 2m of signal lines _{SL 2 i (i = 1,} ···, 2m) is 2 m signal lines SL _{3 i} (i = 1,..., 2 m) are arranged below, and 2 m signal lines SL _{4 i} (i = 1,. 2m) is arranged. In the switching block circuit of this embodiment is, m-number of switching box circuits 1A ₁ to 1A _m of this embodiment is provided. Two signal lines SL _{i 2j−1} , SL _{i 2j} (i = 1,..., 4, j = 1,..., M) are paired and connected to the switching box circuit 1A _j . It has a configuration. The switching block circuit of this specific example is also a switching block circuit with a small area.

  Further, as described in the first embodiment, an FPGA circuit can be configured by using the switching block circuit of the specific example.

  In this embodiment, the spin MOSFET is an n-type spin MOSFET. However, as described in the second embodiment, a switching block circuit, a switching block circuit, and an FPGA circuit are configured using a p-type spin MOSFET. can do.

  As described above, according to the present embodiment, it is possible to obtain a switching box circuit, a switching block circuit, and an FPGA circuit that can achieve high integration and low power consumption.

(Fourth embodiment)
Next, a switching box circuit according to a fourth embodiment of the present invention will be described. In the switching box circuit of the third embodiment, two signal lines are arranged in each direction. In the present embodiment, n (> 3) signal lines are arranged in each direction.

As can be seen from the description of the third embodiment, in the switching box circuit of the present embodiment, one input / output unit is provided corresponding to each signal line in each direction, and 2n connection terminals are provided. . Each input / output unit and each connection terminal are connected via one spin MOSFET. That is, 2n ² (= n × 2n) spin MOSFETs are provided corresponding to each direction.

  Also in this embodiment configured as described above, an arbitrary signal line in a certain direction is connected to an arbitrary signal line in the other direction through each connection terminal, and there are 2n connection paths. In each path, two spin MOSFETs are connected in series. Therefore, similarly to the switching box circuit of the first embodiment, the switching box circuit of this embodiment can be connected to any signal line in any direction.

In the switching box circuit according to the present embodiment, the total number of elements including the MOSFET and the spin MOSFET is (8n ² + 72n). For switching box circuit constituted by a conventional CMOS, the number of elements is ² or 104n. FIG. 15 shows the relationship between the number n of signal lines and the number of elements when a switching box circuit is configured using spin MOSFETs and when a switching box circuit is configured only by CMOS. As can be seen from FIG. 15, when the switching box circuit is configured by using the spin MOSFET, the number of elements is greatly increased as the number of signal lines n is increased as compared with the case where the switching box circuit is configured by only CMOS. It becomes possible to reduce.

  As described above, the switching box circuit of the present embodiment can be configured with a significantly smaller number of elements, and can occupy a smaller circuit area than the switching box circuit using only CMOS, and can be integrated. It becomes possible to do. Also in the present embodiment, low power consumption can be achieved as in the first embodiment.

As in the first embodiment, a switching block circuit can be configured by using the switching box circuit of the present embodiment, and an FPGA circuit can also be configured by using this switching block circuit. . A specific example of a switching block circuit configured using the switching box circuit of this embodiment is shown in FIG. In the switching block circuit of this specific example, m signal line groups are arranged in four directions, and each signal line group is composed of n signal lines. M sets of signal line groups upwards _{SLG 1 i (i = 1,} ···, m) is disposed on the left m sets of signal line groups _{SLG 2 i (i = 1,} ···, m ) are arranged, _SLG m sets of signal lines on the lower side _{3 i (i = 1, ···} , m) is located, m sets of signal line groups to the right _{SLG 4} i (i = 1, ..., m) are arranged. Each signal line group SLG _{i j} (i = 1,..., 4, j = 1,..., M) is composed of n signal lines.

In the switching block circuit of this embodiment is, m-number of switching box circuit 1B ₁ ~1B _m of this embodiment is provided. Each signal line group SLG _{i j} (i = 1,..., 4, j = 1,..., M) is connected to the switching box circuit 1B _j . The switching block circuit of this specific example is also a switching block circuit with a small area.

  Further, as described in the first embodiment, an FPGA circuit can be configured by using the switching block circuit of the specific example.

  In this embodiment, the spin MOSFET is an n-type spin MOSFET. However, as described in the second embodiment, a switching block circuit, a switching block circuit, and an FPGA circuit are configured using a p-type spin MOSFET. can do.

  As described above, according to the present embodiment, it is possible to obtain a switching box circuit, a switching block circuit, and an FPGA circuit that can achieve high integration and low power consumption.

  In the present specification, MOSFET means a field effect transistor using a gate insulating film other than an oxide, for example, a nitride film or a high dielectric insulating film.

  According to each embodiment of the present invention, since a spin MOSFET having a non-volatile magnetic memory is used, the state immediately before turning off the power can be maintained and the circuit operation can be performed immediately after turning on the power. It is possible to start, and it is possible to eliminate the waiting time immediately after the power is turned on, and to reduce the power consumption by turning off the power when the circuit operation is stopped.

  In addition, by using the switching box circuit of each embodiment of the present invention for a reconfigurable logic circuit, an effect that a highly integrated circuit can be manufactured can be obtained.

1 switching box circuit 1A switching box circuit 10 ₁ to 10 ₄ connection terminal 12 _{1 to} 12 ₄ input / output unit 14 _{1 to} 14 ₈ spin MOSFET
SL ₁ ~SL ₄ signal line

Claims (9)

First to nth (≧ 1) signal lines respectively provided in first to fourth directions;
The first to nth input / output units provided in the first to fourth directions, respectively, wherein the i-th (1 ≦ i ≦ n) input / output unit in each direction has a direction corresponding to one end. First to nth input / output units connected to the i-th signal line;
First to 2n connection terminals;
Provided in each of the first to fourth directions, and in order to connect each of the first to nth input / output units and each of the first to second n connection terminals in each direction. 2n ² spin MOSFETs provided one by one and receiving a clock signal at the gate;
A switching box circuit comprising: An address unit that sends the address signal to the gates of all the spin MOSFETs connected to one of the first to second n connection terminals, and makes it conductive;
A first driver / sinker unit electrically connected to the first to second n connection terminals;
A second driver / sinker unit electrically connected between the first to nth input / output units and the spin MOSFET;
With
The first and second driver / sinker units select one spin MOSFET from the spin MOSFETs made conductive by the address unit, pass a current through the selected spin MOSFET, and write to the spin MOSFET. The switching box circuit according to claim 1, wherein the switching box circuit is performed.   The input / output unit receives an electric signal from a signal line to be connected, and inputs the electric signal to a spin MOSFET to be connected, and a signal line to connect an electric signal sent from the spin MOSFET to be connected. An output unit for sending to the memory, and a memory unit for outputting a control signal that operates one of the input unit and the output unit and disables the other according to a storage state of the memory. The switching box circuit according to claim 1, further comprising a switching box circuit.   4. The switching box circuit according to claim 3, wherein all the spin MOSFETs are n-type spin MOSFETs. The memory unit includes a first p-type MOSFET that receives a first control signal at a gate and is applied with a power supply voltage at a source, and a predetermined voltage that is applied to a gate and the source at a drain of the first p-type MOSFET. A second p-type MOSFET to be connected; a first n-type spin MOSFET in which the predetermined voltage is applied to a gate and a drain is connected to a drain of the second p-type MOSFET; A first n-type MOSFET having a drain connected to a source of the first n-type spin MOSFET and having a source grounded, which receives an inverted signal of the control signal, and an inverter; a drain of the second p-type MOSFET; A second control signal is output from a connection node with the drain of the first n-type spin MOSFET, and the inverter receives the second control signal and receives the second control signal. It outputs an inverted signal of the control signal,
The input unit includes a third p-type MOSFET and a second n-type MOSFET, and is a transfer gate that allows the electrical signal to pass based on the second control signal,
The output unit operates based on the second control signal, a sense amplifier that receives an electrical signal from a connected spin MOSFET at a first input terminal and receives a reference voltage at a second input terminal, and a power supply voltage is applied to a source. And a fourth p-type MOSFET having a drain connected to the first input terminal of the sense amplifier, a fifth p-type MOSFET, and a third n-type MOSFET. The sense is based on the second control signal. A transfer gate that passes the output of the amplifier;
The switching box circuit according to claim 4, further comprising:   4. The switching box circuit according to claim 3, wherein all the spin MOSFETs are p-type spin MOSFETs. The memory unit is
A first p-type MOSFET that receives a first control signal at its gate and is applied with a power supply voltage at its source;
A first p-type spin MOSFET in which a predetermined voltage is applied to a gate and a source is connected to a drain of the first p-type MOSFET;
A first n-type MOSFET whose gate is applied with the predetermined voltage and whose drain is connected to the drain of the first p-type spin MOSFET;
A second n-type MOSFET having a gate receiving an inverted signal of the first control signal and a drain connected to the source of the first n-type MOSFET and a source grounded;
An inverter;
A second control signal is output from a connection node between the drain of the first p-type spin MOSFET and the drain of the first n-type MOSFET, and the inverter receives the second control signal and outputs the second control signal. 2 to output the inverted signal of the control signal,
The input unit is
A transfer gate including a second p-type MOSFET and a third n-type MOSFET and allowing the electrical signal to pass based on the second control signal;
The output unit is
A sense amplifier that receives an electrical signal from a connected spin MOSFET at a first input terminal and a reference voltage at a second input terminal;
A fourth n-type MOSFET that operates based on the second control signal and has a source grounded and a drain connected to the first input terminal of the sense amplifier;
A transfer gate including a third p-type MOSFET and a fifth n-type MOSFET and passing the output of the sense amplifier based on the second control signal;
The switching box circuit according to claim 6, further comprising: First to m-th (≧ 2) signal line groups each provided in first to fourth directions, each including n signal lines;
A first to mth (≧ 2) switching box circuit according to any one of claims 1 to 7,
With
A switching block circuit, wherein an i-th (1 ≦ i ≦ m) signal line group in the first to fourth directions is connected to an i-th switching box circuit.   9. An FPGA circuit comprising: the switching block circuit according to claim 8; a cluster logic block circuit including a lookup table; and a connection block circuit for connecting the switching block circuit and the cluster logic block circuit. .

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