JP5686071B2 - Clock frequency detector - Google Patents

Description

  The present invention relates to a clock frequency detection device suitable for detecting the frequency of a clock signal in an electronic device that operates in synchronization with a clock signal having a fixed period.

  In an electronic device 80 that operates in synchronization with a clock signal, such as a microcomputer or an IC, a reference clock with a constant frequency output from the oscillator 4 is divided by using the PLL circuit 10 as illustrated in FIG. Alternatively, an operation clock signal (operation clock) is generated by multiplication.

  For this reason, in this type of electronic device, the frequency of the operation clock may fluctuate due to abnormal oscillation of the oscillator 4, variation in characteristics of the PLL circuit 10, temperature characteristics, or the like, and the frequency is within an allowable range. It is necessary to detect whether or not.

  On the other hand, a frequency detection device that detects the frequency of an input signal usually includes a bandpass filter that selectively passes a signal having a certain frequency to be detected, and inputs the input signal to the bandpass filter. Is detected to detect whether the input signal has a desired frequency (see, for example, Patent Document 1).

  Therefore, in order to determine whether or not the operation clock generated by the PLL circuit 10 of FIG. 10 is normal using such a conventional frequency detection device, a bandpass that allows the operation clock to pass through the electronic device of FIG. A filter (BPF) 82 and a pulse detection circuit 84 that detects a pulse of a predetermined level or higher that has passed through the BPF 82 may be provided.

  That is, in this way, whether or not the operation clock is a desired frequency corresponding to the pass frequency band of the BPF 82 can be determined based on whether or not the pulse detection circuit 84 detects a pulse of a predetermined level or higher.

JP2009-198383

  However, when the frequency of the operation clock is detected using the BPF 82 and the pulse detection circuit 84 as described above, the detection accuracy depends on the accuracy of the BPF 82 and the pulse detection circuit 84.

  For this reason, if the conventional frequency detection device described above is used to detect the operation clock of the electronic device, the operation is affected by variations in the manufacturing of circuit elements constituting the BPF 82 and the pulse detection circuit 84. It is conceivable that the clock frequency (and thus the frequency abnormality) cannot be detected with high accuracy.

  That is, for example, the BPF 82 has a manufacturing variation of several tens of percent in the characteristics of its constituent elements such as the resistor R and the capacitor C, and the characteristics change depending on the temperature. It is difficult to accurately detect the clock frequency.

  The present invention has been made in view of these problems, and can detect the frequency of an operation clock of an electronic device, and thus, an abnormality in frequency with high accuracy without using a filter circuit such as a bandpass filter. It is an object of the present invention to provide a clock frequency detection device that can be used.

  In order to achieve this object, the invention according to claim 1 is an electronic device comprising a voltage signal generating means for receiving a clock signal and generating a voltage signal having a predetermined voltage value. The present invention relates to a clock frequency detection device that detects the frequency of a clock signal, and comprises a mode switching means and a frequency detection means.

  Then, the mode switching means changes the frequency-to-voltage characteristic representing the relationship between the voltage value of the voltage signal output from the voltage signal generating means and the frequency of the clock signal from the first characteristic during normal operation to the second for frequency detection. By switching to the characteristic, the operation mode of the electronic device is switched from the normal operation mode to the frequency detection mode.

  The frequency detection means is a voltage signal output from the voltage signal generation means (specifically, a voltage signal corresponding to the second characteristic) when the operation mode of the electronic device is switched to the frequency detection mode by the mode switching means. The frequency of the clock signal is detected based on the voltage value.

  Therefore, according to the clock frequency detection device of the present invention, based on the voltage value and the second characteristic of the voltage signal output from the voltage signal generation means in the frequency detection mode without using a bandpass filter as in the prior art. The frequency F of the clock signal can be accurately detected.

Further, according to the present invention, the frequency of the voltage signal output from the voltage signal generation unit is not simply detected based on the output from the voltage signal generation unit, but in the normal operation mode in which the frequency is not detected. Since the voltage characteristic is set to the first characteristic, the frequency of the clock signal can be detected without affecting the normal operation of the voltage signal generating means.
The first characteristic is a constant voltage characteristic in which the voltage value of the voltage signal is constant or substantially constant with respect to a frequency change within the allowable variation range of the frequency of the clock signal. Sometimes, a voltage signal having a constant or substantially constant voltage value can be generated, and a constant voltage can be supplied to a circuit that requires the generated constant voltage signal.
On the other hand, the second characteristic of the voltage signal generation means set in the frequency detection mode is that the voltage value of the voltage signal is constant or substantially constant corresponding to the change in frequency within the allowable variation range of the frequency of the clock signal. It is a linear characteristic that changes in proportion.
For this reason, the voltage value of the voltage signal obtained when the voltage signal generating means operates with the second characteristic greatly changes according to the frequency of the clock signal, and the frequency detecting means By using the voltage value, the frequency of the clock signal can be accurately detected.

  Here, the frequency detection means detects a frequency corresponding to the voltage value of the voltage signal output from the voltage signal generation means based on the frequency-to-voltage characteristic (second characteristic) of the voltage signal generation means in the frequency detection mode. You may do it.

However, for example, when determining whether or not the frequency of the operation clock of the electronic device is normal, the frequency detection means may be configured as described in claim 2.
That is, in the clock frequency detection device according to claim 2, when the electronic device is in a frequency detection mode, the frequency detection means has an allowable voltage range in which the voltage value of the voltage signal output from the voltage signal generation means is set in advance. By determining whether the frequency is within the range, it is determined whether the frequency of the clock signal is within the allowable frequency range corresponding to the allowable voltage range in the second characteristic.

  In this case, the frequency detection means does not uniquely detect the frequency from the voltage value, but determines whether the frequency of the clock signal is abnormal depending on whether the voltage value is within the allowable voltage range. If the allowable voltage range to be used is set in consideration of variations in the frequency-voltage characteristics of the voltage signal generation means, it can be accurately determined whether or not the frequency of the clock signal is within the allowable frequency range. .

  On the other hand, the clock frequency detecting device according to claim 3 is provided with mode switching means and frequency detecting means, and the mode switching means changes the operation mode of the electronic device from the normal operation mode to the frequency detection mode. Although the same as the clock frequency detection means according to the first and second embodiments, the frequency detection procedure by the frequency detection means is different from the clock frequency detection apparatus according to the first and second aspects.

  That is, in the clock frequency detection device according to claim 3, when the operation mode of the electronic device is switched to the frequency detection mode by the mode switching unit, the frequency detection unit switches the frequency-to-voltage characteristic of the voltage signal generation unit. A change in the voltage value of the voltage signal caused by the detection is detected as a voltage difference, and the frequency of the clock signal is detected based on the voltage difference.

  For this reason, according to the clock frequency detection device of the third aspect, for example, by using the frequency-to-voltage difference characteristic that represents the voltage value difference between the first characteristic and the second characteristic for each frequency, The frequency of the clock signal can be detected from the difference between the voltage values of the voltage signals (detection voltage difference).

  Further, as in the first aspect, in the normal operation mode, the frequency-voltage characteristic of the voltage signal generating means can be set to the first characteristic during the normal operation, so that the voltage signal generating means can operate normally. The frequency of the clock signal can be detected without affecting it.

  Here, the frequency detection unit according to claim 3 is configured to calculate the voltage difference between the voltage signals output from the voltage signal generation unit in the normal operation mode and the frequency detection mode of the electronic device as the voltage difference used for frequency detection. Alternatively, the frequency characteristic may be detected by switching the frequency-to-voltage characteristic from the second characteristic to the third characteristic in the frequency detection mode of the electronic device, and the second characteristic obtained thereby. The voltage difference between the voltage signals corresponding to the third characteristic may be detected.

  As in the former, in the frequency detection means, the voltage value of the voltage signal corresponding to the first characteristic obtained in the normal operation mode and the voltage value of the voltage signal corresponding to the second characteristic obtained in the frequency detection mode In order to be able to detect the voltage difference, a voltage value input means may be provided as described in claim 4.

  That is, in the clock frequency detection device according to claim 4, when the electronic device is in the frequency detection mode, the voltage value input means determines the voltage value of the voltage signal output from the voltage signal generation means as the voltage in the normal operation mode. Along with the voltage value of the voltage signal output from the signal generation means, it is input to the frequency detection means.

  For this reason, the frequency detection means can detect the frequency of the clock signal using the voltage difference between the two types of voltage values input from the voltage value input means when the electronic device is in the frequency detection mode.

  Further, in this manner, when the operation mode of the electronic device is the frequency detection mode, the voltage value input unit can input the voltage values of the two types of voltage signals to the frequency detection unit. The voltage value holding means may be provided as described above, or the reference voltage generating means may be provided as described in claim 6.

  In other words, in the clock frequency detecting device according to claim 5, the voltage value holding means holds the voltage value of the voltage signal output from the voltage signal generating means when the electronic device is in the normal operation mode, and then Even when the device is switched to the frequency detection mode, the voltage value is continuously held.

  When the electronic device is switched to the frequency detection mode, the voltage value input means detects the voltage value held by the voltage value holding means and the voltage value of the voltage signal output from the voltage signal generation means. Enter the means.

  Therefore, in the clock frequency detection device according to claim 5, the voltage value input means uses the voltage value held in the voltage value holding means to obtain the two kinds of voltage values in the frequency detection mode. Can be entered.

  According to a sixth aspect of the present invention, the reference voltage generating means generates a voltage signal from the clock signal with the first characteristic regardless of the switching state of the operation mode of the electronic device by the mode switching means.

  The voltage value input means, when the electronic device is switched to the frequency detection mode, the voltage value of the voltage signal output from the reference voltage generation means, and the voltage value of the voltage signal output from the voltage signal generation means, Input to the frequency detection means.

  Therefore, in the clock frequency detection device according to claim 6, the voltage value input means uses the voltage value generated by the reference voltage generation means having a constant frequency-to-voltage characteristic (first characteristic), In the frequency detection mode, the two kinds of voltage values can be input to the frequency detection means.

  On the other hand, in the clock frequency detecting device according to claim 7, the mode switching means switches the frequency-to-voltage characteristic of the voltage signal output from the voltage signal generating means from the first characteristic to the second characteristic, thereby operating the electronic device. After setting the mode to the frequency detection mode, the frequency-voltage characteristic is changed from the second characteristic to the third characteristic.

The frequency detection means detects the voltage difference between the voltage signals corresponding to the second characteristic and the third characteristic, which are sequentially output from the voltage signal generation means when the electronic device is in the frequency detection mode, and determines the voltage difference. Based on this, the frequency of the clock signal is detected.
The third characteristic is a linear characteristic in which the voltage value of the voltage signal changes at a constant or substantially constant rate in response to a change in the frequency within the allowable variation range of the frequency of the clock signal. The change rate of the voltage value is different.
For this reason, when the frequency-to-voltage characteristic of the voltage signal generation unit is changed from the second characteristic to the third characteristic, the voltage difference generated for each frequency between the second characteristic and the third characteristic changes according to the frequency. Will do.

  Therefore, according to the clock frequency detecting device of the seventh aspect, the second characteristic and the third characteristic are obtained by using the frequency-to-voltage difference characteristic that represents the difference between the voltage values in the second characteristic and the third characteristic for each frequency. The frequency of the clock signal can be accurately detected from the voltage difference between the voltage signals corresponding to.

  In this way, when the operation mode of the electronic device is the frequency detection mode, the frequency detection unit switches the frequency-to-voltage characteristic of the voltage signal output from the voltage signal generation unit from the second characteristic to the third characteristic. In order to make it possible to detect the frequency of the clock signal, the voltage value holding means and the voltage value input means may be provided as described in claim 8.

  That is, in the clock frequency detection device according to claim 8, the voltage value holding means is when the electronic device is in the frequency detection mode and the frequency-voltage characteristic of the voltage signal output from the voltage signal generation means is the second characteristic. The voltage value of the voltage signal output from the voltage signal generation means is held, and then the voltage value is continuously held even if the frequency-voltage characteristic is switched to the third characteristic.

  Further, the voltage value input means is configured so that when the electronic device is in the frequency detection mode and the frequency-voltage characteristic of the voltage signal output from the voltage signal generation means is switched from the second characteristic to the third characteristic, the voltage value holding means The held voltage value and the voltage value of the voltage signal output from the voltage signal generation unit are input to the frequency detection unit.

  Therefore, in the clock frequency detection device according to claim 8, the frequency detection means switches the operation mode of the electronic device to the frequency detection mode by the operation mode switching means, and further outputs the voltage output from the voltage signal generation means. After the frequency-to-voltage characteristic of the signal is switched from the second characteristic to the third characteristic, the frequency of the clock signal can be detected using the voltage difference between the two types of voltage values input from the voltage value input means. .

  Here, in the clock frequency detection device according to any one of claims 3 to 8, the frequency detection means is based on a voltage difference between voltage values of two kinds of voltage signals obtained in two kinds of environments having different frequency versus voltage characteristics. The frequency of the clock signal is detected. When determining whether or not the frequency of the operation clock of the electronic device is normal, the frequency detection means may be configured as described in claim 9.

  That is, in the clock frequency detection device according to claim 9, the frequency detection means determines whether or not the voltage difference between the two types of voltage signals is within a preset allowable voltage difference range. Is determined to be within the allowable frequency range corresponding to the allowable voltage difference range in the frequency-voltage difference characteristic.

  Therefore, according to the clock frequency detecting device of the ninth aspect, the frequency-to-voltage characteristics (first characteristic and second characteristic or second characteristic and third characteristic) of the voltage signal switched by the mode switching means. Even if the above-described frequency-to-voltage difference characteristic varies due to the variation, whether the frequency of the clock signal is within the allowable frequency range by setting the allowable voltage difference range in advance in consideration of the variation. It becomes possible to judge accurately.

  Next, the mode switching means only needs to be able to switch the frequency-voltage characteristics when the voltage signal generating means receives the clock signal to generate the voltage signal to the above characteristics, and the mode switching means You may make it perform periodically with the preset time interval.

However, if this is done, the operation mode may be switched regardless of the operation state of the electronic device to which the present invention is applied, which may adversely affect the operation of the electronic device.
Therefore, as described in claim 10 , when the mode switching means receives an instruction to switch the operation mode of the electronic device from an internal circuit of the electronic device or an external circuit that controls the electronic device, the mode switching means sets the frequency of the operation mode of the electronic device. It is preferable to switch to the detection mode and activate the frequency detection operation of the clock signal by the frequency detection means.

  In other words, in this way, the operation mode of the electronic device can be switched from the normal operation mode to the frequency detection mode by a switching command from the internal circuit of the electronic device or the external circuit that controls the electronic device. It is possible to prevent an abnormality in the operation of the electronic device by switching the mode.

Further, in switching the operation mode of the electronic device, the mode switching means is connected to the circuit elements constituting the voltage signal generating means and the output path of the voltage signal from the voltage signal generating means, as described in claim 11. It is preferable that the frequency vs. voltage characteristic of the voltage signal is switched from the first characteristic to the second characteristic (or the second characteristic and the third characteristic) by changing at least one of the circuit elements to be processed.

  In this way, in the electronic device provided with the voltage signal generating means, it is not necessary to change the voltage signal generating means to a new one in order to apply the present invention, and the present invention is realized at low cost. It will be possible.

It is a block diagram showing schematic structure of the control apparatus of 1st Embodiment. It is explanatory drawing showing the F / V conversion characteristic of the F / V conversion circuit of 1st Embodiment. It is a flowchart showing operation | movement of the frequency abnormality determination part of 1st Embodiment. It is a block diagram showing schematic structure of the control apparatus of 2nd Embodiment. It is a block diagram showing schematic structure of the control apparatus of 3rd Embodiment. It is a flowchart showing operation | movement of the frequency abnormality determination part of 3rd Embodiment. It is explanatory drawing showing the characteristic of the signal output from the voltage difference detection part of 3rd Embodiment. It is a block diagram showing schematic structure of the control apparatus of the modification 1. FIG. 10 is a block diagram illustrating a schematic configuration of a control device according to a second modification. It is a block diagram showing schematic structure of the conventional electronic device.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
As shown in FIG. 1, the clock frequency detection device according to the present embodiment is incorporated in a control device 2 mainly composed of a microcomputer, such as an electronic control device mounted on an automobile, for example. It detects whether the frequency is normal.

  Like the conventional electronic device shown in FIG. 10, the control device 2 is provided with a PLL circuit 10 that generates an operation clock by dividing or multiplying a reference clock having a constant frequency input from the oscillator 4. Yes.

  The operation clock (clock signal having a constant frequency) generated by the PLL circuit 10 is used as an operation clock for the CPU, ROM, RAM, and peripheral circuits constituting the microcomputer in the control device 2 in the control device 2. Are supplied to each part of

  The control device 2 also includes a frequency / voltage for generating a voltage for writing to the semiconductor memory 12 composed of a rewritable nonvolatile memory, for example, as one of the circuits that operate by receiving a clock signal from the PLL circuit 10. A conversion circuit (hereinafter referred to as an F / V conversion circuit) 20 is provided, and the clock frequency detection device of the present embodiment uses the F / V conversion circuit 20 to operate the frequency of the operation clock (specifically, an abnormal frequency). ) Is detected.

  That is, in the clock frequency detection device of the present embodiment, the operation mode switching unit 32 that switches the operation mode of the F / V conversion circuit 20 from the normal operation mode to the frequency detection mode, and the operation mode of the F / V conversion circuit 20 is the frequency. A voltage detection unit 34 that receives a command from the operation mode switching unit 32 and detects a write voltage output from the F / V conversion circuit 20 to the semiconductor memory 12 when the mode is switched to the detection mode; It comprises a frequency abnormality determination unit 36 that determines abnormality in the frequency of the operation clock based on the voltage value detected by the detection unit 34.

  First, the F / V conversion circuit 20 receives a clock signal (operation clock) input from the PLL circuit 10 and boosts the power supply voltage in the control device 2 generated by a power supply circuit (not shown). The high voltage boosted by the charge pump 22 is output as a write voltage for the semiconductor memory 12.

  Further, the F / V conversion circuit 20 includes a constant current source 24 having one end connected to the voltage output path from the charge pump 22 to the semiconductor memory 12 and the other end of the constant current source 24 grounded to the ground line. A changeover switch SW1 for switching the frequency-to-voltage characteristic (F / V conversion characteristic) of the write voltage output from the F / V conversion circuit 20 by switching between the two is provided.

  That is, since the F / V conversion circuit 20 generates a write voltage for the semiconductor memory 12, the charge pump 22 that generates this voltage writes to the semiconductor memory 12 even if the operation clock fluctuates slightly. The write voltage is generated with the F / V conversion characteristic (first F / V conversion characteristic shown in FIG. 2A) with a small voltage change with respect to the frequency of the operation clock so as not to affect the operation. It is configured.

  In the F / V conversion circuit 20, if the changeover switch SW1 is in the OFF state, a constant current does not flow from the voltage output path to the semiconductor memory 12 via the constant current source 24 to the ground line. The F / V conversion characteristic of the circuit 20 is the first F / V conversion characteristic.

  Even when the changeover switch SW1 is in the OFF state, when the load current flows through the F / V conversion circuit 20 after writing to the semiconductor memory 12, the F / V conversion characteristics of the F / V conversion circuit 20 are satisfied. However, in this embodiment, the frequency of the operation clock is not detected when writing to the semiconductor memory 12 by the processing described later, so the characteristics when writing to the semiconductor memory 12 are not detected. A description of the change is omitted.

On the other hand, when the changeover switch SW1 is turned on, a load current flows from the voltage output path to the semiconductor memory 12 to the ground line via the constant current source 24.
Therefore, in the F / V conversion circuit 20, if the changeover switch SW1 is in the ON state, the F / V conversion characteristics change according to the frequency of the operation clock, and the output voltage decreases as the frequency of the operation clock decreases. F / V conversion characteristics (second F / V conversion characteristics shown in FIG. 2A) are obtained.

  Next, the changeover switch SW1 is turned on / off by the operation mode switching unit 32. That is, the operation mode switching unit 32 turns on the switch SW1 when operating the F / V conversion circuit 20 in the frequency detection mode, and switches the switch SW1 when operating the F / V conversion circuit 20 in the normal operation mode. Is kept off.

  As a result, when the operation mode is the normal operation mode, the F / V conversion circuit 20 generates a voltage signal corresponding to the first F / V conversion characteristic (constant voltage characteristic) in which the voltage value becomes substantially constant with respect to the frequency change. If the operation mode is the frequency detection mode, a voltage signal corresponding to the second F / V conversion characteristic (linear characteristic) in which the voltage value changes corresponding to the frequency is output.

  If the output voltage from the F / V conversion circuit 20 to the semiconductor memory 12 is detected when the operation mode of the F / V conversion circuit 20 is the frequency detection mode, the voltage value and the second F / V conversion characteristic are obtained. By utilizing this, the frequency of the operation clock can be detected.

  Further, in order to improve the detection accuracy of the frequency of the operation clock, as shown in FIG. 2A, the second F / V conversion characteristic is output corresponding to the frequency of the operation clock near the target frequency fo of the operation clock. The voltage may be changed linearly (or substantially linearly).

  Further, in order to determine whether or not the frequency of the operation clock is within the normal frequency range centered on the target frequency fo (in other words, the allowable frequency range), as shown in FIG. It may be determined whether or not the output voltage from the conversion circuit 20 to the semiconductor memory 12 is within a normal output voltage range corresponding to the normal frequency range.

  Therefore, in the present embodiment, the frequency abnormality determination unit 36 outputs an operation mode switching signal to the operation mode switching unit 32, whereby the operation mode of the F / V conversion circuit 20 is set to the normal operation mode switching unit 32. Switch from operation mode to frequency detection mode.

Further, when the operation mode switching unit 32 switches the operation mode of the F / V conversion circuit 20 to the frequency detection mode, the voltage detection unit 34 is activated at the same time.
For this reason, when the frequency abnormality determination unit 36 causes the operation mode switching unit 32 to switch the operation mode of the F / V conversion circuit 20 to the frequency detection mode, the frequency abnormality determination unit 36 reads the detection result from the voltage detection unit 34 after a predetermined delay time. It is determined whether or not the frequency of the operation clock generated by the circuit 10 is normal.

Hereinafter, the operation of the frequency abnormality determination unit 36 will be described in detail with reference to the flowchart shown in FIG.
Note that the frequency abnormality determination unit 36 is realized as, for example, one of control processes executed by a microcomputer (more specifically, a CPU) that constitutes the control device 2, and the flowchart shown in FIG. The frequency abnormality determination process executed by the microcomputer in order to realize the function as the abnormality determination unit 36 is shown.

  As shown in FIG. 3, when the frequency abnormality determination process is started, first, in S110, a predetermined set time To has elapsed since a series of determination processes in S120 to S180 described later were executed last time. Whether or not the set time To elapses.

When it is determined in S110 that the set time To has elapsed, the process proceeds to S120, and it is determined whether data is currently being written to the semiconductor memory 12.
If data is currently being written to the semiconductor memory 12, it is necessary to maintain the operation mode of the F / V conversion circuit 20 in the normal operation mode. Therefore, in S120, the process proceeds to S110 again, so that the semiconductor memory 12 waits for the writing of data to 12 to end.

  Next, when it is determined in S120 that data is not currently being written to the semiconductor memory 12, the process proceeds to S130, and a frequency detection mode switching signal is output to the operation mode switching unit 32. The operation mode switching unit 32 switches the operation mode of the F / V conversion circuit 20 from the normal operation mode to the frequency detection mode.

  Then, in the F / V conversion circuit 20, the changeover switch SW1 is switched from the off state to the on state, and the F / V conversion characteristic of the F / V conversion circuit 20 changes from the first F / V conversion characteristic to the second F / V. Switch to conversion characteristics. Further, the voltage detection unit 34 starts detecting the output voltage from the F / V conversion circuit 20.

  Therefore, after the frequency detection mode switching signal is output in S130, the frequency abnormality determination unit 36 determines that the delay time ΔT required for the detection result by the voltage detection unit 34 to stabilize has elapsed in S140. When the delay time ΔT has elapsed, the process proceeds to S150, and the detection voltage is read from the voltage detection unit 34.

  Next, in subsequent S160, the detected voltage read in S150 deviates from the normal output voltage range (see FIG. 2A) set in advance based on the second F / V conversion characteristic of the F / V conversion circuit 20. By determining whether or not there is an abnormality in the frequency of the operation clock generated by the PLL circuit 10, it is determined.

Note that the normal output voltage range used for this abnormality determination is stored in advance in a memory (not shown).
When it is determined in S160 that there is no abnormality in the frequency of the operation clock, the process proceeds to S180, and the normal operation mode switching signal is output to the operation mode switching unit 32, whereby the operation of the F / V conversion circuit 20 is performed. The mode is switched to the normal operation mode, and the process proceeds to S110 again.

  On the other hand, if it is determined in S160 that there is an abnormality in the frequency of the operation clock, the process proceeds to S170, and the number of continuous abnormality determinations of the operation clock frequency by the processing in S160 exceeds the preset failure determination value N. It is determined whether or not.

  If the number of continuous abnormality determinations exceeds the failure determination value N, it is determined that some abnormality has occurred in the oscillator 4, the PLL circuit 10, or the circuit in the control device 2 connected to the PLL circuit 10. Then, the internal circuit of the control device 2 is restarted by resetting the control device 2.

  If it is determined in S170 that the number of continuous abnormality determinations of the operation clock frequency does not exceed the failure determination value N, the process proceeds to S180, and the operation mode switching unit 32 receives the operation of the F / V conversion circuit 20. The mode is switched to the normal operation mode, and the process proceeds to S110 again.

  As described above, according to the clock frequency detection device of the present embodiment, the F / V conversion characteristic of the F / V conversion circuit 20 built in the control device 2 is changed by the operation mode switching unit 32 for normal operation. Switching from the first F / V conversion characteristic to the second F / V conversion characteristic for frequency detection, and F / V conversion when the F / V conversion circuit 20 is operating with the second F / V conversion characteristic (frequency detection mode). An output voltage from the circuit 20 is detected by the voltage detection unit 34, and the frequency abnormality determination unit 36 receives a clock signal (in other words, an operation clock of the control device 2) input to the F / V conversion circuit 20 from the detected voltage. ) Is normal.

  Therefore, according to the clock frequency detection device of the present embodiment, the frequency of the clock signal (operation clock) generated by the PLL circuit 10 is normal without using a bandpass filter as in the conventional frequency detection device. It is possible to detect whether or not.

  Therefore, according to the control device 2 of the present embodiment, whether or not the frequency of the operation clock of the control device 2 is normal as compared with the case where a conventional frequency detection device is used as the clock frequency detection device (in other words, Whether or not the control device 2 is operating normally based on the clock signal generated by the PLL circuit 10) can be accurately determined.

  In addition, the clock frequency detection device of the present embodiment does not simply determine the abnormality of the frequency of the clock signal (operation clock) based on the output from the F / V conversion circuit 20, but does not perform the abnormality determination of the frequency. By operating the F / V conversion circuit 20 in the normal operation mode, the output voltage from the F / V conversion circuit 20 can be used as a write voltage for the semiconductor memory 12.

  For this reason, according to the clock frequency detection device of the present embodiment, it can be realized by using the existing F / V conversion circuit 20 provided in the control device 2, and the control device 2 has an F dedicated to frequency detection. Since it is not necessary to separately provide a / V conversion circuit, the apparatus configuration can be simplified.

  In the clock frequency detection device according to the present embodiment, the frequency abnormality determination unit 36 determines whether the frequency of the clock signal is normal depending on whether the voltage value detected by the voltage detection unit 34 is within the normal output voltage range. It is determined whether or not it is within the frequency range, but this normal output voltage range is desirably set in consideration of variations in characteristics of the charge pump 22 and the like.

  That is, the charge pump 22 constituting the F / V conversion circuit 20 uses the clock signal (operation clock) input from the PLL 10 to transfer the charge accumulated in the previous stage capacitor to the next stage through the backflow prevention diode. By transferring to the capacitor, the output voltage from the last-stage capacitor is boosted to a voltage value higher than the power supply voltage.

  Therefore, the output voltage from the F / V conversion circuit 20 varies not only with the frequency of the operation clock but also with the capacitance of the capacitor constituting the charge pump 22, the forward voltage of the diode, the number of boosting stages by the capacitor, and the like. .

  When the F / V conversion circuit 20 is operating in the normal operation mode, the F / V conversion characteristic is set to the first F / V conversion characteristic in which the output voltage becomes substantially constant even when the frequency of the clock signal changes. Therefore, even if the capacitor capacity of the charge pump 22 varies, the F / V conversion characteristics of the F / V conversion circuit 20 do not change greatly.

  However, the second F / V conversion characteristic set when the operation mode of the F / V conversion circuit 20 is switched to the frequency detection mode is such that the output voltage is linear (or substantially linear) corresponding to the frequency of the clock signal. Since it changes, as shown in FIG. 2B, it changes under the influence of variations in the capacitor capacity and the like of the charge pump 22.

  Therefore, as in the present embodiment, it is determined whether or not the frequency of the clock signal is within the normal frequency range depending on whether or not the voltage value detected by the voltage detector 34 is within the normal output voltage range. In this case, it is desirable that the normality / abnormality of the frequency of the clock signal can be accurately determined even if the capacitance of the charge pump 22 varies.

  For this purpose, as shown in FIG. 2B, the voltage value of the second F / V conversion characteristic having the highest voltage value at the lowest frequency in the normal frequency range is set as the lower limit value of the normal voltage range, and the normal frequency is set. The voltage value of the second F / V conversion characteristic having the lowest voltage value at the maximum frequency within the range may be set as the upper limit value of the normal voltage range.

Here, in the present embodiment, the control device 2 corresponds to the electronic device described in the claims, and the F / V conversion circuit 20 corresponds to the voltage signal generation means described in the claims. The operation mode switching unit corresponds to the mode switching unit of the present invention, and the voltage detection unit 34 and the frequency abnormality determination unit 36 correspond to the frequency detection unit of the present invention, and the first F / conversion characteristic and the second F / V. The conversion characteristics correspond to the first characteristic and the second characteristic of the present invention, respectively.
[Second Embodiment]
Next, FIG. 4 is a block diagram showing a schematic configuration of the control device 2 including the clock frequency detection device of the second embodiment to which the present invention is applied.

  As shown in FIG. 4, the control device 2 of the present embodiment is configured around a microcomputer as in the control device of the first embodiment, and includes an operation clock generation PLL circuit 10 and a semiconductor memory 12. And an F / V conversion circuit 20 for generating a voltage for writing to the semiconductor memory 12.

In addition, the control device 2 includes a voltage detection unit 34, a frequency abnormality determination unit 36, and an operation mode switching unit 32 as a clock frequency detection device.
The difference of the control device 2 of the present embodiment from the first embodiment is that the F / V conversion circuit 20 is composed only of a charge pump 22 having a built-in changeover switch SW1 for switching the operation mode. There are other configurations similar to those described in the first embodiment.

  As shown in FIG. 4, the charge pump 22 constituting the F / V conversion circuit 20 receives a power supply voltage VDD (DC constant voltage) from a power supply circuit (not shown) and serially flows current to the output side. It comprises five connected diodes D1 to D5 and capacitors C1 to C5 connected to the cathodes of the diodes D1 to D5, respectively.

  A voltage output path to the semiconductor memory 12 is connected to the cathode of the last-stage diode D5 among the five diodes D1 to D5. The other end of the capacitor C5 connected to the cathode is grounded to the ground line.

  The other ends of the capacitors C1 and C3 having one ends connected to the cathodes of the first-stage and third-stage diodes D1 and D3 are connected to the operation clock input path from the PLL circuit 10, and the second and fourth stages. The other ends of the capacitors C2 and C4 whose one ends are connected to the cathodes of the diodes D2 and D4 are connected to the input path of the operation clock from the PLL circuit 10 via the inverter INV1.

  The changeover switch SW1 for changing the operation mode is connected between the input path of the operation clock from the PLL circuit 10 and the capacitor C1, and the operation mode switching unit 32 is in an on / off state of the changeover switch SW1. Is switched to switch the operation mode of the F / V conversion circuit 20.

  That is, in the capacitors C1 to C4 constituting the F / V conversion circuit 20 (in other words, the charge pump 22), if the voltage applied to the side opposite to the diodes D1 to D4 is at a low level, the diodes D1 to D4. Charges are accumulated by the voltage input via.

  Further, when the voltage applied to the opposite side of the diodes D1 to D4 becomes high level, the potential on the diode side of the capacitors C1 to C4 rises by the applied voltage, and the subsequent capacitor via the diodes D2 to D5. Charge is transferred to C2 to C5.

  Since the operation clock is alternately inverted and applied to the opposite sides of the capacitors C1 to C4 from the diodes D1 to D4, the potential on the diode D5 side of the capacitor C5 in the final stage is synchronized with the operation clock. The write voltage obtained by boosting the power supply voltage VDD is output from the F / V conversion circuit 20 to the semiconductor memory 12.

  Also, the output voltage from the F / V conversion circuit 20 to the semiconductor memory 12 changes according to the frequency of the operation clock as shown in FIG. 2, and if the frequency of the operation clock is the same, the voltage of the capacitor used for boosting It changes according to the number of steps.

  Therefore, in the present embodiment, the operation mode switching unit 32 turns on the switch SW1 in the normal operation mode and turns off the switch SW1 in the frequency detection mode according to the operation mode specified by the frequency abnormality determination unit 36. By switching to the state, the F / V conversion characteristic of the F / V conversion circuit 20 is switched from the first F / V conversion characteristic shown in FIG. 2A to the second F / V conversion characteristic. A capacity of ~ C5 is set.

  As described above, in this embodiment, instead of switching whether or not the constant current source 24 is connected to the output side of the charge pump 22 as in the first embodiment, the number of capacitor stages constituting the charge pump 22 is changed. By switching, the F / V conversion characteristic of the F / V conversion circuit 20 is switched between the first F / V conversion characteristic and the second F / V conversion characteristic.

Therefore, according to the present embodiment, the F / V conversion characteristics of the F / V conversion circuit 20 are switched and the operation clock of the F / V conversion circuit 20 is switched as in the first embodiment without externally attaching the constant current source 24 to the charge pump 22. An abnormality in frequency can be determined.
[Third Embodiment]
Next, FIG. 5 is a block diagram illustrating a schematic configuration of the control device 2 including the clock frequency detection device according to the third embodiment to which the present invention is applied.

  As shown in FIG. 5, the control device 2 according to the present embodiment is configured around a microcomputer as in the control devices according to the first and second embodiments described above, and is a PLL circuit for generating an operation clock. 10, a semiconductor memory 12, and an F / V conversion circuit 20 that generates a voltage for writing to the semiconductor memory 12.

The control device 2 is provided with a voltage difference detection unit 38, a frequency abnormality determination unit 36, and an operation mode switching unit 32 as clock frequency detection devices.
Here, the F / V conversion circuit 20 of the present embodiment is provided with a charge pump 22, a constant current source 24, and a changeover switch SW1, as in the first embodiment.

  In addition, a series circuit composed of a constant current source 24 and a changeover switch SW1 is connected in parallel to a series circuit composed of a constant current source 24 and a changeover switch SW1. .

  The voltage output path to which these two constant current sources 24 and 26 are connected is connected to the input terminal of the sample hold circuit (S / H circuit) 28 via the changeover switch SW3 and via the changeover switch SW4. The voltage difference detector 38 is connected to one input terminal.

  Note that the output terminal of the S / H circuit 28 is connected to the other input terminal of the voltage difference detection unit 38, and the S / H circuit 28 follows the command from the operation mode switching unit 32 to switch the changeover switch SW 3. When ON, the output voltage is sampled and held and output to the voltage difference detector 38.

  The voltage difference detector 38 detects a voltage difference between the voltage value of the output voltage sampled and held by the S / H circuit 28 and the voltage value of the output voltage input when the changeover switch SW4 is turned on. Yes, the detection timing is controlled by a command from the operation mode switching unit 32.

  Next, when receiving the frequency detection mode switching signal from the frequency abnormality determination unit 36, the operation mode switching unit 32 of the present embodiment performs switching in the F / V conversion circuit 20 by a series of operations shown in the right column of FIG. By sequentially turning on the switches SW1 and SW3, SW2 and SW4, the operation mode of the F / V conversion circuit 20 is switched from the normal operation mode to the frequency detection mode. In addition, the operation mode switching unit 32 drives the voltage difference detection unit 38 in synchronization with turning on SW2 and SW4.

Hereinafter, the operation of the operation mode switching unit 32 will be described with reference to the flowchart shown in the right column of FIG.
The flowchart shown in the left column of FIG. 6 represents the frequency abnormality determination process executed by the frequency abnormality determination unit 36 of this embodiment, and the frequency abnormality determination process of the first embodiment shown in FIG. The difference is that the processes of S155 and S165 are executed instead of the processes of S150 and S160.

  In S155, the voltage difference ΔV is read from the voltage difference detector 38, and in S165, an abnormality in the frequency of the operation clock is determined from the voltage difference ΔV. This series of processing will be described in detail later.

  As shown in FIG. 6, upon receiving the frequency detection mode switching signal from the frequency abnormality determining unit 36, the operation mode switching unit 32 first switches the changeover switches SW1 and SW3 to the on state in S210, and proceeds to S220. Note that the selector switches SW1 to SW4 are all held in the OFF state in the normal operation mode.

  Next, in S220, the delay time Δ required for the F / V conversion characteristic of the F / V conversion circuit 20 to be stabilized to the second F / V conversion characteristic after the changeover switches SW1 and SW3 are turned on in S210. The process waits for T1 to elapse, and when the delay time ΔT1 elapses, the process proceeds to S230.

  As a result, the S / H circuit 28 outputs a voltage signal output from the F / V conversion circuit 20 to the semiconductor memory 12 when the F / V conversion characteristic of the F / V conversion circuit 20 is the second F / V conversion characteristic. The voltage value is latched and the voltage value is output to the voltage difference detector 38.

As described above, when the process proceeds to S230, the changeover switches SW1 and SW3 are returned to the off state, and the changeover switches SW2 and SW4 are turned on.
As a result, the F / V conversion characteristic of the F / V conversion circuit 20 is changed from the second F / V conversion characteristic corresponding to the current value flowing through the constant current source 24 to the third F / V corresponding to the current value flowing through the constant current source 26. Switching to V conversion characteristics.

  For this reason, the operation mode switching unit 32 passes the predetermined delay time ΔT2 required for stabilizing the F / V conversion characteristic of the F / V conversion circuit 20 to the third F / V conversion characteristic in the subsequent S240. When the delay time ΔT2 has elapsed, the process proceeds to S250, and the voltage difference detection unit 38 is driven.

  As a result, the voltage difference detection unit 38 uses the voltage value of the output voltage in the second F / V conversion characteristic latched by the S / H circuit 28 and the third F / V characteristic input via the changeover switch SW4. The voltage difference ΔV with the output voltage value is detected, and the voltage difference ΔV is output.

  When the voltage difference detection unit 38 is driven in S250 as described above, the operation mode switching unit 32 proceeds to S260 and waits for the normal operation mode switching signal to be input from the frequency abnormality determination unit 36, and then the normal operation mode. When the switching signal is input, the selector switches SW2 and SW4 are returned to the OFF state, and the S / H circuit 28 is reset.

As a result, all changeover switches SW1 to SW4 in the F / V conversion circuit 20 are turned off, and the operation mode of the F / V conversion circuit 20 is switched to the normal operation mode.
On the other hand, in the frequency abnormality determination process executed by the frequency abnormality determination unit 36, when a frequency detection mode switching signal is output to the operation mode switching unit 32 in S130, a predetermined delay time ΔT is thereafter obtained in S140. Wait for it to elapse.

  The delay time ΔT is set to a time longer than the time obtained by adding the delay times ΔT1 and ΔT2 that the operation mode switching unit 32 measures in S220 and S240, and the delay time ΔT has elapsed in S140. If it determines with having performed, it will transfer to S155 and will read voltage difference (DELTA) V from the voltage difference detection part 38. FIG.

  In the subsequent S165, whether or not the voltage difference ΔV read in S155 is out of the normal voltage difference range set in advance based on the frequency versus voltage difference characteristic (F / ΔV characteristic) shown in FIG. By determining whether or not there is an abnormality in the frequency of the operation clock generated by the PLL circuit 10.

  Note that the F / ΔV characteristics shown in FIG. 7A are obtained by comparing the voltage value of the output voltage obtained when the F / V conversion circuit 20 operates with the second F / V conversion characteristics, and the F / V conversion circuit. The difference (ie, voltage difference) ΔV from the voltage value of the output voltage obtained when 20 is operating with the third F / V conversion characteristic is described for each frequency of the operation clock.

  The third F / V conversion characteristic of the F / V conversion circuit 20 corresponds to the frequency in the same way as the second F / V conversion characteristic, although the slope of the voltage value with respect to the frequency is different from that of the second F / V conversion characteristic. Therefore, in the F / ΔV characteristic, the voltage difference ΔV becomes larger as the frequency of the operation clock is lower.

  For this reason, the normal voltage difference range used for determining whether or not there is an abnormality in the frequency of the operation clock in S165 includes the normal frequency range of the operation clock in the F / ΔV characteristic shown in FIG. The upper and lower limit values of the voltage difference ΔV corresponding to are set.

  Next, when it is determined in S165 that there is no abnormality in the frequency of the operation clock, the process proceeds to S180 and a normal operation mode switching signal is output to the operation mode switching unit 32, whereby the F / V conversion circuit 20 is operated. The operation mode is switched to the normal operation mode, and the process proceeds to S110 again.

  If it is determined in S165 that there is an abnormality in the frequency of the operation clock, the process proceeds to S170, and the number of continuous abnormality determinations of the operation clock frequency by the process in S165 is set to a preset failure determination value N. Judge whether or not.

  If the number of continuous abnormality determinations exceeds the failure determination value N, it is determined that some abnormality has occurred in the oscillator 4, the PLL circuit 10, or the circuit in the control device 2 connected to the PLL circuit 10. Then, the internal circuit of the control device 2 is restarted by resetting the control device 2.

  If it is determined in S170 that the number of continuous abnormality determinations of the operation clock frequency does not exceed the failure determination value N, the process proceeds to S180, and the operation mode switching unit 32 receives the operation of the F / V conversion circuit 20. The mode is switched to the normal operation mode, and the process proceeds to S110 again.

  As described above, according to the clock frequency detection device of the present embodiment, when inspecting whether or not the frequency of the operation clock is normal, the operation mode switching unit 32 includes the F / V conversion circuit 20. The F / V conversion characteristic is sequentially switched from the first F / V conversion characteristic for normal operation to the second and third F / V conversion characteristics for frequency detection, and the voltage difference detection unit 38 receives the second and third F / V conversion characteristics. The voltage difference ΔV of the voltage value of the voltage signal output from the F / V conversion circuit 20 when operating with the conversion characteristics is detected.

  Then, the frequency abnormality determination unit 36 determines the frequency of the clock signal (in other words, the operation clock of the control device 2) input to the F / V conversion circuit 20 from the voltage difference ΔV detected by the voltage difference detection unit 38. Whether or not is normal.

  For this reason, also in the clock frequency detection device of the present embodiment, whether or not the frequency of the clock signal (operation clock) generated by the PLL circuit 10 is normal, as in the clock frequency detection devices of the first and second embodiments. Can be accurately determined.

  In the clock frequency detection device of this embodiment, the frequency of the operation clock is based on the difference in output voltage when the F / V conversion circuit 20 is operated with the second F / V conversion characteristic and the third F / V conversion characteristic. Therefore, it is possible to eliminate determination errors due to circuit element manufacturing variations and temperature characteristics that affect the output voltage, and to increase frequency abnormality determination accuracy compared to the first and second embodiments. be able to.

  That is, for example, the output voltage from the charge pump 22 varies depending on the capacitor capacity, the forward voltage of the diode, the number of boosting stages by the capacitor, the power supply voltage VDD, etc., but the voltage difference ΔV is detected as in this embodiment. In this case, changes in the output voltage due to the forward voltage of the diode of the charge pump 22, the number of boosting stages, and the power supply voltage are canceled out. For this reason, according to this embodiment, the frequency abnormality determination accuracy can be made higher than those of the first and second embodiments.

  In the clock frequency detection device of this embodiment, the detection accuracy of the operation clock frequency based on the voltage difference ΔV depends on the load current difference between the constant current sources 24 and 26 and the capacitor capacity.

  If the constant current sources 24 and 26 are formed in the same chip, the accuracy of the current difference between the constant current sources 24 and 26 can be guaranteed. Therefore, the detection accuracy of the operation clock frequency based on the voltage difference ΔV is approximately the capacitance of the capacitor. As shown in FIG. 7B, the F / ΔV characteristic changes due to variations in capacitor capacity.

  For this reason, in order to further improve the abnormality determination accuracy of the frequency of the operation clock, the variation of the F / ΔV characteristic is taken into consideration as shown in FIG. It is preferable to obtain an upper limit value and a lower limit value of the voltage difference ΔV within which the frequency range falls within the normal frequency range, and set this voltage range as a normal voltage difference range for determination.

  Here, in the present embodiment, the S / H circuit 28 corresponds to the voltage value holding means of the present invention, and the changeover switches SW3 and SW4 and the operation mode switching unit 32 for driving the switches SW3 and SW4 are voltage value input means of the present invention. It corresponds to.

As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, a various aspect can be taken.
[Modification 1]
In each of the above-described embodiments, the F / V conversion circuit 20 has been described as being incorporated in the control device 2 formed of a microcomputer. However, the present invention may be implemented by, for example, the F / V conversion circuit 20 as shown in FIG. Even if the power supply device (IC) 50 for supplying power to the semiconductor memory 12 is configured separately from the microcomputer 40, it can be applied in the same manner as in the above embodiment.

That is, as shown in FIG. 8, when the F / V conversion circuit 20 is provided in a power supply device (IC) 50 configured separately from the microcomputer 40, the voltage difference detection unit 38 and the operation mode switching unit 32. Is provided in the power supply device (IC) 50, and the frequency abnormality determination process shown in FIG. 6 is executed by the microcomputer 40, a clock frequency detection device similar to that of the third embodiment can be realized.
[Modification 2]
Further, in each of the above embodiments, the F / V conversion circuit 20 provided in the control device 2 has been described as being one. However, as illustrated in FIG. 9, the control device 2 includes a charge pump having the same configuration. Two F / V conversion circuits 20 and 21 may be mounted.

  In this case, for example, one F / V conversion circuit 20 is configured similarly to that of the first embodiment shown in FIG. 1, and the other F / V conversion circuit 21 has an F / V conversion characteristic of the first F. The reference voltage generating means is fixed to the / V conversion characteristic.

  The writing voltage is supplied to the semiconductor memory 12 from the F / V conversion circuit 21 serving as a reference voltage generation unit. The F / V conversion circuit 20 operates in the same manner as in the first embodiment in the operation mode switching unit 32. Thus, the operation mode is switched from the normal operation mode to the frequency detection mode.

  In addition, the control device 2 is provided with a voltage difference detection unit 38 according to the third embodiment instead of the voltage detection unit 34 according to the first embodiment, and the operation mode switching unit 32 operates in the operation mode of the F / V conversion circuit 20. Is switched to the frequency detection mode, the voltage difference detection unit 38 is driven at a timing when a predetermined standby time ΔT3 required for the output of the F / V conversion circuit 20 to stabilize is passed, and the frequency abnormality determination unit 36 Based on the voltage difference ΔV detected by the voltage difference detector 38, an abnormality in the frequency of the operation clock is determined.

  As a result, according to the clock frequency detection device shown in FIG. 9, the frequency abnormality determination unit 36 performs the frequency of the operation clock in the same procedure (frequency abnormality determination processing shown in FIG. 6) as that of the third embodiment. The abnormality can be determined.

  When the voltage difference detector 38 detects the voltage difference ΔV, if the semiconductor memory 12 is writing data, the output voltage from the F / V conversion circuit 21 varies depending on the load current flowing through the semiconductor memory 12. Therefore, as one of the conditions for the frequency abnormality determination unit 36 to output the frequency detection mode switching signal to the operation mode switching unit 32, the writing to the semiconductor memory 12 is not performed (S120: NO) is desirable to set.

In other words, in this way, it is possible to keep the operating conditions of the F / V conversion circuits 20 and 21 when detecting the voltage difference ΔV constant and prevent the detection accuracy of the frequency of the operating clock from being lowered.
[Modification 3]
Next, in the clock frequency detection device of the third embodiment shown in FIG. 5, the F / V conversion circuit 20 is provided with two constant current sources 24 and 26 and changeover switches SW1 and SW2, and the F / V conversion circuit. When the 20 operation modes are switched from the normal operation mode to the frequency detection mode, the F / V conversion characteristics of the F / V conversion circuit 20 are changed to the second F / V by sequentially turning on the two changeover switches SW1 and SW2. Although the description has been made assuming that the conversion characteristics and the third F / V conversion characteristics are sequentially switched, only one constant current source and a changeover switch may be provided as in the first embodiment.

  In this case, in the normal operation mode in which the changeover switch SW1 is held in the off state, the changeover switch SW3 is turned on and output to the semiconductor memory 12 on condition that the semiconductor memory 12 stops writing data. The S / H circuit 28 samples and holds the output voltage.

  In the frequency detection mode in which the changeover switch SW1 is turned on, the changeover switch SW4 is turned on to drive the voltage difference detection unit 38, whereby the voltage difference detection unit 38 holds the S / H circuit 28. The voltage difference ΔV between the output voltage in the normal operation mode and the output voltage output to the semiconductor memory 12 in the frequency detection mode is detected.

  That is, even in this way, it is possible to detect an abnormality in the frequency of the operation clock from the voltage difference ΔV detected by the voltage difference detection unit 38 as in the clock frequency detection device of the third embodiment. become.

In this case, since the constant current source 26 and the changeover switch SW2 can be deleted from those shown in FIG. 5, the configuration of the F / V conversion circuit 20 (and thus the control device 2) is simplified. be able to.
[Modification 4]
Next, in the above-described embodiment, the F / V conversion circuit 20 as the voltage signal generation unit has been described as being configured by a charge pump. However, the present invention can be operated by integrating a pulse signal, for example. A circuit that generates a voltage signal corresponding to the frequency of the operation clock, provided in an electronic device to be mounted with a clock frequency detection device, such as an integral type F / V converter that generates a voltage signal corresponding to the frequency of the clock. For example, as in the above embodiment, the frequency (or frequency abnormality) of the operation clock can be detected using the circuit.

  DESCRIPTION OF SYMBOLS 2 ... Control apparatus, 4 ... Oscillator, 10 ... PLL circuit, 12 ... Semiconductor memory, 20, 21 ... F / V conversion circuit, 22 ... Charge pump, 24, 26 ... Constant current source, 28 ... S / H circuit ( (Sample hold circuit), 32 ... operation mode switching section, 34 ... voltage detection section, 36 ... frequency abnormality determination section, 38 ... voltage difference detection section, 40 ... microcomputer, SW1 to SW4 ... changeover switch, C1 to C5 ... capacitor, D1 to D5: Diode, INV1: Inverter, 82: BPF (band pass filter), 84: Pulse detection circuit.

Claims (11)

A clock frequency detection device provided in an electronic device including voltage signal generation means for receiving a clock signal and generating a voltage signal having a predetermined voltage value, and detecting the frequency of the clock signal,
By switching the frequency-to-voltage characteristic representing the relationship between the voltage value of the voltage signal output from the voltage signal generating means and the frequency of the clock signal from the first characteristic during normal operation to the second characteristic for frequency detection. Mode switching means for switching the operation mode of the electronic device from the normal operation mode to the frequency detection mode;
Frequency detection for detecting the frequency of the clock signal based on the voltage value of the voltage signal output from the voltage signal generation means when the operation mode of the electronic device is switched to the frequency detection mode by the mode switching means. Means,
Bei to give a,
Among the frequency-to-voltage characteristics of the voltage signal generation means switched by the mode switching means, the first characteristic is that the voltage value of the voltage signal is constant with respect to a frequency change within an allowable variation range of the frequency of the clock signal. Or a constant voltage characteristic that is substantially constant, wherein the second characteristic is a ratio at which the voltage value of the voltage signal is constant or substantially constant corresponding to a change in frequency within an allowable variation range of the frequency of the clock signal. A clock frequency detecting device characterized by changing linear characteristics .   The frequency detection means determines whether the voltage value of the voltage signal output from the voltage signal generation means is within a preset allowable voltage range when the electronic device is in the frequency detection mode. 2. The clock frequency detection device according to claim 1, wherein whether or not the frequency of the clock signal is within an allowable frequency range corresponding to the allowable voltage range in the second characteristic is determined. A clock frequency detection device provided in an electronic device including voltage signal generation means for receiving a clock signal and generating a voltage signal having a predetermined voltage value, and detecting the frequency of the clock signal,
By switching the frequency-to-voltage characteristic representing the relationship between the voltage value of the voltage signal output from the voltage signal generating means and the frequency of the clock signal from the first characteristic during normal operation to the second characteristic for frequency detection. Mode switching means for switching the operation mode of the electronic device from the normal operation mode to the frequency detection mode;
When the operation mode of the electronic device is switched to the frequency detection mode by the mode switching means, a change in voltage value of the voltage signal caused by switching of the frequency-to-voltage characteristic of the voltage signal generating means is defined as a voltage difference. Frequency detecting means for detecting and detecting the frequency of the clock signal based on the voltage difference;
Bei to give a,
Among the frequency-to-voltage characteristics of the voltage signal generation means switched by the mode switching means, the first characteristic is that the voltage value of the voltage signal is constant with respect to a frequency change within an allowable variation range of the frequency of the clock signal. Or a constant voltage characteristic that is substantially constant, wherein the second characteristic is a ratio at which the voltage value of the voltage signal is constant or substantially constant corresponding to a change in frequency within an allowable variation range of the frequency of the clock signal. A clock frequency detecting device characterized by changing linear characteristics . When the electronic device is in a frequency detection mode, the voltage value of the voltage signal output from the voltage signal generation unit is set together with the voltage value of the voltage signal output from the voltage signal generation unit in the normal operation mode. Voltage value input means for input to the detection means,
The frequency detection means detects the frequency of the clock signal using a voltage difference between the voltage values input from the voltage value input means when the electronic device is in a frequency detection mode. The clock frequency detection device according to claim 3. Voltage that holds the voltage value of the voltage signal output from the voltage signal generation means when the electronic device is in the normal operation mode, and continues to hold the voltage value even when the electronic device is switched to the frequency detection mode A value holding means,
The voltage value input means, when the electronic device is switched to the frequency detection mode, the voltage value held by the voltage value holding means and the voltage value of the voltage signal output from the voltage signal generation means, 5. The clock frequency detection device according to claim 4, wherein the clock frequency detection device inputs the frequency detection means. Reference voltage generating means for generating a voltage signal from the clock signal with the first characteristic regardless of the switching state of the operation mode of the electronic device by the mode switching means,
The voltage value input means includes a voltage value of a voltage signal output from the reference voltage generation means and a voltage value of a voltage signal output from the voltage signal generation means when the electronic device is switched to a frequency detection mode. The clock frequency detection device according to claim 4, wherein the frequency detection means is input to the clock frequency detection means. The mode switching means switches the frequency-to-voltage characteristic of the voltage signal output from the voltage signal generating means from the first characteristic to the second characteristic, and sets the operation mode of the electronic device to the frequency detection mode. A linear characteristic in which the voltage value of the voltage signal changes at a constant or substantially constant rate corresponding to a change in the frequency within an allowable fluctuation range of the frequency of the clock signal from the second characteristic. And the second characteristic is changed to a third characteristic having a different change rate of the voltage value ,
The frequency detection means detects a voltage difference between voltage signals corresponding to the second characteristic and the third characteristic, which are sequentially output from the voltage signal generation means when the electronic device is in a frequency detection mode, The clock frequency detection device according to claim 3, wherein the frequency of the clock signal is detected based on a voltage difference. When the frequency characteristic of the voltage signal output from the voltage signal generation unit in the frequency detection mode is the second characteristic, the electronic device holds the voltage value of the voltage signal output from the voltage signal generation unit, Thereafter, voltage value holding means for continuing holding the voltage value even when the frequency vs. voltage characteristic is switched to the third characteristic;
When the electronic device is in the frequency detection mode and the frequency-to-voltage characteristic of the voltage signal output from the voltage signal generation unit is switched from the second characteristic to the third characteristic, the voltage value is held by the voltage value holding unit. Voltage value input means for inputting the voltage value and the voltage value of the voltage signal output from the voltage signal generation means to the frequency detection means;
The clock frequency detection device according to claim 7, further comprising:   The frequency detection means determines whether the frequency of the clock signal is within an allowable frequency range by determining whether the voltage difference is within a preset allowable voltage difference range. The clock frequency detection device according to claim 3, wherein the clock frequency detection device is a clock frequency detection device. The mode switching means switches the operation mode of the electronic device to the frequency detection mode upon receiving a command for switching the operation mode of the electronic device from an internal circuit of the electronic device or an external circuit that controls the electronic device, 10. The clock frequency detection device according to claim 1, wherein a frequency detection operation of the clock signal by a frequency detection unit is started. 11. The mode switching means changes at least one of a circuit element constituting the voltage signal generation means and a circuit element connected to an output path of the voltage signal from the voltage signal generation means. The clock frequency detection device according to any one of claims 1 to 10 , wherein a frequency-to-voltage characteristic is switched from the first characteristic to the second characteristic.

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