JPS62209370A - Cycle measuring apparatus - Google Patents

Abstract

PURPOSE:To measure a cycle from low frequency to high frequency with good accuracy by a counter having a reduced number of bits, by changing over the input clock frequency of the counter corresponding to the length of an input pulse cycle. CONSTITUTION:The pulse PI having a short cycle corresponding to a rotational speed is converted to a synchronous pulse PS by a converter 12 and further delayed by a delay circuit 13 to bring a counter CT15 to a load state and FF16 is reset. CT15 counts an input clock CLK and the count output thereof is sent out through a latch 20 and a D/A converter 21. The carry pulse of CT15 sets FF16 and the output SQ thereof is applied to a latch 25 and CT15 is reset to change over the input clock to CT15 to 1/256 frequency dividing output. Therefore, the pulse PI having a long cycle is counted by CT15. At this time, by the comparison of the outputs of the latches 20, 25 with the outputs of CR15 and FF16 by a comparator 42, a switch 41 is connected to the side of a contact D.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a period detection device that detects the period of an input signal over a wide range.

[Conventional technology]

Measure the period of the input signal as a clock count value,
A period measuring device is known that converts this count value, for example, from D/A to obtain an output converted to voltage.

Conventionally, the method of measuring the period of an input signal is to convert the input signal frequency to voltage, and calculate the period as the divided output.
How to obtain the detection output, measure the period of the input signal as a clock pulse count value, and use the count value as a D/A
There is a way to convert it and get the output as a voltage.

In this case, if you want to accurately measure the period over a wide range of input signals from high to low frequencies, the method using a frequency-to-voltage conversion circuit will not work well with one frequency-to-voltage conversion circuit, so it is necessary to use two conversion circuits. do.

That is, FIG. 5 is a block diagram of an example of this, in which (1) is a high-speed frequency-voltage conversion circuit that shares, for example, 10Hz to 1kHz, and (2) is a low-speed frequency-voltage conversion circuit that shares 10Hz or less. The frequency signal from (3) is supplied to both conversion circuits (1) and (2).

The conversion circuit (1) has IOV at 1kHz and 0.0V at 10Hz, as shown by the solid line (8) in the characteristic diagram of FIG. It has a linear characteristic of IV, and an output in which the input frequency is converted into a voltage is obtained at the output end [6] along the characteristic straight line of this solid line (8) through the switch (5).

When the input frequency becomes 10Hz or less, the output voltage of the conversion circuit (1) becomes 0.1V or less, which is detected by the comparison circuit (4), and the output of this comparison circuit (4) causes the switch (5) to switch to the The state can be switched from the state to the opposite state.

As shown by the broken line (9) in the characteristic diagram of FIG.
) output is 1/10 by the voltage dividing variable resistor (7).
0, and when it is 10H2, it becomes O, IV.

In this way, precise measurements can be made using two frequency-voltage conversion circuits in both low-frequency and high-frequency parts.

However, since this method requires two frequency-voltage conversion circuits, it has the disadvantage of a complicated configuration and high cost.

On the other hand, in the case of the method of measuring the period as a count value of a counter, considering the case of high frequency measurement, it is necessary to increase the clock frequency; Since the clock must be counted for a long time, it was necessary to use a counter with a large number of bits.

[Means for solving problems]

In this invention, period measurement is performed by measuring a clock with a counter, and in particular, it is possible to perform accurate measurement over a wide range with a counter with a small number of bits. A counting means for measuring the period as a count value, a first storage means for storing the count value of the measured period, a second storage means for storing the carry output of the counting means, and the second storage means. means for switching the frequency of the clock according to the output of the clock.

[Effect]

When the period becomes longer than the number of bits of the counting means, the carry pulse from the counting means is latched into the second storage means, and the clock frequency is changed to a lower frequency by the storage output thereof. Therefore, long period measurement is possible within the range of the number of bits of this counting means.

In this way, period measurement over a wide range from high speed to low speed becomes possible.

〔Example〕

FIG. 1 shows an embodiment of the device according to the invention.

In the same figure, (11) is an input terminal, and for example, a pulse PI with a period corresponding to the rotational speed of the rotating body is input to this input terminal (11).
11) to the monostable multi-by-break (12), from which the pulse PS synchronized with the input pulse PI
(Fig. 2A) is obtained. This pulse PS is supplied to the single-committee multi-by-break (13), from which the pulse P
A pulse PR (FIG. B) in which S is slightly at= is obtained.

This pulse PR is supplied to the load terminal of the counter (15) via the OR gate (14) and also to the reset terminal of the RS flip-flop (16).

In this example, a 12-bit counter (15) is used, and the output SQ of the RS flip-flop (16) is supplied as the 9th bit input (2') of the 12-bit preset input of this counter (15). Ru. In this case, all other bits of the precent input are set to O''.

(17) is a clock generator for this counter (15), and the clock pulse CLK from this is the switch (1
The signal is supplied as it is to the clock input terminal of the counter (15) through the terminal A side of the switch (8), and is also supplied to the frequency divider (19) where the frequency is divided to 1/256.
8) is supplied to the clock input terminal of the counter (15) through the terminal B side of the counter (15).

The switch (18) is switched to the terminal A side by the output SQ of the RS flip-flop (16) when the output SQ is o'', and to the terminal B side when it is "1".

Therefore, when the large-power pulse PI arrives, the pulse PR is generated as described above, and the RS flip-flop (16) is reset and its output SQ becomes "0", so the counter (15) is reset by this pulse PR. On the other hand, since the switch (18) is switched to the terminal A side, the counter (15) starts counting the clock CLK from "0".

The count value output (FIG. 2C) of this counter (15) is supplied to the latch circuit (20). On the other hand, a pulse PS that is more advanced than the pulse PR is supplied to the strobe terminal of this latch circuit (20), and this pulse PS causes the pulse P to
The count value before the counter (15) is reset by R, that is, the measured count value of the period of the input pulse PI is latched in the latch circuit (20).

The latched period measurement count value is supplied to a D/A converter (21) using a multiplication type D/A converter, and from this, an analog voltage (D in Figure 2) corresponding to the reciprocal of the period, that is, the frequency is obtained. , which is led out to the output terminal (23) via the amplifier (22).

If the period of the high-power pulse PI is a 12-bit counter (15) and is too short to reach the full scale, the above operation is repeated (see FIG. 2C).

However, in this invention, even if the period of the input pulse PI is so long that the counter (15) reaches full scale and generates a carry pulse CA for a carry, only this counter (15) is used to It is possible to measure the cycle.

That is, when the period of the high-power pulse PI becomes longer and a carry pulse CA is generated from the counter (15), the RS flip-flop (16) is set, and the output SQ of this RS flip-flop (16) becomes It becomes “1”. Then, the monostable multipipe rake (24) is triggered to obtain a pulse PC, which is supplied to the load terminal of the counter (15) via the or game (14).

At this time, since the output SQ is "L", this pulse P
The counter (15) is preset to r256J by C.

On the other hand, since the switch (18) is connected to the terminal B side,
The pulse CLK' from the frequency divider (19), which is the clock pulse CLK divided by 1/256, is counted and amplified by the counter (15) from the count value r256J.

At this time, due to the relationship between the clock frequency and the number of bits of the counter (15), the slope of the increase in the count value of the counter (15) is as shown in FIG.
It will be 1/16 compared to when.

The preset value r256J is when the counter (15) starts counting the clock CLK' from "0".
From the same point, the clock CLK is set to “0” by the counter (15).
'' until the carry pulse CA is generated, that is, the clock CLK' is counted until it reaches full scale. Therefore, the counter (15
), a period up to 16 times the length of the previous input pulse PI can be measured as a count value.

Then, the period-divided analog voltage obtained at the output terminal (23) is outputted with the gain lowered to 1/16 in accordance with the slope of the rising straight line of the count value of the counter (15).

That is, the output SQ of the RS flip-flop (16) is supplied to the latch circuit (25).

Then, the pulse PS from the monostable multi-bibreak (12) is supplied to the strobe terminal of this latch circuit (25). Prior to the current cycle measurement, this latch circuit (25) detects whether the counter (15) reached full scale during the previous count and generated a carry pulse CA, and when the carry pulse CA occurs, the RS Since the output SQ of the flip-flop (16) is 1, this latch circuit (25)
is latched. At other times, the output CQ of this latch circuit (25) is always "0". This latch circuit (25)
The output CQ is supplied to a gain switching switch (26) as a switching signal.

The gain of the operational amplifier (22) is determined by the ratio of the resistor (27) to the resistor connected in the feedback loop of the operational amplifier (22), but in this case, the switch (26) changes the resistor in the feedback loop to the resistor (28). and (29
) and when the period of the input pulse PI is short (
When the period of the input pulse PI is long and the carry pulse CA is generated (resistance (29) is selected), the gain is set to 1/16 (resistance (29) is selected).

Therefore, when the carry pulse CA is generated during the previous count, the count value obtained by counting the clock CLK' is latched in the latch circuit (20) by the input pulses P and S that arrive next, and the latch circuit (25)
) is latched, indicating that the carry pulse CA has occurred, and the output gain is reduced to 1/16.
An analog voltage corresponding to a long period is obtained at the output terminal (23).

Note that the D/A converter (21) can be configured as a reference voltage generator (33) by connecting a multiplier type D/A converter IC (31) into the feedback loop of an operational amplifier (32) as shown in FIG. It is possible to use an output that can be obtained by dividing an analog input voltage VIN corresponding to the output of , by a digital input (count value). In this case, the gain may be switched by configuring the resistors (35) and (36) to be switched by a switch (34), and by switching the switch (34) by the output CQ of the launch circuit (25).

In the example shown in Figure 1, when the period of the input pulse PI changes to become shorter, the output voltage at the output terminal (23) changes immediately in response to the change, but as the period becomes longer. When changing, the output voltage holds the previous period measurement output value until the next input pulse PI arrives, resulting in poor response.

The example in Fig. 4 is an example in which this point has been improved, and the output pulse PS of the monostable multi-bi break (12) is connected to the switch (41).
latch circuits (20) and (2) through one terminal C side of
5) is supplied to the strobe terminal.

The other terminal of this switch (41) is grounded.

Therefore, when the switch (41) is connected to the terminal C, the latch circuit (20) latches the count value output of the counter (15) by the pulse PS, and the latch circuit (25) latches the count value output of the counter (15). output SQ of
Latch. On the other hand, when the switch (41) is connected to the terminal, the latch circuits (20) and (25) output their inputs as they are.

Then, the current count value output from the counter (15), the carry bit output from the RS flip-flop (16), the previous count value output from the latch circuit (20), and the digit value from the latch circuit (25). The higher bit output is supplied to the comparator circuit (42) and compared, and when the current count value output exceeds the previous count value output, an output rising to "1" is obtained from the comparator circuit (42). This rise causes the RS flip-flop (4
3) is set. On the other hand, this RS flip-flop (43) is reset by the pulse PS. Therefore, as shown in FIG. 2E, the output TQ of this RS flip-flop (43) becomes "1" from the time when the current count value output exceeds the previous count value output, and at the time of the arriving pulse 280. becomes “0”.

The switch (41) is this RS flip-flop (43)
When the output TQ of the terminal is “1”, the terminal C is O”
Switched to the side.

Therefore, when the period of the input pulse PI changes to a longer period, the switch (41) is connected to the terminal side from the point where the current count value output exceeds the previous count value output, and the counter (15) Since the count value output is directly supplied to the D/A converter (21) and converted into an analog voltage, the output voltage of the output terminal (23) decreases hyperbolically as the count value increases, as shown in Figure 2 F. It becomes like this.

Therefore, when the period of the input pulse PI changes to become longer, the output voltage changes with good responsiveness.

Note that the above is a case where this invention device is realized as a discrete circuit configuration, but a D/A converter (21
) can be realized by replacing most of the input parts with microcomputer software.

〔Effect of the invention〕

According to this invention, the input clock frequency of the counting means is switched depending on whether the input has a long cycle that causes a carry pulse to be generated by the counting means or the input has a shorter cycle. The counter is accurate from low to high frequencies (it can measure periods).

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the device of this invention, FIG. 2 is a waveform diagram for explaining the same, FIG. 3 is a diagram showing an example of the configuration of a part of the circuit, and FIG. 4 is a diagram of another example of the device of this invention. FIG. 5 is a block diagram of an example of a conventional measuring device, and FIG. 6 is a diagram for explaining the same. (15) is a counter, (16) is a flip-flop for detecting the occurrence of the carry pulse, (18) is a switch for switching the clock frequency, and (21) is a D/
A converter (26) is a switch for changing the gain of analog output.

Claims (1)

[Claims] (a) Counting means for counting the clock and measuring the period of the input signal as a count value; (b) First storage means for storing the count value of the measured period; (c ) a second memory for storing the carry output of the counting means;
(d) means for switching the frequency of the clock according to the output of the second storage means.